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Merge pull request #11198 from SteveCEvans/sce_rc2
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_HAL_Driver / Inc / stm32f4xx_hal_can.h
blobc540ce6d5a96bd8bdfaf2ceee2428e654c2f00b6
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_can.h
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 14-April-2017
7 * @brief Header file of CAN HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_CAN_H
40 #define __STM32F4xx_HAL_CAN_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
47 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
48 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
49 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
50 defined(STM32F423xx)
51 /* Includes ------------------------------------------------------------------*/
52 #include "stm32f4xx_hal_def.h"
53
54 /** @addtogroup STM32F4xx_HAL_Driver
55 * @{
56 */
57
58 /** @addtogroup CAN
59 * @{
60 */
61
62 /* Exported types ------------------------------------------------------------*/
63 /** @defgroup CAN_Exported_Types CAN Exported Types
64 * @{
65 */
66
67 /**
68 * @brief HAL State structures definition
69 */
70 typedef enum
71 {
72 HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
73 HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
74 HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
75 HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
76 HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
77 HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
78 HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
79 HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
80 HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
81 HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
82 HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
83 HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
84
85 }HAL_CAN_StateTypeDef;
86
87 /**
88 * @brief CAN init structure definition
89 */
90 typedef struct
91 {
92 uint32_t Prescaler; /*!< Specifies the length of a time quantum.
93 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
94
95 uint32_t Mode; /*!< Specifies the CAN operating mode.
96 This parameter can be a value of @ref CAN_operating_mode */
97
98 uint32_t SJW; /*!< Specifies the maximum number of time quanta
99 the CAN hardware is allowed to lengthen or
100 shorten a bit to perform resynchronization.
101 This parameter can be a value of @ref CAN_synchronisation_jump_width */
102
103 uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
104 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
105
106 uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
107 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
108
109 uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
110 This parameter can be set to ENABLE or DISABLE. */
111
112 uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
113 This parameter can be set to ENABLE or DISABLE */
114
115 uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
116 This parameter can be set to ENABLE or DISABLE */
117
118 uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
119 This parameter can be set to ENABLE or DISABLE */
120
121 uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
122 This parameter can be set to ENABLE or DISABLE */
123
124 uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
125 This parameter can be set to ENABLE or DISABLE */
126 }CAN_InitTypeDef;
127
128 /**
129 * @brief CAN filter configuration structure definition
130 */
131 typedef struct
132 {
133 uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
134 configuration, first one for a 16-bit configuration).
135 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
136
137 uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
138 configuration, second one for a 16-bit configuration).
139 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
140
141 uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
142 according to the mode (MSBs for a 32-bit configuration,
143 first one for a 16-bit configuration).
144 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
145
146 uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
147 according to the mode (LSBs for a 32-bit configuration,
148 second one for a 16-bit configuration).
149 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
150
151 uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
152 This parameter can be a value of @ref CAN_filter_FIFO */
153
154 uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
155 This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
156
157 uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
158 This parameter can be a value of @ref CAN_filter_mode */
159
160 uint32_t FilterScale; /*!< Specifies the filter scale.
161 This parameter can be a value of @ref CAN_filter_scale */
162
163 uint32_t FilterActivation; /*!< Enable or disable the filter.
164 This parameter can be set to ENABLE or DISABLE. */
165
166 uint32_t BankNumber; /*!< Select the start slave bank filter.
167 This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
168
169 }CAN_FilterConfTypeDef;
170
171 /**
172 * @brief CAN Tx message structure definition
173 */
174 typedef struct
175 {
176 uint32_t StdId; /*!< Specifies the standard identifier.
177 This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
178
179 uint32_t ExtId; /*!< Specifies the extended identifier.
180 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
181
182 uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
183 This parameter can be a value of @ref CAN_Identifier_Type */
184
185 uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
186 This parameter can be a value of @ref CAN_remote_transmission_request */
187
188 uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
189 This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
190
191 uint8_t Data[8]; /*!< Contains the data to be transmitted.
192 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
193
194 }CanTxMsgTypeDef;
195
196 /**
197 * @brief CAN Rx message structure definition
198 */
199 typedef struct
200 {
201 uint32_t StdId; /*!< Specifies the standard identifier.
202 This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
203
204 uint32_t ExtId; /*!< Specifies the extended identifier.
205 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
206
207 uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
208 This parameter can be a value of @ref CAN_Identifier_Type */
209
210 uint32_t RTR; /*!< Specifies the type of frame for the received message.
211 This parameter can be a value of @ref CAN_remote_transmission_request */
212
213 uint32_t DLC; /*!< Specifies the length of the frame that will be received.
214 This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
215
216 uint8_t Data[8]; /*!< Contains the data to be received.
217 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
218
219 uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
220 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
221
222 uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
223 This parameter can be CAN_FIFO0 or CAN_FIFO1 */
224
225 }CanRxMsgTypeDef;
226
227 /**
228 * @brief CAN handle Structure definition
229 */
230 typedef struct
231 {
232 CAN_TypeDef *Instance; /*!< Register base address */
233
234 CAN_InitTypeDef Init; /*!< CAN required parameters */
235
236 CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
237
238 CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
239
240 CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
241
242 __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
243
244 HAL_LockTypeDef Lock; /*!< CAN locking object */
245
246 __IO uint32_t ErrorCode; /*!< CAN Error code */
247
248 }CAN_HandleTypeDef;
249
250 /**
251 * @}
252 */
253
254 /* Exported constants --------------------------------------------------------*/
255 /** @defgroup CAN_Exported_Constants CAN Exported Constants
256 * @{
257 */
258
259 /** @defgroup CAN_Error_Code CAN Error Code
260 * @{
261 */
262 #define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
263 #define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
264 #define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
265 #define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
266 #define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
267 #define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
268 #define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
269 #define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
270 #define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
271 #define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
272 #define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
273 #define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
274 #define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
275 /**
276 * @}
277 */
278
279 /** @defgroup CAN_InitStatus CAN InitStatus
280 * @{
281 */
282 #define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */
283 #define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */
284 /**
285 * @}
286 */
287
288 /** @defgroup CAN_operating_mode CAN Operating Mode
289 * @{
290 */
291 #define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */
292 #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
293 #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
294 #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
295 /**
296 * @}
297 */
298
299 /** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
300 * @{
301 */
302 #define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */
303 #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
304 #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
305 #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
306 /**
307 * @}
308 */
309
310 /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
311 * @{
312 */
313 #define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */
314 #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
315 #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
316 #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
317 #define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
318 #define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
319 #define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
320 #define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
321 #define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
322 #define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
323 #define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
324 #define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
325 #define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
326 #define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
327 #define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
328 #define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
329 /**
330 * @}
331 */
332
333 /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
334 * @{
335 */
336 #define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */
337 #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
338 #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
339 #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
340 #define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
341 #define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
342 #define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
343 #define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
344 /**
345 * @}
346 */
347
348 /** @defgroup CAN_filter_mode CAN Filter Mode
349 * @{
350 */
351 #define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
352 #define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
353 /**
354 * @}
355 */
356
357 /** @defgroup CAN_filter_scale CAN Filter Scale
358 * @{
359 */
360 #define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
361 #define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
362 /**
363 * @}
364 */
365
366 /** @defgroup CAN_filter_FIFO CAN Filter FIFO
367 * @{
368 */
369 #define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
370 #define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
371 /**
372 * @}
373 */
374
375 /** @defgroup CAN_Identifier_Type CAN Identifier Type
376 * @{
377 */
378 #define CAN_ID_STD 0x00000000U /*!< Standard Id */
379 #define CAN_ID_EXT 0x00000004U /*!< Extended Id */
380 /**
381 * @}
382 */
383
384 /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
385 * @{
386 */
387 #define CAN_RTR_DATA 0x00000000U /*!< Data frame */
388 #define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */
389 /**
390 * @}
391 */
392
393 /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
394 * @{
395 */
396 #define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
397 #define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
398 /**
399 * @}
400 */
401
402 /** @defgroup CAN_flags CAN Flags
403 * @{
404 */
405 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
406 and CAN_ClearFlag() functions. */
407 /* If the flag is 0x1XXXXXXX, it means that it can only be used with
408 CAN_GetFlagStatus() function. */
409
410 /* Transmit Flags */
411 #define CAN_FLAG_RQCP0 0x00000500U /*!< Request MailBox0 flag */
412 #define CAN_FLAG_RQCP1 0x00000508U /*!< Request MailBox1 flag */
413 #define CAN_FLAG_RQCP2 0x00000510U /*!< Request MailBox2 flag */
414 #define CAN_FLAG_TXOK0 0x00000501U /*!< Transmission OK MailBox0 flag */
415 #define CAN_FLAG_TXOK1 0x00000509U /*!< Transmission OK MailBox1 flag */
416 #define CAN_FLAG_TXOK2 0x00000511U /*!< Transmission OK MailBox2 flag */
417 #define CAN_FLAG_TME0 0x0000051AU /*!< Transmit mailbox 0 empty flag */
418 #define CAN_FLAG_TME1 0x0000051BU /*!< Transmit mailbox 0 empty flag */
419 #define CAN_FLAG_TME2 0x0000051CU /*!< Transmit mailbox 0 empty flag */
420
421 /* Receive Flags */
422 #define CAN_FLAG_FF0 0x00000203U /*!< FIFO 0 Full flag */
423 #define CAN_FLAG_FOV0 0x00000204U /*!< FIFO 0 Overrun flag */
424
425 #define CAN_FLAG_FF1 0x00000403U /*!< FIFO 1 Full flag */
426 #define CAN_FLAG_FOV1 0x00000404U /*!< FIFO 1 Overrun flag */
427
428 /* Operating Mode Flags */
429 #define CAN_FLAG_INAK 0x00000100U /*!< Initialization acknowledge flag */
430 #define CAN_FLAG_SLAK 0x00000101U /*!< Sleep acknowledge flag */
431 #define CAN_FLAG_ERRI 0x00000102U /*!< Error flag */
432 #define CAN_FLAG_WKU 0x00000103U /*!< Wake up flag */
433 #define CAN_FLAG_SLAKI 0x00000104U /*!< Sleep acknowledge flag */
434
435 /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
436 In this case the SLAK bit can be polled.*/
437
438 /* Error Flags */
439 #define CAN_FLAG_EWG 0x00000300U /*!< Error warning flag */
440 #define CAN_FLAG_EPV 0x00000301U /*!< Error passive flag */
441 #define CAN_FLAG_BOF 0x00000302U /*!< Bus-Off flag */
442 /**
443 * @}
444 */
445
446 /** @defgroup CAN_Interrupts CAN Interrupts
447 * @{
448 */
449 #define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
450
451 /* Receive Interrupts */
452 #define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
453 #define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
454 #define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
455 #define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
456 #define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
457 #define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
458
459 /* Operating Mode Interrupts */
460 #define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
461 #define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
462
463 /* Error Interrupts */
464 #define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
465 #define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
466 #define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
467 #define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
468 #define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
469 /**
470 * @}
471 */
472
473 /** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
474 * @{
475 */
476 #define CAN_TXMAILBOX_0 ((uint8_t)0x00)
477 #define CAN_TXMAILBOX_1 ((uint8_t)0x01)
478 #define CAN_TXMAILBOX_2 ((uint8_t)0x02)
479 /**
480 * @}
481 */
482
483 /**
484 * @}
485 */
486
487 /* Exported macro ------------------------------------------------------------*/
488 /** @defgroup CAN_Exported_Macros CAN Exported Macros
489 * @{
490 */
491
492 /** @brief Reset CAN handle state
493 * @param __HANDLE__: specifies the CAN Handle.
494 * @retval None
495 */
496 #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
497
498 /**
499 * @brief Enable the specified CAN interrupts.
500 * @param __HANDLE__: CAN handle
501 * @param __INTERRUPT__: CAN Interrupt
502 * @retval None
503 */
504 #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
505
506 /**
507 * @brief Disable the specified CAN interrupts.
508 * @param __HANDLE__: CAN handle
509 * @param __INTERRUPT__: CAN Interrupt
510 * @retval None
511 */
512 #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
513
514 /**
515 * @brief Return the number of pending received messages.
516 * @param __HANDLE__: CAN handle
517 * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
518 * @retval The number of pending message.
519 */
520 #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
521 ((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U)))
522
523 /** @brief Check whether the specified CAN flag is set or not.
524 * @param __HANDLE__: CAN Handle
525 * @param __FLAG__: specifies the flag to check.
526 * This parameter can be one of the following values:
527 * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
528 * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
529 * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
530 * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
531 * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
532 * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
533 * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
534 * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
535 * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
536 * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
537 * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
538 * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
539 * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
540 * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
541 * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
542 * @arg CAN_FLAG_WKU: Wake up Flag
543 * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
544 * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
545 * @arg CAN_FLAG_EWG: Error Warning Flag
546 * @arg CAN_FLAG_EPV: Error Passive Flag
547 * @arg CAN_FLAG_BOF: Bus-Off Flag
548 * @retval The new state of __FLAG__ (TRUE or FALSE).
549 */
550 #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
551 ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
552 (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
553 (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
554 (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
555 ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
556
557 /** @brief Clear the specified CAN pending flag.
558 * @param __HANDLE__: CAN Handle.
559 * @param __FLAG__: specifies the flag to check.
560 * This parameter can be one of the following values:
561 * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
562 * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
563 * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
564 * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
565 * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
566 * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
567 * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
568 * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
569 * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
570 * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
571 * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
572 * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
573 * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
574 * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
575 * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
576 * @arg CAN_FLAG_WKU: Wake up Flag
577 * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
578 * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
579 * @retval The new state of __FLAG__ (TRUE or FALSE).
580 */
581 #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
582 ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
583 (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
584 (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
585 (((__HANDLE__)->Instance->MSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))))
586
587 /** @brief Check if the specified CAN interrupt source is enabled or disabled.
588 * @param __HANDLE__: CAN Handle
589 * @param __INTERRUPT__: specifies the CAN interrupt source to check.
590 * This parameter can be one of the following values:
591 * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
592 * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
593 * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
594 * @retval The new state of __IT__ (TRUE or FALSE).
595 */
596 #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
597
598 /**
599 * @brief Check the transmission status of a CAN Frame.
600 * @param __HANDLE__: CAN Handle
601 * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
602 * @retval The new status of transmission (TRUE or FALSE).
603 */
604 #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
605 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
606 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
607 ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
608
609 /**
610 * @brief Release the specified receive FIFO.
611 * @param __HANDLE__: CAN handle
612 * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
613 * @retval None
614 */
615 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
616 ((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
617
618 /**
619 * @brief Cancel a transmit request.
620 * @param __HANDLE__: CAN Handle
621 * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
622 * @retval None
623 */
624 #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
625 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
626 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
627 ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
628
629 /**
630 * @brief Enable or disable the DBG Freeze for CAN.
631 * @param __HANDLE__: CAN Handle
632 * @param __NEWSTATE__: new state of the CAN peripheral.
633 * This parameter can be: ENABLE (CAN reception/transmission is frozen
634 * during debug. Reception FIFOs can still be accessed/controlled normally)
635 * or DISABLE (CAN is working during debug).
636 * @retval None
637 */
638 #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
639 ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
640
641 /**
642 * @}
643 */
644
645 /* Exported functions --------------------------------------------------------*/
646 /** @addtogroup CAN_Exported_Functions
647 * @{
648 */
649
650 /** @addtogroup CAN_Exported_Functions_Group1
651 * @{
652 */
653 /* Initialization/de-initialization functions ***********************************/
654 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
655 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
656 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
657 void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
658 void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
659 /**
660 * @}
661 */
662
663 /** @addtogroup CAN_Exported_Functions_Group2
664 * @{
665 */
666 /* I/O operation functions ******************************************************/
667 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
668 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
669 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
670 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
671 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
672 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
673 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
674 void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
675 void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
676 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
677 /**
678 * @}
679 */
680
681 /** @addtogroup CAN_Exported_Functions_Group3
682 * @{
683 */
684 /* Peripheral State functions ***************************************************/
685 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
686 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
687 /**
688 * @}
689 */
690
691 /**
692 * @}
693 */
694
695 /* Private types -------------------------------------------------------------*/
696 /** @defgroup CAN_Private_Types CAN Private Types
697 * @{
698 */
699
700 /**
701 * @}
702 */
703
704 /* Private variables ---------------------------------------------------------*/
705 /** @defgroup CAN_Private_Variables CAN Private Variables
706 * @{
707 */
708
709 /**
710 * @}
711 */
712
713 /* Private constants ---------------------------------------------------------*/
714 /** @defgroup CAN_Private_Constants CAN Private Constants
715 * @{
716 */
717 #define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
718 #define CAN_FLAG_MASK 0x000000FFU
719 /**
720 * @}
721 */
722
723 /* Private macros ------------------------------------------------------------*/
724 /** @defgroup CAN_Private_Macros CAN Private Macros
725 * @{
726 */
727 #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
728 ((MODE) == CAN_MODE_LOOPBACK)|| \
729 ((MODE) == CAN_MODE_SILENT) || \
730 ((MODE) == CAN_MODE_SILENT_LOOPBACK))
731 #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
732 ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
733 #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
734 #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
735 #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
736 #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
737 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
738 ((MODE) == CAN_FILTERMODE_IDLIST))
739 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
740 ((SCALE) == CAN_FILTERSCALE_32BIT))
741 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
742 ((FIFO) == CAN_FILTER_FIFO1))
743 #define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
744
745 #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
746 #define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FFU))
747 #define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
748 #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
749
750 #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
751 ((IDTYPE) == CAN_ID_EXT))
752 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
753 #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
754
755 /**
756 * @}
757 */
758
759 /* Private functions ---------------------------------------------------------*/
760 /** @defgroup CAN_Private_Functions CAN Private Functions
761 * @{
762 */
763
764 /**
765 * @}
766 */
767
768 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
769 STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
770 STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
771
772 /**
773 * @}
774 */
775
776 /**
777 * @}
778 */
779
780 #ifdef __cplusplus
781 }
782 #endif
783
784 #endif /* __STM32F4xx_CAN_H */
785
786
787 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/