lib/main/STM32F4/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_hal_dma.h
   4   * @author  MCD Application Team
   5   * @version V1.7.1
   6   * @date    14-April-2017
   7   * @brief   Header file of DMA HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F4xx_HAL_DMA_H
  40 #define __STM32F4xx_HAL_DMA_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f4xx_hal_def.h"
  48
  49 /** @addtogroup STM32F4xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup DMA
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58
  59 /** @defgroup DMA_Exported_Types DMA Exported Types
  60   * @brief    DMA Exported Types
  61   * @{
  62   */
  63
  64 /**
  65   * @brief  DMA Configuration Structure definition
  66   */
  67 typedef struct
  68 {
  69   uint32_t Channel;              /*!< Specifies the channel used for the specified stream.
  70                                       This parameter can be a value of @ref DMA_Channel_selection                    */
  71
  72   uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral,
  73                                       from memory to memory or from peripheral to memory.
  74                                       This parameter can be a value of @ref DMA_Data_transfer_direction              */
  75
  76   uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
  77                                       This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
  78
  79   uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
  80                                       This parameter can be a value of @ref DMA_Memory_incremented_mode              */
  81
  82   uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
  83                                       This parameter can be a value of @ref DMA_Peripheral_data_size                 */
  84
  85   uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
  86                                       This parameter can be a value of @ref DMA_Memory_data_size                     */
  87
  88   uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
  89                                       This parameter can be a value of @ref DMA_mode
  90                                       @note The circular buffer mode cannot be used if the memory-to-memory
  91                                             data transfer is configured on the selected Stream                        */
  92
  93   uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
  94                                       This parameter can be a value of @ref DMA_Priority_level                       */
  95
  96   uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
  97                                       This parameter can be a value of @ref DMA_FIFO_direct_mode
  98                                       @note The Direct mode (FIFO mode disabled) cannot be used if the
  99                                             memory-to-memory data transfer is configured on the selected stream       */
 100
 101   uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
 102                                       This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
 103
 104   uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers.
 105                                       It specifies the amount of data to be transferred in a single non interruptible
 106                                       transaction.
 107                                       This parameter can be a value of @ref DMA_Memory_burst
 108                                       @note The burst mode is possible only if the address Increment mode is enabled. */
 109
 110   uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers.
 111                                       It specifies the amount of data to be transferred in a single non interruptible
 112                                       transaction.
 113                                       This parameter can be a value of @ref DMA_Peripheral_burst
 114                                       @note The burst mode is possible only if the address Increment mode is enabled. */
 115 }DMA_InitTypeDef;
 116
 117
 118 /**
 119   * @brief  HAL DMA State structures definition
 120   */
 121 typedef enum
 122 {
 123   HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
 124   HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
 125   HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
 126   HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                   */
 127   HAL_DMA_STATE_ERROR             = 0x04U,  /*!< DMA error state                     */
 128   HAL_DMA_STATE_ABORT             = 0x05U,  /*!< DMA Abort state                     */
 129 }HAL_DMA_StateTypeDef;
 130
 131 /**
 132   * @brief  HAL DMA Error Code structure definition
 133   */
 134 typedef enum
 135 {
 136   HAL_DMA_FULL_TRANSFER           = 0x00U,  /*!< Full transfer     */
 137   HAL_DMA_HALF_TRANSFER           = 0x01U   /*!< Half Transfer     */
 138 }HAL_DMA_LevelCompleteTypeDef;
 139
 140 /**
 141   * @brief  HAL DMA Error Code structure definition
 142   */
 143 typedef enum
 144 {
 145   HAL_DMA_XFER_CPLT_CB_ID         = 0x00U,  /*!< Full transfer     */
 146   HAL_DMA_XFER_HALFCPLT_CB_ID     = 0x01U,  /*!< Half Transfer     */
 147   HAL_DMA_XFER_M1CPLT_CB_ID       = 0x02U,  /*!< M1 Full Transfer  */
 148   HAL_DMA_XFER_M1HALFCPLT_CB_ID   = 0x03U,  /*!< M1 Half Transfer  */
 149   HAL_DMA_XFER_ERROR_CB_ID        = 0x04U,  /*!< Error             */
 150   HAL_DMA_XFER_ABORT_CB_ID        = 0x05U,  /*!< Abort             */
 151   HAL_DMA_XFER_ALL_CB_ID          = 0x06U   /*!< All               */
 152 }HAL_DMA_CallbackIDTypeDef;
 153
 154 /**
 155   * @brief  DMA handle Structure definition
 156   */
 157 typedef struct __DMA_HandleTypeDef
 158 {
 159   DMA_Stream_TypeDef         *Instance;                                                        /*!< Register base address                  */
 160
 161   DMA_InitTypeDef            Init;                                                             /*!< DMA communication parameters           */
 162
 163   HAL_LockTypeDef            Lock;                                                             /*!< DMA locking object                     */
 164
 165   __IO HAL_DMA_StateTypeDef  State;                                                            /*!< DMA transfer state                     */
 166
 167   void                       *Parent;                                                          /*!< Parent object state                    */
 168
 169   void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);         /*!< DMA transfer complete callback         */
 170
 171   void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA Half transfer complete callback    */
 172
 173   void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer complete Memory1 callback */
 174
 175   void                       (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback */
 176
 177   void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer error callback            */
 178
 179   void                       (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer Abort callback            */
 180
 181   __IO uint32_t              ErrorCode;                                                        /*!< DMA Error code                          */
 182
 183   uint32_t                   StreamBaseAddress;                                                /*!< DMA Stream Base Address                */
 184
 185   uint32_t                   StreamIndex;                                                      /*!< DMA Stream Index                       */
 186
 187 }DMA_HandleTypeDef;
 188
 189 /**
 190   * @}
 191   */
 192
 193 /* Exported constants --------------------------------------------------------*/
 194
 195 /** @defgroup DMA_Exported_Constants DMA Exported Constants
 196   * @brief    DMA Exported constants
 197   * @{
 198   */
 199
 200 /** @defgroup DMA_Error_Code DMA Error Code
 201   * @brief    DMA Error Code
 202   * @{
 203   */
 204 #define HAL_DMA_ERROR_NONE            0x00000000U    /*!< No error                               */
 205 #define HAL_DMA_ERROR_TE              0x00000001U    /*!< Transfer error                         */
 206 #define HAL_DMA_ERROR_FE              0x00000002U    /*!< FIFO error                             */
 207 #define HAL_DMA_ERROR_DME             0x00000004U    /*!< Direct Mode error                      */
 208 #define HAL_DMA_ERROR_TIMEOUT         0x00000020U    /*!< Timeout error                          */
 209 #define HAL_DMA_ERROR_PARAM           0x00000040U    /*!< Parameter error                        */
 210 #define HAL_DMA_ERROR_NO_XFER         0x00000080U    /*!< Abort requested with no Xfer ongoing   */
 211 #define HAL_DMA_ERROR_NOT_SUPPORTED   0x00000100U    /*!< Not supported mode                     */
 212 /**
 213   * @}
 214   */
 215
 216 /** @defgroup DMA_Channel_selection DMA Channel selection
 217   * @brief    DMA channel selection
 218   * @{
 219   */
 220 #define DMA_CHANNEL_0                 0x00000000U    /*!< DMA Channel 0 */
 221 #define DMA_CHANNEL_1                 0x02000000U    /*!< DMA Channel 1 */
 222 #define DMA_CHANNEL_2                 0x04000000U    /*!< DMA Channel 2 */
 223 #define DMA_CHANNEL_3                 0x06000000U    /*!< DMA Channel 3 */
 224 #define DMA_CHANNEL_4                 0x08000000U    /*!< DMA Channel 4 */
 225 #define DMA_CHANNEL_5                 0x0A000000U    /*!< DMA Channel 5 */
 226 #define DMA_CHANNEL_6                 0x0C000000U    /*!< DMA Channel 6 */
 227 #define DMA_CHANNEL_7                 0x0E000000U    /*!< DMA Channel 7 */
 228 #if defined (DMA_SxCR_CHSEL_3)
 229 #define DMA_CHANNEL_8                 0x10000000U    /*!< DMA Channel 8 */
 230 #define DMA_CHANNEL_9                 0x12000000U    /*!< DMA Channel 9 */
 231 #define DMA_CHANNEL_10                0x14000000U    /*!< DMA Channel 10 */
 232 #define DMA_CHANNEL_11                0x16000000U    /*!< DMA Channel 11 */
 233 #define DMA_CHANNEL_12                0x18000000U    /*!< DMA Channel 12 */
 234 #define DMA_CHANNEL_13                0x1A000000U    /*!< DMA Channel 13 */
 235 #define DMA_CHANNEL_14                0x1C000000U    /*!< DMA Channel 14 */
 236 #define DMA_CHANNEL_15                0x1E000000U    /*!< DMA Channel 15 */
 237 #endif /* DMA_SxCR_CHSEL_3 */
 238 /**
 239   * @}
 240   */
 241
 242 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
 243   * @brief    DMA data transfer direction
 244   * @{
 245   */
 246 #define DMA_PERIPH_TO_MEMORY          0x00000000U                 /*!< Peripheral to memory direction */
 247 #define DMA_MEMORY_TO_PERIPH          ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
 248 #define DMA_MEMORY_TO_MEMORY          ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
 249 /**
 250   * @}
 251   */
 252
 253 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
 254   * @brief    DMA peripheral incremented mode
 255   * @{
 256   */
 257 #define DMA_PINC_ENABLE               ((uint32_t)DMA_SxCR_PINC)   /*!< Peripheral increment mode enable  */
 258 #define DMA_PINC_DISABLE              0x00000000U                 /*!< Peripheral increment mode disable */
 259 /**
 260   * @}
 261   */
 262
 263 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
 264   * @brief    DMA memory incremented mode
 265   * @{
 266   */
 267 #define DMA_MINC_ENABLE               ((uint32_t)DMA_SxCR_MINC)   /*!< Memory increment mode enable  */
 268 #define DMA_MINC_DISABLE              0x00000000U                 /*!< Memory increment mode disable */
 269 /**
 270   * @}
 271   */
 272
 273 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
 274   * @brief    DMA peripheral data size
 275   * @{
 276   */
 277 #define DMA_PDATAALIGN_BYTE           0x00000000U                  /*!< Peripheral data alignment: Byte     */
 278 #define DMA_PDATAALIGN_HALFWORD       ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
 279 #define DMA_PDATAALIGN_WORD           ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word     */
 280 /**
 281   * @}
 282   */
 283
 284 /** @defgroup DMA_Memory_data_size DMA Memory data size
 285   * @brief    DMA memory data size
 286   * @{
 287   */
 288 #define DMA_MDATAALIGN_BYTE           0x00000000U                  /*!< Memory data alignment: Byte     */
 289 #define DMA_MDATAALIGN_HALFWORD       ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
 290 #define DMA_MDATAALIGN_WORD           ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word     */
 291 /**
 292   * @}
 293   */
 294
 295 /** @defgroup DMA_mode DMA mode
 296   * @brief    DMA mode
 297   * @{
 298   */
 299 #define DMA_NORMAL                    0x00000000U                  /*!< Normal mode                  */
 300 #define DMA_CIRCULAR                  ((uint32_t)DMA_SxCR_CIRC)    /*!< Circular mode                */
 301 #define DMA_PFCTRL                    ((uint32_t)DMA_SxCR_PFCTRL)  /*!< Peripheral flow control mode */
 302 /**
 303   * @}
 304   */
 305
 306 /** @defgroup DMA_Priority_level DMA Priority level
 307   * @brief    DMA priority levels
 308   * @{
 309   */
 310 #define DMA_PRIORITY_LOW              0x00000000U                 /*!< Priority level: Low       */
 311 #define DMA_PRIORITY_MEDIUM           ((uint32_t)DMA_SxCR_PL_0)   /*!< Priority level: Medium    */
 312 #define DMA_PRIORITY_HIGH             ((uint32_t)DMA_SxCR_PL_1)   /*!< Priority level: High      */
 313 #define DMA_PRIORITY_VERY_HIGH        ((uint32_t)DMA_SxCR_PL)     /*!< Priority level: Very High */
 314 /**
 315   * @}
 316   */
 317
 318 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
 319   * @brief    DMA FIFO direct mode
 320   * @{
 321   */
 322 #define DMA_FIFOMODE_DISABLE          0x00000000U                 /*!< FIFO mode disable */
 323 #define DMA_FIFOMODE_ENABLE           ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable  */
 324 /**
 325   * @}
 326   */
 327
 328 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
 329   * @brief    DMA FIFO level
 330   * @{
 331   */
 332 #define DMA_FIFO_THRESHOLD_1QUARTERFULL       0x00000000U                  /*!< FIFO threshold 1 quart full configuration  */
 333 #define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
 334 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
 335 #define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
 336 /**
 337   * @}
 338   */
 339
 340 /** @defgroup DMA_Memory_burst DMA Memory burst
 341   * @brief    DMA memory burst
 342   * @{
 343   */
 344 #define DMA_MBURST_SINGLE             0x00000000U
 345 #define DMA_MBURST_INC4               ((uint32_t)DMA_SxCR_MBURST_0)
 346 #define DMA_MBURST_INC8               ((uint32_t)DMA_SxCR_MBURST_1)
 347 #define DMA_MBURST_INC16              ((uint32_t)DMA_SxCR_MBURST)
 348 /**
 349   * @}
 350   */
 351
 352 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
 353   * @brief    DMA peripheral burst
 354   * @{
 355   */
 356 #define DMA_PBURST_SINGLE             0x00000000U
 357 #define DMA_PBURST_INC4               ((uint32_t)DMA_SxCR_PBURST_0)
 358 #define DMA_PBURST_INC8               ((uint32_t)DMA_SxCR_PBURST_1)
 359 #define DMA_PBURST_INC16              ((uint32_t)DMA_SxCR_PBURST)
 360 /**
 361   * @}
 362   */
 363
 364 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
 365   * @brief    DMA interrupts definition
 366   * @{
 367   */
 368 #define DMA_IT_TC                     ((uint32_t)DMA_SxCR_TCIE)
 369 #define DMA_IT_HT                     ((uint32_t)DMA_SxCR_HTIE)
 370 #define DMA_IT_TE                     ((uint32_t)DMA_SxCR_TEIE)
 371 #define DMA_IT_DME                    ((uint32_t)DMA_SxCR_DMEIE)
 372 #define DMA_IT_FE                     0x00000080U
 373 /**
 374   * @}
 375   */
 376
 377 /** @defgroup DMA_flag_definitions DMA flag definitions
 378   * @brief    DMA flag definitions
 379   * @{
 380   */
 381 #define DMA_FLAG_FEIF0_4              0x00800001U
 382 #define DMA_FLAG_DMEIF0_4             0x00800004U
 383 #define DMA_FLAG_TEIF0_4              0x00000008U
 384 #define DMA_FLAG_HTIF0_4              0x00000010U
 385 #define DMA_FLAG_TCIF0_4              0x00000020U
 386 #define DMA_FLAG_FEIF1_5              0x00000040U
 387 #define DMA_FLAG_DMEIF1_5             0x00000100U
 388 #define DMA_FLAG_TEIF1_5              0x00000200U
 389 #define DMA_FLAG_HTIF1_5              0x00000400U
 390 #define DMA_FLAG_TCIF1_5              0x00000800U
 391 #define DMA_FLAG_FEIF2_6              0x00010000U
 392 #define DMA_FLAG_DMEIF2_6             0x00040000U
 393 #define DMA_FLAG_TEIF2_6              0x00080000U
 394 #define DMA_FLAG_HTIF2_6              0x00100000U
 395 #define DMA_FLAG_TCIF2_6              0x00200000U
 396 #define DMA_FLAG_FEIF3_7              0x00400000U
 397 #define DMA_FLAG_DMEIF3_7             0x01000000U
 398 #define DMA_FLAG_TEIF3_7              0x02000000U
 399 #define DMA_FLAG_HTIF3_7              0x04000000U
 400 #define DMA_FLAG_TCIF3_7              0x08000000U
 401 /**
 402   * @}
 403   */
 404
 405 /**
 406   * @}
 407   */
 408
 409 /* Exported macro ------------------------------------------------------------*/
 410
 411 /** @brief Reset DMA handle state
 412   * @param  __HANDLE__: specifies the DMA handle.
 413   * @retval None
 414   */
 415 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
 416
 417 /**
 418   * @brief  Return the current DMA Stream FIFO filled level.
 419   * @param  __HANDLE__: DMA handle
 420   * @retval The FIFO filling state.
 421   *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
 422   *                                              and not empty.
 423   *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
 424   *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
 425   *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
 426   *           - DMA_FIFOStatus_Empty: when FIFO is empty
 427   *           - DMA_FIFOStatus_Full: when FIFO is full
 428   */
 429 #define __HAL_DMA_GET_FS(__HANDLE__)      (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
 430
 431 /**
 432   * @brief  Enable the specified DMA Stream.
 433   * @param  __HANDLE__: DMA handle
 434   * @retval None
 435   */
 436 #define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)
 437
 438 /**
 439   * @brief  Disable the specified DMA Stream.
 440   * @param  __HANDLE__: DMA handle
 441   * @retval None
 442   */
 443 #define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)
 444
 445 /* Interrupt & Flag management */
 446
 447 /**
 448   * @brief  Return the current DMA Stream transfer complete flag.
 449   * @param  __HANDLE__: DMA handle
 450   * @retval The specified transfer complete flag index.
 451   */
 452 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
 453 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
 454  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
 455  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
 456  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
 457  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
 458  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
 459  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
 460  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
 461  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
 462  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
 463  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
 464  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
 465    DMA_FLAG_TCIF3_7)
 466
 467 /**
 468   * @brief  Return the current DMA Stream half transfer complete flag.
 469   * @param  __HANDLE__: DMA handle
 470   * @retval The specified half transfer complete flag index.
 471   */
 472 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
 473 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
 474  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
 475  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
 476  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
 477  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
 478  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
 479  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
 480  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
 481  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
 482  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
 483  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
 484  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
 485    DMA_FLAG_HTIF3_7)
 486
 487 /**
 488   * @brief  Return the current DMA Stream transfer error flag.
 489   * @param  __HANDLE__: DMA handle
 490   * @retval The specified transfer error flag index.
 491   */
 492 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
 493 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
 494  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
 495  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
 496  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
 497  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
 498  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
 499  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
 500  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
 501  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
 502  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
 503  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
 504  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
 505    DMA_FLAG_TEIF3_7)
 506
 507 /**
 508   * @brief  Return the current DMA Stream FIFO error flag.
 509   * @param  __HANDLE__: DMA handle
 510   * @retval The specified FIFO error flag index.
 511   */
 512 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
 513 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
 514  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
 515  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
 516  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
 517  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
 518  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
 519  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
 520  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
 521  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
 522  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
 523  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
 524  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
 525    DMA_FLAG_FEIF3_7)
 526
 527 /**
 528   * @brief  Return the current DMA Stream direct mode error flag.
 529   * @param  __HANDLE__: DMA handle
 530   * @retval The specified direct mode error flag index.
 531   */
 532 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
 533 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
 534  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
 535  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
 536  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
 537  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
 538  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
 539  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
 540  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
 541  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
 542  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
 543  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
 544  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
 545    DMA_FLAG_DMEIF3_7)
 546
 547 /**
 548   * @brief  Get the DMA Stream pending flags.
 549   * @param  __HANDLE__: DMA handle
 550   * @param  __FLAG__: Get the specified flag.
 551   *          This parameter can be any combination of the following values:
 552   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
 553   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
 554   *            @arg DMA_FLAG_TEIFx: Transfer error flag.
 555   *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
 556   *            @arg DMA_FLAG_FEIFx: FIFO error flag.
 557   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
 558   * @retval The state of FLAG (SET or RESET).
 559   */
 560 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
 561 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
 562  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
 563  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
 564
 565 /**
 566   * @brief  Clear the DMA Stream pending flags.
 567   * @param  __HANDLE__: DMA handle
 568   * @param  __FLAG__: specifies the flag to clear.
 569   *          This parameter can be any combination of the following values:
 570   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
 571   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
 572   *            @arg DMA_FLAG_TEIFx: Transfer error flag.
 573   *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
 574   *            @arg DMA_FLAG_FEIFx: FIFO error flag.
 575   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
 576   * @retval None
 577   */
 578 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
 579 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
 580  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
 581  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
 582
 583 /**
 584   * @brief  Enable the specified DMA Stream interrupts.
 585   * @param  __HANDLE__: DMA handle
 586   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
 587   *        This parameter can be any combination of the following values:
 588   *           @arg DMA_IT_TC: Transfer complete interrupt mask.
 589   *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
 590   *           @arg DMA_IT_TE: Transfer error interrupt mask.
 591   *           @arg DMA_IT_FE: FIFO error interrupt mask.
 592   *           @arg DMA_IT_DME: Direct mode error interrupt.
 593   * @retval None
 594   */
 595 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
 596 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
 597
 598 /**
 599   * @brief  Disable the specified DMA Stream interrupts.
 600   * @param  __HANDLE__: DMA handle
 601   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
 602   *         This parameter can be any combination of the following values:
 603   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
 604   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
 605   *            @arg DMA_IT_TE: Transfer error interrupt mask.
 606   *            @arg DMA_IT_FE: FIFO error interrupt mask.
 607   *            @arg DMA_IT_DME: Direct mode error interrupt.
 608   * @retval None
 609   */
 610 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
 611 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
 612
 613 /**
 614   * @brief  Check whether the specified DMA Stream interrupt is enabled or disabled.
 615   * @param  __HANDLE__: DMA handle
 616   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
 617   *         This parameter can be one of the following values:
 618   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
 619   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
 620   *            @arg DMA_IT_TE: Transfer error interrupt mask.
 621   *            @arg DMA_IT_FE: FIFO error interrupt mask.
 622   *            @arg DMA_IT_DME: Direct mode error interrupt.
 623   * @retval The state of DMA_IT.
 624   */
 625 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
 626                                                         ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
 627                                                         ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
 628
 629 /**
 630   * @brief  Writes the number of data units to be transferred on the DMA Stream.
 631   * @param  __HANDLE__: DMA handle
 632   * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535)
 633   *          Number of data items depends only on the Peripheral data format.
 634   *
 635   * @note   If Peripheral data format is Bytes: number of data units is equal
 636   *         to total number of bytes to be transferred.
 637   *
 638   * @note   If Peripheral data format is Half-Word: number of data units is
 639   *         equal to total number of bytes to be transferred / 2.
 640   *
 641   * @note   If Peripheral data format is Word: number of data units is equal
 642   *         to total  number of bytes to be transferred / 4.
 643   *
 644   * @retval The number of remaining data units in the current DMAy Streamx transfer.
 645   */
 646 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
 647
 648 /**
 649   * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
 650   * @param  __HANDLE__: DMA handle
 651   *
 652   * @retval The number of remaining data units in the current DMA Stream transfer.
 653   */
 654 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
 655
 656
 657 /* Include DMA HAL Extension module */
 658 #include "stm32f4xx_hal_dma_ex.h"
 659
 660 /* Exported functions --------------------------------------------------------*/
 661
 662 /** @defgroup DMA_Exported_Functions DMA Exported Functions
 663   * @brief    DMA Exported functions
 664   * @{
 665   */
 666
 667 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
 668   * @brief   Initialization and de-initialization functions
 669   * @{
 670   */
 671 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
 672 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
 673 /**
 674   * @}
 675   */
 676
 677 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
 678   * @brief   I/O operation functions
 679   * @{
 680   */
 681 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 682 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 683 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
 684 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
 685 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
 686 void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
 687 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
 688 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
 689 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
 690
 691 /**
 692   * @}
 693   */
 694
 695 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
 696   * @brief    Peripheral State functions
 697   * @{
 698   */
 699 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
 700 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
 701 /**
 702   * @}
 703   */
 704 /**
 705   * @}
 706   */
 707 /* Private Constants -------------------------------------------------------------*/
 708 /** @defgroup DMA_Private_Constants DMA Private Constants
 709   * @brief    DMA private defines and constants
 710   * @{
 711   */
 712 /**
 713   * @}
 714   */
 715
 716 /* Private macros ------------------------------------------------------------*/
 717 /** @defgroup DMA_Private_Macros DMA Private Macros
 718   * @brief    DMA private macros
 719   * @{
 720   */
 721 #if defined (DMA_SxCR_CHSEL_3)
 722 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
 723                                  ((CHANNEL) == DMA_CHANNEL_1) || \
 724                                  ((CHANNEL) == DMA_CHANNEL_2) || \
 725                                  ((CHANNEL) == DMA_CHANNEL_3) || \
 726                                  ((CHANNEL) == DMA_CHANNEL_4) || \
 727                                  ((CHANNEL) == DMA_CHANNEL_5) || \
 728                                  ((CHANNEL) == DMA_CHANNEL_6) || \
 729                                  ((CHANNEL) == DMA_CHANNEL_7) || \
 730                                  ((CHANNEL) == DMA_CHANNEL_8) || \
 731                                  ((CHANNEL) == DMA_CHANNEL_9) || \
 732                                  ((CHANNEL) == DMA_CHANNEL_10)|| \
 733                                  ((CHANNEL) == DMA_CHANNEL_11)|| \
 734                                  ((CHANNEL) == DMA_CHANNEL_12)|| \
 735                                  ((CHANNEL) == DMA_CHANNEL_13)|| \
 736                                  ((CHANNEL) == DMA_CHANNEL_14)|| \
 737                                  ((CHANNEL) == DMA_CHANNEL_15))
 738 #else
 739 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
 740                                  ((CHANNEL) == DMA_CHANNEL_1) || \
 741                                  ((CHANNEL) == DMA_CHANNEL_2) || \
 742                                  ((CHANNEL) == DMA_CHANNEL_3) || \
 743                                  ((CHANNEL) == DMA_CHANNEL_4) || \
 744                                  ((CHANNEL) == DMA_CHANNEL_5) || \
 745                                  ((CHANNEL) == DMA_CHANNEL_6) || \
 746                                  ((CHANNEL) == DMA_CHANNEL_7))
 747 #endif /* DMA_SxCR_CHSEL_3 */
 748
 749 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
 750                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
 751                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
 752
 753 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
 754
 755 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
 756                                             ((STATE) == DMA_PINC_DISABLE))
 757
 758 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
 759                                         ((STATE) == DMA_MINC_DISABLE))
 760
 761 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
 762                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
 763                                            ((SIZE) == DMA_PDATAALIGN_WORD))
 764
 765 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
 766                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
 767                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
 768
 769 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
 770                            ((MODE) == DMA_CIRCULAR) || \
 771                            ((MODE) == DMA_PFCTRL))
 772
 773 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
 774                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
 775                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
 776                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
 777
 778 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
 779                                        ((STATE) == DMA_FIFOMODE_ENABLE))
 780
 781 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
 782                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
 783                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
 784                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
 785
 786 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
 787                                     ((BURST) == DMA_MBURST_INC4)   || \
 788                                     ((BURST) == DMA_MBURST_INC8)   || \
 789                                     ((BURST) == DMA_MBURST_INC16))
 790
 791 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
 792                                         ((BURST) == DMA_PBURST_INC4)   || \
 793                                         ((BURST) == DMA_PBURST_INC8)   || \
 794                                         ((BURST) == DMA_PBURST_INC16))
 795 /**
 796   * @}
 797   */
 798
 799 /* Private functions ---------------------------------------------------------*/
 800 /** @defgroup DMA_Private_Functions DMA Private Functions
 801   * @brief    DMA private  functions
 802   * @{
 803   */
 804 /**
 805   * @}
 806   */
 807
 808 /**
 809   * @}
 810   */
 811
 812 /**
 813   * @}
 814   */
 815
 816 #ifdef __cplusplus
 817 }
 818 #endif
 819
 820 #endif /* __STM32F4xx_HAL_DMA_H */
 821
 822 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/