lib/main/STM32F4/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_hal_dma2d.h
   4   * @author  MCD Application Team
   5   * @version V1.7.1
   6   * @date    14-April-2017
   7   * @brief   Header file of DMA2D HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F4xx_HAL_DMA2D_H
  40 #define __STM32F4xx_HAL_DMA2D_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
  47     defined(STM32F469xx) || defined(STM32F479xx)
  48 /* Includes ------------------------------------------------------------------*/
  49 #include "stm32f4xx_hal_def.h"
  50
  51 /** @addtogroup STM32F4xx_HAL_Driver
  52   * @{
  53   */
  54
  55 /** @addtogroup DMA2D DMA2D
  56   * @brief DMA2D HAL module driver
  57   * @{
  58   */
  59
  60 /* Exported types ------------------------------------------------------------*/
  61 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types
  62   * @{
  63   */
  64 #define MAX_DMA2D_LAYER  2U
  65
  66 /**
  67   * @brief DMA2D color Structure definition
  68   */
  69 typedef struct
  70 {
  71   uint32_t             Blue;               /*!< Configures the blue value.
  72                                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
  73
  74   uint32_t             Green;              /*!< Configures the green value.
  75                                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
  76
  77   uint32_t             Red;                /*!< Configures the red value.
  78                                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
  79 } DMA2D_ColorTypeDef;
  80
  81 /**
  82   * @brief DMA2D CLUT Structure definition
  83   */
  84 typedef struct
  85 {
  86   uint32_t             *pCLUT;             /*!< Configures the DMA2D CLUT memory address.*/
  87
  88   uint32_t             CLUTColorMode;      /*!< Configures the DMA2D CLUT color mode.
  89                                                 This parameter can be one value of @ref DMA2D_CLUT_CM. */
  90
  91   uint32_t             Size;               /*!< Configures the DMA2D CLUT size.
  92                                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
  93 } DMA2D_CLUTCfgTypeDef;
  94
  95 /**
  96   * @brief DMA2D Init structure definition
  97   */
  98 typedef struct
  99 {
 100   uint32_t             Mode;               /*!< Configures the DMA2D transfer mode.
 101                                                 This parameter can be one value of @ref DMA2D_Mode. */
 102
 103   uint32_t             ColorMode;          /*!< Configures the color format of the output image.
 104                                                 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
 105
 106   uint32_t             OutputOffset;       /*!< Specifies the Offset value.
 107                                                 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
 108
 109 } DMA2D_InitTypeDef;
 110
 111 /**
 112   * @brief DMA2D Layer structure definition
 113   */
 114 typedef struct
 115 {
 116   uint32_t             InputOffset;        /*!< Configures the DMA2D foreground or background offset.
 117                                                 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
 118
 119   uint32_t             InputColorMode;     /*!< Configures the DMA2D foreground or background color mode.
 120                                                 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
 121
 122   uint32_t             AlphaMode;          /*!< Configures the DMA2D foreground or background alpha mode.
 123                                                 This parameter can be one value of @ref DMA2D_Alpha_Mode. */
 124
 125   uint32_t             InputAlpha;         /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
 126                                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
 127                                                 @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
 128                                                 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
 129                                                 - InputAlpha[24:31] is the alpha value ALPHA[0:7]
 130                                                 - InputAlpha[16:23] is the red value RED[0:7]
 131                                                 - InputAlpha[8:15] is the green value GREEN[0:7]
 132                                                 - InputAlpha[0:7] is the blue value BLUE[0:7]. */
 133
 134 } DMA2D_LayerCfgTypeDef;
 135
 136 /**
 137   * @brief  HAL DMA2D State structures definition
 138   */
 139 typedef enum
 140 {
 141   HAL_DMA2D_STATE_RESET             = 0x00U,    /*!< DMA2D not yet initialized or disabled       */
 142   HAL_DMA2D_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
 143   HAL_DMA2D_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
 144   HAL_DMA2D_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
 145   HAL_DMA2D_STATE_ERROR             = 0x04U,    /*!< DMA2D state error                           */
 146   HAL_DMA2D_STATE_SUSPEND           = 0x05U     /*!< DMA2D process is suspended                  */
 147 }HAL_DMA2D_StateTypeDef;
 148
 149 /**
 150   * @brief  DMA2D handle Structure definition
 151   */
 152 typedef struct __DMA2D_HandleTypeDef
 153 {
 154   DMA2D_TypeDef               *Instance;                                                    /*!< DMA2D register base address.               */
 155
 156   DMA2D_InitTypeDef           Init;                                                         /*!< DMA2D communication parameters.            */
 157
 158   void                        (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d);  /*!< DMA2D transfer complete callback.          */
 159
 160   void                        (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback.             */
 161
 162   DMA2D_LayerCfgTypeDef       LayerCfg[MAX_DMA2D_LAYER];                                    /*!< DMA2D Layers parameters                    */
 163
 164   HAL_LockTypeDef             Lock;                                                         /*!< DMA2D lock.                                */
 165
 166   __IO HAL_DMA2D_StateTypeDef State;                                                        /*!< DMA2D transfer state.                      */
 167
 168   __IO uint32_t               ErrorCode;                                                    /*!< DMA2D error code.                          */
 169 } DMA2D_HandleTypeDef;
 170 /**
 171   * @}
 172   */
 173
 174 /* Exported constants --------------------------------------------------------*/
 175 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
 176   * @{
 177   */
 178
 179 /** @defgroup DMA2D_Error_Code DMA2D Error Code
 180   * @{
 181   */
 182 #define HAL_DMA2D_ERROR_NONE        0x00000000U              /*!< No error             */
 183 #define HAL_DMA2D_ERROR_TE          0x00000001U              /*!< Transfer error       */
 184 #define HAL_DMA2D_ERROR_CE          0x00000002U              /*!< Configuration error  */
 185 #define HAL_DMA2D_ERROR_CAE         0x00000004U              /*!< CLUT access error    */
 186 #define HAL_DMA2D_ERROR_TIMEOUT     0x00000020U              /*!< Timeout error        */
 187 /**
 188   * @}
 189   */
 190
 191 /** @defgroup DMA2D_Mode DMA2D Mode
 192   * @{
 193   */
 194 #define DMA2D_M2M                   0x00000000U              /*!< DMA2D memory to memory transfer mode                              */
 195 #define DMA2D_M2M_PFC               DMA2D_CR_MODE_0          /*!< DMA2D memory to memory with pixel format conversion transfer mode */
 196 #define DMA2D_M2M_BLEND             DMA2D_CR_MODE_1          /*!< DMA2D memory to memory with blending transfer mode                */
 197 #define DMA2D_R2M                   DMA2D_CR_MODE            /*!< DMA2D register to memory transfer mode                            */
 198 /**
 199   * @}
 200   */
 201
 202 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
 203   * @{
 204   */
 205 #define DMA2D_OUTPUT_ARGB8888       0x00000000U                           /*!< ARGB8888 DMA2D color mode */
 206 #define DMA2D_OUTPUT_RGB888         DMA2D_OPFCCR_CM_0                     /*!< RGB888 DMA2D color mode   */
 207 #define DMA2D_OUTPUT_RGB565         DMA2D_OPFCCR_CM_1                     /*!< RGB565 DMA2D color mode   */
 208 #define DMA2D_OUTPUT_ARGB1555       (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
 209 #define DMA2D_OUTPUT_ARGB4444       DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 DMA2D color mode */
 210 /**
 211   * @}
 212   */
 213
 214 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
 215   * @{
 216   */
 217 #define DMA2D_INPUT_ARGB8888        0x00000000U              /*!< ARGB8888 color mode */
 218 #define DMA2D_INPUT_RGB888          0x00000001U              /*!< RGB888 color mode   */
 219 #define DMA2D_INPUT_RGB565          0x00000002U              /*!< RGB565 color mode   */
 220 #define DMA2D_INPUT_ARGB1555        0x00000003U              /*!< ARGB1555 color mode */
 221 #define DMA2D_INPUT_ARGB4444        0x00000004U              /*!< ARGB4444 color mode */
 222 #define DMA2D_INPUT_L8              0x00000005U              /*!< L8 color mode       */
 223 #define DMA2D_INPUT_AL44            0x00000006U              /*!< AL44 color mode     */
 224 #define DMA2D_INPUT_AL88            0x00000007U              /*!< AL88 color mode     */
 225 #define DMA2D_INPUT_L4              0x00000008U              /*!< L4 color mode       */
 226 #define DMA2D_INPUT_A8              0x00000009U              /*!< A8 color mode       */
 227 #define DMA2D_INPUT_A4              0x0000000AU              /*!< A4 color mode       */
 228 /**
 229   * @}
 230   */
 231
 232 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
 233   * @{
 234   */
 235 #define DMA2D_NO_MODIF_ALPHA        0x00000000U              /*!< No modification of the alpha channel value                     */
 236 #define DMA2D_REPLACE_ALPHA         0x00000001U              /*!< Replace original alpha channel value by programmed alpha value */
 237 #define DMA2D_COMBINE_ALPHA         0x00000002U              /*!< Replace original alpha channel value by programmed alpha value
 238                                                                   with original alpha channel value                                */
 239 /**
 240   * @}
 241   */
 242
 243 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
 244   * @{
 245   */
 246 #define DMA2D_CCM_ARGB8888          0x00000000U              /*!< ARGB8888 DMA2D CLUT color mode */
 247 #define DMA2D_CCM_RGB888            0x00000001U              /*!< RGB888 DMA2D CLUT color mode   */
 248 /**
 249   * @}
 250   */
 251
 252 /** @defgroup DMA2D_Interrupts DMA2D Interrupts
 253   * @{
 254   */
 255 #define DMA2D_IT_CE                 DMA2D_CR_CEIE            /*!< Configuration Error Interrupt    */
 256 #define DMA2D_IT_CTC                DMA2D_CR_CTCIE           /*!< CLUT Transfer Complete Interrupt */
 257 #define DMA2D_IT_CAE                DMA2D_CR_CAEIE           /*!< CLUT Access Error Interrupt      */
 258 #define DMA2D_IT_TW                 DMA2D_CR_TWIE            /*!< Transfer Watermark Interrupt     */
 259 #define DMA2D_IT_TC                 DMA2D_CR_TCIE            /*!< Transfer Complete Interrupt      */
 260 #define DMA2D_IT_TE                 DMA2D_CR_TEIE            /*!< Transfer Error Interrupt         */
 261 /**
 262   * @}
 263   */
 264
 265 /** @defgroup DMA2D_Flags DMA2D Flags
 266   * @{
 267   */
 268 #define DMA2D_FLAG_CE               DMA2D_ISR_CEIF           /*!< Configuration Error Interrupt Flag    */
 269 #define DMA2D_FLAG_CTC              DMA2D_ISR_CTCIF          /*!< CLUT Transfer Complete Interrupt Flag */
 270 #define DMA2D_FLAG_CAE              DMA2D_ISR_CAEIF          /*!< CLUT Access Error Interrupt Flag      */
 271 #define DMA2D_FLAG_TW               DMA2D_ISR_TWIF           /*!< Transfer Watermark Interrupt Flag     */
 272 #define DMA2D_FLAG_TC               DMA2D_ISR_TCIF           /*!< Transfer Complete Interrupt Flag      */
 273 #define DMA2D_FLAG_TE               DMA2D_ISR_TEIF           /*!< Transfer Error Interrupt Flag         */
 274 /**
 275   * @}
 276   */
 277
 278 /** @defgroup DMA2D_Aliases DMA2D API Aliases
 279   * @{
 280   */
 281 #define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
 282 /**
 283   * @}
 284   */
 285
 286 /**
 287   * @}
 288   */
 289 /* Exported macros ------------------------------------------------------------*/
 290 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
 291   * @{
 292   */
 293
 294 /** @brief Reset DMA2D handle state
 295   * @param  __HANDLE__: specifies the DMA2D handle.
 296   * @retval None
 297   */
 298 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
 299
 300 /**
 301   * @brief  Enable the DMA2D.
 302   * @param  __HANDLE__: DMA2D handle
 303   * @retval None.
 304   */
 305 #define __HAL_DMA2D_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
 306
 307 /* Interrupt & Flag management */
 308 /**
 309   * @brief  Get the DMA2D pending flags.
 310   * @param  __HANDLE__: DMA2D handle
 311   * @param  __FLAG__: flag to check.
 312   *          This parameter can be any combination of the following values:
 313   *            @arg DMA2D_FLAG_CE:  Configuration error flag
 314   *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
 315   *            @arg DMA2D_FLAG_CAE: CLUT access error flag
 316   *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
 317   *            @arg DMA2D_FLAG_TC:  Transfer complete flag
 318   *            @arg DMA2D_FLAG_TE:  Transfer error flag
 319   * @retval The state of FLAG.
 320   */
 321 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
 322
 323 /**
 324   * @brief  Clear the DMA2D pending flags.
 325   * @param  __HANDLE__: DMA2D handle
 326   * @param  __FLAG__: specifies the flag to clear.
 327   *          This parameter can be any combination of the following values:
 328   *            @arg DMA2D_FLAG_CE:  Configuration error flag
 329   *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
 330   *            @arg DMA2D_FLAG_CAE: CLUT access error flag
 331   *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
 332   *            @arg DMA2D_FLAG_TC:  Transfer complete flag
 333   *            @arg DMA2D_FLAG_TE:  Transfer error flag
 334   * @retval None
 335   */
 336 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
 337
 338 /**
 339   * @brief  Enable the specified DMA2D interrupts.
 340   * @param  __HANDLE__: DMA2D handle
 341   * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
 342   *          This parameter can be any combination of the following values:
 343   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
 344   *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
 345   *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
 346   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
 347   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
 348   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
 349   * @retval None
 350   */
 351 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
 352
 353 /**
 354   * @brief  Disable the specified DMA2D interrupts.
 355   * @param  __HANDLE__: DMA2D handle
 356   * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
 357   *          This parameter can be any combination of the following values:
 358   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
 359   *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
 360   *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
 361   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
 362   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
 363   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
 364   * @retval None
 365   */
 366 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
 367
 368 /**
 369   * @brief  Check whether the specified DMA2D interrupt source is enabled or not.
 370   * @param  __HANDLE__: DMA2D handle
 371   * @param  __INTERRUPT__: specifies the DMA2D interrupt source to check.
 372   *          This parameter can be one of the following values:
 373   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
 374   *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
 375   *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
 376   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
 377   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
 378   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
 379   * @retval The state of INTERRUPT source.
 380   */
 381 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
 382
 383 /**
 384   * @}
 385   */
 386
 387 /* Exported functions --------------------------------------------------------*/
 388 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
 389   * @{
 390   */
 391
 392 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
 393   * @{
 394   */
 395
 396 /* Initialization and de-initialization functions *******************************/
 397 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
 398 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
 399 void              HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
 400 void              HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
 401
 402 /**
 403   * @}
 404   */
 405
 406 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
 407   * @{
 408   */
 409
 410 /* IO operation functions *******************************************************/
 411 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
 412 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height);
 413 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
 414 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
 415 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
 416 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
 417 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
 418 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
 419 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
 420 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
 421 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
 422 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
 423 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
 424 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
 425 void              HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
 426 void              HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
 427 void              HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
 428
 429 /**
 430   * @}
 431   */
 432
 433 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
 434   * @{
 435   */
 436
 437 /* Peripheral Control functions *************************************************/
 438 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
 439 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
 440 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
 441 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
 442 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
 443 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
 444
 445 /**
 446   * @}
 447   */
 448
 449 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
 450   * @{
 451   */
 452
 453 /* Peripheral State functions ***************************************************/
 454 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
 455 uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
 456
 457 /**
 458   * @}
 459   */
 460
 461 /**
 462   * @}
 463   */
 464
 465 /* Private constants ---------------------------------------------------------*/
 466
 467 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
 468   * @{
 469   */
 470
 471 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
 472   * @{
 473   */
 474 #define DMA2D_LINE_WATERMARK_MAX         DMA2D_LWR_LW            /*!< DMA2D maximum line watermark */
 475 /**
 476   * @}
 477   */
 478
 479 /** @defgroup DMA2D_Color_Value DMA2D Color Value
 480   * @{
 481   */
 482 #define DMA2D_COLOR_VALUE                 0x000000FFU            /*!< Color value mask */
 483 /**
 484   * @}
 485   */
 486
 487 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
 488   * @{
 489   */
 490 #define DMA2D_MAX_LAYER                   2U                     /*!< DMA2D maximum number of layers */
 491 /**
 492   * @}
 493   */
 494
 495 /** @defgroup DMA2D_Offset DMA2D Offset
 496   * @{
 497   */
 498 #define DMA2D_OFFSET                      DMA2D_FGOR_LO          /*!< Line Offset */
 499 /**
 500   * @}
 501   */
 502
 503 /** @defgroup DMA2D_Size DMA2D Size
 504   * @{
 505   */
 506 #define DMA2D_PIXEL                       (DMA2D_NLR_PL >> 16U)  /*!< DMA2D number of pixels per line */
 507 #define DMA2D_LINE                        DMA2D_NLR_NL           /*!< DMA2D number of lines           */
 508 /**
 509   * @}
 510   */
 511
 512 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
 513   * @{
 514   */
 515 #define DMA2D_CLUT_SIZE                   (DMA2D_FGPFCCR_CS >> 8U)  /*!< DMA2D CLUT size */
 516 /**
 517   * @}
 518   */
 519
 520 /**
 521   * @}
 522   */
 523
 524 /* Private macros ------------------------------------------------------------*/
 525 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros
 526   * @{
 527   */
 528 #define IS_DMA2D_LAYER(LAYER)                 ((LAYER) <= DMA2D_MAX_LAYER)
 529 #define IS_DMA2D_MODE(MODE)                   (((MODE) == DMA2D_M2M)       || ((MODE) == DMA2D_M2M_PFC) || \
 530                                                ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
 531 #define IS_DMA2D_CMODE(MODE_ARGB)             (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888)   || \
 532                                                ((MODE_ARGB) == DMA2D_OUTPUT_RGB565)   || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
 533                                                ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
 534 #define IS_DMA2D_COLOR(COLOR)                 ((COLOR) <= DMA2D_COLOR_VALUE)
 535 #define IS_DMA2D_LINE(LINE)                   ((LINE) <= DMA2D_LINE)
 536 #define IS_DMA2D_PIXEL(PIXEL)                 ((PIXEL) <= DMA2D_PIXEL)
 537 #define IS_DMA2D_OFFSET(OOFFSET)              ((OOFFSET) <= DMA2D_OFFSET)
 538 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)   (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888)   || \
 539                                                ((INPUT_CM) == DMA2D_INPUT_RGB565)   || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
 540                                                ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8)       || \
 541                                                ((INPUT_CM) == DMA2D_INPUT_AL44)     || ((INPUT_CM) == DMA2D_INPUT_AL88)     || \
 542                                                ((INPUT_CM) == DMA2D_INPUT_L4)       || ((INPUT_CM) == DMA2D_INPUT_A8)       || \
 543                                                ((INPUT_CM) == DMA2D_INPUT_A4))
 544 #define IS_DMA2D_ALPHA_MODE(AlphaMode)        (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
 545                                                ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \
 546                                                ((AlphaMode) == DMA2D_COMBINE_ALPHA))
 547
 548 #define IS_DMA2D_CLUT_CM(CLUT_CM)             (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
 549 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE)         ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
 550 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
 551 #define IS_DMA2D_IT(IT)                       (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
 552                                                ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
 553                                                ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
 554 #define IS_DMA2D_GET_FLAG(FLAG)               (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
 555                                                ((FLAG) == DMA2D_FLAG_TW)   || ((FLAG) == DMA2D_FLAG_TC)  || \
 556                                                ((FLAG) == DMA2D_FLAG_TE)   || ((FLAG) == DMA2D_FLAG_CE))
 557 /**
 558   * @}
 559   */
 560
 561 /**
 562   * @}
 563   */
 564
 565 /**
 566   * @}
 567   */
 568
 569 #endif /* STM32F427xx || STM32F437xx  || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
 570
 571 #ifdef __cplusplus
 572 }
 573 #endif
 574
 575 #endif /* __STM32F4xx_HAL_DMA2D_H */
 576
 577 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/