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Merge pull request #11198 from SteveCEvans/sce_rc2
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_HAL_Driver / Inc / stm32f4xx_hal_qspi.h
blobd51be14baa2dc2ae0df98dbe37b3d6c695dc8f46
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_qspi.h
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 14-April-2017
7 * @brief Header file of QSPI HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_QSPI_H
40 #define __STM32F4xx_HAL_QSPI_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
47 defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
48 /* Includes ------------------------------------------------------------------*/
49 #include "stm32f4xx_hal_def.h"
50
51 /** @addtogroup STM32F4xx_HAL_Driver
52 * @{
53 */
54
55 /** @addtogroup QSPI
56 * @{
57 */
58
59 /* Exported types ------------------------------------------------------------*/
60 /** @defgroup QSPI_Exported_Types QSPI Exported Types
61 * @{
62 */
63
64 /**
65 * @brief QSPI Init structure definition
66 */
67
68 typedef struct
69 {
70 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
71 This parameter can be a number between 0 and 255 */
72
73 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
74 This parameter can be a value between 1 and 32 */
75
76 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
77 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
78 This parameter can be a value of @ref QSPI_SampleShifting */
79
80 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
81 required to address the flash memory. The flash capacity can be up to 4GB
82 (addressed using 32 bits) in indirect mode, but the addressable space in
83 memory-mapped mode is limited to 256MB
84 This parameter can be a number between 0 and 31 */
85
86 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
87 of clock cycles which the chip select must remain high between commands.
88 This parameter can be a value of @ref QSPI_ChipSelectHighTime */
89
90 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
91 This parameter can be a value of @ref QSPI_ClockMode */
92
93 uint32_t FlashID; /* Specifies the Flash which will be used,
94 This parameter can be a value of @ref QSPI_Flash_Select */
95
96 uint32_t DualFlash; /* Specifies the Dual Flash Mode State
97 This parameter can be a value of @ref QSPI_DualFlash_Mode */
98 }QSPI_InitTypeDef;
99
100 /**
101 * @brief HAL QSPI State structures definition
102 */
103 typedef enum
104 {
105 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
106 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
107 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */
108 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */
109 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */
110 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */
111 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
112 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */
113 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */
114 }HAL_QSPI_StateTypeDef;
115
116 /**
117 * @brief QSPI Handle Structure definition
118 */
119 typedef struct
120 {
121 QUADSPI_TypeDef *Instance; /* QSPI registers base address */
122 QSPI_InitTypeDef Init; /* QSPI communication parameters */
123 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
124 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
125 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
126 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
127 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
128 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
129 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
130 __IO HAL_LockTypeDef Lock; /* Locking object */
131 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
132 __IO uint32_t ErrorCode; /* QSPI Error code */
133 uint32_t Timeout; /* Timeout for the QSPI memory access */
134 }QSPI_HandleTypeDef;
135
136 /**
137 * @brief QSPI Command structure definition
138 */
139 typedef struct
140 {
141 uint32_t Instruction; /* Specifies the Instruction to be sent
142 This parameter can be a value (8-bit) between 0x00 and 0xFF */
143 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
144 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
145 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
146 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
147 uint32_t AddressSize; /* Specifies the Address Size
148 This parameter can be a value of @ref QSPI_AddressSize */
149 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
150 This parameter can be a value of @ref QSPI_AlternateBytesSize */
151 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
152 This parameter can be a number between 0 and 31 */
153 uint32_t InstructionMode; /* Specifies the Instruction Mode
154 This parameter can be a value of @ref QSPI_InstructionMode */
155 uint32_t AddressMode; /* Specifies the Address Mode
156 This parameter can be a value of @ref QSPI_AddressMode */
157 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
158 This parameter can be a value of @ref QSPI_AlternateBytesMode */
159 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
160 This parameter can be a value of @ref QSPI_DataMode */
161 uint32_t NbData; /* Specifies the number of data to transfer.
162 This parameter can be any value between 0 and 0xFFFFFFFFU (0 means undefined length
163 until end of memory)*/
164 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
165 This parameter can be a value of @ref QSPI_DdrMode */
166 uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
167 system clock in DDR mode.
168 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
169 uint32_t SIOOMode; /* Specifies the send instruction only once mode
170 This parameter can be a value of @ref QSPI_SIOOMode */
171 }QSPI_CommandTypeDef;
172
173 /**
174 * @brief QSPI Auto Polling mode configuration structure definition
175 */
176 typedef struct
177 {
178 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
179 This parameter can be any value between 0 and 0xFFFFFFFFU */
180 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
181 This parameter can be any value between 0 and 0xFFFFFFFFU */
182 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
183 This parameter can be any value between 0 and 0xFFFFU */
184 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
185 This parameter can be any value between 1 and 4 */
186 uint32_t MatchMode; /* Specifies the method used for determining a match.
187 This parameter can be a value of @ref QSPI_MatchMode */
188 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
189 This parameter can be a value of @ref QSPI_AutomaticStop */
190 }QSPI_AutoPollingTypeDef;
191
192 /**
193 * @brief QSPI Memory Mapped mode configuration structure definition
194 */
195 typedef struct
196 {
197 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
198 This parameter can be any value between 0 and 0xFFFFU */
199 uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
200 This parameter can be a value of @ref QSPI_TimeOutActivation */
201 }QSPI_MemoryMappedTypeDef;
202 /**
203 * @}
204 */
205
206 /* Exported constants --------------------------------------------------------*/
207 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
208 * @{
209 */
210 /** @defgroup QSPI_ErrorCode QSPI Error Code
211 * @{
212 */
213 #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
214 #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
215 #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
216 #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
217 #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
218 /**
219 * @}
220 */
221
222 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
223 * @{
224 */
225 #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/
226 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
227 /**
228 * @}
229 */
230
231 /** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
232 * @{
233 */
234 #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/
235 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
236 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
237 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
238 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
239 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
240 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
241 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
242 /**
243 * @}
244 */
245
246 /** @defgroup QSPI_ClockMode QSPI Clock Mode
247 * @{
248 */
249 #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/
250 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
251 /**
252 * @}
253 */
254
255 /** @defgroup QSPI_Flash_Select QSPI Flash Select
256 * @{
257 */
258 #define QSPI_FLASH_ID_1 0x00000000U
259 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
260 /**
261 * @}
262 */
263
264 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
265 * @{
266 */
267 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
268 #define QSPI_DUALFLASH_DISABLE 0x00000000U
269 /**
270 * @}
271 */
272
273 /** @defgroup QSPI_AddressSize QSPI Address Size
274 * @{
275 */
276 #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/
277 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
278 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
279 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
280 /**
281 * @}
282 */
283
284 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
285 * @{
286 */
287 #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/
288 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
289 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
290 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
291 /**
292 * @}
293 */
294
295 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode
296 * @{
297 */
298 #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/
299 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
300 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
301 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
302 /**
303 * @}
304 */
305
306 /** @defgroup QSPI_AddressMode QSPI Address Mode
307 * @{
308 */
309 #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/
310 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
311 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
312 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
313 /**
314 * @}
315 */
316
317 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
318 * @{
319 */
320 #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/
321 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
322 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
323 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
324 /**
325 * @}
326 */
327
328 /** @defgroup QSPI_DataMode QSPI Data Mode
329 * @{
330 */
331 #define QSPI_DATA_NONE 0x00000000U /*!<No data*/
332 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
333 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
334 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
335 /**
336 * @}
337 */
338
339 /** @defgroup QSPI_DdrMode QSPI Ddr Mode
340 * @{
341 */
342 #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/
343 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
344 /**
345 * @}
346 */
347
348 /** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
349 * @{
350 */
351 #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/
352 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
353 /**
354 * @}
355 */
356
357 /** @defgroup QSPI_SIOOMode QSPI SIOO Mode
358 * @{
359 */
360 #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/
361 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
362 /**
363 * @}
364 */
365
366 /** @defgroup QSPI_MatchMode QSPI Match Mode
367 * @{
368 */
369 #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/
370 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
371 /**
372 * @}
373 */
374
375 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
376 * @{
377 */
378 #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/
379 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
380 /**
381 * @}
382 */
383
384 /** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
385 * @{
386 */
387 #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/
388 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
389 /**
390 * @}
391 */
392
393 /** @defgroup QSPI_Flags QSPI Flags
394 * @{
395 */
396 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
397 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
398 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
399 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
400 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
401 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
402 /**
403 * @}
404 */
405
406 /** @defgroup QSPI_Interrupts QSPI Interrupts
407 * @{
408 */
409 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
410 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
411 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
412 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
413 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
414 /**
415 * @}
416 */
417
418 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition
419 * @{
420 */
421 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
422 /**
423 * @}
424 */
425
426 /**
427 * @}
428 */
429
430 /* Exported macros -----------------------------------------------------------*/
431 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
432 * @{
433 */
434
435 /** @brief Reset QSPI handle state
436 * @param __HANDLE__: QSPI handle.
437 * @retval None
438 */
439 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
440
441 /** @brief Enable QSPI
442 * @param __HANDLE__: specifies the QSPI Handle.
443 * @retval None
444 */
445 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
446
447 /** @brief Disable QSPI
448 * @param __HANDLE__: specifies the QSPI Handle.
449 * @retval None
450 */
451 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
452
453 /** @brief Enables the specified QSPI interrupt.
454 * @param __HANDLE__: specifies the QSPI Handle.
455 * @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
456 * This parameter can be one of the following values:
457 * @arg QSPI_IT_TO: QSPI Time out interrupt
458 * @arg QSPI_IT_SM: QSPI Status match interrupt
459 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
460 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
461 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
462 * @retval None
463 */
464 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
465
466
467 /** @brief Disables the specified QSPI interrupt.
468 * @param __HANDLE__: specifies the QSPI Handle.
469 * @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
470 * This parameter can be one of the following values:
471 * @arg QSPI_IT_TO: QSPI Timeout interrupt
472 * @arg QSPI_IT_SM: QSPI Status match interrupt
473 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
474 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
475 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
476 * @retval None
477 */
478 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
479
480 /** @brief Checks whether the specified QSPI interrupt source is enabled.
481 * @param __HANDLE__: specifies the QSPI Handle.
482 * @param __INTERRUPT__: specifies the QSPI interrupt source to check.
483 * This parameter can be one of the following values:
484 * @arg QSPI_IT_TO: QSPI Time out interrupt
485 * @arg QSPI_IT_SM: QSPI Status match interrupt
486 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
487 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
488 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
489 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
490 */
491 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
492
493 /**
494 * @brief Get the selected QSPI's flag status.
495 * @param __HANDLE__: specifies the QSPI Handle.
496 * @param __FLAG__: specifies the QSPI flag to check.
497 * This parameter can be one of the following values:
498 * @arg QSPI_FLAG_BUSY: QSPI Busy flag
499 * @arg QSPI_FLAG_TO: QSPI Time out flag
500 * @arg QSPI_FLAG_SM: QSPI Status match flag
501 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
502 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
503 * @arg QSPI_FLAG_TE: QSPI Transfer error flag
504 * @retval None
505 */
506 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U)
507
508 /** @brief Clears the specified QSPI's flag status.
509 * @param __HANDLE__: specifies the QSPI Handle.
510 * @param __FLAG__: specifies the QSPI clear register flag that needs to be set
511 * This parameter can be one of the following values:
512 * @arg QSPI_FLAG_TO: QSPI Time out flag
513 * @arg QSPI_FLAG_SM: QSPI Status match flag
514 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
515 * @arg QSPI_FLAG_TE: QSPI Transfer error flag
516 * @retval None
517 */
518 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
519 /**
520 * @}
521 */
522
523 /* Exported functions --------------------------------------------------------*/
524 /** @addtogroup QSPI_Exported_Functions
525 * @{
526 */
527
528 /** @addtogroup QSPI_Exported_Functions_Group1
529 * @{
530 */
531 /* Initialization/de-initialization functions ********************************/
532 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
533 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
534 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
535 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
536 /**
537 * @}
538 */
539
540 /** @addtogroup QSPI_Exported_Functions_Group2
541 * @{
542 */
543 /* IO operation functions *****************************************************/
544 /* QSPI IRQ handler method */
545 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
546
547 /* QSPI indirect mode */
548 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
549 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
550 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
551 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
552 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
553 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
554 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
555 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
556
557 /* QSPI status flag polling mode */
558 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
559 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
560
561 /* QSPI memory-mapped mode */
562 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
563 /**
564 * @}
565 */
566
567 /** @addtogroup QSPI_Exported_Functions_Group3
568 * @{
569 */
570 /* Callback functions in non-blocking modes ***********************************/
571 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
572 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
573 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
574
575 /* QSPI indirect mode */
576 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
577 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
578 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
579 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
580 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
581
582 /* QSPI status flag polling mode */
583 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
584
585 /* QSPI memory-mapped mode */
586 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
587 /**
588 * @}
589 */
590
591 /** @addtogroup QSPI_Exported_Functions_Group4
592 * @{
593 */
594 /* Peripheral Control and State functions ************************************/
595 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
596 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
597 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
598 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
599 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
600 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
601 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
602 /**
603 * @}
604 */
605
606 /* Private macros ------------------------------------------------------------*/
607 /** @defgroup QSPI_Private_Macros QSPI Private Macros
608 * @{
609 */
610 /** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
611 * @{
612 */
613 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
614 /**
615 * @}
616 */
617
618 /** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold
619 * @{
620 */
621 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
622 /**
623 * @}
624 */
625
626 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
627 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
628
629 /** @defgroup QSPI_FlashSize QSPI Flash Size
630 * @{
631 */
632 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
633 /**
634 * @}
635 */
636
637 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
638 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
639 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
640 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
641 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
642 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
643 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
644 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
645
646 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
647 ((CLKMODE) == QSPI_CLOCK_MODE_3))
648
649 #define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \
650 ((FLA) == QSPI_FLASH_ID_2))
651
652 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
653 ((MODE) == QSPI_DUALFLASH_DISABLE))
654
655
656 /** @defgroup QSPI_Instruction QSPI Instruction
657 * @{
658 */
659 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
660 /**
661 * @}
662 */
663
664 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
665 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
666 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
667 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
668
669 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
670 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
671 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
672 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
673
674
675 /** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
676 * @{
677 */
678 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
679 /**
680 * @}
681 */
682
683 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
684 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
685 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
686 ((MODE) == QSPI_INSTRUCTION_4_LINES))
687
688 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
689 ((MODE) == QSPI_ADDRESS_1_LINE) || \
690 ((MODE) == QSPI_ADDRESS_2_LINES) || \
691 ((MODE) == QSPI_ADDRESS_4_LINES))
692
693 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
694 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
695 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
696 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
697
698 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
699 ((MODE) == QSPI_DATA_1_LINE) || \
700 ((MODE) == QSPI_DATA_2_LINES) || \
701 ((MODE) == QSPI_DATA_4_LINES))
702
703 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
704 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
705
706 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
707 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
708
709 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
710 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
711
712 /** @defgroup QSPI_Interval QSPI Interval
713 * @{
714 */
715 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
716 /**
717 * @}
718 */
719
720 /** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
721 * @{
722 */
723 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
724 /**
725 * @}
726 */
727 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
728 ((MODE) == QSPI_MATCH_MODE_OR))
729
730 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
731 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
732
733 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
734 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
735
736 /** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period
737 * @{
738 */
739 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
740 /**
741 * @}
742 */
743
744 #define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \
745 ((FLAG) == QSPI_FLAG_TO) || \
746 ((FLAG) == QSPI_FLAG_SM) || \
747 ((FLAG) == QSPI_FLAG_FT) || \
748 ((FLAG) == QSPI_FLAG_TC) || \
749 ((FLAG) == QSPI_FLAG_TE))
750
751 #define IS_QSPI_IT(IT) ((((IT) & 0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))
752 /**
753 * @}
754 */
755
756 /* Private functions ---------------------------------------------------------*/
757 /** @defgroup QSPI_Private_Functions QSPI Private Functions
758 * @{
759 */
760
761 /**
762 * @}
763 */
764
765 /**
766 * @}
767 */
768
769 /**
770 * @}
771 */
772
773 /**
774 * @}
775 */
776 #endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||
777 STM32F413xx || STM32F423xx */
778
779 #ifdef __cplusplus
780 }
781 #endif
782
783 #endif /* __STM32F4xx_HAL_QSPI_H */
784
785 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/