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Merge pull request #11198 from SteveCEvans/sce_rc2
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_HAL_Driver / Inc / stm32f4xx_hal_tim.h
blob35172181f9966f6448c03f99d9cbc02ba5b9d7b7
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_tim.h
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 14-April-2017
7 * @brief Header file of TIM HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_TIM_H
40 #define __STM32F4xx_HAL_TIM_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx_hal_def.h"
48
49 /** @addtogroup STM32F4xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup TIM
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup TIM_Exported_Types TIM Exported Types
59 * @{
60 */
61
62 /**
63 * @brief TIM Time base Configuration Structure definition
64 */
65 typedef struct
66 {
67 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
68 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
69
70 uint32_t CounterMode; /*!< Specifies the counter mode.
71 This parameter can be a value of @ref TIM_Counter_Mode */
72
73 uint32_t Period; /*!< Specifies the period value to be loaded into the active
74 Auto-Reload Register at the next update event.
75 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFF. */
76
77 uint32_t ClockDivision; /*!< Specifies the clock division.
78 This parameter can be a value of @ref TIM_ClockDivision */
79
80 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
81 reaches zero, an update event is generated and counting restarts
82 from the RCR value (N).
83 This means in PWM mode that (N+1) corresponds to:
84 - the number of PWM periods in edge-aligned mode
85 - the number of half PWM period in center-aligned mode
86 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
87 @note This parameter is valid only for TIM1 and TIM8. */
88 } TIM_Base_InitTypeDef;
89
90 /**
91 * @brief TIM Output Compare Configuration Structure definition
92 */
93
94 typedef struct
95 {
96 uint32_t OCMode; /*!< Specifies the TIM mode.
97 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
98
99 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
100 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
101
102 uint32_t OCPolarity; /*!< Specifies the output polarity.
103 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
104
105 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
106 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
107 @note This parameter is valid only for TIM1 and TIM8. */
108
109 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
110 This parameter can be a value of @ref TIM_Output_Fast_State
111 @note This parameter is valid only in PWM1 and PWM2 mode. */
112
113
114 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
115 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
116 @note This parameter is valid only for TIM1 and TIM8. */
117
118 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
119 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
120 @note This parameter is valid only for TIM1 and TIM8. */
121 } TIM_OC_InitTypeDef;
122
123 /**
124 * @brief TIM One Pulse Mode Configuration Structure definition
125 */
126 typedef struct
127 {
128 uint32_t OCMode; /*!< Specifies the TIM mode.
129 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
130
131 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
132 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
133
134 uint32_t OCPolarity; /*!< Specifies the output polarity.
135 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
136
137 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
138 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
139 @note This parameter is valid only for TIM1 and TIM8. */
140
141 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
142 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
143 @note This parameter is valid only for TIM1 and TIM8. */
144
145 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
146 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
147 @note This parameter is valid only for TIM1 and TIM8. */
148
149 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
150 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
151
152 uint32_t ICSelection; /*!< Specifies the input.
153 This parameter can be a value of @ref TIM_Input_Capture_Selection */
154
155 uint32_t ICFilter; /*!< Specifies the input capture filter.
156 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
157 } TIM_OnePulse_InitTypeDef;
158
159
160 /**
161 * @brief TIM Input Capture Configuration Structure definition
162 */
163
164 typedef struct
165 {
166 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
167 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
168
169 uint32_t ICSelection; /*!< Specifies the input.
170 This parameter can be a value of @ref TIM_Input_Capture_Selection */
171
172 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
173 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
174
175 uint32_t ICFilter; /*!< Specifies the input capture filter.
176 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
177 } TIM_IC_InitTypeDef;
178
179 /**
180 * @brief TIM Encoder Configuration Structure definition
181 */
182
183 typedef struct
184 {
185 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
186 This parameter can be a value of @ref TIM_Encoder_Mode */
187
188 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
189 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
190
191 uint32_t IC1Selection; /*!< Specifies the input.
192 This parameter can be a value of @ref TIM_Input_Capture_Selection */
193
194 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
195 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
196
197 uint32_t IC1Filter; /*!< Specifies the input capture filter.
198 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
199
200 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
201 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
202
203 uint32_t IC2Selection; /*!< Specifies the input.
204 This parameter can be a value of @ref TIM_Input_Capture_Selection */
205
206 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
207 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
208
209 uint32_t IC2Filter; /*!< Specifies the input capture filter.
210 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
211 } TIM_Encoder_InitTypeDef;
212
213 /**
214 * @brief Clock Configuration Handle Structure definition
215 */
216 typedef struct
217 {
218 uint32_t ClockSource; /*!< TIM clock sources.
219 This parameter can be a value of @ref TIM_Clock_Source */
220 uint32_t ClockPolarity; /*!< TIM clock polarity.
221 This parameter can be a value of @ref TIM_Clock_Polarity */
222 uint32_t ClockPrescaler; /*!< TIM clock prescaler.
223 This parameter can be a value of @ref TIM_Clock_Prescaler */
224 uint32_t ClockFilter; /*!< TIM clock filter.
225 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
226 }TIM_ClockConfigTypeDef;
227
228 /**
229 * @brief Clear Input Configuration Handle Structure definition
230 */
231 typedef struct
232 {
233 uint32_t ClearInputState; /*!< TIM clear Input state.
234 This parameter can be ENABLE or DISABLE */
235 uint32_t ClearInputSource; /*!< TIM clear Input sources.
236 This parameter can be a value of @ref TIM_ClearInput_Source */
237 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
238 This parameter can be a value of @ref TIM_ClearInput_Polarity */
239 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
240 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
241 uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
242 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
243 }TIM_ClearInputConfigTypeDef;
244
245 /**
246 * @brief TIM Slave configuration Structure definition
247 */
248 typedef struct {
249 uint32_t SlaveMode; /*!< Slave mode selection
250 This parameter can be a value of @ref TIM_Slave_Mode */
251 uint32_t InputTrigger; /*!< Input Trigger source
252 This parameter can be a value of @ref TIM_Trigger_Selection */
253 uint32_t TriggerPolarity; /*!< Input Trigger polarity
254 This parameter can be a value of @ref TIM_Trigger_Polarity */
255 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
256 This parameter can be a value of @ref TIM_Trigger_Prescaler */
257 uint32_t TriggerFilter; /*!< Input trigger filter
258 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
259
260 }TIM_SlaveConfigTypeDef;
261
262 /**
263 * @brief HAL State structures definition
264 */
265 typedef enum
266 {
267 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
268 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
269 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
270 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
271 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
272 }HAL_TIM_StateTypeDef;
273
274 /**
275 * @brief HAL Active channel structures definition
276 */
277 typedef enum
278 {
279 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
280 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
281 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
282 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
283 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
284 }HAL_TIM_ActiveChannel;
285
286 /**
287 * @brief TIM Time Base Handle Structure definition
288 */
289 typedef struct
290 {
291 TIM_TypeDef *Instance; /*!< Register base address */
292 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
293 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
294 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
295 This array is accessed by a @ref DMA_Handle_index */
296 HAL_LockTypeDef Lock; /*!< Locking object */
297 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
298 }TIM_HandleTypeDef;
299 /**
300 * @}
301 */
302
303 /* Exported constants --------------------------------------------------------*/
304 /** @defgroup TIM_Exported_Constants TIM Exported Constants
305 * @{
306 */
307
308 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
309 * @{
310 */
311 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
312 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
313 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
314 /**
315 * @}
316 */
317
318 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
319 * @{
320 */
321 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
322 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
323 /**
324 * @}
325 */
326
327 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
328 * @{
329 */
330 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
331 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
332 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
333 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
334 /**
335 * @}
336 */
337
338 /** @defgroup TIM_Counter_Mode TIM Counter Mode
339 * @{
340 */
341 #define TIM_COUNTERMODE_UP 0x00000000U
342 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
343 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
344 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
345 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
346 /**
347 * @}
348 */
349
350 /** @defgroup TIM_ClockDivision TIM Clock Division
351 * @{
352 */
353 #define TIM_CLOCKDIVISION_DIV1 0x00000000U
354 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
355 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
356 /**
357 * @}
358 */
359
360 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
361 * @{
362 */
363 #define TIM_OCMODE_TIMING 0x00000000U
364 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
365 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
366 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
367 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
368 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
369 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
370 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
371
372 /**
373 * @}
374 */
375
376 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
377 * @{
378 */
379 #define TIM_OCFAST_DISABLE 0x00000000U
380 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
381 /**
382 * @}
383 */
384
385 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
386 * @{
387 */
388 #define TIM_OCPOLARITY_HIGH 0x00000000U
389 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
390 /**
391 * @}
392 */
393
394 /** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
395 * @{
396 */
397 #define TIM_OCNPOLARITY_HIGH 0x00000000U
398 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
399 /**
400 * @}
401 */
402
403 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
404 * @{
405 */
406 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
407 #define TIM_OCIDLESTATE_RESET 0x00000000U
408 /**
409 * @}
410 */
411
412 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
413 * @{
414 */
415 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
416 #define TIM_OCNIDLESTATE_RESET 0x00000000U
417 /**
418 * @}
419 */
420
421 /** @defgroup TIM_Channel TIM Channel
422 * @{
423 */
424 #define TIM_CHANNEL_1 0x00000000U
425 #define TIM_CHANNEL_2 0x00000004U
426 #define TIM_CHANNEL_3 0x00000008U
427 #define TIM_CHANNEL_4 0x0000000CU
428 #define TIM_CHANNEL_ALL 0x00000018U
429
430 /**
431 * @}
432 */
433
434 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
435 * @{
436 */
437 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
438 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
439 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
440 /**
441 * @}
442 */
443
444 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
445 * @{
446 */
447 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
448 connected to IC1, IC2, IC3 or IC4, respectively */
449 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
450 connected to IC2, IC1, IC4 or IC3, respectively */
451 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
452
453 /**
454 * @}
455 */
456
457 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
458 * @{
459 */
460 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
461 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
462 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
463 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
464 /**
465 * @}
466 */
467
468 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
469 * @{
470 */
471 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
472 #define TIM_OPMODE_REPETITIVE 0x00000000U
473 /**
474 * @}
475 */
476
477 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
478 * @{
479 */
480 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
481 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
482 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
483
484 /**
485 * @}
486 */
487
488 /** @defgroup TIM_Interrupt_definition TIM Interrupt definition
489 * @{
490 */
491 #define TIM_IT_UPDATE (TIM_DIER_UIE)
492 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
493 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
494 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
495 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
496 #define TIM_IT_COM (TIM_DIER_COMIE)
497 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
498 #define TIM_IT_BREAK (TIM_DIER_BIE)
499 /**
500 * @}
501 */
502
503 /** @defgroup TIM_Commutation_Source TIM Commutation Source
504 * @{
505 */
506 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
507 #define TIM_COMMUTATION_SOFTWARE 0x00000000U
508 /**
509 * @}
510 */
511
512 /** @defgroup TIM_DMA_sources TIM DMA sources
513 * @{
514 */
515 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
516 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
517 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
518 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
519 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
520 #define TIM_DMA_COM (TIM_DIER_COMDE)
521 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
522 /**
523 * @}
524 */
525
526 /** @defgroup TIM_Event_Source TIM Event Source
527 * @{
528 */
529 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
530 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
531 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
532 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
533 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
534 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
535 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
536 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
537
538 /**
539 * @}
540 */
541
542 /** @defgroup TIM_Flag_definition TIM Flag definition
543 * @{
544 */
545 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
546 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
547 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
548 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
549 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
550 #define TIM_FLAG_COM (TIM_SR_COMIF)
551 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
552 #define TIM_FLAG_BREAK (TIM_SR_BIF)
553 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
554 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
555 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
556 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
557 /**
558 * @}
559 */
560
561 /** @defgroup TIM_Clock_Source TIM Clock Source
562 * @{
563 */
564 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
565 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
566 #define TIM_CLOCKSOURCE_ITR0 0x00000000U
567 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
568 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
569 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
570 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
571 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
572 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
573 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
574 /**
575 * @}
576 */
577
578 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
579 * @{
580 */
581 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
582 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
583 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
584 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
585 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
586 /**
587 * @}
588 */
589
590 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
591 * @{
592 */
593 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
594 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
595 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
596 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
597 /**
598 * @}
599 */
600
601 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
602 * @{
603 */
604 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U
605 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U
606 /**
607 * @}
608 */
609
610 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
611 * @{
612 */
613 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
614 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
615 /**
616 * @}
617 */
618
619 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
620 * @{
621 */
622 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
623 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
624 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
625 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
626 /**
627 * @}
628 */
629
630 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
631 * @{
632 */
633 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
634 #define TIM_OSSR_DISABLE 0x00000000U
635 /**
636 * @}
637 */
638
639 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
640 * @{
641 */
642 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
643 #define TIM_OSSI_DISABLE 0x00000000U
644 /**
645 * @}
646 */
647
648 /** @defgroup TIM_Lock_level TIM Lock level
649 * @{
650 */
651 #define TIM_LOCKLEVEL_OFF 0x00000000U
652 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
653 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
654 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
655 /**
656 * @}
657 */
658 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
659 * @{
660 */
661 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
662 #define TIM_BREAK_DISABLE 0x00000000U
663 /**
664 * @}
665 */
666
667 /** @defgroup TIM_Break_Polarity TIM Break Polarity
668 * @{
669 */
670 #define TIM_BREAKPOLARITY_LOW 0x00000000U
671 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
672 /**
673 * @}
674 */
675
676 /** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
677 * @{
678 */
679 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
680 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
681 /**
682 * @}
683 */
684
685 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
686 * @{
687 */
688 #define TIM_TRGO_RESET 0x00000000U
689 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
690 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
691 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
692 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
693 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
694 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
695 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
696 /**
697 * @}
698 */
699
700 /** @defgroup TIM_Slave_Mode TIM Slave Mode
701 * @{
702 */
703 #define TIM_SLAVEMODE_DISABLE 0x00000000U
704 #define TIM_SLAVEMODE_RESET 0x00000004U
705 #define TIM_SLAVEMODE_GATED 0x00000005U
706 #define TIM_SLAVEMODE_TRIGGER 0x00000006U
707 #define TIM_SLAVEMODE_EXTERNAL1 0x00000007U
708 /**
709 * @}
710 */
711
712 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
713 * @{
714 */
715 #define TIM_MASTERSLAVEMODE_ENABLE 0x00000080U
716 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
717 /**
718 * @}
719 */
720
721 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
722 * @{
723 */
724 #define TIM_TS_ITR0 0x00000000U
725 #define TIM_TS_ITR1 0x00000010U
726 #define TIM_TS_ITR2 0x00000020U
727 #define TIM_TS_ITR3 0x00000030U
728 #define TIM_TS_TI1F_ED 0x00000040U
729 #define TIM_TS_TI1FP1 0x00000050U
730 #define TIM_TS_TI2FP2 0x00000060U
731 #define TIM_TS_ETRF 0x00000070U
732 #define TIM_TS_NONE 0x0000FFFFU
733 /**
734 * @}
735 */
736
737 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
738 * @{
739 */
740 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
741 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
742 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
743 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
744 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
745 /**
746 * @}
747 */
748
749 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
750 * @{
751 */
752 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
753 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
754 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
755 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
756 /**
757 * @}
758 */
759
760
761 /** @defgroup TIM_TI1_Selection TIM TI1 Selection
762 * @{
763 */
764 #define TIM_TI1SELECTION_CH1 0x00000000U
765 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
766 /**
767 * @}
768 */
769
770 /** @defgroup TIM_DMA_Base_address TIM DMA Base address
771 * @{
772 */
773 #define TIM_DMABASE_CR1 0x00000000U
774 #define TIM_DMABASE_CR2 0x00000001U
775 #define TIM_DMABASE_SMCR 0x00000002U
776 #define TIM_DMABASE_DIER 0x00000003U
777 #define TIM_DMABASE_SR 0x00000004U
778 #define TIM_DMABASE_EGR 0x00000005U
779 #define TIM_DMABASE_CCMR1 0x00000006U
780 #define TIM_DMABASE_CCMR2 0x00000007U
781 #define TIM_DMABASE_CCER 0x00000008U
782 #define TIM_DMABASE_CNT 0x00000009U
783 #define TIM_DMABASE_PSC 0x0000000AU
784 #define TIM_DMABASE_ARR 0x0000000BU
785 #define TIM_DMABASE_RCR 0x0000000CU
786 #define TIM_DMABASE_CCR1 0x0000000DU
787 #define TIM_DMABASE_CCR2 0x0000000EU
788 #define TIM_DMABASE_CCR3 0x0000000FU
789 #define TIM_DMABASE_CCR4 0x00000010U
790 #define TIM_DMABASE_BDTR 0x00000011U
791 #define TIM_DMABASE_DCR 0x00000012U
792 #define TIM_DMABASE_OR 0x00000013U
793 /**
794 * @}
795 */
796
797 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
798 * @{
799 */
800 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
801 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
802 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
803 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
804 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
805 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
806 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
807 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
808 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
809 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
810 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
811 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
812 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
813 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
814 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
815 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
816 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
817 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
818 /**
819 * @}
820 */
821
822 /** @defgroup DMA_Handle_index DMA Handle index
823 * @{
824 */
825 #define TIM_DMA_ID_UPDATE ((uint16_t)0x0000) /*!< Index of the DMA handle used for Update DMA requests */
826 #define TIM_DMA_ID_CC1 ((uint16_t)0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
827 #define TIM_DMA_ID_CC2 ((uint16_t)0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
828 #define TIM_DMA_ID_CC3 ((uint16_t)0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
829 #define TIM_DMA_ID_CC4 ((uint16_t)0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
830 #define TIM_DMA_ID_COMMUTATION ((uint16_t)0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
831 #define TIM_DMA_ID_TRIGGER ((uint16_t)0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
832 /**
833 * @}
834 */
835
836 /** @defgroup Channel_CC_State Channel CC State
837 * @{
838 */
839 #define TIM_CCx_ENABLE 0x00000001U
840 #define TIM_CCx_DISABLE 0x00000000U
841 #define TIM_CCxN_ENABLE 0x00000004U
842 #define TIM_CCxN_DISABLE 0x00000000U
843 /**
844 * @}
845 */
846
847 /**
848 * @}
849 */
850
851 /* Exported macro ------------------------------------------------------------*/
852 /** @defgroup TIM_Exported_Macros TIM Exported Macros
853 * @{
854 */
855 /** @brief Reset TIM handle state
856 * @param __HANDLE__: TIM handle
857 * @retval None
858 */
859 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
860
861 /**
862 * @brief Enable the TIM peripheral.
863 * @param __HANDLE__: TIM handle
864 * @retval None
865 */
866 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
867
868 /**
869 * @brief Enable the TIM main Output.
870 * @param __HANDLE__: TIM handle
871 * @retval None
872 */
873 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
874
875
876 /**
877 * @brief Disable the TIM peripheral.
878 * @param __HANDLE__: TIM handle
879 * @retval None
880 */
881 #define __HAL_TIM_DISABLE(__HANDLE__) \
882 do { \
883 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
884 { \
885 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
886 { \
887 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
888 } \
889 } \
890 } while(0U)
891
892 /* The Main Output of a timer instance is disabled only if all the CCx and CCxN
893 channels have been disabled */
894 /**
895 * @brief Disable the TIM main Output.
896 * @param __HANDLE__: TIM handle
897 * @retval None
898 */
899 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
900 do { \
901 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
902 { \
903 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
904 { \
905 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
906 } \
907 } \
908 } while(0U)
909
910 /**
911 * @brief Disable the TIM main Output.
912 * @param __HANDLE__: TIM handle
913 * @retval None
914 * @note The Main Output Enable of a timer instance is disabled unconditionally
915 */
916 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
917
918 /** @brief Enable the specified TIM interrupt.
919 * @param __HANDLE__: specifies the TIM Handle.
920 * @param __INTERRUPT__: specifies the TIM interrupt source to enable.
921 * This parameter can be one of the following values:
922 * @arg TIM_IT_UPDATE: Update interrupt
923 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
924 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
925 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
926 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
927 * @arg TIM_IT_COM: Commutation interrupt
928 * @arg TIM_IT_TRIGGER: Trigger interrupt
929 * @arg TIM_IT_BREAK: Break interrupt
930 * @retval None
931 */
932 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
933
934
935 /** @brief Disable the specified TIM interrupt.
936 * @param __HANDLE__: specifies the TIM Handle.
937 * @param __INTERRUPT__: specifies the TIM interrupt source to disable.
938 * This parameter can be one of the following values:
939 * @arg TIM_IT_UPDATE: Update interrupt
940 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
941 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
942 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
943 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
944 * @arg TIM_IT_COM: Commutation interrupt
945 * @arg TIM_IT_TRIGGER: Trigger interrupt
946 * @arg TIM_IT_BREAK: Break interrupt
947 * @retval None
948 */
949 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
950
951 /** @brief Enable the specified DMA request.
952 * @param __HANDLE__: specifies the TIM Handle.
953 * @param __DMA__: specifies the TIM DMA request to enable.
954 * This parameter can be one of the following values:
955 * @arg TIM_DMA_UPDATE: Update DMA request
956 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
957 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
958 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
959 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
960 * @arg TIM_DMA_COM: Commutation DMA request
961 * @arg TIM_DMA_TRIGGER: Trigger DMA request
962 * @retval None
963 */
964 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
965
966 /** @brief Disable the specified DMA request.
967 * @param __HANDLE__: specifies the TIM Handle.
968 * @param __DMA__: specifies the TIM DMA request to disable.
969 * This parameter can be one of the following values:
970 * @arg TIM_DMA_UPDATE: Update DMA request
971 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
972 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
973 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
974 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
975 * @arg TIM_DMA_COM: Commutation DMA request
976 * @arg TIM_DMA_TRIGGER: Trigger DMA request
977 * @retval None
978 */
979 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
980
981 /** @brief Check whether the specified TIM interrupt flag is set or not.
982 * @param __HANDLE__: specifies the TIM Handle.
983 * @param __FLAG__: specifies the TIM interrupt flag to check.
984 * This parameter can be one of the following values:
985 * @arg TIM_FLAG_UPDATE: Update interrupt flag
986 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
987 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
988 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
989 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
990 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
991 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
992 * @arg TIM_FLAG_COM: Commutation interrupt flag
993 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
994 * @arg TIM_FLAG_BREAK: Break interrupt flag
995 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
996 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
997 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
998 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
999 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1000 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1001 * @retval The new state of __FLAG__ (TRUE or FALSE).
1002 */
1003 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1004
1005 /** @brief Clear the specified TIM interrupt flag.
1006 * @param __HANDLE__: specifies the TIM Handle.
1007 * @param __FLAG__: specifies the TIM interrupt flag to clear.
1008 * This parameter can be one of the following values:
1009 * @arg TIM_FLAG_UPDATE: Update interrupt flag
1010 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1011 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1012 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1013 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1014 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
1015 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
1016 * @arg TIM_FLAG_COM: Commutation interrupt flag
1017 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1018 * @arg TIM_FLAG_BREAK: Break interrupt flag
1019 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
1020 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
1021 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1022 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1023 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1024 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1025 * @retval The new state of __FLAG__ (TRUE or FALSE).
1026 */
1027 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1028
1029 /**
1030 * @brief Check whether the specified TIM interrupt source is enabled or not.
1031 * @param __HANDLE__: TIM handle
1032 * @param __INTERRUPT__: specifies the TIM interrupt source to check.
1033 * This parameter can be one of the following values:
1034 * @arg TIM_IT_UPDATE: Update interrupt
1035 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1036 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1037 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1038 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1039 * @arg TIM_IT_COM: Commutation interrupt
1040 * @arg TIM_IT_TRIGGER: Trigger interrupt
1041 * @arg TIM_IT_BREAK: Break interrupt
1042 * @retval The state of TIM_IT (SET or RESET).
1043 */
1044 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
1045
1046 /** @brief Clear the TIM interrupt pending bits.
1047 * @param __HANDLE__: TIM handle
1048 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
1049 * This parameter can be one of the following values:
1050 * @arg TIM_IT_UPDATE: Update interrupt
1051 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1052 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1053 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1054 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1055 * @arg TIM_IT_COM: Commutation interrupt
1056 * @arg TIM_IT_TRIGGER: Trigger interrupt
1057 * @arg TIM_IT_BREAK: Break interrupt
1058 * @retval None
1059 */
1060 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1061
1062 /**
1063 * @brief Indicates whether or not the TIM Counter is used as downcounter.
1064 * @param __HANDLE__: TIM handle.
1065 * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
1066 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
1067 mode.
1068 */
1069 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
1070
1071 /**
1072 * @brief Set the TIM Prescaler on runtime.
1073 * @param __HANDLE__: TIM handle.
1074 * @param __PRESC__: specifies the Prescaler new value.
1075 * @retval None
1076 */
1077 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1078
1079 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
1080 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
1081 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
1082 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
1083 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
1084
1085 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
1086 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
1087 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
1088 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
1089 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
1090
1091 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1092 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
1093 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
1094 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
1095 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
1096
1097 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
1098 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
1099 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
1100 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
1101 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
1102
1103 /**
1104 * @brief Sets the TIM Capture Compare Register value on runtime without
1105 * calling another time ConfigChannel function.
1106 * @param __HANDLE__: TIM handle.
1107 * @param __CHANNEL__ : TIM Channels to be configured.
1108 * This parameter can be one of the following values:
1109 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1110 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1111 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1112 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1113 * @param __COMPARE__: specifies the Capture Compare register new value.
1114 * @retval None
1115 */
1116 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1117 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
1118
1119 /**
1120 * @brief Gets the TIM Capture Compare Register value on runtime.
1121 * @param __HANDLE__: TIM handle.
1122 * @param __CHANNEL__: TIM Channel associated with the capture compare register
1123 * This parameter can be one of the following values:
1124 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
1125 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
1126 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
1127 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
1128 * @arg TIM_CHANNEL_5: get capture/compare 5 register value
1129 * @arg TIM_CHANNEL_6: get capture/compare 6 register value
1130 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
1131 */
1132 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1133 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
1134
1135 /**
1136 * @brief Sets the TIM Counter Register value on runtime.
1137 * @param __HANDLE__: TIM handle.
1138 * @param __COUNTER__: specifies the Counter register new value.
1139 * @retval None
1140 */
1141 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1142
1143 /**
1144 * @brief Gets the TIM Counter Register value on runtime.
1145 * @param __HANDLE__: TIM handle.
1146 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
1147 */
1148 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
1149
1150 /**
1151 * @brief Sets the TIM Autoreload Register value on runtime without calling
1152 * another time any Init function.
1153 * @param __HANDLE__: TIM handle.
1154 * @param __AUTORELOAD__: specifies the Counter register new value.
1155 * @retval None
1156 */
1157 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1158 do{ \
1159 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1160 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1161 } while(0U)
1162 /**
1163 * @brief Gets the TIM Autoreload Register value on runtime.
1164 * @param __HANDLE__: TIM handle.
1165 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
1166 */
1167 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
1168
1169 /**
1170 * @brief Sets the TIM Clock Division value on runtime without calling another time any Init function.
1171 * @param __HANDLE__: TIM handle.
1172 * @param __CKD__: specifies the clock division value.
1173 * This parameter can be one of the following value:
1174 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1175 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1176 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1177 * @retval None
1178 */
1179 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1180 do{ \
1181 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
1182 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1183 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1184 } while(0U)
1185 /**
1186 * @brief Gets the TIM Clock Division value on runtime.
1187 * @param __HANDLE__: TIM handle.
1188 * @retval The clock division can be one of the following values:
1189 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1190 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1191 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1192 */
1193 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1194
1195 /**
1196 * @brief Sets the TIM Input Capture prescaler on runtime without calling
1197 * another time HAL_TIM_IC_ConfigChannel() function.
1198 * @param __HANDLE__: TIM handle.
1199 * @param __CHANNEL__ : TIM Channels to be configured.
1200 * This parameter can be one of the following values:
1201 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1202 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1203 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1204 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1205 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
1206 * This parameter can be one of the following values:
1207 * @arg TIM_ICPSC_DIV1: no prescaler
1208 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1209 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1210 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1211 * @retval None
1212 */
1213 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1214 do{ \
1215 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1216 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1217 } while(0U)
1218
1219 /**
1220 * @brief Get the TIM Input Capture prescaler on runtime.
1221 * @param __HANDLE__: TIM handle.
1222 * @param __CHANNEL__: TIM Channels to be configured.
1223 * This parameter can be one of the following values:
1224 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1225 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1226 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1227 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1228 * @retval The input capture prescaler can be one of the following values:
1229 * @arg TIM_ICPSC_DIV1: no prescaler
1230 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1231 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1232 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1233 */
1234 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1235 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1236 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
1237 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1238 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
1239
1240 /**
1241 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
1242 * @param __HANDLE__: TIM handle.
1243 * @note When the USR bit of the TIMx_CR1 register is set, only counter
1244 * overflow/underflow generates an update interrupt or DMA request (if
1245 * enabled)
1246 * @retval None
1247 */
1248 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
1249 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
1250
1251 /**
1252 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
1253 * @param __HANDLE__: TIM handle.
1254 * @note When the USR bit of the TIMx_CR1 register is reset, any of the
1255 * following events generate an update interrupt or DMA request (if
1256 * enabled):
1257 * _ Counter overflow/underflow
1258 * _ Setting the UG bit
1259 * _ Update generation through the slave mode controller
1260 * @retval None
1261 */
1262 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
1263 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
1264
1265 /**
1266 * @brief Sets the TIM Capture x input polarity on runtime.
1267 * @param __HANDLE__: TIM handle.
1268 * @param __CHANNEL__: TIM Channels to be configured.
1269 * This parameter can be one of the following values:
1270 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1271 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1272 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1273 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1274 * @param __POLARITY__: Polarity for TIx source
1275 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
1276 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
1277 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
1278 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
1279 * @retval None
1280 */
1281 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1282 do{ \
1283 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1284 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1285 }while(0U)
1286 /**
1287 * @}
1288 */
1289
1290 /* Include TIM HAL Extension module */
1291 #include "stm32f4xx_hal_tim_ex.h"
1292
1293 /* Exported functions --------------------------------------------------------*/
1294 /** @addtogroup TIM_Exported_Functions
1295 * @{
1296 */
1297
1298 /** @addtogroup TIM_Exported_Functions_Group1
1299 * @{
1300 */
1301
1302 /* Time Base functions ********************************************************/
1303 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
1304 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
1305 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
1306 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
1307 /* Blocking mode: Polling */
1308 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
1309 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
1310 /* Non-Blocking mode: Interrupt */
1311 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
1312 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
1313 /* Non-Blocking mode: DMA */
1314 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
1315 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
1316 /**
1317 * @}
1318 */
1319
1320 /** @addtogroup TIM_Exported_Functions_Group2
1321 * @{
1322 */
1323 /* Timer Output Compare functions **********************************************/
1324 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
1325 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
1326 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
1327 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
1328 /* Blocking mode: Polling */
1329 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1330 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1331 /* Non-Blocking mode: Interrupt */
1332 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1333 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1334 /* Non-Blocking mode: DMA */
1335 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1336 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1337
1338 /**
1339 * @}
1340 */
1341
1342 /** @addtogroup TIM_Exported_Functions_Group3
1343 * @{
1344 */
1345 /* Timer PWM functions *********************************************************/
1346 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
1347 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
1348 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
1349 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
1350 /* Blocking mode: Polling */
1351 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1352 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1353 /* Non-Blocking mode: Interrupt */
1354 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1355 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1356 /* Non-Blocking mode: DMA */
1357 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1358 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1359
1360 /**
1361 * @}
1362 */
1363
1364 /** @addtogroup TIM_Exported_Functions_Group4
1365 * @{
1366 */
1367 /* Timer Input Capture functions ***********************************************/
1368 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
1369 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
1370 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
1371 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
1372 /* Blocking mode: Polling */
1373 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1374 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1375 /* Non-Blocking mode: Interrupt */
1376 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1377 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1378 /* Non-Blocking mode: DMA */
1379 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1380 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1381
1382 /**
1383 * @}
1384 */
1385
1386 /** @addtogroup TIM_Exported_Functions_Group5
1387 * @{
1388 */
1389 /* Timer One Pulse functions ***************************************************/
1390 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
1391 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
1392 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
1393 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
1394 /* Blocking mode: Polling */
1395 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1396 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1397
1398 /* Non-Blocking mode: Interrupt */
1399 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1400 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1401
1402 /**
1403 * @}
1404 */
1405
1406 /** @addtogroup TIM_Exported_Functions_Group6
1407 * @{
1408 */
1409 /* Timer Encoder functions *****************************************************/
1410 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
1411 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
1412 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
1413 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
1414 /* Blocking mode: Polling */
1415 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1416 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1417 /* Non-Blocking mode: Interrupt */
1418 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1419 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1420 /* Non-Blocking mode: DMA */
1421 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
1422 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1423
1424 /**
1425 * @}
1426 */
1427
1428 /** @addtogroup TIM_Exported_Functions_Group7
1429 * @{
1430 */
1431 /* Interrupt Handler functions **********************************************/
1432 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
1433
1434 /**
1435 * @}
1436 */
1437
1438 /** @addtogroup TIM_Exported_Functions_Group8
1439 * @{
1440 */
1441 /* Control functions *********************************************************/
1442 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1443 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1444 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
1445 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
1446 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
1447 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
1448 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
1449 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1450 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1451 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1452 uint32_t *BurstBuffer, uint32_t BurstLength);
1453 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1454 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1455 uint32_t *BurstBuffer, uint32_t BurstLength);
1456 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1457 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
1458 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
1459
1460 /**
1461 * @}
1462 */
1463
1464 /** @addtogroup TIM_Exported_Functions_Group9
1465 * @{
1466 */
1467 /* Callback in non blocking modes (Interrupt and DMA) *************************/
1468 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
1469 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
1470 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
1471 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
1472 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
1473 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
1474
1475 /**
1476 * @}
1477 */
1478
1479 /** @addtogroup TIM_Exported_Functions_Group10
1480 * @{
1481 */
1482 /* Peripheral State functions **************************************************/
1483 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
1484 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
1485 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
1486 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
1487 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
1488 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
1489
1490 /**
1491 * @}
1492 */
1493
1494 /**
1495 * @}
1496 */
1497
1498 /* Private macros ------------------------------------------------------------*/
1499 /** @defgroup TIM_Private_Macros TIM Private Macros
1500 * @{
1501 */
1502
1503 /** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
1504 * @{
1505 */
1506 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
1507 ((MODE) == TIM_COUNTERMODE_DOWN) || \
1508 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
1509 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
1510 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
1511
1512 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
1513 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
1514 ((DIV) == TIM_CLOCKDIVISION_DIV4))
1515
1516 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
1517 ((MODE) == TIM_OCMODE_PWM2))
1518
1519 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
1520 ((MODE) == TIM_OCMODE_ACTIVE) || \
1521 ((MODE) == TIM_OCMODE_INACTIVE) || \
1522 ((MODE) == TIM_OCMODE_TOGGLE) || \
1523 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
1524 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
1525
1526 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
1527 ((STATE) == TIM_OCFAST_ENABLE))
1528
1529 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
1530 ((POLARITY) == TIM_OCPOLARITY_LOW))
1531
1532 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
1533 ((POLARITY) == TIM_OCNPOLARITY_LOW))
1534
1535 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
1536 ((STATE) == TIM_OCIDLESTATE_RESET))
1537
1538 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
1539 ((STATE) == TIM_OCNIDLESTATE_RESET))
1540
1541 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
1542 ((CHANNEL) == TIM_CHANNEL_2) || \
1543 ((CHANNEL) == TIM_CHANNEL_3) || \
1544 ((CHANNEL) == TIM_CHANNEL_4) || \
1545 ((CHANNEL) == TIM_CHANNEL_ALL))
1546
1547 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
1548 ((CHANNEL) == TIM_CHANNEL_2))
1549
1550 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
1551 ((CHANNEL) == TIM_CHANNEL_2) || \
1552 ((CHANNEL) == TIM_CHANNEL_3))
1553
1554 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
1555 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
1556 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
1557
1558 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
1559 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
1560 ((SELECTION) == TIM_ICSELECTION_TRC))
1561
1562 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
1563 ((PRESCALER) == TIM_ICPSC_DIV2) || \
1564 ((PRESCALER) == TIM_ICPSC_DIV4) || \
1565 ((PRESCALER) == TIM_ICPSC_DIV8))
1566
1567 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
1568 ((MODE) == TIM_OPMODE_REPETITIVE))
1569
1570 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
1571
1572 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
1573 ((MODE) == TIM_ENCODERMODE_TI2) || \
1574 ((MODE) == TIM_ENCODERMODE_TI12))
1575
1576 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
1577
1578 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
1579 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
1580 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
1581 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
1582 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
1583 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
1584 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
1585 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
1586 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
1587 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
1588
1589 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
1590 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
1591 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
1592 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
1593 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
1594
1595 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
1596 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
1597 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
1598 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
1599
1600 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
1601
1602 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
1603 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
1604
1605 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
1606 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1607
1608 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
1609 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
1610 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
1611 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
1612
1613 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
1614
1615 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
1616 ((STATE) == TIM_OSSR_DISABLE))
1617
1618 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
1619 ((STATE) == TIM_OSSI_DISABLE))
1620
1621 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
1622 ((LEVEL) == TIM_LOCKLEVEL_1) || \
1623 ((LEVEL) == TIM_LOCKLEVEL_2) || \
1624 ((LEVEL) == TIM_LOCKLEVEL_3))
1625
1626 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
1627 ((STATE) == TIM_BREAK_DISABLE))
1628
1629 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
1630 ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
1631
1632 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
1633 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
1634
1635 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
1636 ((SOURCE) == TIM_TRGO_ENABLE) || \
1637 ((SOURCE) == TIM_TRGO_UPDATE) || \
1638 ((SOURCE) == TIM_TRGO_OC1) || \
1639 ((SOURCE) == TIM_TRGO_OC1REF) || \
1640 ((SOURCE) == TIM_TRGO_OC2REF) || \
1641 ((SOURCE) == TIM_TRGO_OC3REF) || \
1642 ((SOURCE) == TIM_TRGO_OC4REF))
1643
1644 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
1645 ((MODE) == TIM_SLAVEMODE_GATED) || \
1646 ((MODE) == TIM_SLAVEMODE_RESET) || \
1647 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
1648 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
1649
1650 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
1651 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
1652
1653 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
1654 ((SELECTION) == TIM_TS_ITR1) || \
1655 ((SELECTION) == TIM_TS_ITR2) || \
1656 ((SELECTION) == TIM_TS_ITR3) || \
1657 ((SELECTION) == TIM_TS_TI1F_ED) || \
1658 ((SELECTION) == TIM_TS_TI1FP1) || \
1659 ((SELECTION) == TIM_TS_TI2FP2) || \
1660 ((SELECTION) == TIM_TS_ETRF))
1661
1662 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
1663 ((SELECTION) == TIM_TS_ITR1) || \
1664 ((SELECTION) == TIM_TS_ITR2) || \
1665 ((SELECTION) == TIM_TS_ITR3) || \
1666 ((SELECTION) == TIM_TS_NONE))
1667
1668 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
1669 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
1670 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
1671 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
1672 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
1673
1674 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
1675 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
1676 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
1677 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
1678
1679 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
1680
1681 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
1682 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
1683
1684 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
1685 ((BASE) == TIM_DMABASE_CR2) || \
1686 ((BASE) == TIM_DMABASE_SMCR) || \
1687 ((BASE) == TIM_DMABASE_DIER) || \
1688 ((BASE) == TIM_DMABASE_SR) || \
1689 ((BASE) == TIM_DMABASE_EGR) || \
1690 ((BASE) == TIM_DMABASE_CCMR1) || \
1691 ((BASE) == TIM_DMABASE_CCMR2) || \
1692 ((BASE) == TIM_DMABASE_CCER) || \
1693 ((BASE) == TIM_DMABASE_CNT) || \
1694 ((BASE) == TIM_DMABASE_PSC) || \
1695 ((BASE) == TIM_DMABASE_ARR) || \
1696 ((BASE) == TIM_DMABASE_RCR) || \
1697 ((BASE) == TIM_DMABASE_CCR1) || \
1698 ((BASE) == TIM_DMABASE_CCR2) || \
1699 ((BASE) == TIM_DMABASE_CCR3) || \
1700 ((BASE) == TIM_DMABASE_CCR4) || \
1701 ((BASE) == TIM_DMABASE_BDTR) || \
1702 ((BASE) == TIM_DMABASE_DCR) || \
1703 ((BASE) == TIM_DMABASE_OR))
1704
1705 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
1706 ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
1707 ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
1708 ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
1709 ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
1710 ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
1711 ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
1712 ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
1713 ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
1714 ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
1715 ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
1716 ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
1717 ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
1718 ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
1719 ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
1720 ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
1721 ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
1722 ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
1723
1724 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
1725 /**
1726 * @}
1727 */
1728
1729 /** @defgroup TIM_Mask_Definitions TIM Mask Definition
1730 * @{
1731 */
1732 /* The counter of a timer instance is disabled only if all the CCx and CCxN
1733 channels have been disabled */
1734 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1735 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
1736 /**
1737 * @}
1738 */
1739
1740 /**
1741 * @}
1742 */
1743
1744 /* Private functions ---------------------------------------------------------*/
1745 /** @defgroup TIM_Private_Functions TIM Private Functions
1746 * @{
1747 */
1748 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
1749 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
1750 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1751 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
1752 void TIM_DMAError(DMA_HandleTypeDef *hdma);
1753 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
1754 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
1755 /**
1756 * @}
1757 */
1758
1759 /**
1760 * @}
1761 */
1762
1763 /**
1764 * @}
1765 */
1766
1767 #ifdef __cplusplus
1768 }
1769 #endif
1770
1771 #endif /* __STM32F4xx_HAL_TIM_H */
1772
1773 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/