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Merge pull request #11198 from SteveCEvans/sce_rc2
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_HAL_Driver / Inc / stm32f4xx_ll_bus.h
blobb90e75a1fdd2cb219372c1608ab2982a13c48f38
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_bus.h
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 14-April-2017
7 * @brief Header file of BUS LL module.
8
9 @verbatim
10 ##### RCC Limitations #####
11 ==============================================================================
12 [..]
13 A delay between an RCC peripheral clock enable and the effective peripheral
14 enabling should be taken into account in order to manage the peripheral read/write
15 from/to registers.
16 (+) This delay depends on the peripheral mapping.
17 (++) AHB & APB peripherals, 1 dummy read is necessary
18
19 [..]
20 Workarounds:
21 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
22 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
23
24 @endverbatim
25 ******************************************************************************
26 * @attention
27 *
28 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
29 *
30 * Redistribution and use in source and binary forms, with or without modification,
31 * are permitted provided that the following conditions are met:
32 * 1. Redistributions of source code must retain the above copyright notice,
33 * this list of conditions and the following disclaimer.
34 * 2. Redistributions in binary form must reproduce the above copyright notice,
35 * this list of conditions and the following disclaimer in the documentation
36 * and/or other materials provided with the distribution.
37 * 3. Neither the name of STMicroelectronics nor the names of its contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
40 *
41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
44 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
48 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 *
52 ******************************************************************************
53 */
54
55 /* Define to prevent recursive inclusion -------------------------------------*/
56 #ifndef __STM32F4xx_LL_BUS_H
57 #define __STM32F4xx_LL_BUS_H
58
59 #ifdef __cplusplus
60 extern "C" {
61 #endif
62
63 /* Includes ------------------------------------------------------------------*/
64 #include "stm32f4xx.h"
65
66 /** @addtogroup STM32F4xx_LL_Driver
67 * @{
68 */
69
70 #if defined(RCC)
71
72 /** @defgroup BUS_LL BUS
73 * @{
74 */
75
76 /* Private types -------------------------------------------------------------*/
77 /* Private variables ---------------------------------------------------------*/
78 /* Private constants ---------------------------------------------------------*/
79 /* Private macros ------------------------------------------------------------*/
80 /* Exported types ------------------------------------------------------------*/
81 /* Exported constants --------------------------------------------------------*/
82 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
83 * @{
84 */
85
86 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
87 * @{
88 */
89 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
90 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN
91 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN
92 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN
93 #if defined(GPIOD)
94 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN
95 #endif /* GPIOD */
96 #if defined(GPIOE)
97 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN
98 #endif /* GPIOE */
99 #if defined(GPIOF)
100 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN
101 #endif /* GPIOF */
102 #if defined(GPIOG)
103 #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN
104 #endif /* GPIOG */
105 #if defined(GPIOH)
106 #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN
107 #endif /* GPIOH */
108 #if defined(GPIOI)
109 #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN
110 #endif /* GPIOI */
111 #if defined(GPIOJ)
112 #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN
113 #endif /* GPIOJ */
114 #if defined(GPIOK)
115 #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN
116 #endif /* GPIOK */
117 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
118 #if defined(RCC_AHB1ENR_BKPSRAMEN)
119 #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN
120 #endif /* RCC_AHB1ENR_BKPSRAMEN */
121 #if defined(RCC_AHB1ENR_CCMDATARAMEN)
122 #define LL_AHB1_GRP1_PERIPH_CCMDATARAM RCC_AHB1ENR_CCMDATARAMEN
123 #endif /* RCC_AHB1ENR_CCMDATARAMEN */
124 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
125 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
126 #if defined(RCC_AHB1ENR_RNGEN)
127 #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHB1ENR_RNGEN
128 #endif /* RCC_AHB1ENR_RNGEN */
129 #if defined(DMA2D)
130 #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
131 #endif /* DMA2D */
132 #if defined(ETH)
133 #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN
134 #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN
135 #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN
136 #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN
137 #endif /* ETH */
138 #if defined(USB_OTG_HS)
139 #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN
140 #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN
141 #endif /* USB_OTG_HS */
142 #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN
143 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN
144 #if defined(RCC_AHB1LPENR_SRAM2LPEN)
145 #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN
146 #endif /* RCC_AHB1LPENR_SRAM2LPEN */
147 #if defined(RCC_AHB1LPENR_SRAM3LPEN)
148 #define LL_AHB1_GRP1_PERIPH_SRAM3 RCC_AHB1LPENR_SRAM3LPEN
149 #endif /* RCC_AHB1LPENR_SRAM3LPEN */
150 /**
151 * @}
152 */
153
154 #if defined(RCC_AHB2_SUPPORT)
155 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
156 * @{
157 */
158 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
159 #if defined(DCMI)
160 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
161 #endif /* DCMI */
162 #if defined(CRYP)
163 #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
164 #endif /* CRYP */
165 #if defined(AES)
166 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
167 #endif /* AES */
168 #if defined(HASH)
169 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
170 #endif /* HASH */
171 #if defined(RCC_AHB2ENR_RNGEN)
172 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
173 #endif /* RCC_AHB2ENR_RNGEN */
174 #if defined(USB_OTG_FS)
175 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
176 #endif /* USB_OTG_FS */
177 /**
178 * @}
179 */
180 #endif /* RCC_AHB2_SUPPORT */
181
182 #if defined(RCC_AHB3_SUPPORT)
183 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
184 * @{
185 */
186 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
187 #if defined(FSMC_Bank1)
188 #define LL_AHB3_GRP1_PERIPH_FSMC RCC_AHB3ENR_FSMCEN
189 #endif /* FSMC_Bank1 */
190 #if defined(FMC_Bank1)
191 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
192 #endif /* FMC_Bank1 */
193 #if defined(QUADSPI)
194 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
195 #endif /* QUADSPI */
196 /**
197 * @}
198 */
199 #endif /* RCC_AHB3_SUPPORT */
200
201 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
202 * @{
203 */
204 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
205 #if defined(TIM2)
206 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
207 #endif /* TIM2 */
208 #if defined(TIM3)
209 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
210 #endif /* TIM3 */
211 #if defined(TIM4)
212 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
213 #endif /* TIM4 */
214 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
215 #if defined(TIM6)
216 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
217 #endif /* TIM6 */
218 #if defined(TIM7)
219 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
220 #endif /* TIM7 */
221 #if defined(TIM12)
222 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
223 #endif /* TIM12 */
224 #if defined(TIM13)
225 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
226 #endif /* TIM13 */
227 #if defined(TIM14)
228 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
229 #endif /* TIM14 */
230 #if defined(LPTIM1)
231 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN
232 #endif /* LPTIM1 */
233 #if defined(RCC_APB1ENR_RTCAPBEN)
234 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCAPBEN
235 #endif /* RCC_APB1ENR_RTCAPBEN */
236 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
237 #if defined(SPI2)
238 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
239 #endif /* SPI2 */
240 #if defined(SPI3)
241 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
242 #endif /* SPI3 */
243 #if defined(SPDIFRX)
244 #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN
245 #endif /* SPDIFRX */
246 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
247 #if defined(USART3)
248 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
249 #endif /* USART3 */
250 #if defined(UART4)
251 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
252 #endif /* UART4 */
253 #if defined(UART5)
254 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
255 #endif /* UART5 */
256 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
257 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
258 #if defined(I2C3)
259 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
260 #endif /* I2C3 */
261 #if defined(FMPI2C1)
262 #define LL_APB1_GRP1_PERIPH_FMPI2C1 RCC_APB1ENR_FMPI2C1EN
263 #endif /* FMPI2C1 */
264 #if defined(CAN1)
265 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
266 #endif /* CAN1 */
267 #if defined(CAN2)
268 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
269 #endif /* CAN2 */
270 #if defined(CAN3)
271 #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN
272 #endif /* CAN3 */
273 #if defined(CEC)
274 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
275 #endif /* CEC */
276 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
277 #if defined(DAC1)
278 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
279 #endif /* DAC1 */
280 #if defined(UART7)
281 #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN
282 #endif /* UART7 */
283 #if defined(UART8)
284 #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN
285 #endif /* UART8 */
286 /**
287 * @}
288 */
289
290 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
291 * @{
292 */
293 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
294 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
295 #if defined(TIM8)
296 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
297 #endif /* TIM8 */
298 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
299 #if defined(USART6)
300 #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
301 #endif /* USART6 */
302 #if defined(UART9)
303 #define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN
304 #endif /* UART9 */
305 #if defined(UART10)
306 #define LL_APB2_GRP1_PERIPH_UART10 RCC_APB2ENR_UART10EN
307 #endif /* UART10 */
308 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
309 #if defined(ADC2)
310 #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
311 #endif /* ADC2 */
312 #if defined(ADC3)
313 #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
314 #endif /* ADC3 */
315 #if defined(SDIO)
316 #define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN
317 #endif /* SDIO */
318 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
319 #if defined(SPI4)
320 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
321 #endif /* SPI4 */
322 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
323 #if defined(RCC_APB2ENR_EXTITEN)
324 #define LL_APB2_GRP1_PERIPH_EXTI RCC_APB2ENR_EXTITEN
325 #endif /* RCC_APB2ENR_EXTITEN */
326 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
327 #if defined(TIM10)
328 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
329 #endif /* TIM10 */
330 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
331 #if defined(SPI5)
332 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
333 #endif /* SPI5 */
334 #if defined(SPI6)
335 #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN
336 #endif /* SPI6 */
337 #if defined(SAI1)
338 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
339 #endif /* SAI1 */
340 #if defined(SAI2)
341 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
342 #endif /* SAI2 */
343 #if defined(LTDC)
344 #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
345 #endif /* LTDC */
346 #if defined(DSI)
347 #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN
348 #endif /* DSI */
349 #if defined(DFSDM1_Channel0)
350 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
351 #endif /* DFSDM1_Channel0 */
352 #if defined(DFSDM2_Channel0)
353 #define LL_APB2_GRP1_PERIPH_DFSDM2 RCC_APB2ENR_DFSDM2EN
354 #endif /* DFSDM2_Channel0 */
355 #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST
356 /**
357 * @}
358 */
359
360 /**
361 * @}
362 */
363
364 /* Exported macro ------------------------------------------------------------*/
365 /* Exported functions --------------------------------------------------------*/
366 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
367 * @{
368 */
369
370 /** @defgroup BUS_LL_EF_AHB1 AHB1
371 * @{
372 */
373
374 /**
375 * @brief Enable AHB1 peripherals clock.
376 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
377 * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
378 * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
379 * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n
380 * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
381 * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
382 * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
383 * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
384 * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n
385 * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n
386 * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n
387 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
388 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n
389 * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_EnableClock\n
390 * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
391 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
392 * AHB1ENR RNGEN LL_AHB1_GRP1_EnableClock\n
393 * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
394 * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
395 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
396 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
397 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n
398 * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n
399 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock
400 * @param Periphs This parameter can be a combination of the following values:
401 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
402 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
403 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
404 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
405 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
406 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
407 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
408 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
409 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
410 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
411 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
412 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
413 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
414 * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
415 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
416 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
417 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
418 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
419 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
420 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
421 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
422 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
423 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
424 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
425 *
426 * (*) value not defined in all devices.
427 * @retval None
428 */
429 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
430 {
431 __IO uint32_t tmpreg;
432 SET_BIT(RCC->AHB1ENR, Periphs);
433 /* Delay after an RCC peripheral clock enabling */
434 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
435 (void)tmpreg;
436 }
437
438 /**
439 * @brief Check if AHB1 peripheral clock is enabled or not
440 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
441 * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
442 * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
443 * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
444 * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
445 * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
446 * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
447 * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
448 * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n
449 * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n
450 * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n
451 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
452 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n
453 * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_IsEnabledClock\n
454 * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
455 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
456 * AHB1ENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n
457 * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
458 * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
459 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
460 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
461 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n
462 * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
463 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock
464 * @param Periphs This parameter can be a combination of the following values:
465 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
466 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
467 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
468 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
469 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
470 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
471 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
472 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
473 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
474 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
475 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
476 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
477 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
478 * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
479 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
480 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
481 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
482 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
483 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
484 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
485 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
486 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
487 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
488 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
489 *
490 * (*) value not defined in all devices.
491 * @retval State of Periphs (1 or 0).
492 */
493 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
494 {
495 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
496 }
497
498 /**
499 * @brief Disable AHB1 peripherals clock.
500 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
501 * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
502 * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
503 * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n
504 * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
505 * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
506 * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
507 * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
508 * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n
509 * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n
510 * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n
511 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
512 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n
513 * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_DisableClock\n
514 * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
515 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
516 * AHB1ENR RNGEN LL_AHB1_GRP1_DisableClock\n
517 * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
518 * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
519 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
520 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
521 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n
522 * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n
523 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock
524 * @param Periphs This parameter can be a combination of the following values:
525 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
526 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
527 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
528 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
529 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
530 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
531 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
532 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
533 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
534 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
535 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
536 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
537 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
538 * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
539 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
540 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
541 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
542 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
543 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
544 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
545 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
546 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
547 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
548 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
549 *
550 * (*) value not defined in all devices.
551 * @retval None
552 */
553 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
554 {
555 CLEAR_BIT(RCC->AHB1ENR, Periphs);
556 }
557
558 /**
559 * @brief Force AHB1 peripherals reset.
560 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
561 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
562 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
563 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
564 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
565 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
566 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
567 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
568 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n
569 * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n
570 * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n
571 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
572 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
573 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
574 * AHB1RSTR RNGRST LL_AHB1_GRP1_ForceReset\n
575 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n
576 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
577 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset
578 * @param Periphs This parameter can be a combination of the following values:
579 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
580 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
581 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
582 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
583 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
584 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
585 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
586 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
587 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
588 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
589 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
590 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
591 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
592 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
593 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
594 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
595 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
596 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
597 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
598 *
599 * (*) value not defined in all devices.
600 * @retval None
601 */
602 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
603 {
604 SET_BIT(RCC->AHB1RSTR, Periphs);
605 }
606
607 /**
608 * @brief Release AHB1 peripherals reset.
609 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
610 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
611 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
612 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
613 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
614 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
615 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
616 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
617 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n
618 * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n
619 * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n
620 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
621 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
622 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
623 * AHB1RSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n
624 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n
625 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
626 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset
627 * @param Periphs This parameter can be a combination of the following values:
628 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
629 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
630 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
631 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
632 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
633 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
634 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
635 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
636 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
637 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
638 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
639 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
640 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
641 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
642 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
643 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
644 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
645 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
646 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
647 *
648 * (*) value not defined in all devices.
649 * @retval None
650 */
651 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
652 {
653 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
654 }
655
656 /**
657 * @brief Enable AHB1 peripheral clocks in low-power mode
658 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n
659 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n
660 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
661 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n
662 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n
663 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
664 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
665 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n
666 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n
667 * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n
668 * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n
669 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
670 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
671 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
672 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
673 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
674 * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_EnableClockLowPower\n
675 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
676 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
677 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
678 * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n
679 * AHB1LPENR RNGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
680 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n
681 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
682 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
683 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n
684 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n
685 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower
686 * @param Periphs This parameter can be a combination of the following values:
687 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
688 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
689 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
690 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
691 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
692 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
693 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
694 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
695 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
696 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
697 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
698 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
699 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
700 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
701 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
702 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
703 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
704 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
705 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
706 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
707 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
708 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
709 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
710 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
711 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
712 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
713 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
714 *
715 * (*) value not defined in all devices.
716 * @retval None
717 */
718 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
719 {
720 __IO uint32_t tmpreg;
721 SET_BIT(RCC->AHB1LPENR, Periphs);
722 /* Delay after an RCC peripheral clock enabling */
723 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
724 (void)tmpreg;
725 }
726
727 /**
728 * @brief Disable AHB1 peripheral clocks in low-power mode
729 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n
730 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n
731 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
732 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n
733 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n
734 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
735 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
736 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n
737 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n
738 * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n
739 * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n
740 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
741 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
742 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
743 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
744 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
745 * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_DisableClockLowPower\n
746 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
747 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
748 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
749 * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n
750 * AHB1LPENR RNGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
751 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n
752 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
753 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
754 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n
755 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n
756 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower
757 * @param Periphs This parameter can be a combination of the following values:
758 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
759 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
760 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
761 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
762 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
763 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
764 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
765 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
766 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
767 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
768 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
769 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
770 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
771 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
772 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
773 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
774 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
775 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
776 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
777 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
778 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
779 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
780 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
781 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
782 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
783 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
784 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
785 *
786 * (*) value not defined in all devices.
787 * @retval None
788 */
789 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
790 {
791 CLEAR_BIT(RCC->AHB1LPENR, Periphs);
792 }
793
794 /**
795 * @}
796 */
797
798 #if defined(RCC_AHB2_SUPPORT)
799 /** @defgroup BUS_LL_EF_AHB2 AHB2
800 * @{
801 */
802
803 /**
804 * @brief Enable AHB2 peripherals clock.
805 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
806 * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n
807 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
808 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
809 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
810 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock
811 * @param Periphs This parameter can be a combination of the following values:
812 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
813 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
814 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
815 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
816 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
817 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
818 *
819 * (*) value not defined in all devices.
820 * @retval None
821 */
822 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
823 {
824 __IO uint32_t tmpreg;
825 SET_BIT(RCC->AHB2ENR, Periphs);
826 /* Delay after an RCC peripheral clock enabling */
827 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
828 (void)tmpreg;
829 }
830
831 /**
832 * @brief Check if AHB2 peripheral clock is enabled or not
833 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
834 * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n
835 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
836 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
837 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
838 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock
839 * @param Periphs This parameter can be a combination of the following values:
840 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
841 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
842 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
843 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
844 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
845 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
846 *
847 * (*) value not defined in all devices.
848 * @retval State of Periphs (1 or 0).
849 */
850 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
851 {
852 return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
853 }
854
855 /**
856 * @brief Disable AHB2 peripherals clock.
857 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
858 * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n
859 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
860 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
861 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
862 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock
863 * @param Periphs This parameter can be a combination of the following values:
864 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
865 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
866 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
867 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
868 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
869 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
870 *
871 * (*) value not defined in all devices.
872 * @retval None
873 */
874 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
875 {
876 CLEAR_BIT(RCC->AHB2ENR, Periphs);
877 }
878
879 /**
880 * @brief Force AHB2 peripherals reset.
881 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
882 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n
883 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
884 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
885 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
886 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset
887 * @param Periphs This parameter can be a combination of the following values:
888 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
889 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
890 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
891 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
892 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
893 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
894 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
895 *
896 * (*) value not defined in all devices.
897 * @retval None
898 */
899 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
900 {
901 SET_BIT(RCC->AHB2RSTR, Periphs);
902 }
903
904 /**
905 * @brief Release AHB2 peripherals reset.
906 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
907 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n
908 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
909 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
910 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
911 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset
912 * @param Periphs This parameter can be a combination of the following values:
913 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
914 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
915 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
916 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
917 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
918 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
919 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
920 *
921 * (*) value not defined in all devices.
922 * @retval None
923 */
924 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
925 {
926 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
927 }
928
929 /**
930 * @brief Enable AHB2 peripheral clocks in low-power mode
931 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n
932 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n
933 * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n
934 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n
935 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n
936 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower
937 * @param Periphs This parameter can be a combination of the following values:
938 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
939 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
940 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
941 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
942 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
943 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
944 *
945 * (*) value not defined in all devices.
946 * @retval None
947 */
948 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
949 {
950 __IO uint32_t tmpreg;
951 SET_BIT(RCC->AHB2LPENR, Periphs);
952 /* Delay after an RCC peripheral clock enabling */
953 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
954 (void)tmpreg;
955 }
956
957 /**
958 * @brief Disable AHB2 peripheral clocks in low-power mode
959 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n
960 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n
961 * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n
962 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n
963 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n
964 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower
965 * @param Periphs This parameter can be a combination of the following values:
966 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
967 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
968 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
969 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
970 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
971 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
972 *
973 * (*) value not defined in all devices.
974 * @retval None
975 */
976 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
977 {
978 CLEAR_BIT(RCC->AHB2LPENR, Periphs);
979 }
980
981 /**
982 * @}
983 */
984 #endif /* RCC_AHB2_SUPPORT */
985
986 #if defined(RCC_AHB3_SUPPORT)
987 /** @defgroup BUS_LL_EF_AHB3 AHB3
988 * @{
989 */
990
991 /**
992 * @brief Enable AHB3 peripherals clock.
993 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
994 * AHB3ENR FSMCEN LL_AHB3_GRP1_EnableClock\n
995 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
996 * @param Periphs This parameter can be a combination of the following values:
997 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
998 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
999 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1000 *
1001 * (*) value not defined in all devices.
1002 * @retval None
1003 */
1004 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
1005 {
1006 __IO uint32_t tmpreg;
1007 SET_BIT(RCC->AHB3ENR, Periphs);
1008 /* Delay after an RCC peripheral clock enabling */
1009 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
1010 (void)tmpreg;
1011 }
1012
1013 /**
1014 * @brief Check if AHB3 peripheral clock is enabled or not
1015 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
1016 * AHB3ENR FSMCEN LL_AHB3_GRP1_IsEnabledClock\n
1017 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
1018 * @param Periphs This parameter can be a combination of the following values:
1019 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1020 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1021 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1022 *
1023 * (*) value not defined in all devices.
1024 * @retval State of Periphs (1 or 0).
1025 */
1026 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
1027 {
1028 return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
1029 }
1030
1031 /**
1032 * @brief Disable AHB3 peripherals clock.
1033 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
1034 * AHB3ENR FSMCEN LL_AHB3_GRP1_DisableClock\n
1035 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
1036 * @param Periphs This parameter can be a combination of the following values:
1037 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1038 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1039 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1040 *
1041 * (*) value not defined in all devices.
1042 * @retval None
1043 */
1044 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
1045 {
1046 CLEAR_BIT(RCC->AHB3ENR, Periphs);
1047 }
1048
1049 /**
1050 * @brief Force AHB3 peripherals reset.
1051 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
1052 * AHB3RSTR FSMCRST LL_AHB3_GRP1_ForceReset\n
1053 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
1054 * @param Periphs This parameter can be a combination of the following values:
1055 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
1056 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1057 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1058 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1059 *
1060 * (*) value not defined in all devices.
1061 * @retval None
1062 */
1063 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
1064 {
1065 SET_BIT(RCC->AHB3RSTR, Periphs);
1066 }
1067
1068 /**
1069 * @brief Release AHB3 peripherals reset.
1070 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
1071 * AHB3RSTR FSMCRST LL_AHB3_GRP1_ReleaseReset\n
1072 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
1073 * @param Periphs This parameter can be a combination of the following values:
1074 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1075 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1076 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1077 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1078 *
1079 * (*) value not defined in all devices.
1080 * @retval None
1081 */
1082 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
1083 {
1084 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
1085 }
1086
1087 /**
1088 * @brief Enable AHB3 peripheral clocks in low-power mode
1089 * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n
1090 * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n
1091 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower
1092 * @param Periphs This parameter can be a combination of the following values:
1093 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1094 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1095 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1096 *
1097 * (*) value not defined in all devices.
1098 * @retval None
1099 */
1100 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
1101 {
1102 __IO uint32_t tmpreg;
1103 SET_BIT(RCC->AHB3LPENR, Periphs);
1104 /* Delay after an RCC peripheral clock enabling */
1105 tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
1106 (void)tmpreg;
1107 }
1108
1109 /**
1110 * @brief Disable AHB3 peripheral clocks in low-power mode
1111 * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n
1112 * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n
1113 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower
1114 * @param Periphs This parameter can be a combination of the following values:
1115 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1116 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1117 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1118 *
1119 * (*) value not defined in all devices.
1120 * @retval None
1121 */
1122 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
1123 {
1124 CLEAR_BIT(RCC->AHB3LPENR, Periphs);
1125 }
1126
1127 /**
1128 * @}
1129 */
1130 #endif /* RCC_AHB3_SUPPORT */
1131
1132 /** @defgroup BUS_LL_EF_APB1 APB1
1133 * @{
1134 */
1135
1136 /**
1137 * @brief Enable APB1 peripherals clock.
1138 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
1139 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
1140 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
1141 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
1142 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
1143 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
1144 * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
1145 * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
1146 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
1147 * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n
1148 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
1149 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
1150 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
1151 * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n
1152 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
1153 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
1154 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
1155 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
1156 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
1157 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
1158 * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n
1159 * APB1ENR FMPI2C1EN LL_APB1_GRP1_EnableClock\n
1160 * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
1161 * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
1162 * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n
1163 * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
1164 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
1165 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
1166 * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n
1167 * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n
1168 * APB1ENR RTCAPBEN LL_APB1_GRP1_EnableClock
1169 * @param Periphs This parameter can be a combination of the following values:
1170 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1171 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1172 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1173 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1174 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1175 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1176 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1177 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1178 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1179 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1180 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1181 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1182 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1183 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1184 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1185 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1186 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1187 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1188 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1189 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1190 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1191 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1192 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1193 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1194 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1195 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1196 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1197 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1198 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1199 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1200 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1201 *
1202 * (*) value not defined in all devices.
1203 * @retval None
1204 */
1205 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1206 {
1207 __IO uint32_t tmpreg;
1208 SET_BIT(RCC->APB1ENR, Periphs);
1209 /* Delay after an RCC peripheral clock enabling */
1210 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
1211 (void)tmpreg;
1212 }
1213
1214 /**
1215 * @brief Check if APB1 peripheral clock is enabled or not
1216 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
1217 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
1218 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
1219 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
1220 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
1221 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
1222 * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
1223 * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
1224 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
1225 * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n
1226 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
1227 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
1228 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
1229 * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n
1230 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
1231 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
1232 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
1233 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
1234 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
1235 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
1236 * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
1237 * APB1ENR FMPI2C1EN LL_APB1_GRP1_IsEnabledClock\n
1238 * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
1239 * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
1240 * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n
1241 * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
1242 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
1243 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
1244 * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n
1245 * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n
1246 * APB1ENR RTCAPBEN LL_APB1_GRP1_IsEnabledClock
1247 * @param Periphs This parameter can be a combination of the following values:
1248 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1249 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1250 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1251 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1252 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1253 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1254 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1255 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1256 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1257 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1258 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1259 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1260 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1261 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1262 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1263 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1264 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1265 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1266 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1267 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1268 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1269 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1270 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1271 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1272 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1273 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1274 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1275 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1276 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1277 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1278 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1279 *
1280 * (*) value not defined in all devices.
1281 * @retval State of Periphs (1 or 0).
1282 */
1283 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1284 {
1285 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
1286 }
1287
1288 /**
1289 * @brief Disable APB1 peripherals clock.
1290 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
1291 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
1292 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
1293 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
1294 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
1295 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
1296 * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
1297 * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
1298 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
1299 * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n
1300 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
1301 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
1302 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
1303 * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n
1304 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
1305 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
1306 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
1307 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
1308 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
1309 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
1310 * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n
1311 * APB1ENR FMPI2C1EN LL_APB1_GRP1_DisableClock\n
1312 * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
1313 * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
1314 * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n
1315 * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
1316 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
1317 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
1318 * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n
1319 * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n
1320 * APB1ENR RTCAPBEN LL_APB1_GRP1_DisableClock
1321 * @param Periphs This parameter can be a combination of the following values:
1322 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1323 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1324 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1325 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1326 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1327 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1328 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1329 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1330 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1331 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1332 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1333 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1334 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1335 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1336 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1337 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1338 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1339 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1340 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1341 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1342 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1343 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1344 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1345 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1346 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1347 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1348 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1349 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1350 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1351 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1352 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1353 *
1354 * (*) value not defined in all devices.
1355 * @retval None
1356 */
1357 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1358 {
1359 CLEAR_BIT(RCC->APB1ENR, Periphs);
1360 }
1361
1362 /**
1363 * @brief Force APB1 peripherals reset.
1364 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
1365 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
1366 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
1367 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
1368 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
1369 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
1370 * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
1371 * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
1372 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
1373 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n
1374 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
1375 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
1376 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
1377 * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n
1378 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
1379 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
1380 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
1381 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
1382 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
1383 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
1384 * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n
1385 * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ForceReset\n
1386 * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
1387 * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
1388 * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n
1389 * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
1390 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
1391 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
1392 * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n
1393 * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset
1394 * @param Periphs This parameter can be a combination of the following values:
1395 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1396 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1397 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1398 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1399 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1400 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1401 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1402 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1403 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1404 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1405 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1406 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1407 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1408 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1409 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1410 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1411 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1412 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1413 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1414 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1415 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1416 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1417 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1418 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1419 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1420 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1421 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1422 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1423 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1424 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1425 *
1426 * (*) value not defined in all devices.
1427 * @retval None
1428 */
1429 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1430 {
1431 SET_BIT(RCC->APB1RSTR, Periphs);
1432 }
1433
1434 /**
1435 * @brief Release APB1 peripherals reset.
1436 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
1437 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
1438 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
1439 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
1440 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
1441 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
1442 * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
1443 * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
1444 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
1445 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n
1446 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
1447 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
1448 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
1449 * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n
1450 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
1451 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
1452 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
1453 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
1454 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
1455 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
1456 * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
1457 * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ReleaseReset\n
1458 * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
1459 * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
1460 * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n
1461 * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
1462 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
1463 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
1464 * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n
1465 * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset
1466 * @param Periphs This parameter can be a combination of the following values:
1467 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1468 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1469 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1470 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1471 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1472 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1473 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1474 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1475 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1476 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1477 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1478 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1479 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1480 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1481 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1482 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1483 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1484 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1485 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1486 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1487 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1488 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1489 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1490 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1491 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1492 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1493 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1494 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1495 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1496 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1497 *
1498 * (*) value not defined in all devices.
1499 * @retval None
1500 */
1501 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1502 {
1503 CLEAR_BIT(RCC->APB1RSTR, Periphs);
1504 }
1505
1506 /**
1507 * @brief Enable APB1 peripheral clocks in low-power mode
1508 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1509 * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1510 * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1511 * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n
1512 * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n
1513 * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n
1514 * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n
1515 * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n
1516 * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n
1517 * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1518 * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n
1519 * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1520 * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1521 * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n
1522 * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1523 * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1524 * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1525 * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n
1526 * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1527 * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1528 * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1529 * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1530 * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1531 * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1532 * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1533 * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n
1534 * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n
1535 * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n
1536 * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n
1537 * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n
1538 * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_EnableClockLowPower
1539 * @param Periphs This parameter can be a combination of the following values:
1540 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1541 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1542 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1543 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1544 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1545 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1546 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1547 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1548 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1549 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1550 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1551 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1552 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1553 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1554 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1555 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1556 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1557 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1558 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1559 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1560 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1561 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1562 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1563 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1564 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1565 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1566 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1567 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1568 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1569 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1570 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1571 *
1572 * (*) value not defined in all devices.
1573 * @retval None
1574 */
1575 __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
1576 {
1577 __IO uint32_t tmpreg;
1578 SET_BIT(RCC->APB1LPENR, Periphs);
1579 /* Delay after an RCC peripheral clock enabling */
1580 tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
1581 (void)tmpreg;
1582 }
1583
1584 /**
1585 * @brief Disable APB1 peripheral clocks in low-power mode
1586 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1587 * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1588 * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1589 * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n
1590 * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n
1591 * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n
1592 * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n
1593 * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n
1594 * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n
1595 * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1596 * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n
1597 * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1598 * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1599 * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n
1600 * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1601 * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1602 * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1603 * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n
1604 * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1605 * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1606 * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1607 * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1608 * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1609 * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1610 * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1611 * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n
1612 * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n
1613 * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n
1614 * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n
1615 * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n
1616 * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_DisableClockLowPower
1617 * @param Periphs This parameter can be a combination of the following values:
1618 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1619 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1620 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1621 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1622 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1623 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1624 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1625 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1626 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1627 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1628 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1629 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1630 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1631 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1632 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1633 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1634 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1635 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1636 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1637 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1638 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1639 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1640 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1641 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1642 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1643 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1644 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1645 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1646 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1647 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1648 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1649 *
1650 * (*) value not defined in all devices.
1651 * @retval None
1652 */
1653 __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
1654 {
1655 CLEAR_BIT(RCC->APB1LPENR, Periphs);
1656 }
1657
1658 /**
1659 * @}
1660 */
1661
1662 /** @defgroup BUS_LL_EF_APB2 APB2
1663 * @{
1664 */
1665
1666 /**
1667 * @brief Enable APB2 peripherals clock.
1668 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1669 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
1670 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1671 * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n
1672 * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n
1673 * APB2ENR UART10EN LL_APB2_GRP1_EnableClock\n
1674 * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
1675 * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
1676 * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
1677 * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n
1678 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1679 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
1680 * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
1681 * APB2ENR EXTITEN LL_APB2_GRP1_EnableClock\n
1682 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
1683 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
1684 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
1685 * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n
1686 * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n
1687 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
1688 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
1689 * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
1690 * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n
1691 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
1692 * APB2ENR DFSDM2EN LL_APB2_GRP1_EnableClock
1693 * @param Periphs This parameter can be a combination of the following values:
1694 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1695 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1696 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1697 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1698 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1699 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1700 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1701 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
1702 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
1703 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1704 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1705 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1706 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1707 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
1708 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1709 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1710 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1711 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1712 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1713 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1714 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1715 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1716 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1717 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1718 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1719
1720 *
1721 * (*) value not defined in all devices.
1722 * @retval None
1723 */
1724 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1725 {
1726 __IO uint32_t tmpreg;
1727 SET_BIT(RCC->APB2ENR, Periphs);
1728 /* Delay after an RCC peripheral clock enabling */
1729 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1730 (void)tmpreg;
1731 }
1732
1733 /**
1734 * @brief Check if APB2 peripheral clock is enabled or not
1735 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1736 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
1737 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1738 * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n
1739 * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n
1740 * APB2ENR UART10EN LL_APB2_GRP1_IsEnabledClock\n
1741 * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
1742 * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
1743 * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
1744 * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n
1745 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1746 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
1747 * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
1748 * APB2ENR EXTITEN LL_APB2_GRP1_IsEnabledClock\n
1749 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
1750 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
1751 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
1752 * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n
1753 * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n
1754 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
1755 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
1756 * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
1757 * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n
1758 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
1759 * APB2ENR DFSDM2EN LL_APB2_GRP1_IsEnabledClock
1760 * @param Periphs This parameter can be a combination of the following values:
1761 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1762 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1763 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1764 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1765 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1766 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1767 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1768 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
1769 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
1770 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1771 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1772 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1773 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1774 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
1775 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1776 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1777 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1778 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1779 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1780 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1781 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1782 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1783 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1784 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1785 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1786 *
1787 * (*) value not defined in all devices.
1788 * @retval State of Periphs (1 or 0).
1789 */
1790 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1791 {
1792 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
1793 }
1794
1795 /**
1796 * @brief Disable APB2 peripherals clock.
1797 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1798 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
1799 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1800 * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n
1801 * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n
1802 * APB2ENR UART10EN LL_APB2_GRP1_DisableClock\n
1803 * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
1804 * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
1805 * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
1806 * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n
1807 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1808 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
1809 * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
1810 * APB2ENR EXTITEN LL_APB2_GRP1_DisableClock\n
1811 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
1812 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
1813 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
1814 * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n
1815 * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n
1816 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
1817 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
1818 * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
1819 * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n
1820 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
1821 * APB2ENR DFSDM2EN LL_APB2_GRP1_DisableClock
1822 * @param Periphs This parameter can be a combination of the following values:
1823 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1824 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1825 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1826 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1827 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1828 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1829 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1830 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
1831 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
1832 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1833 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1834 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1835 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1836 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
1837 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1838 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1839 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1840 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1841 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1842 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1843 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1844 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1845 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1846 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1847 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1848 *
1849 * (*) value not defined in all devices.
1850 * @retval None
1851 */
1852 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1853 {
1854 CLEAR_BIT(RCC->APB2ENR, Periphs);
1855 }
1856
1857 /**
1858 * @brief Force APB2 peripherals reset.
1859 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1860 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
1861 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1862 * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n
1863 * APB2RSTR UART9RST LL_APB2_GRP1_ForceReset\n
1864 * APB2RSTR UART10RST LL_APB2_GRP1_ForceReset\n
1865 * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n
1866 * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n
1867 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1868 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
1869 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
1870 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
1871 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
1872 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
1873 * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n
1874 * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n
1875 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
1876 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
1877 * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
1878 * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n
1879 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
1880 * APB2RSTR DFSDM2RST LL_APB2_GRP1_ForceReset
1881 * @param Periphs This parameter can be a combination of the following values:
1882 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1883 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1884 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1885 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1886 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1887 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1888 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1889 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1890 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1891 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1892 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1893 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1894 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1895 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1896 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1897 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1898 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1899 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1900 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1901 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1902 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1903 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1904 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1905 *
1906 * (*) value not defined in all devices.
1907 * @retval None
1908 */
1909 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1910 {
1911 SET_BIT(RCC->APB2RSTR, Periphs);
1912 }
1913
1914 /**
1915 * @brief Release APB2 peripherals reset.
1916 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
1917 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
1918 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
1919 * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n
1920 * APB2RSTR UART9RST LL_APB2_GRP1_ReleaseReset\n
1921 * APB2RSTR UART10RST LL_APB2_GRP1_ReleaseReset\n
1922 * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n
1923 * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n
1924 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
1925 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
1926 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
1927 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
1928 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
1929 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
1930 * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n
1931 * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n
1932 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
1933 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
1934 * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
1935 * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n
1936 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
1937 * APB2RSTR DFSDM2RST LL_APB2_GRP1_ReleaseReset
1938 * @param Periphs This parameter can be a combination of the following values:
1939 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1940 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1941 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1942 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1943 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1944 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1945 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1946 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1947 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1948 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1949 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1950 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1951 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
1952 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1953 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1954 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1955 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1956 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1957 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1958 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1959 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1960 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1961 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1962 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1963 *
1964 * (*) value not defined in all devices.
1965 * @retval None
1966 */
1967 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1968 {
1969 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1970 }
1971
1972 /**
1973 * @brief Enable APB2 peripheral clocks in low-power mode
1974 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1975 * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n
1976 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1977 * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n
1978 * APB2LPENR UART9LPEN LL_APB2_GRP1_EnableClockLowPower\n
1979 * APB2LPENR UART10LPEN LL_APB2_GRP1_EnableClockLowPower\n
1980 * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1981 * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n
1982 * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n
1983 * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockLowPower\n
1984 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1985 * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n
1986 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n
1987 * APB2LPENR EXTITLPEN LL_APB2_GRP1_EnableClockLowPower\n
1988 * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n
1989 * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n
1990 * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n
1991 * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n
1992 * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n
1993 * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1994 * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n
1995 * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n
1996 * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n
1997 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1998 * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n
1999 * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_EnableClockLowPower
2000 * @param Periphs This parameter can be a combination of the following values:
2001 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2002 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2003 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2004 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
2005 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2006 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
2007 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
2008 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
2009 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
2010 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
2011 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2012 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2013 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
2014 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
2015 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
2016 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
2017 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
2018 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
2019 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2020 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2021 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2022 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
2023 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
2024 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
2025 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
2026 *
2027 * (*) value not defined in all devices.
2028 * @retval None
2029 */
2030 __STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
2031 {
2032 __IO uint32_t tmpreg;
2033 SET_BIT(RCC->APB2LPENR, Periphs);
2034 /* Delay after an RCC peripheral clock enabling */
2035 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
2036 (void)tmpreg;
2037 }
2038
2039 /**
2040 * @brief Disable APB2 peripheral clocks in low-power mode
2041 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2042 * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n
2043 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2044 * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n
2045 * APB2LPENR UART9LPEN LL_APB2_GRP1_DisableClockLowPower\n
2046 * APB2LPENR UART10LPEN LL_APB2_GRP1_DisableClockLowPower\n
2047 * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2048 * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n
2049 * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n
2050 * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockLowPower\n
2051 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2052 * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n
2053 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n
2054 * APB2LPENR EXTITLPEN LL_APB2_GRP1_DisableClockLowPower\n
2055 * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n
2056 * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n
2057 * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n
2058 * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n
2059 * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n
2060 * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2061 * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n
2062 * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n
2063 * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n
2064 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2065 * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n
2066 * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_DisableClockLowPower
2067 * @param Periphs This parameter can be a combination of the following values:
2068 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2069 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2070 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2071 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
2072 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2073 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
2074 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
2075 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
2076 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
2077 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
2078 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2079 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2080 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
2081 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
2082 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
2083 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
2084 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
2085 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
2086 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2087 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2088 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2089 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
2090 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
2091 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
2092 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
2093 *
2094 * (*) value not defined in all devices.
2095 * @retval None
2096 */
2097 __STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
2098 {
2099 CLEAR_BIT(RCC->APB2LPENR, Periphs);
2100 }
2101
2102 /**
2103 * @}
2104 */
2105
2106 /**
2107 * @}
2108 */
2109
2110 /**
2111 * @}
2112 */
2113
2114 #endif /* defined(RCC) */
2115
2116 /**
2117 * @}
2118 */
2119
2120 #ifdef __cplusplus
2121 }
2122 #endif
2123
2124 #endif /* __STM32F4xx_LL_BUS_H */
2125
2126 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/