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Merge pull request #11198 from SteveCEvans/sce_rc2
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_HAL_Driver / Inc / stm32f4xx_ll_fmc.h
blob3b65f306caea6da3cb8f4f07df0acc18bd779e19
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_fmc.h
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 14-April-2017
7 * @brief Header file of FMC HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_LL_FMC_H
40 #define __STM32F4xx_LL_FMC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx_hal_def.h"
48
49 /** @addtogroup STM32F4xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup FMC_LL
54 * @{
55 */
56 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
57 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
58 /* Private types -------------------------------------------------------------*/
59 /** @defgroup FMC_LL_Private_Types FMC Private Types
60 * @{
61 */
62
63 /**
64 * @brief FMC NORSRAM Configuration Structure definition
65 */
66 typedef struct
67 {
68 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
69 This parameter can be a value of @ref FMC_NORSRAM_Bank */
70
71 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
72 multiplexed on the data bus or not.
73 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
74
75 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
76 the corresponding memory device.
77 This parameter can be a value of @ref FMC_Memory_Type */
78
79 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
80 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
81
82 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
83 valid only with synchronous burst Flash memories.
84 This parameter can be a value of @ref FMC_Burst_Access_Mode */
85
86 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
87 the Flash memory in burst mode.
88 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
89
90 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
91 memory, valid only when accessing Flash memories in burst mode.
92 This parameter can be a value of @ref FMC_Wrap_Mode
93 This mode is not available for the STM32F446/467/479xx devices */
94
95 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
96 clock cycle before the wait state or during the wait state,
97 valid only when accessing memories in burst mode.
98 This parameter can be a value of @ref FMC_Wait_Timing */
99
100 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
101 This parameter can be a value of @ref FMC_Write_Operation */
102
103 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
104 signal, valid for Flash memory access in burst mode.
105 This parameter can be a value of @ref FMC_Wait_Signal */
106
107 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
108 This parameter can be a value of @ref FMC_Extended_Mode */
109
110 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
111 valid only with asynchronous Flash memories.
112 This parameter can be a value of @ref FMC_AsynchronousWait */
113
114 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
115 This parameter can be a value of @ref FMC_Write_Burst */
116
117 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
118 This parameter is only enabled through the FMC_BCR1 register, and don't care
119 through FMC_BCR2..4 registers.
120 This parameter can be a value of @ref FMC_Continous_Clock */
121
122 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
123 This parameter is only enabled through the FMC_BCR1 register, and don't care
124 through FMC_BCR2..4 registers.
125 This parameter can be a value of @ref FMC_Write_FIFO
126 This mode is available only for the STM32F446/469/479xx devices */
127
128 uint32_t PageSize; /*!< Specifies the memory page size.
129 This parameter can be a value of @ref FMC_Page_Size */
130 }FMC_NORSRAM_InitTypeDef;
131
132 /**
133 * @brief FMC NORSRAM Timing parameters structure definition
134 */
135 typedef struct
136 {
137 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
138 the duration of the address setup time.
139 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
140 @note This parameter is not used with synchronous NOR Flash memories. */
141
142 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
143 the duration of the address hold time.
144 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
145 @note This parameter is not used with synchronous NOR Flash memories. */
146
147 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
148 the duration of the data setup time.
149 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
150 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
151 NOR Flash memories. */
152
153 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
154 the duration of the bus turnaround.
155 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
156 @note This parameter is only used for multiplexed NOR Flash memories. */
157
158 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
159 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
160 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
161 accesses. */
162
163 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
164 to the memory before getting the first data.
165 The parameter value depends on the memory type as shown below:
166 - It must be set to 0 in case of a CRAM
167 - It is don't care in asynchronous NOR, SRAM or ROM accesses
168 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
169 with synchronous burst mode enable */
170
171 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
172 This parameter can be a value of @ref FMC_Access_Mode */
173 }FMC_NORSRAM_TimingTypeDef;
174
175 /**
176 * @brief FMC NAND Configuration Structure definition
177 */
178 typedef struct
179 {
180 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
181 This parameter can be a value of @ref FMC_NAND_Bank */
182
183 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
184 This parameter can be any value of @ref FMC_Wait_feature */
185
186 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
187 This parameter can be any value of @ref FMC_NAND_Data_Width */
188
189 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
190 This parameter can be any value of @ref FMC_ECC */
191
192 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
193 This parameter can be any value of @ref FMC_ECC_Page_Size */
194
195 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
196 delay between CLE low and RE low.
197 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
198
199 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
200 delay between ALE low and RE low.
201 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
202 }FMC_NAND_InitTypeDef;
203
204 /**
205 * @brief FMC NAND/PCCARD Timing parameters structure definition
206 */
207 typedef struct
208 {
209 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
210 the command assertion for NAND-Flash read or write access
211 to common/Attribute or I/O memory space (depending on
212 the memory space timing to be configured).
213 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
214
215 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
216 command for NAND-Flash read or write access to
217 common/Attribute or I/O memory space (depending on the
218 memory space timing to be configured).
219 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
220
221 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
222 (and data for write access) after the command de-assertion
223 for NAND-Flash read or write access to common/Attribute
224 or I/O memory space (depending on the memory space timing
225 to be configured).
226 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
227
228 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
229 data bus is kept in HiZ after the start of a NAND-Flash
230 write access to common/Attribute or I/O memory space (depending
231 on the memory space timing to be configured).
232 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
233 }FMC_NAND_PCC_TimingTypeDef;
234
235 /**
236 * @brief FMC NAND Configuration Structure definition
237 */
238 typedef struct
239 {
240 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
241 This parameter can be any value of @ref FMC_Wait_feature */
242
243 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
244 delay between CLE low and RE low.
245 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
246
247 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
248 delay between ALE low and RE low.
249 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
250 }FMC_PCCARD_InitTypeDef;
251
252 /**
253 * @brief FMC SDRAM Configuration Structure definition
254 */
255 typedef struct
256 {
257 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
258 This parameter can be a value of @ref FMC_SDRAM_Bank */
259
260 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
261 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
262
263 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
264 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
265
266 uint32_t MemoryDataWidth; /*!< Defines the memory device width.
267 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
268
269 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
270 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
271
272 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
273 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
274
275 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
276 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
277
278 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
279 to disable the clock before changing frequency.
280 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
281
282 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
283 commands during the CAS latency and stores data in the Read FIFO.
284 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
285
286 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
287 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
288 }FMC_SDRAM_InitTypeDef;
289
290 /**
291 * @brief FMC SDRAM Timing parameters structure definition
292 */
293 typedef struct
294 {
295 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
296 an active or Refresh command in number of memory clock cycles.
297 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
298
299 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
300 issuing the Activate command in number of memory clock cycles.
301 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
302
303 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
304 cycles.
305 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
306
307 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
308 and the delay between two consecutive Refresh commands in number of
309 memory clock cycles.
310 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
311
312 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
313 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
314
315 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
316 in number of memory clock cycles.
317 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
318
319 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
320 command in number of memory clock cycles.
321 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
322 }FMC_SDRAM_TimingTypeDef;
323
324 /**
325 * @brief SDRAM command parameters structure definition
326 */
327 typedef struct
328 {
329 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
330 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
331
332 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
333 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
334
335 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
336 in auto refresh mode.
337 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
338 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
339 }FMC_SDRAM_CommandTypeDef;
340 /**
341 * @}
342 */
343
344 /* Private constants ---------------------------------------------------------*/
345 /** @defgroup FMC_LL_Private_Constants FMC Private Constants
346 * @{
347 */
348
349 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
350 * @{
351 */
352 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
353 * @{
354 */
355 #define FMC_NORSRAM_BANK1 0x00000000U
356 #define FMC_NORSRAM_BANK2 0x00000002U
357 #define FMC_NORSRAM_BANK3 0x00000004U
358 #define FMC_NORSRAM_BANK4 0x00000006U
359 /**
360 * @}
361 */
362
363 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
364 * @{
365 */
366 #define FMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
367 #define FMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
368 /**
369 * @}
370 */
371
372 /** @defgroup FMC_Memory_Type FMC Memory Type
373 * @{
374 */
375 #define FMC_MEMORY_TYPE_SRAM 0x00000000U
376 #define FMC_MEMORY_TYPE_PSRAM 0x00000004U
377 #define FMC_MEMORY_TYPE_NOR 0x00000008U
378 /**
379 * @}
380 */
381
382 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
383 * @{
384 */
385 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
386 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
387 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
388 /**
389 * @}
390 */
391
392 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
393 * @{
394 */
395 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
396 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
397 /**
398 * @}
399 */
400
401 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
402 * @{
403 */
404 #define FMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
405 #define FMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
406 /**
407 * @}
408 */
409
410 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
411 * @{
412 */
413 #define FMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
414 #define FMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
415 /**
416 * @}
417 */
418
419 /** @defgroup FMC_Wrap_Mode FMC Wrap Mode
420 * @{
421 */
422 /** @note This mode is not available for the STM32F446/469/479xx devices
423 */
424 #define FMC_WRAP_MODE_DISABLE 0x00000000U
425 #define FMC_WRAP_MODE_ENABLE 0x00000400U
426 /**
427 * @}
428 */
429
430 /** @defgroup FMC_Wait_Timing FMC Wait Timing
431 * @{
432 */
433 #define FMC_WAIT_TIMING_BEFORE_WS 0x00000000U
434 #define FMC_WAIT_TIMING_DURING_WS 0x00000800U
435 /**
436 * @}
437 */
438
439 /** @defgroup FMC_Write_Operation FMC Write Operation
440 * @{
441 */
442 #define FMC_WRITE_OPERATION_DISABLE 0x00000000U
443 #define FMC_WRITE_OPERATION_ENABLE 0x00001000U
444 /**
445 * @}
446 */
447
448 /** @defgroup FMC_Wait_Signal FMC Wait Signal
449 * @{
450 */
451 #define FMC_WAIT_SIGNAL_DISABLE 0x00000000U
452 #define FMC_WAIT_SIGNAL_ENABLE 0x00002000U
453 /**
454 * @}
455 */
456
457 /** @defgroup FMC_Extended_Mode FMC Extended Mode
458 * @{
459 */
460 #define FMC_EXTENDED_MODE_DISABLE 0x00000000U
461 #define FMC_EXTENDED_MODE_ENABLE 0x00004000U
462 /**
463 * @}
464 */
465
466 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
467 * @{
468 */
469 #define FMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
470 #define FMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
471 /**
472 * @}
473 */
474
475 /** @defgroup FMC_Page_Size FMC Page Size
476 * @{
477 */
478 #define FMC_PAGE_SIZE_NONE 0x00000000U
479 #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
480 #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
481 #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1))
482 #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
483 /**
484 * @}
485 */
486
487 /** @defgroup FMC_Write_FIFO FMC Write FIFO
488 * @note These values are available only for the STM32F446/469/479xx devices.
489 * @{
490 */
491 #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
492 #define FMC_WRITE_FIFO_ENABLE 0x00000000U
493 /**
494 * @}
495 */
496
497 /** @defgroup FMC_Write_Burst FMC Write Burst
498 * @{
499 */
500 #define FMC_WRITE_BURST_DISABLE 0x00000000U
501 #define FMC_WRITE_BURST_ENABLE 0x00080000U
502 /**
503 * @}
504 */
505
506 /** @defgroup FMC_Continous_Clock FMC Continuous Clock
507 * @{
508 */
509 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
510 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
511 /**
512 * @}
513 */
514
515 /** @defgroup FMC_Access_Mode FMC Access Mode
516 * @{
517 */
518 #define FMC_ACCESS_MODE_A 0x00000000U
519 #define FMC_ACCESS_MODE_B 0x10000000U
520 #define FMC_ACCESS_MODE_C 0x20000000U
521 #define FMC_ACCESS_MODE_D 0x30000000U
522 /**
523 * @}
524 */
525
526 /**
527 * @}
528 */
529
530 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
531 * @{
532 */
533 /** @defgroup FMC_NAND_Bank FMC NAND Bank
534 * @{
535 */
536 #define FMC_NAND_BANK2 0x00000010U
537 #define FMC_NAND_BANK3 0x00000100U
538 /**
539 * @}
540 */
541
542 /** @defgroup FMC_Wait_feature FMC Wait feature
543 * @{
544 */
545 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
546 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
547 /**
548 * @}
549 */
550
551 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
552 * @{
553 */
554 #define FMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
555 #define FMC_PCR_MEMORY_TYPE_NAND 0x00000008U
556 /**
557 * @}
558 */
559
560 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
561 * @{
562 */
563 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
564 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
565 /**
566 * @}
567 */
568
569 /** @defgroup FMC_ECC FMC ECC
570 * @{
571 */
572 #define FMC_NAND_ECC_DISABLE 0x00000000U
573 #define FMC_NAND_ECC_ENABLE 0x00000040U
574 /**
575 * @}
576 */
577
578 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
579 * @{
580 */
581 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
582 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
583 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
584 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
585 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
586 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
587 /**
588 * @}
589 */
590
591 /**
592 * @}
593 */
594
595 /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
596 * @{
597 */
598 /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
599 * @{
600 */
601 #define FMC_SDRAM_BANK1 0x00000000U
602 #define FMC_SDRAM_BANK2 0x00000001U
603 /**
604 * @}
605 */
606
607 /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
608 * @{
609 */
610 #define FMC_SDRAM_COLUMN_BITS_NUM_8 0x00000000U
611 #define FMC_SDRAM_COLUMN_BITS_NUM_9 0x00000001U
612 #define FMC_SDRAM_COLUMN_BITS_NUM_10 0x00000002U
613 #define FMC_SDRAM_COLUMN_BITS_NUM_11 0x00000003U
614 /**
615 * @}
616 */
617
618 /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
619 * @{
620 */
621 #define FMC_SDRAM_ROW_BITS_NUM_11 0x00000000U
622 #define FMC_SDRAM_ROW_BITS_NUM_12 0x00000004U
623 #define FMC_SDRAM_ROW_BITS_NUM_13 0x00000008U
624 /**
625 * @}
626 */
627
628 /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
629 * @{
630 */
631 #define FMC_SDRAM_MEM_BUS_WIDTH_8 0x00000000U
632 #define FMC_SDRAM_MEM_BUS_WIDTH_16 0x00000010U
633 #define FMC_SDRAM_MEM_BUS_WIDTH_32 0x00000020U
634 /**
635 * @}
636 */
637
638 /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
639 * @{
640 */
641 #define FMC_SDRAM_INTERN_BANKS_NUM_2 0x00000000U
642 #define FMC_SDRAM_INTERN_BANKS_NUM_4 0x00000040U
643 /**
644 * @}
645 */
646
647 /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
648 * @{
649 */
650 #define FMC_SDRAM_CAS_LATENCY_1 0x00000080U
651 #define FMC_SDRAM_CAS_LATENCY_2 0x00000100U
652 #define FMC_SDRAM_CAS_LATENCY_3 0x00000180U
653 /**
654 * @}
655 */
656
657 /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
658 * @{
659 */
660 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE 0x00000000U
661 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE 0x00000200U
662
663 /**
664 * @}
665 */
666
667 /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
668 * @{
669 */
670 #define FMC_SDRAM_CLOCK_DISABLE 0x00000000U
671 #define FMC_SDRAM_CLOCK_PERIOD_2 0x00000800U
672 #define FMC_SDRAM_CLOCK_PERIOD_3 0x00000C00U
673 /**
674 * @}
675 */
676
677 /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
678 * @{
679 */
680 #define FMC_SDRAM_RBURST_DISABLE 0x00000000U
681 #define FMC_SDRAM_RBURST_ENABLE 0x00001000U
682 /**
683 * @}
684 */
685
686 /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
687 * @{
688 */
689 #define FMC_SDRAM_RPIPE_DELAY_0 0x00000000U
690 #define FMC_SDRAM_RPIPE_DELAY_1 0x00002000U
691 #define FMC_SDRAM_RPIPE_DELAY_2 0x00004000U
692 /**
693 * @}
694 */
695
696 /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
697 * @{
698 */
699 #define FMC_SDRAM_CMD_NORMAL_MODE 0x00000000U
700 #define FMC_SDRAM_CMD_CLK_ENABLE 0x00000001U
701 #define FMC_SDRAM_CMD_PALL 0x00000002U
702 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE 0x00000003U
703 #define FMC_SDRAM_CMD_LOAD_MODE 0x00000004U
704 #define FMC_SDRAM_CMD_SELFREFRESH_MODE 0x00000005U
705 #define FMC_SDRAM_CMD_POWERDOWN_MODE 0x00000006U
706 /**
707 * @}
708 */
709
710 /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
711 * @{
712 */
713 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
714 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
715 #define FMC_SDRAM_CMD_TARGET_BANK1_2 0x00000018U
716 /**
717 * @}
718 */
719
720 /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
721 * @{
722 */
723 #define FMC_SDRAM_NORMAL_MODE 0x00000000U
724 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
725 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
726 /**
727 * @}
728 */
729
730 /**
731 * @}
732 */
733
734 /** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
735 * @{
736 */
737 #define FMC_IT_RISING_EDGE 0x00000008U
738 #define FMC_IT_LEVEL 0x00000010U
739 #define FMC_IT_FALLING_EDGE 0x00000020U
740 #define FMC_IT_REFRESH_ERROR 0x00004000U
741 /**
742 * @}
743 */
744
745 /** @defgroup FMC_LL_Flag_definition FMC Flag definition
746 * @{
747 */
748 #define FMC_FLAG_RISING_EDGE 0x00000001U
749 #define FMC_FLAG_LEVEL 0x00000002U
750 #define FMC_FLAG_FALLING_EDGE 0x00000004U
751 #define FMC_FLAG_FEMPT 0x00000040U
752 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
753 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
754 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
755 /**
756 * @}
757 */
758
759 /** @defgroup FMC_LL_Alias_definition FMC Alias definition
760 * @{
761 */
762 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
763 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
764 #else
765 #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
766 #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
767 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
768 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
769 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
770 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
771
772
773 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
774 #define FMC_NAND_DEVICE FMC_Bank3
775 #else
776 #define FMC_NAND_DEVICE FMC_Bank2_3
777 #define FMC_PCCARD_DEVICE FMC_Bank4
778 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
779 #define FMC_NORSRAM_DEVICE FMC_Bank1
780 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
781 #define FMC_SDRAM_DEVICE FMC_Bank5_6
782 /**
783 * @}
784 */
785
786 /**
787 * @}
788 */
789
790 /* Private macro -------------------------------------------------------------*/
791 /** @defgroup FMC_LL_Private_Macros FMC Private Macros
792 * @{
793 */
794
795 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
796 * @brief macros to handle NOR device enable/disable and read/write operations
797 * @{
798 */
799 /**
800 * @brief Enable the NORSRAM device access.
801 * @param __INSTANCE__: FMC_NORSRAM Instance
802 * @param __BANK__: FMC_NORSRAM Bank
803 * @retval None
804 */
805 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
806
807 /**
808 * @brief Disable the NORSRAM device access.
809 * @param __INSTANCE__: FMC_NORSRAM Instance
810 * @param __BANK__: FMC_NORSRAM Bank
811 * @retval None
812 */
813 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
814 /**
815 * @}
816 */
817
818 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
819 * @brief macros to handle NAND device enable/disable
820 * @{
821 */
822 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
823 /**
824 * @brief Enable the NAND device access.
825 * @param __INSTANCE__: FMC_NAND Instance
826 * @param __BANK__: FMC_NAND Bank
827 * @retval None
828 */
829 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
830
831 /**
832 * @brief Disable the NAND device access.
833 * @param __INSTANCE__: FMC_NAND Instance
834 * @param __BANK__: FMC_NAND Bank
835 * @retval None
836 */
837 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
838 #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
839 /**
840 * @brief Enable the NAND device access.
841 * @param __INSTANCE__: FMC_NAND Instance
842 * @param __BANK__: FMC_NAND Bank
843 * @retval None
844 */
845 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
846 ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
847
848 /**
849 * @brief Disable the NAND device access.
850 * @param __INSTANCE__: FMC_NAND Instance
851 * @param __BANK__: FMC_NAND Bank
852 * @retval None
853 */
854 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
855 ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
856
857 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
858 /**
859 * @}
860 */
861 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
862 /** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
863 * @brief macros to handle SRAM read/write operations
864 * @{
865 */
866 /**
867 * @brief Enable the PCCARD device access.
868 * @param __INSTANCE__: FMC_PCCARD Instance
869 * @retval None
870 */
871 #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
872
873 /**
874 * @brief Disable the PCCARD device access.
875 * @param __INSTANCE__: FMC_PCCARD Instance
876 * @retval None
877 */
878 #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
879 /**
880 * @}
881 */
882 #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
883
884 /** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
885 * @brief macros to handle FMC flags and interrupts
886 * @{
887 */
888 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
889 /**
890 * @brief Enable the NAND device interrupt.
891 * @param __INSTANCE__: FMC_NAND instance
892 * @param __BANK__: FMC_NAND Bank
893 * @param __INTERRUPT__: FMC_NAND interrupt
894 * This parameter can be any combination of the following values:
895 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
896 * @arg FMC_IT_LEVEL: Interrupt level.
897 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
898 * @retval None
899 */
900 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
901
902 /**
903 * @brief Disable the NAND device interrupt.
904 * @param __INSTANCE__: FMC_NAND Instance
905 * @param __BANK__: FMC_NAND Bank
906 * @param __INTERRUPT__: FMC_NAND interrupt
907 * This parameter can be any combination of the following values:
908 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
909 * @arg FMC_IT_LEVEL: Interrupt level.
910 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
911 * @retval None
912 */
913 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
914
915 /**
916 * @brief Get flag status of the NAND device.
917 * @param __INSTANCE__: FMC_NAND Instance
918 * @param __BANK__: FMC_NAND Bank
919 * @param __FLAG__: FMC_NAND flag
920 * This parameter can be any combination of the following values:
921 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
922 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
923 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
924 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
925 * @retval The state of FLAG (SET or RESET).
926 */
927 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
928 /**
929 * @brief Clear flag status of the NAND device.
930 * @param __INSTANCE__: FMC_NAND Instance
931 * @param __BANK__: FMC_NAND Bank
932 * @param __FLAG__: FMC_NAND flag
933 * This parameter can be any combination of the following values:
934 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
935 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
936 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
937 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
938 * @retval None
939 */
940 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
941 #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
942 /**
943 * @brief Enable the NAND device interrupt.
944 * @param __INSTANCE__: FMC_NAND instance
945 * @param __BANK__: FMC_NAND Bank
946 * @param __INTERRUPT__: FMC_NAND interrupt
947 * This parameter can be any combination of the following values:
948 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
949 * @arg FMC_IT_LEVEL: Interrupt level.
950 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
951 * @retval None
952 */
953 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
954 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
955
956 /**
957 * @brief Disable the NAND device interrupt.
958 * @param __INSTANCE__: FMC_NAND Instance
959 * @param __BANK__: FMC_NAND Bank
960 * @param __INTERRUPT__: FMC_NAND interrupt
961 * This parameter can be any combination of the following values:
962 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
963 * @arg FMC_IT_LEVEL: Interrupt level.
964 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
965 * @retval None
966 */
967 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
968 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
969
970 /**
971 * @brief Get flag status of the NAND device.
972 * @param __INSTANCE__: FMC_NAND Instance
973 * @param __BANK__: FMC_NAND Bank
974 * @param __FLAG__: FMC_NAND flag
975 * This parameter can be any combination of the following values:
976 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
977 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
978 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
979 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
980 * @retval The state of FLAG (SET or RESET).
981 */
982 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
983 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
984 /**
985 * @brief Clear flag status of the NAND device.
986 * @param __INSTANCE__: FMC_NAND Instance
987 * @param __BANK__: FMC_NAND Bank
988 * @param __FLAG__: FMC_NAND flag
989 * This parameter can be any combination of the following values:
990 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
991 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
992 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
993 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
994 * @retval None
995 */
996 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
997 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
998 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
999
1000 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
1001 /**
1002 * @brief Enable the PCCARD device interrupt.
1003 * @param __INSTANCE__: FMC_PCCARD instance
1004 * @param __INTERRUPT__: FMC_PCCARD interrupt
1005 * This parameter can be any combination of the following values:
1006 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
1007 * @arg FMC_IT_LEVEL: Interrupt level.
1008 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
1009 * @retval None
1010 */
1011 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
1012
1013 /**
1014 * @brief Disable the PCCARD device interrupt.
1015 * @param __INSTANCE__: FMC_PCCARD instance
1016 * @param __INTERRUPT__: FMC_PCCARD interrupt
1017 * This parameter can be any combination of the following values:
1018 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
1019 * @arg FMC_IT_LEVEL: Interrupt level.
1020 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
1021 * @retval None
1022 */
1023 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
1024
1025 /**
1026 * @brief Get flag status of the PCCARD device.
1027 * @param __INSTANCE__: FMC_PCCARD instance
1028 * @param __FLAG__: FMC_PCCARD flag
1029 * This parameter can be any combination of the following values:
1030 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
1031 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
1032 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
1033 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
1034 * @retval The state of FLAG (SET or RESET).
1035 */
1036 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
1037
1038 /**
1039 * @brief Clear flag status of the PCCARD device.
1040 * @param __INSTANCE__: FMC_PCCARD instance
1041 * @param __FLAG__: FMC_PCCARD flag
1042 * This parameter can be any combination of the following values:
1043 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
1044 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
1045 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
1046 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
1047 * @retval None
1048 */
1049 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
1050 #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
1051
1052 /**
1053 * @brief Enable the SDRAM device interrupt.
1054 * @param __INSTANCE__: FMC_SDRAM instance
1055 * @param __INTERRUPT__: FMC_SDRAM interrupt
1056 * This parameter can be any combination of the following values:
1057 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
1058 * @retval None
1059 */
1060 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
1061
1062 /**
1063 * @brief Disable the SDRAM device interrupt.
1064 * @param __INSTANCE__: FMC_SDRAM instance
1065 * @param __INTERRUPT__: FMC_SDRAM interrupt
1066 * This parameter can be any combination of the following values:
1067 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
1068 * @retval None
1069 */
1070 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
1071
1072 /**
1073 * @brief Get flag status of the SDRAM device.
1074 * @param __INSTANCE__: FMC_SDRAM instance
1075 * @param __FLAG__: FMC_SDRAM flag
1076 * This parameter can be any combination of the following values:
1077 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
1078 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
1079 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
1080 * @retval The state of FLAG (SET or RESET).
1081 */
1082 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
1083
1084 /**
1085 * @brief Clear flag status of the SDRAM device.
1086 * @param __INSTANCE__: FMC_SDRAM instance
1087 * @param __FLAG__: FMC_SDRAM flag
1088 * This parameter can be any combination of the following values:
1089 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
1090 * @retval None
1091 */
1092 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
1093 /**
1094 * @}
1095 */
1096
1097 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
1098 * @{
1099 */
1100 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
1101 ((BANK) == FMC_NORSRAM_BANK2) || \
1102 ((BANK) == FMC_NORSRAM_BANK3) || \
1103 ((BANK) == FMC_NORSRAM_BANK4))
1104
1105 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
1106 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
1107
1108 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
1109 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
1110 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
1111
1112 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
1113 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
1114 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
1115
1116 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
1117 ((__MODE__) == FMC_ACCESS_MODE_B) || \
1118 ((__MODE__) == FMC_ACCESS_MODE_C) || \
1119 ((__MODE__) == FMC_ACCESS_MODE_D))
1120
1121 #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
1122 ((BANK) == FMC_NAND_BANK3))
1123
1124 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
1125 ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
1126
1127 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
1128 ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
1129
1130 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
1131 ((STATE) == FMC_NAND_ECC_ENABLE))
1132
1133 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
1134 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
1135 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
1136 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
1137 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
1138 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
1139
1140 #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255U)
1141
1142 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255U)
1143
1144 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255U)
1145
1146 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255U)
1147
1148 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255U)
1149
1150 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255U)
1151
1152 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
1153
1154 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
1155
1156 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
1157
1158 #define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
1159
1160 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
1161 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
1162
1163 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
1164 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
1165
1166 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
1167 #define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
1168 ((__MODE__) == FMC_WRAP_MODE_ENABLE))
1169 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1170
1171 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
1172 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
1173
1174 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
1175 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
1176
1177 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
1178 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
1179
1180 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
1181 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
1182
1183 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
1184 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
1185
1186 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
1187 ((__BURST__) == FMC_WRITE_BURST_ENABLE))
1188
1189 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
1190 ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
1191
1192 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
1193
1194 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
1195
1196 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
1197
1198 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
1199
1200 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
1201
1202 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
1203
1204 #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
1205 ((BANK) == FMC_SDRAM_BANK2))
1206
1207 #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
1208 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
1209 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
1210 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
1211
1212 #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
1213 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
1214 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
1215
1216 #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
1217 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
1218 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
1219
1220 #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
1221 ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
1222
1223
1224 #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
1225 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
1226 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
1227
1228 #define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \
1229 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \
1230 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
1231
1232 #define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \
1233 ((RBURST) == FMC_SDRAM_RBURST_ENABLE))
1234
1235
1236 #define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \
1237 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
1238 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
1239
1240 #define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1241
1242 #define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1243
1244 #define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
1245
1246 #define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1247
1248 #define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
1249
1250 #define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1251
1252 #define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1253
1254 #define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \
1255 ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \
1256 ((COMMAND) == FMC_SDRAM_CMD_PALL) || \
1257 ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
1258 ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \
1259 ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
1260 ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
1261
1262 #define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \
1263 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
1264 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
1265
1266 #define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0U) && ((NUMBER) <= 16U))
1267
1268 #define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191U)
1269
1270 #define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191U)
1271
1272 #define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
1273
1274 #define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
1275 ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
1276
1277 #define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) || \
1278 ((SIZE) == FMC_PAGE_SIZE_128) || \
1279 ((SIZE) == FMC_PAGE_SIZE_256) || \
1280 ((SIZE) == FMC_PAGE_SIZE_512) || \
1281 ((SIZE) == FMC_PAGE_SIZE_1024))
1282
1283 #if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
1284 #define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) || \
1285 ((FIFO) == FMC_WRITE_FIFO_ENABLE))
1286 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
1287
1288 /**
1289 * @}
1290 */
1291
1292 /**
1293 * @}
1294 */
1295
1296 /* Private functions ---------------------------------------------------------*/
1297 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
1298 * @{
1299 */
1300
1301 /** @defgroup FMC_LL_NORSRAM NOR SRAM
1302 * @{
1303 */
1304 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
1305 * @{
1306 */
1307 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
1308 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1309 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
1310 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1311 /**
1312 * @}
1313 */
1314
1315 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
1316 * @{
1317 */
1318 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1319 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1320 /**
1321 * @}
1322 */
1323 /**
1324 * @}
1325 */
1326
1327 /** @defgroup FMC_LL_NAND NAND
1328 * @{
1329 */
1330 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
1331 * @{
1332 */
1333 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
1334 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1335 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1336 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1337 /**
1338 * @}
1339 */
1340
1341 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
1342 * @{
1343 */
1344 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1345 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1346 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
1347
1348 /**
1349 * @}
1350 */
1351 /**
1352 * @}
1353 */
1354 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
1355 /** @defgroup FMC_LL_PCCARD PCCARD
1356 * @{
1357 */
1358 /** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
1359 * @{
1360 */
1361 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
1362 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1363 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1364 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1365 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
1366 /**
1367 * @}
1368 */
1369 /**
1370 * @}
1371 */
1372 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1373
1374 /** @defgroup FMC_LL_SDRAM SDRAM
1375 * @{
1376 */
1377 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
1378 * @{
1379 */
1380 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
1381 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
1382 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1383 /**
1384 * @}
1385 */
1386
1387 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
1388 * @{
1389 */
1390 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1391 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1392 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
1393 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
1394 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
1395 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1396 /**
1397 * @}
1398 */
1399 /**
1400 * @}
1401 */
1402
1403 /**
1404 * @}
1405 */
1406
1407 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
1408 /**
1409 * @}
1410 */
1411
1412 /**
1413 * @}
1414 */
1415 #ifdef __cplusplus
1416 }
1417 #endif
1418
1419 #endif /* __STM32F4xx_LL_FMC_H */
1420
1421 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/