lib/main/STM32F4/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_ll_pwr.h
   4   * @author  MCD Application Team
   5   * @version V1.7.1
   6   * @date    14-April-2017
   7   * @brief   Header file of PWR LL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F4xx_LL_PWR_H
  40 #define __STM32F4xx_LL_PWR_H
  41
  42 #ifdef __cplusplus
  43 extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f4xx.h"
  48
  49 /** @addtogroup STM32F4xx_LL_Driver
  50   * @{
  51   */
  52
  53 #if defined(PWR)
  54
  55 /** @defgroup PWR_LL PWR
  56   * @{
  57   */
  58
  59 /* Private types -------------------------------------------------------------*/
  60 /* Private variables ---------------------------------------------------------*/
  61 /* Private constants ---------------------------------------------------------*/
  62 /* Private macros ------------------------------------------------------------*/
  63 /* Exported types ------------------------------------------------------------*/
  64 /* Exported constants --------------------------------------------------------*/
  65 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
  66   * @{
  67   */
  68
  69 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
  70   * @brief    Flags defines which can be used with LL_PWR_WriteReg function
  71   * @{
  72   */
  73 #define LL_PWR_CR_CSBF                     PWR_CR_CSBF            /*!< Clear standby flag */
  74 #define LL_PWR_CR_CWUF                     PWR_CR_CWUF            /*!< Clear wakeup flag */
  75 /**
  76   * @}
  77   */
  78
  79 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
  80   * @brief    Flags defines which can be used with LL_PWR_ReadReg function
  81   * @{
  82   */
  83 #define LL_PWR_CSR_WUF                     PWR_CSR_WUF            /*!< Wakeup flag */
  84 #define LL_PWR_CSR_SBF                     PWR_CSR_SBF            /*!< Standby flag */
  85 #define LL_PWR_CSR_PVDO                    PWR_CSR_PVDO           /*!< Power voltage detector output flag */
  86 #define LL_PWR_CSR_VOS                     PWR_CSR_VOSRDY            /*!< Voltage scaling select flag */
  87 #if defined(PWR_CSR_EWUP)
  88 #define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP           /*!< Enable WKUP pin */
  89 #elif defined(PWR_CSR_EWUP1)
  90 #define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP1          /*!< Enable WKUP pin 1 */
  91 #endif /* PWR_CSR_EWUP */
  92 #if defined(PWR_CSR_EWUP2)
  93 #define LL_PWR_CSR_EWUP2                   PWR_CSR_EWUP2          /*!< Enable WKUP pin 2 */
  94 #endif /* PWR_CSR_EWUP2 */
  95 #if defined(PWR_CSR_EWUP3)
  96 #define LL_PWR_CSR_EWUP3                   PWR_CSR_EWUP3          /*!< Enable WKUP pin 3 */
  97 #endif /* PWR_CSR_EWUP3 */
  98 /**
  99   * @}
 100   */
 101
 102 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
 103   * @{
 104   */
 105 #if defined(PWR_CR_VOS_0)
 106 #define LL_PWR_REGU_VOLTAGE_SCALE3         (PWR_CR_VOS_0)
 107 #define LL_PWR_REGU_VOLTAGE_SCALE2         (PWR_CR_VOS_1)
 108 #define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */
 109 #else
 110 #define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR_VOS)
 111 #define LL_PWR_REGU_VOLTAGE_SCALE2         0x00000000U
 112 #endif /* PWR_CR_VOS_0 */
 113 /**
 114   * @}
 115   */
 116
 117 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
 118   * @{
 119   */
 120 #define LL_PWR_MODE_STOP_MAINREGU             0x00000000U                    /*!< Enter Stop mode when the CPU enters deepsleep */
 121 #define LL_PWR_MODE_STOP_LPREGU               (PWR_CR_LPDS)                  /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
 122 #if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
 123 #define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE  (PWR_CR_MRUDS | PWR_CR_FPDS)                 /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */
 124 #define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE    (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS)   /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */
 125 #endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
 126 #if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
 127 #define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP  (PWR_CR_MRLVDS | PWR_CR_FPDS)                 /*!< Enter Stop mode (with main Regulator in Deep Sleep mode) when the CPU enters deepsleep */
 128 #define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP    (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS)   /*!< Enter Stop mode (with low power Regulator in Deep Sleep mode) when the CPU enters deepsleep */
 129 #endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */
 130 #define LL_PWR_MODE_STANDBY                   (PWR_CR_PDDS)                  /*!< Enter Standby mode when the CPU enters deepsleep */
 131 /**
 132   * @}
 133   */
 134
 135 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
 136  * @{
 137  */
 138 #define LL_PWR_REGU_DSMODE_MAIN        0x00000000U           /*!< Voltage Regulator in main mode during deepsleep mode */
 139 #define LL_PWR_REGU_DSMODE_LOW_POWER   (PWR_CR_LPDS)         /*!< Voltage Regulator in low-power mode during deepsleep mode */
 140 /**
 141   * @}
 142   */
 143
 144 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
 145   * @{
 146   */
 147 #define LL_PWR_PVDLEVEL_0                  (PWR_CR_PLS_LEV0)      /*!< Voltage threshold detected by PVD 2.2 V */
 148 #define LL_PWR_PVDLEVEL_1                  (PWR_CR_PLS_LEV1)      /*!< Voltage threshold detected by PVD 2.3 V */
 149 #define LL_PWR_PVDLEVEL_2                  (PWR_CR_PLS_LEV2)      /*!< Voltage threshold detected by PVD 2.4 V */
 150 #define LL_PWR_PVDLEVEL_3                  (PWR_CR_PLS_LEV3)      /*!< Voltage threshold detected by PVD 2.5 V */
 151 #define LL_PWR_PVDLEVEL_4                  (PWR_CR_PLS_LEV4)      /*!< Voltage threshold detected by PVD 2.6 V */
 152 #define LL_PWR_PVDLEVEL_5                  (PWR_CR_PLS_LEV5)      /*!< Voltage threshold detected by PVD 2.7 V */
 153 #define LL_PWR_PVDLEVEL_6                  (PWR_CR_PLS_LEV6)      /*!< Voltage threshold detected by PVD 2.8 V */
 154 #define LL_PWR_PVDLEVEL_7                  (PWR_CR_PLS_LEV7)      /*!< Voltage threshold detected by PVD 2.9 V */
 155 /**
 156   * @}
 157   */
 158 /** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
 159   * @{
 160   */
 161 #if defined(PWR_CSR_EWUP)
 162 #define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP)         /*!< WKUP pin : PA0 */
 163 #endif /* PWR_CSR_EWUP */
 164 #if defined(PWR_CSR_EWUP1)
 165 #define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP1)        /*!< WKUP pin 1 : PA0 */
 166 #endif /* PWR_CSR_EWUP1 */
 167 #if defined(PWR_CSR_EWUP2)
 168 #define LL_PWR_WAKEUP_PIN2                 (PWR_CSR_EWUP2)        /*!< WKUP pin 2 : PC0 or PC13 according to device */
 169 #endif /* PWR_CSR_EWUP2 */
 170 #if defined(PWR_CSR_EWUP3)
 171 #define LL_PWR_WAKEUP_PIN3                 (PWR_CSR_EWUP3)        /*!< WKUP pin 3 : PC1 */
 172 #endif /* PWR_CSR_EWUP3 */
 173 /**
 174   * @}
 175   */
 176
 177 /**
 178   * @}
 179   */
 180
 181
 182 /* Exported macro ------------------------------------------------------------*/
 183 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
 184   * @{
 185   */
 186
 187 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
 188   * @{
 189   */
 190
 191 /**
 192   * @brief  Write a value in PWR register
 193   * @param  __REG__ Register to be written
 194   * @param  __VALUE__ Value to be written in the register
 195   * @retval None
 196   */
 197 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
 198
 199 /**
 200   * @brief  Read a value in PWR register
 201   * @param  __REG__ Register to be read
 202   * @retval Register value
 203   */
 204 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
 205 /**
 206   * @}
 207   */
 208
 209 /**
 210   * @}
 211   */
 212
 213 /* Exported functions --------------------------------------------------------*/
 214 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
 215   * @{
 216   */
 217
 218 /** @defgroup PWR_LL_EF_Configuration Configuration
 219   * @{
 220   */
 221 #if defined(PWR_CR_FISSR)
 222 /**
 223   * @brief  Enable FLASH interface STOP while system Run is ON
 224   * @rmtoll CR    FISSR       LL_PWR_EnableFLASHInterfaceSTOP
 225   * @note  This mode is enabled only with STOP low power mode.
 226   * @retval None
 227   */
 228 __STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void)
 229 {
 230   SET_BIT(PWR->CR, PWR_CR_FISSR);
 231 }
 232
 233 /**
 234   * @brief  Disable FLASH Interface STOP while system Run is ON
 235   * @rmtoll CR    FISSR       LL_PWR_DisableFLASHInterfaceSTOP
 236   * @retval None
 237   */
 238 __STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void)
 239 {
 240   CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
 241 }
 242
 243 /**
 244   * @brief  Check if FLASH Interface STOP while system Run feature is enabled
 245   * @rmtoll CR    FISSR       LL_PWR_IsEnabledFLASHInterfaceSTOP
 246   * @retval State of bit (1 or 0).
 247   */
 248 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void)
 249 {
 250   return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR));
 251 }
 252 #endif /* PWR_CR_FISSR */
 253
 254 #if defined(PWR_CR_FMSSR)
 255 /**
 256   * @brief  Enable FLASH Memory STOP while system Run is ON
 257   * @rmtoll CR    FMSSR       LL_PWR_EnableFLASHMemorySTOP
 258   * @note  This mode is enabled only with STOP low power mode.
 259   * @retval None
 260   */
 261 __STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void)
 262 {
 263   SET_BIT(PWR->CR, PWR_CR_FMSSR);
 264 }
 265
 266 /**
 267   * @brief  Disable FLASH Memory STOP while system Run is ON
 268   * @rmtoll CR    FMSSR       LL_PWR_DisableFLASHMemorySTOP
 269   * @retval None
 270   */
 271 __STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void)
 272 {
 273   CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
 274 }
 275
 276 /**
 277   * @brief  Check if FLASH Memory STOP while system Run feature is enabled
 278   * @rmtoll CR    FMSSR       LL_PWR_IsEnabledFLASHMemorySTOP
 279   * @retval State of bit (1 or 0).
 280   */
 281 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void)
 282 {
 283   return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR));
 284 }
 285 #endif /* PWR_CR_FMSSR */
 286 #if defined(PWR_CR_UDEN)
 287 /**
 288   * @brief  Enable Under Drive Mode
 289   * @rmtoll CR    UDEN       LL_PWR_EnableUnderDriveMode
 290   * @note  This mode is enabled only with STOP low power mode.
 291   *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This
 292   *        mode is only available when the main Regulator or the low power Regulator
 293   *        is in low voltage mode.
 294   * @note  If the Under-drive mode was enabled, it is automatically disabled after
 295   *        exiting Stop mode.
 296   *        When the voltage Regulator operates in Under-drive mode, an additional
 297   *        startup delay is induced when waking up from Stop mode.
 298   * @retval None
 299   */
 300 __STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)
 301 {
 302   SET_BIT(PWR->CR, PWR_CR_UDEN);
 303 }
 304
 305 /**
 306   * @brief  Disable Under Drive Mode
 307   * @rmtoll CR    UDEN       LL_PWR_DisableUnderDriveMode
 308   * @retval None
 309   */
 310 __STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)
 311 {
 312   CLEAR_BIT(PWR->CR, PWR_CR_UDEN);
 313 }
 314
 315 /**
 316   * @brief  Check if Under Drive Mode is enabled
 317   * @rmtoll CR    UDEN       LL_PWR_IsEnabledUnderDriveMode
 318   * @retval State of bit (1 or 0).
 319   */
 320 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)
 321 {
 322   return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN));
 323 }
 324 #endif /* PWR_CR_UDEN */
 325
 326 #if defined(PWR_CR_ODSWEN)
 327 /**
 328   * @brief  Enable Over drive switching
 329   * @rmtoll CR    ODSWEN       LL_PWR_EnableOverDriveSwitching
 330   * @retval None
 331   */
 332 __STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)
 333 {
 334   SET_BIT(PWR->CR, PWR_CR_ODSWEN);
 335 }
 336
 337 /**
 338   * @brief  Disable Over drive switching
 339   * @rmtoll CR    ODSWEN       LL_PWR_DisableOverDriveSwitching
 340   * @retval None
 341   */
 342 __STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)
 343 {
 344   CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN);
 345 }
 346
 347 /**
 348   * @brief  Check if Over drive switching is enabled
 349   * @rmtoll CR    ODSWEN       LL_PWR_IsEnabledOverDriveSwitching
 350   * @retval State of bit (1 or 0).
 351   */
 352 __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)
 353 {
 354   return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN));
 355 }
 356 #endif /* PWR_CR_ODSWEN */
 357 #if defined(PWR_CR_ODEN)
 358 /**
 359   * @brief  Enable Over drive Mode
 360   * @rmtoll CR    ODEN       LL_PWR_EnableOverDriveMode
 361   * @retval None
 362   */
 363 __STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)
 364 {
 365   SET_BIT(PWR->CR, PWR_CR_ODEN);
 366 }
 367
 368 /**
 369   * @brief  Disable Over drive Mode
 370   * @rmtoll CR    ODEN       LL_PWR_DisableOverDriveMode
 371   * @retval None
 372   */
 373 __STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)
 374 {
 375   CLEAR_BIT(PWR->CR, PWR_CR_ODEN);
 376 }
 377
 378 /**
 379   * @brief  Check if Over drive switching is enabled
 380   * @rmtoll CR    ODEN       LL_PWR_IsEnabledOverDriveMode
 381   * @retval State of bit (1 or 0).
 382   */
 383 __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)
 384 {
 385   return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN));
 386 }
 387 #endif /* PWR_CR_ODEN */
 388 #if defined(PWR_CR_MRUDS)
 389 /**
 390   * @brief  Enable Main Regulator in deepsleep under-drive Mode
 391   * @rmtoll CR    MRUDS       LL_PWR_EnableMainRegulatorDeepSleepUDMode
 392   * @retval None
 393   */
 394 __STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)
 395 {
 396   SET_BIT(PWR->CR, PWR_CR_MRUDS);
 397 }
 398
 399 /**
 400   * @brief  Disable Main Regulator in deepsleep under-drive Mode
 401   * @rmtoll CR    MRUDS       LL_PWR_DisableMainRegulatorDeepSleepUDMode
 402   * @retval None
 403   */
 404 __STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)
 405 {
 406   CLEAR_BIT(PWR->CR, PWR_CR_MRUDS);
 407 }
 408
 409 /**
 410   * @brief  Check if Main Regulator in deepsleep under-drive Mode is enabled
 411   * @rmtoll CR    MRUDS       LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode
 412   * @retval State of bit (1 or 0).
 413   */
 414 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)
 415 {
 416   return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS));
 417 }
 418 #endif /* PWR_CR_MRUDS */
 419
 420 #if defined(PWR_CR_LPUDS)
 421 /**
 422   * @brief  Enable Low Power Regulator in deepsleep under-drive Mode
 423   * @rmtoll CR    LPUDS       LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode
 424   * @retval None
 425   */
 426 __STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)
 427 {
 428   SET_BIT(PWR->CR, PWR_CR_LPUDS);
 429 }
 430
 431 /**
 432   * @brief  Disable Low Power Regulator in deepsleep under-drive Mode
 433   * @rmtoll CR    LPUDS       LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode
 434   * @retval None
 435   */
 436 __STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)
 437 {
 438   CLEAR_BIT(PWR->CR, PWR_CR_LPUDS);
 439 }
 440
 441 /**
 442   * @brief  Check if Low Power Regulator in deepsleep under-drive Mode is enabled
 443   * @rmtoll CR    LPUDS       LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode
 444   * @retval State of bit (1 or 0).
 445   */
 446 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)
 447 {
 448   return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS));
 449 }
 450 #endif /* PWR_CR_LPUDS */
 451
 452 #if defined(PWR_CR_MRLVDS)
 453 /**
 454   * @brief  Enable Main Regulator low voltage Mode
 455   * @rmtoll CR    MRLVDS       LL_PWR_EnableMainRegulatorLowVoltageMode
 456   * @retval None
 457   */
 458 __STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void)
 459 {
 460   SET_BIT(PWR->CR, PWR_CR_MRLVDS);
 461 }
 462
 463 /**
 464   * @brief  Disable Main Regulator low voltage Mode
 465   * @rmtoll CR    MRLVDS       LL_PWR_DisableMainRegulatorLowVoltageMode
 466   * @retval None
 467   */
 468 __STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void)
 469 {
 470   CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS);
 471 }
 472
 473 /**
 474   * @brief  Check if Main Regulator low voltage Mode is enabled
 475   * @rmtoll CR    MRLVDS       LL_PWR_IsEnabledMainRegulatorLowVoltageMode
 476   * @retval State of bit (1 or 0).
 477   */
 478 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void)
 479 {
 480   return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS));
 481 }
 482 #endif /* PWR_CR_MRLVDS */
 483
 484 #if defined(PWR_CR_LPLVDS)
 485 /**
 486   * @brief  Enable Low Power Regulator low voltage Mode
 487   * @rmtoll CR    LPLVDS       LL_PWR_EnableLowPowerRegulatorLowVoltageMode
 488   * @retval None
 489   */
 490 __STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void)
 491 {
 492   SET_BIT(PWR->CR, PWR_CR_LPLVDS);
 493 }
 494
 495 /**
 496   * @brief  Disable Low Power Regulator low voltage Mode
 497   * @rmtoll CR    LPLVDS       LL_PWR_DisableLowPowerRegulatorLowVoltageMode
 498   * @retval None
 499   */
 500 __STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void)
 501 {
 502   CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS);
 503 }
 504
 505 /**
 506   * @brief  Check if Low Power Regulator low voltage Mode is enabled
 507   * @rmtoll CR    LPLVDS       LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode
 508   * @retval State of bit (1 or 0).
 509   */
 510 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void)
 511 {
 512   return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS));
 513 }
 514 #endif /* PWR_CR_LPLVDS */
 515 /**
 516   * @brief  Set the main internal Regulator output voltage
 517   * @rmtoll CR    VOS       LL_PWR_SetRegulVoltageScaling
 518   * @param  VoltageScaling This parameter can be one of the following values:
 519   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
 520   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
 521   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
 522   *         (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
 523   * @retval None
 524   */
 525 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
 526 {
 527   MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
 528 }
 529
 530 /**
 531   * @brief  Get the main internal Regulator output voltage
 532   * @rmtoll CR    VOS       LL_PWR_GetRegulVoltageScaling
 533   * @retval Returned value can be one of the following values:
 534   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
 535   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
 536   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
 537   *         (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
 538   */
 539 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
 540 {
 541   return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
 542 }
 543 /**
 544   * @brief  Enable the Flash Power Down in Stop Mode
 545   * @rmtoll CR    FPDS       LL_PWR_EnableFlashPowerDown
 546   * @retval None
 547   */
 548 __STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
 549 {
 550   SET_BIT(PWR->CR, PWR_CR_FPDS);
 551 }
 552
 553 /**
 554   * @brief  Disable the Flash Power Down in Stop Mode
 555   * @rmtoll CR    FPDS       LL_PWR_DisableFlashPowerDown
 556   * @retval None
 557   */
 558 __STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
 559 {
 560   CLEAR_BIT(PWR->CR, PWR_CR_FPDS);
 561 }
 562
 563 /**
 564   * @brief  Check if the Flash Power Down in Stop Mode is enabled
 565   * @rmtoll CR    FPDS       LL_PWR_IsEnabledFlashPowerDown
 566   * @retval State of bit (1 or 0).
 567   */
 568 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
 569 {
 570   return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS));
 571 }
 572
 573 /**
 574   * @brief  Enable access to the backup domain
 575   * @rmtoll CR    DBP       LL_PWR_EnableBkUpAccess
 576   * @retval None
 577   */
 578 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
 579 {
 580   SET_BIT(PWR->CR, PWR_CR_DBP);
 581 }
 582
 583 /**
 584   * @brief  Disable access to the backup domain
 585   * @rmtoll CR    DBP       LL_PWR_DisableBkUpAccess
 586   * @retval None
 587   */
 588 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
 589 {
 590   CLEAR_BIT(PWR->CR, PWR_CR_DBP);
 591 }
 592
 593 /**
 594   * @brief  Check if the backup domain is enabled
 595   * @rmtoll CR    DBP       LL_PWR_IsEnabledBkUpAccess
 596   * @retval State of bit (1 or 0).
 597   */
 598 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
 599 {
 600   return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
 601 }
 602 /**
 603   * @brief  Enable the backup Regulator
 604   * @rmtoll CSR    BRE       LL_PWR_EnableBkUpRegulator
 605   * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
 606   * The LL_PWR_EnableBkUpAccess() must be called before using this API.
 607   * @retval None
 608   */
 609 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
 610 {
 611   SET_BIT(PWR->CSR, PWR_CSR_BRE);
 612 }
 613
 614 /**
 615   * @brief  Disable the backup Regulator
 616   * @rmtoll CSR    BRE       LL_PWR_DisableBkUpRegulator
 617   * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
 618   * The LL_PWR_EnableBkUpAccess() must be called before using this API.
 619   * @retval None
 620   */
 621 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
 622 {
 623   CLEAR_BIT(PWR->CSR, PWR_CSR_BRE);
 624 }
 625
 626 /**
 627   * @brief  Check if the backup Regulator is enabled
 628   * @rmtoll CSR    BRE       LL_PWR_IsEnabledBkUpRegulator
 629   * @retval State of bit (1 or 0).
 630   */
 631 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
 632 {
 633   return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE));
 634 }
 635
 636 /**
 637   * @brief  Set voltage Regulator mode during deep sleep mode
 638   * @rmtoll CR    LPDS         LL_PWR_SetRegulModeDS
 639   * @param  RegulMode This parameter can be one of the following values:
 640   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
 641   *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
 642   * @retval None
 643   */
 644 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
 645 {
 646   MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
 647 }
 648
 649 /**
 650   * @brief  Get voltage Regulator mode during deep sleep mode
 651   * @rmtoll CR    LPDS         LL_PWR_GetRegulModeDS
 652   * @retval Returned value can be one of the following values:
 653   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
 654   *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
 655   */
 656 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
 657 {
 658   return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
 659 }
 660
 661 /**
 662   * @brief  Set Power Down mode when CPU enters deepsleep
 663   * @rmtoll CR    PDDS         LL_PWR_SetPowerMode\n
 664   * @rmtoll CR    MRUDS        LL_PWR_SetPowerMode\n
 665   * @rmtoll CR    LPUDS        LL_PWR_SetPowerMode\n
 666   * @rmtoll CR    FPDS         LL_PWR_SetPowerMode\n
 667   * @rmtoll CR    MRLVDS       LL_PWR_SetPowerMode\n
 668   * @rmtoll CR    LPlVDS       LL_PWR_SetPowerMode\n
 669   * @rmtoll CR    FPDS         LL_PWR_SetPowerMode\n
 670   * @rmtoll CR    LPDS         LL_PWR_SetPowerMode
 671   * @param  PDMode This parameter can be one of the following values:
 672   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
 673   *         @arg @ref LL_PWR_MODE_STOP_LPREGU
 674   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
 675   *         @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
 676   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
 677   *         @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
 678   *
 679   *         (*) not available on all devices
 680   *         @arg @ref LL_PWR_MODE_STANDBY
 681   * @retval None
 682   */
 683 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
 684 {
 685 #if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
 686   MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode);
 687 #elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
 688   MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode);
 689 #else
 690   MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
 691 #endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
 692 }
 693
 694 /**
 695   * @brief  Get Power Down mode when CPU enters deepsleep
 696   * @rmtoll CR    PDDS         LL_PWR_GetPowerMode\n
 697   * @rmtoll CR    MRUDS        LL_PWR_GetPowerMode\n
 698   * @rmtoll CR    LPUDS        LL_PWR_GetPowerMode\n
 699   * @rmtoll CR    FPDS         LL_PWR_GetPowerMode\n
 700   * @rmtoll CR    MRLVDS       LL_PWR_GetPowerMode\n
 701   * @rmtoll CR    LPLVDS       LL_PWR_GetPowerMode\n
 702   * @rmtoll CR    FPDS         LL_PWR_GetPowerMode\n
 703   * @rmtoll CR    LPDS         LL_PWR_GetPowerMode
 704   * @retval Returned value can be one of the following values:
 705   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
 706   *         @arg @ref LL_PWR_MODE_STOP_LPREGU
 707   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
 708   *         @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
 709   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
 710   *         @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
 711   *
 712   *         (*) not available on all devices
 713   *         @arg @ref LL_PWR_MODE_STANDBY
 714   */
 715 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
 716 {
 717 #if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
 718   return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS)));
 719 #elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
 720   return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS)));
 721 #else
 722   return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
 723 #endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
 724 }
 725
 726 /**
 727   * @brief  Configure the voltage threshold detected by the Power Voltage Detector
 728   * @rmtoll CR    PLS       LL_PWR_SetPVDLevel
 729   * @param  PVDLevel This parameter can be one of the following values:
 730   *         @arg @ref LL_PWR_PVDLEVEL_0
 731   *         @arg @ref LL_PWR_PVDLEVEL_1
 732   *         @arg @ref LL_PWR_PVDLEVEL_2
 733   *         @arg @ref LL_PWR_PVDLEVEL_3
 734   *         @arg @ref LL_PWR_PVDLEVEL_4
 735   *         @arg @ref LL_PWR_PVDLEVEL_5
 736   *         @arg @ref LL_PWR_PVDLEVEL_6
 737   *         @arg @ref LL_PWR_PVDLEVEL_7
 738   * @retval None
 739   */
 740 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
 741 {
 742   MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
 743 }
 744
 745 /**
 746   * @brief  Get the voltage threshold detection
 747   * @rmtoll CR    PLS       LL_PWR_GetPVDLevel
 748   * @retval Returned value can be one of the following values:
 749   *         @arg @ref LL_PWR_PVDLEVEL_0
 750   *         @arg @ref LL_PWR_PVDLEVEL_1
 751   *         @arg @ref LL_PWR_PVDLEVEL_2
 752   *         @arg @ref LL_PWR_PVDLEVEL_3
 753   *         @arg @ref LL_PWR_PVDLEVEL_4
 754   *         @arg @ref LL_PWR_PVDLEVEL_5
 755   *         @arg @ref LL_PWR_PVDLEVEL_6
 756   *         @arg @ref LL_PWR_PVDLEVEL_7
 757   */
 758 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
 759 {
 760   return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
 761 }
 762
 763 /**
 764   * @brief  Enable Power Voltage Detector
 765   * @rmtoll CR    PVDE       LL_PWR_EnablePVD
 766   * @retval None
 767   */
 768 __STATIC_INLINE void LL_PWR_EnablePVD(void)
 769 {
 770   SET_BIT(PWR->CR, PWR_CR_PVDE);
 771 }
 772
 773 /**
 774   * @brief  Disable Power Voltage Detector
 775   * @rmtoll CR    PVDE       LL_PWR_DisablePVD
 776   * @retval None
 777   */
 778 __STATIC_INLINE void LL_PWR_DisablePVD(void)
 779 {
 780   CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
 781 }
 782
 783 /**
 784   * @brief  Check if Power Voltage Detector is enabled
 785   * @rmtoll CR    PVDE       LL_PWR_IsEnabledPVD
 786   * @retval State of bit (1 or 0).
 787   */
 788 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
 789 {
 790   return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
 791 }
 792
 793 /**
 794   * @brief  Enable the WakeUp PINx functionality
 795   * @rmtoll CSR   EWUP        LL_PWR_EnableWakeUpPin\n
 796   * @rmtoll CSR   EWUP1       LL_PWR_EnableWakeUpPin\n
 797   * @rmtoll CSR   EWUP2       LL_PWR_EnableWakeUpPin\n
 798   * @rmtoll CSR   EWUP3       LL_PWR_EnableWakeUpPin
 799   * @param  WakeUpPin This parameter can be one of the following values:
 800   *         @arg @ref LL_PWR_WAKEUP_PIN1
 801   *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
 802   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
 803   *
 804   *         (*) not available on all devices
 805   * @retval None
 806   */
 807 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
 808 {
 809   SET_BIT(PWR->CSR, WakeUpPin);
 810 }
 811
 812 /**
 813   * @brief  Disable the WakeUp PINx functionality
 814   * @rmtoll CSR   EWUP        LL_PWR_DisableWakeUpPin\n
 815   * @rmtoll CSR   EWUP1       LL_PWR_DisableWakeUpPin\n
 816   * @rmtoll CSR   EWUP2       LL_PWR_DisableWakeUpPin\n
 817   * @rmtoll CSR   EWUP3       LL_PWR_DisableWakeUpPin
 818   * @param  WakeUpPin This parameter can be one of the following values:
 819   *         @arg @ref LL_PWR_WAKEUP_PIN1
 820   *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
 821   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
 822   *
 823   *         (*) not available on all devices
 824   * @retval None
 825   */
 826 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
 827 {
 828   CLEAR_BIT(PWR->CSR, WakeUpPin);
 829 }
 830
 831 /**
 832   * @brief  Check if the WakeUp PINx functionality is enabled
 833   * @rmtoll CSR   EWUP        LL_PWR_IsEnabledWakeUpPin\n
 834   * @rmtoll CSR   EWUP1       LL_PWR_IsEnabledWakeUpPin\n
 835   * @rmtoll CSR   EWUP2       LL_PWR_IsEnabledWakeUpPin\n
 836   * @rmtoll CSR   EWUP3       LL_PWR_IsEnabledWakeUpPin
 837   * @param  WakeUpPin This parameter can be one of the following values:
 838   *         @arg @ref LL_PWR_WAKEUP_PIN1
 839   *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
 840   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
 841   *
 842   *         (*) not available on all devices
 843   * @retval State of bit (1 or 0).
 844   */
 845 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
 846 {
 847   return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
 848 }
 849
 850
 851 /**
 852   * @}
 853   */
 854
 855 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
 856   * @{
 857   */
 858
 859 /**
 860   * @brief  Get Wake-up Flag
 861   * @rmtoll CSR   WUF       LL_PWR_IsActiveFlag_WU
 862   * @retval State of bit (1 or 0).
 863   */
 864 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
 865 {
 866   return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
 867 }
 868
 869 /**
 870   * @brief  Get Standby Flag
 871   * @rmtoll CSR   SBF       LL_PWR_IsActiveFlag_SB
 872   * @retval State of bit (1 or 0).
 873   */
 874 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
 875 {
 876   return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
 877 }
 878
 879 /**
 880   * @brief  Get Backup Regulator ready Flag
 881   * @rmtoll CSR   BRR       LL_PWR_IsActiveFlag_BRR
 882   * @retval State of bit (1 or 0).
 883   */
 884 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
 885 {
 886   return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR));
 887 }
 888 /**
 889   * @brief  Indicate whether VDD voltage is below the selected PVD threshold
 890   * @rmtoll CSR   PVDO       LL_PWR_IsActiveFlag_PVDO
 891   * @retval State of bit (1 or 0).
 892   */
 893 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
 894 {
 895   return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
 896 }
 897
 898 /**
 899   * @brief  Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
 900   * @rmtoll CSR   VOS       LL_PWR_IsActiveFlag_VOS
 901   * @retval State of bit (1 or 0).
 902   */
 903 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
 904 {
 905   return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));
 906 }
 907 #if defined(PWR_CR_ODEN)
 908 /**
 909   * @brief  Indicate whether the Over-Drive mode is ready or not
 910   * @rmtoll CSR   ODRDY       LL_PWR_IsActiveFlag_OD
 911   * @retval State of bit (1 or 0).
 912   */
 913 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)
 914 {
 915   return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY));
 916 }
 917 #endif /* PWR_CR_ODEN */
 918
 919 #if defined(PWR_CR_ODSWEN)
 920 /**
 921   * @brief  Indicate whether the Over-Drive mode switching is ready or not
 922   * @rmtoll CSR   ODSWRDY       LL_PWR_IsActiveFlag_ODSW
 923   * @retval State of bit (1 or 0).
 924   */
 925 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)
 926 {
 927   return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY));
 928 }
 929 #endif /* PWR_CR_ODSWEN */
 930
 931 #if defined(PWR_CR_UDEN)
 932 /**
 933   * @brief  Indicate whether the Under-Drive mode is ready or not
 934   * @rmtoll CSR   UDRDY       LL_PWR_IsActiveFlag_UD
 935   * @retval State of bit (1 or 0).
 936   */
 937 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)
 938 {
 939   return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY));
 940 }
 941 #endif /* PWR_CR_UDEN */
 942 /**
 943   * @brief  Clear Standby Flag
 944   * @rmtoll CR   CSBF       LL_PWR_ClearFlag_SB
 945   * @retval None
 946   */
 947 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
 948 {
 949   SET_BIT(PWR->CR, PWR_CR_CSBF);
 950 }
 951
 952 /**
 953   * @brief  Clear Wake-up Flags
 954   * @rmtoll CR   CWUF       LL_PWR_ClearFlag_WU
 955   * @retval None
 956   */
 957 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
 958 {
 959   SET_BIT(PWR->CR, PWR_CR_CWUF);
 960 }
 961 #if defined(PWR_CSR_UDRDY)
 962 /**
 963   * @brief  Clear Under-Drive ready Flag
 964   * @rmtoll CSR          UDRDY         LL_PWR_ClearFlag_UD
 965   * @retval None
 966   */
 967 __STATIC_INLINE void LL_PWR_ClearFlag_UD(void)
 968 {
 969   WRITE_REG(PWR->CSR, PWR_CSR_UDRDY);
 970 }
 971 #endif /* PWR_CSR_UDRDY */
 972
 973 /**
 974   * @}
 975   */
 976
 977 #if defined(USE_FULL_LL_DRIVER)
 978 /** @defgroup PWR_LL_EF_Init De-initialization function
 979   * @{
 980   */
 981 ErrorStatus LL_PWR_DeInit(void);
 982 /**
 983   * @}
 984   */
 985 #endif /* USE_FULL_LL_DRIVER */
 986
 987 /**
 988   * @}
 989   */
 990
 991 /**
 992   * @}
 993   */
 994
 995 #endif /* defined(PWR) */
 996
 997 /**
 998   * @}
 999   */
1000
1001 #ifdef __cplusplus
1002 }
1003 #endif
1004
1005 #endif /* __STM32F4xx_LL_PWR_H */
1006
1007 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/