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Merge pull request #11198 from SteveCEvans/sce_rc2
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_HAL_Driver / Inc / stm32f4xx_ll_rcc.h
blobddac927182a60d458d3b7b34293d3a1c188e626a
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_rcc.h
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 14-April-2017
7 * @brief Header file of RCC LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_LL_RCC_H
40 #define __STM32F4xx_LL_RCC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx.h"
48
49 /** @addtogroup STM32F4xx_LL_Driver
50 * @{
51 */
52
53 #if defined(RCC)
54
55 /** @defgroup RCC_LL RCC
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
62 * @{
63 */
64
65 #if defined(RCC_DCKCFGR_PLLSAIDIVR)
66 static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
67 #endif /* RCC_DCKCFGR_PLLSAIDIVR */
68
69 /**
70 * @}
71 */
72 /* Private constants ---------------------------------------------------------*/
73 /* Private macros ------------------------------------------------------------*/
74 #if defined(USE_FULL_LL_DRIVER)
75 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
76 * @{
77 */
78 /**
79 * @}
80 */
81 #endif /*USE_FULL_LL_DRIVER*/
82 /* Exported types ------------------------------------------------------------*/
83 #if defined(USE_FULL_LL_DRIVER)
84 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
85 * @{
86 */
87
88 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
89 * @{
90 */
91
92 /**
93 * @brief RCC Clocks Frequency Structure
94 */
95 typedef struct
96 {
97 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
98 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
99 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
100 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
101 } LL_RCC_ClocksTypeDef;
102
103 /**
104 * @}
105 */
106
107 /**
108 * @}
109 */
110 #endif /* USE_FULL_LL_DRIVER */
111
112 /* Exported constants --------------------------------------------------------*/
113 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
114 * @{
115 */
116
117 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
118 * @brief Defines used to adapt values of different oscillators
119 * @note These values could be modified in the user environment according to
120 * HW set-up.
121 * @{
122 */
123 #if !defined (HSE_VALUE)
124 #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */
125 #endif /* HSE_VALUE */
126
127 #if !defined (HSI_VALUE)
128 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
129 #endif /* HSI_VALUE */
130
131 #if !defined (LSE_VALUE)
132 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
133 #endif /* LSE_VALUE */
134
135 #if !defined (LSI_VALUE)
136 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
137 #endif /* LSI_VALUE */
138
139 #if !defined (EXTERNAL_CLOCK_VALUE)
140 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
141 #endif /* EXTERNAL_CLOCK_VALUE */
142 /**
143 * @}
144 */
145
146 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
147 * @brief Flags defines which can be used with LL_RCC_WriteReg function
148 * @{
149 */
150 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
151 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
152 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
153 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
154 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
155 #if defined(RCC_PLLI2S_SUPPORT)
156 #define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */
157 #endif /* RCC_PLLI2S_SUPPORT */
158 #if defined(RCC_PLLSAI_SUPPORT)
159 #define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */
160 #endif /* RCC_PLLSAI_SUPPORT */
161 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
162 /**
163 * @}
164 */
165
166 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
167 * @brief Flags defines which can be used with LL_RCC_ReadReg function
168 * @{
169 */
170 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
171 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
172 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
173 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
174 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
175 #if defined(RCC_PLLI2S_SUPPORT)
176 #define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */
177 #endif /* RCC_PLLI2S_SUPPORT */
178 #if defined(RCC_PLLSAI_SUPPORT)
179 #define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */
180 #endif /* RCC_PLLSAI_SUPPORT */
181 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
182 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
183 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
184 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
185 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
186 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
187 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
188 #if defined(RCC_CSR_BORRSTF)
189 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
190 #endif /* RCC_CSR_BORRSTF */
191 /**
192 * @}
193 */
194
195 /** @defgroup RCC_LL_EC_IT IT Defines
196 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
197 * @{
198 */
199 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
200 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
201 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
202 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
203 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
204 #if defined(RCC_PLLI2S_SUPPORT)
205 #define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */
206 #endif /* RCC_PLLI2S_SUPPORT */
207 #if defined(RCC_PLLSAI_SUPPORT)
208 #define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable */
209 #endif /* RCC_PLLSAI_SUPPORT */
210 /**
211 * @}
212 */
213
214 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
215 * @{
216 */
217 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
218 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
219 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
220 #if defined(RCC_CFGR_SW_PLLR)
221 #define LL_RCC_SYS_CLKSOURCE_PLLR RCC_CFGR_SW_PLLR /*!< PLLR selection as system clock */
222 #endif /* RCC_CFGR_SW_PLLR */
223 /**
224 * @}
225 */
226
227 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
228 * @{
229 */
230 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
231 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
232 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
233 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
234 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR RCC_CFGR_SWS_PLLR /*!< PLLR used as system clock */
235 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
236 /**
237 * @}
238 */
239
240 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
241 * @{
242 */
243 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
244 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
245 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
246 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
247 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
248 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
249 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
250 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
251 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
252 /**
253 * @}
254 */
255
256 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
257 * @{
258 */
259 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
260 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
261 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
262 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
263 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
264 /**
265 * @}
266 */
267
268 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
269 * @{
270 */
271 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
272 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
273 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
274 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
275 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
276 /**
277 * @}
278 */
279
280 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
281 * @{
282 */
283 #define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */
284 #define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */
285 #define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */
286 #define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */
287 #if defined(RCC_CFGR_MCO2)
288 #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */
289 #define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */
290 #define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */
291 #define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */
292 #endif /* RCC_CFGR_MCO2 */
293 /**
294 * @}
295 */
296
297 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
298 * @{
299 */
300 #define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */
301 #define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */
302 #define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */
303 #define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */
304 #define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */
305 #if defined(RCC_CFGR_MCO2PRE)
306 #define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */
307 #define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */
308 #define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */
309 #define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */
310 #define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */
311 #endif /* RCC_CFGR_MCO2PRE */
312 /**
313 * @}
314 */
315
316 /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
317 * @{
318 */
319 #define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */
320 #define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */
321 #define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */
322 #define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */
323 #define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */
324 #define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */
325 #define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */
326 #define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */
327 #define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */
328 #define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */
329 #define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */
330 #define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */
331 #define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */
332 #define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */
333 #define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */
334 #define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */
335 #define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */
336 #define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */
337 #define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */
338 #define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */
339 #define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */
340 #define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */
341 #define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */
342 #define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */
343 #define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */
344 #define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */
345 #define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */
346 #define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */
347 #define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */
348 #define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */
349 #define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */
350 /**
351 * @}
352 */
353
354 #if defined(USE_FULL_LL_DRIVER)
355 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
356 * @{
357 */
358 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
359 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
360 /**
361 * @}
362 */
363 #endif /* USE_FULL_LL_DRIVER */
364
365 #if defined(FMPI2C1)
366 /** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE Peripheral FMPI2C clock source selection
367 * @{
368 */
369 #define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as FMPI2C1 clock source */
370 #define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK RCC_DCKCFGR2_FMPI2C1SEL_0 /*!< SYSCLK clock used as FMPI2C1 clock source */
371 #define LL_RCC_FMPI2C1_CLKSOURCE_HSI RCC_DCKCFGR2_FMPI2C1SEL_1 /*!< HSI clock used as FMPI2C1 clock source */
372 /**
373 * @}
374 */
375 #endif /* FMPI2C1 */
376
377 #if defined(LPTIM1)
378 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
379 * @{
380 */
381 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock */
382 #define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock used as LPTIM1 clock */
383 #define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock used as LPTIM1 clock */
384 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) /*!< LSE oscillator clock used as LPTIM1 clock */
385 /**
386 * @}
387 */
388 #endif /* LPTIM1 */
389
390 #if defined(SAI1)
391 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
392 * @{
393 */
394 #if defined(RCC_DCKCFGR_SAI1SRC)
395 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1SRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 clock source */
396 #define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 clock source */
397 #define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_1 >> 16)) /*!< PLL clock used as SAI1 clock source */
398 #define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC >> 16)) /*!< External pin clock used as SAI1 clock source */
399 #endif /* RCC_DCKCFGR_SAI1SRC */
400 #if defined(RCC_DCKCFGR_SAI2SRC)
401 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI2SRC | 0x00000000U) /*!< PLLSAI clock used as SAI2 clock source */
402 #define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_0 >> 16)) /*!< PLLI2S clock used as SAI2 clock source */
403 #define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_1 >> 16)) /*!< PLL clock used as SAI2 clock source */
404 #define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC >> 16)) /*!< PLL Main clock used as SAI2 clock source */
405 #endif /* RCC_DCKCFGR_SAI2SRC */
406 #if defined(RCC_DCKCFGR_SAI1ASRC)
407 #if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
408 #define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block A clock source */
409 #define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< External pin used as SAI1 block A clock source */
410 #define LL_RCC_SAI1_A_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< PLL clock used as SAI1 block A clock source */
411 #define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC >> 16)) /*!< PLL Main clock used as SAI1 block A clock source */
412 #else
413 #define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block A clock source */
414 #define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block A clock source */
415 #define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< External pin clock used as SAI1 block A clock source */
416 #endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
417 #endif /* RCC_DCKCFGR_SAI1ASRC */
418 #if defined(RCC_DCKCFGR_SAI1BSRC)
419 #if defined(RCC_SAI1B_PLLSOURCE_SUPPORT)
420 #define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block B clock source */
421 #define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< External pin used as SAI1 block B clock source */
422 #define LL_RCC_SAI1_B_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< PLL clock used as SAI1 block B clock source */
423 #define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC >> 16)) /*!< PLL Main clock used as SAI1 block B clock source */
424 #else
425 #define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block B clock source */
426 #define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block B clock source */
427 #define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< External pin clock used as SAI1 block B clock source */
428 #endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */
429 #endif /* RCC_DCKCFGR_SAI1BSRC */
430 /**
431 * @}
432 */
433 #endif /* SAI1 */
434
435 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
436 /** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE Peripheral SDIO clock source selection
437 * @{
438 */
439 #define LL_RCC_SDIO_CLKSOURCE_PLL48CLK 0x00000000U /*!< PLL 48M domain clock used as SDIO clock */
440 #if defined(RCC_DCKCFGR_SDIOSEL)
441 #define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR_SDIOSEL /*!< System clock clock used as SDIO clock */
442 #else
443 #define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDIOSEL /*!< System clock clock used as SDIO clock */
444 #endif /* RCC_DCKCFGR_SDIOSEL */
445 /**
446 * @}
447 */
448 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
449
450 #if defined(DSI)
451 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
452 * @{
453 */
454 #define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */
455 #define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR_DSISEL /*!< PLL clock used as DSI byte lane clock source */
456 /**
457 * @}
458 */
459 #endif /* DSI */
460
461 #if defined(CEC)
462 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
463 * @{
464 */
465 #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as CEC clock */
466 #define LL_RCC_CEC_CLKSOURCE_LSE RCC_DCKCFGR2_CECSEL /*!< LSE oscillator clock used as CEC clock */
467 /**
468 * @}
469 */
470 #endif /* CEC */
471
472 /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
473 * @{
474 */
475 #if defined(RCC_CFGR_I2SSRC)
476 #define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */
477 #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */
478 #endif /* RCC_CFGR_I2SSRC */
479 #if defined(RCC_DCKCFGR_I2SSRC)
480 #define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2SSRC | 0x00000000U) /*!< PLL clock used as I2S1 clock source */
481 #define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_0 >> 16)) /*!< External pin used as I2S1 clock source */
482 #define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_1 >> 16)) /*!< PLL Main clock used as I2S1 clock source */
483 #endif /* RCC_DCKCFGR_I2SSRC */
484 #if defined(RCC_DCKCFGR_I2S1SRC)
485 #define LL_RCC_I2S1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S1SRC | 0x00000000U) /*!< PLLI2S clock used as I2S1 clock source */
486 #define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /*!< External pin used as I2S1 clock source */
487 #define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /*!< PLL clock used as I2S1 clock source */
488 #define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC >> 16)) /*!< PLL Main clock used as I2S1 clock source */
489 #endif /* RCC_DCKCFGR_I2S1SRC */
490 #if defined(RCC_DCKCFGR_I2S2SRC)
491 #define LL_RCC_I2S2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S2SRC | 0x00000000U) /*!< PLLI2S clock used as I2S2 clock source */
492 #define LL_RCC_I2S2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /*!< External pin used as I2S2 clock source */
493 #define LL_RCC_I2S2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /*!< PLL clock used as I2S2 clock source */
494 #define LL_RCC_I2S2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC >> 16)) /*!< PLL Main clock used as I2S2 clock source */
495 #endif /* RCC_DCKCFGR_I2S2SRC */
496 /**
497 * @}
498 */
499
500 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
501 /** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection
502 * @{
503 */
504 #if defined(RCC_DCKCFGR_CK48MSEL)
505 #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */
506 #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
507 #endif /* RCC_DCKCFGR_CK48MSEL */
508 #if defined(RCC_DCKCFGR2_CK48MSEL)
509 #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */
510 #if defined(RCC_PLLSAI_SUPPORT)
511 #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
512 #endif /* RCC_PLLSAI_SUPPORT */
513 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
514 #define LL_RCC_CK48M_CLKSOURCE_PLLI2S RCC_DCKCFGR2_CK48MSEL /*!< PLLI2S oscillator clock used as 48Mhz domain clock */
515 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
516 #endif /* RCC_DCKCFGR2_CK48MSEL */
517 /**
518 * @}
519 */
520
521 #if defined(RNG)
522 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
523 * @{
524 */
525 #define LL_RCC_RNG_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as RNG clock source */
526 #if defined(RCC_PLLSAI_SUPPORT)
527 #define LL_RCC_RNG_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as RNG clock source */
528 #endif /* RCC_PLLSAI_SUPPORT */
529 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
530 #define LL_RCC_RNG_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as RNG clock source */
531 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
532 /**
533 * @}
534 */
535 #endif /* RNG */
536
537 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
538 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
539 * @{
540 */
541 #define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as USB clock source */
542 #if defined(RCC_PLLSAI_SUPPORT)
543 #define LL_RCC_USB_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as USB clock source */
544 #endif /* RCC_PLLSAI_SUPPORT */
545 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
546 #define LL_RCC_USB_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as USB clock source */
547 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
548 /**
549 * @}
550 */
551 #endif /* USB_OTG_FS || USB_OTG_HS */
552
553 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
554
555 #if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
556 /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection
557 * @{
558 */
559 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM1 Audio clock source */
560 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /*!< I2S2 clock used as DFSDM1 Audio clock source */
561 #if defined(DFSDM2_Channel0)
562 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM2 Audio clock source */
563 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /*!< I2S2 clock used as DFSDM2 Audio clock source */
564 #endif /* DFSDM2_Channel0 */
565 /**
566 * @}
567 */
568
569 /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection
570 * @{
571 */
572 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock */
573 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM1 clock */
574 #if defined(DFSDM2_Channel0)
575 #define LL_RCC_DFSDM2_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM2 clock */
576 #define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM2 clock */
577 #endif /* DFSDM2_Channel0 */
578 /**
579 * @}
580 */
581 #endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
582
583 #if defined(FMPI2C1)
584 /** @defgroup RCC_LL_EC_FMPI2C1 Peripheral FMPI2C get clock source
585 * @{
586 */
587 #define LL_RCC_FMPI2C1_CLKSOURCE RCC_DCKCFGR2_FMPI2C1SEL /*!< FMPI2C1 Clock source selection */
588 /**
589 * @}
590 */
591 #endif /* FMPI2C1 */
592
593 #if defined(SPDIFRX)
594 /** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection
595 * @{
596 */
597 #define LL_RCC_SPDIFRX1_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as SPDIFRX clock source */
598 #define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S RCC_DCKCFGR2_SPDIFRXSEL /*!< PLLI2S clock used as SPDIFRX clock source */
599 /**
600 * @}
601 */
602 #endif /* SPDIFRX */
603
604 #if defined(LPTIM1)
605 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
606 * @{
607 */
608 #define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */
609 /**
610 * @}
611 */
612 #endif /* LPTIM1 */
613
614 #if defined(SAI1)
615 /** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
616 * @{
617 */
618 #if defined(RCC_DCKCFGR_SAI1ASRC)
619 #define LL_RCC_SAI1_A_CLKSOURCE RCC_DCKCFGR_SAI1ASRC /*!< SAI1 block A Clock source selection */
620 #endif /* RCC_DCKCFGR_SAI1ASRC */
621 #if defined(RCC_DCKCFGR_SAI1BSRC)
622 #define LL_RCC_SAI1_B_CLKSOURCE RCC_DCKCFGR_SAI1BSRC /*!< SAI1 block B Clock source selection */
623 #endif /* RCC_DCKCFGR_SAI1BSRC */
624 #if defined(RCC_DCKCFGR_SAI1SRC)
625 #define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR_SAI1SRC /*!< SAI1 Clock source selection */
626 #endif /* RCC_DCKCFGR_SAI1SRC */
627 #if defined(RCC_DCKCFGR_SAI2SRC)
628 #define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR_SAI2SRC /*!< SAI2 Clock source selection */
629 #endif /* RCC_DCKCFGR_SAI2SRC */
630 /**
631 * @}
632 */
633 #endif /* SAI1 */
634
635 #if defined(SDIO)
636 /** @defgroup RCC_LL_EC_SDIOx Peripheral SDIO get clock source
637 * @{
638 */
639 #if defined(RCC_DCKCFGR_SDIOSEL)
640 #define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR_SDIOSEL /*!< SDIO Clock source selection */
641 #elif defined(RCC_DCKCFGR2_SDIOSEL)
642 #define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR2_SDIOSEL /*!< SDIO Clock source selection */
643 #else
644 #define LL_RCC_SDIO_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< SDIO Clock source selection */
645 #endif
646 /**
647 * @}
648 */
649 #endif /* SDIO */
650
651 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
652 /** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source
653 * @{
654 */
655 #if defined(RCC_DCKCFGR_CK48MSEL)
656 #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR_CK48MSEL /*!< CK48M Domain clock source selection */
657 #endif /* RCC_DCKCFGR_CK48MSEL */
658 #if defined(RCC_DCKCFGR2_CK48MSEL)
659 #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */
660 #endif /* RCC_DCKCFGR_CK48MSEL */
661 /**
662 * @}
663 */
664 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
665
666 #if defined(RNG)
667 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
668 * @{
669 */
670 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
671 #define LL_RCC_RNG_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< RNG Clock source selection */
672 #else
673 #define LL_RCC_RNG_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< RNG Clock source selection */
674 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
675 /**
676 * @}
677 */
678 #endif /* RNG */
679
680 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
681 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
682 * @{
683 */
684 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
685 #define LL_RCC_USB_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< USB Clock source selection */
686 #else
687 #define LL_RCC_USB_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< USB Clock source selection */
688 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
689 /**
690 * @}
691 */
692 #endif /* USB_OTG_FS || USB_OTG_HS */
693
694 #if defined(CEC)
695 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
696 * @{
697 */
698 #define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */
699 /**
700 * @}
701 */
702 #endif /* CEC */
703
704 /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
705 * @{
706 */
707 #if defined(RCC_CFGR_I2SSRC)
708 #define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S1 Clock source selection */
709 #endif /* RCC_CFGR_I2SSRC */
710 #if defined(RCC_DCKCFGR_I2SSRC)
711 #define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2SSRC /*!< I2S1 Clock source selection */
712 #endif /* RCC_DCKCFGR_I2SSRC */
713 #if defined(RCC_DCKCFGR_I2S1SRC)
714 #define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2S1SRC /*!< I2S1 Clock source selection */
715 #endif /* RCC_DCKCFGR_I2S1SRC */
716 #if defined(RCC_DCKCFGR_I2S2SRC)
717 #define LL_RCC_I2S2_CLKSOURCE RCC_DCKCFGR_I2S2SRC /*!< I2S2 Clock source selection */
718 #endif /* RCC_DCKCFGR_I2S2SRC */
719 /**
720 * @}
721 */
722
723 #if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
724 /** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source
725 * @{
726 */
727 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM1ASEL /*!< DFSDM1 Audio Clock source selection */
728 #if defined(DFSDM2_Channel0)
729 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM2ASEL /*!< DFSDM2 Audio Clock source selection */
730 #endif /* DFSDM2_Channel0 */
731 /**
732 * @}
733 */
734
735 /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
736 * @{
737 */
738 #define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM1 Clock source selection */
739 #if defined(DFSDM2_Channel0)
740 #define LL_RCC_DFSDM2_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM2 Clock source selection */
741 #endif /* DFSDM2_Channel0 */
742 /**
743 * @}
744 */
745 #endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
746
747 #if defined(SPDIFRX)
748 /** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source
749 * @{
750 */
751 #define LL_RCC_SPDIFRX1_CLKSOURCE RCC_DCKCFGR2_SPDIFRXSEL /*!< SPDIFRX Clock source selection */
752 /**
753 * @}
754 */
755 #endif /* SPDIFRX */
756
757 #if defined(DSI)
758 /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
759 * @{
760 */
761 #define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR_DSISEL /*!< DSI Clock source selection */
762 /**
763 * @}
764 */
765 #endif /* DSI */
766
767 #if defined(LTDC)
768 /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
769 * @{
770 */
771 #define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR_PLLSAIDIVR /*!< LTDC Clock source selection */
772 /**
773 * @}
774 */
775 #endif /* LTDC */
776
777
778 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
779 * @{
780 */
781 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
782 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
783 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
784 #define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */
785 /**
786 * @}
787 */
788
789 #if defined(RCC_DCKCFGR_TIMPRE)
790 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
791 * @{
792 */
793 #define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice PCLK */
794 #define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR_TIMPRE /*!< Timers clock to four time PCLK */
795 /**
796 * @}
797 */
798 #endif /* RCC_DCKCFGR_TIMPRE */
799
800 /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source
801 * @{
802 */
803 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
804 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
805 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
806 #define LL_RCC_PLLI2SSOURCE_PIN (RCC_PLLI2SCFGR_PLLI2SSRC | 0x80U) /*!< I2S External pin input clock selected as PLLI2S entry clock source */
807 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
808 /**
809 * @}
810 */
811
812 /** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor
813 * @{
814 */
815 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */
816 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */
817 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */
818 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */
819 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */
820 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */
821 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */
822 #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */
823 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */
824 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */
825 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */
826 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */
827 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */
828 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */
829 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */
830 #define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */
831 #define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */
832 #define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */
833 #define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */
834 #define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */
835 #define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */
836 #define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */
837 #define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */
838 #define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */
839 #define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */
840 #define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */
841 #define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */
842 #define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */
843 #define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */
844 #define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */
845 #define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */
846 #define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */
847 #define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */
848 #define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */
849 #define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */
850 #define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */
851 #define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */
852 #define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */
853 #define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */
854 #define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */
855 #define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */
856 #define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */
857 #define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */
858 #define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */
859 #define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */
860 #define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */
861 #define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */
862 #define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */
863 #define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */
864 #define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */
865 #define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */
866 #define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */
867 #define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */
868 #define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */
869 #define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */
870 #define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */
871 #define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */
872 #define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */
873 #define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */
874 #define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */
875 #define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */
876 #define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */
877 /**
878 * @}
879 */
880
881 #if defined(RCC_PLLCFGR_PLLR)
882 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
883 * @{
884 */
885 #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
886 #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
887 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
888 #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
889 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
890 #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
891 /**
892 * @}
893 */
894 #endif /* RCC_PLLCFGR_PLLR */
895
896 #if defined(RCC_DCKCFGR_PLLDIVR)
897 /** @defgroup RCC_LL_EC_PLLDIVR PLLDIVR division factor (PLLDIVR)
898 * @{
899 */
900 #define LL_RCC_PLLDIVR_DIV_1 (RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 1 */
901 #define LL_RCC_PLLDIVR_DIV_2 (RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 2 */
902 #define LL_RCC_PLLDIVR_DIV_3 (RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 3 */
903 #define LL_RCC_PLLDIVR_DIV_4 (RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 4 */
904 #define LL_RCC_PLLDIVR_DIV_5 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 5 */
905 #define LL_RCC_PLLDIVR_DIV_6 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 6 */
906 #define LL_RCC_PLLDIVR_DIV_7 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 7 */
907 #define LL_RCC_PLLDIVR_DIV_8 (RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 8 */
908 #define LL_RCC_PLLDIVR_DIV_9 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 9 */
909 #define LL_RCC_PLLDIVR_DIV_10 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 10 */
910 #define LL_RCC_PLLDIVR_DIV_11 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 11 */
911 #define LL_RCC_PLLDIVR_DIV_12 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 12 */
912 #define LL_RCC_PLLDIVR_DIV_13 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 13 */
913 #define LL_RCC_PLLDIVR_DIV_14 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 14 */
914 #define LL_RCC_PLLDIVR_DIV_15 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 15 */
915 #define LL_RCC_PLLDIVR_DIV_16 (RCC_DCKCFGR_PLLDIVR_4) /*!< PLL division factor for PLLDIVR output by 16 */
916 #define LL_RCC_PLLDIVR_DIV_17 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 17 */
917 #define LL_RCC_PLLDIVR_DIV_18 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 18 */
918 #define LL_RCC_PLLDIVR_DIV_19 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 19 */
919 #define LL_RCC_PLLDIVR_DIV_20 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 20 */
920 #define LL_RCC_PLLDIVR_DIV_21 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 21 */
921 #define LL_RCC_PLLDIVR_DIV_22 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 22 */
922 #define LL_RCC_PLLDIVR_DIV_23 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 23 */
923 #define LL_RCC_PLLDIVR_DIV_24 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 24 */
924 #define LL_RCC_PLLDIVR_DIV_25 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 25 */
925 #define LL_RCC_PLLDIVR_DIV_26 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 26 */
926 #define LL_RCC_PLLDIVR_DIV_27 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 27 */
927 #define LL_RCC_PLLDIVR_DIV_28 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 28 */
928 #define LL_RCC_PLLDIVR_DIV_29 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 29 */
929 #define LL_RCC_PLLDIVR_DIV_30 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 30 */
930 #define LL_RCC_PLLDIVR_DIV_31 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 31 */
931 /**
932 * @}
933 */
934 #endif /* RCC_DCKCFGR_PLLDIVR */
935
936 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
937 * @{
938 */
939 #define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */
940 #define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */
941 #define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */
942 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */
943 /**
944 * @}
945 */
946
947 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
948 * @{
949 */
950 #define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */
951 #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */
952 #define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */
953 #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */
954 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
955 #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */
956 #define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */
957 #define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */
958 #define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */
959 #define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */
960 #define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */
961 #define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */
962 #define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */
963 #define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */
964 /**
965 * @}
966 */
967
968 /** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
969 * @{
970 */
971 #define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */
972 #define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */
973 /**
974 * @}
975 */
976
977 #if defined(RCC_PLLI2S_SUPPORT)
978 /** @defgroup RCC_LL_EC_PLLI2SM PLLI2SM division factor (PLLI2SM)
979 * @{
980 */
981 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
982 #define LL_RCC_PLLI2SM_DIV_2 (RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 2 */
983 #define LL_RCC_PLLI2SM_DIV_3 (RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 3 */
984 #define LL_RCC_PLLI2SM_DIV_4 (RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 4 */
985 #define LL_RCC_PLLI2SM_DIV_5 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 5 */
986 #define LL_RCC_PLLI2SM_DIV_6 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 6 */
987 #define LL_RCC_PLLI2SM_DIV_7 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 7 */
988 #define LL_RCC_PLLI2SM_DIV_8 (RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 8 */
989 #define LL_RCC_PLLI2SM_DIV_9 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 9 */
990 #define LL_RCC_PLLI2SM_DIV_10 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 10 */
991 #define LL_RCC_PLLI2SM_DIV_11 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 11 */
992 #define LL_RCC_PLLI2SM_DIV_12 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 12 */
993 #define LL_RCC_PLLI2SM_DIV_13 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 13 */
994 #define LL_RCC_PLLI2SM_DIV_14 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 14 */
995 #define LL_RCC_PLLI2SM_DIV_15 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 15 */
996 #define LL_RCC_PLLI2SM_DIV_16 (RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 16 */
997 #define LL_RCC_PLLI2SM_DIV_17 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 17 */
998 #define LL_RCC_PLLI2SM_DIV_18 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 18 */
999 #define LL_RCC_PLLI2SM_DIV_19 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 19 */
1000 #define LL_RCC_PLLI2SM_DIV_20 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 20 */
1001 #define LL_RCC_PLLI2SM_DIV_21 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 21 */
1002 #define LL_RCC_PLLI2SM_DIV_22 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 22 */
1003 #define LL_RCC_PLLI2SM_DIV_23 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 23 */
1004 #define LL_RCC_PLLI2SM_DIV_24 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 24 */
1005 #define LL_RCC_PLLI2SM_DIV_25 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 25 */
1006 #define LL_RCC_PLLI2SM_DIV_26 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 26 */
1007 #define LL_RCC_PLLI2SM_DIV_27 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 27 */
1008 #define LL_RCC_PLLI2SM_DIV_28 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 28 */
1009 #define LL_RCC_PLLI2SM_DIV_29 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 29 */
1010 #define LL_RCC_PLLI2SM_DIV_30 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 30 */
1011 #define LL_RCC_PLLI2SM_DIV_31 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 31 */
1012 #define LL_RCC_PLLI2SM_DIV_32 (RCC_PLLI2SCFGR_PLLI2SM_5) /*!< PLLI2S division factor for PLLI2SM output by 32 */
1013 #define LL_RCC_PLLI2SM_DIV_33 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 33 */
1014 #define LL_RCC_PLLI2SM_DIV_34 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 34 */
1015 #define LL_RCC_PLLI2SM_DIV_35 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 35 */
1016 #define LL_RCC_PLLI2SM_DIV_36 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 36 */
1017 #define LL_RCC_PLLI2SM_DIV_37 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 37 */
1018 #define LL_RCC_PLLI2SM_DIV_38 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 38 */
1019 #define LL_RCC_PLLI2SM_DIV_39 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 39 */
1020 #define LL_RCC_PLLI2SM_DIV_40 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 40 */
1021 #define LL_RCC_PLLI2SM_DIV_41 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 41 */
1022 #define LL_RCC_PLLI2SM_DIV_42 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 42 */
1023 #define LL_RCC_PLLI2SM_DIV_43 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 43 */
1024 #define LL_RCC_PLLI2SM_DIV_44 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 44 */
1025 #define LL_RCC_PLLI2SM_DIV_45 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 45 */
1026 #define LL_RCC_PLLI2SM_DIV_46 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 46 */
1027 #define LL_RCC_PLLI2SM_DIV_47 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 47 */
1028 #define LL_RCC_PLLI2SM_DIV_48 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 48 */
1029 #define LL_RCC_PLLI2SM_DIV_49 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 49 */
1030 #define LL_RCC_PLLI2SM_DIV_50 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 50 */
1031 #define LL_RCC_PLLI2SM_DIV_51 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 51 */
1032 #define LL_RCC_PLLI2SM_DIV_52 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 52 */
1033 #define LL_RCC_PLLI2SM_DIV_53 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 53 */
1034 #define LL_RCC_PLLI2SM_DIV_54 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 54 */
1035 #define LL_RCC_PLLI2SM_DIV_55 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 55 */
1036 #define LL_RCC_PLLI2SM_DIV_56 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 56 */
1037 #define LL_RCC_PLLI2SM_DIV_57 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 57 */
1038 #define LL_RCC_PLLI2SM_DIV_58 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 58 */
1039 #define LL_RCC_PLLI2SM_DIV_59 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 59 */
1040 #define LL_RCC_PLLI2SM_DIV_60 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 60 */
1041 #define LL_RCC_PLLI2SM_DIV_61 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 61 */
1042 #define LL_RCC_PLLI2SM_DIV_62 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 62 */
1043 #define LL_RCC_PLLI2SM_DIV_63 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 63 */
1044 #else
1045 #define LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLI2S division factor for PLLI2SM output by 2 */
1046 #define LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLI2S division factor for PLLI2SM output by 3 */
1047 #define LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLI2S division factor for PLLI2SM output by 4 */
1048 #define LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLI2S division factor for PLLI2SM output by 5 */
1049 #define LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLI2S division factor for PLLI2SM output by 6 */
1050 #define LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLI2S division factor for PLLI2SM output by 7 */
1051 #define LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLI2S division factor for PLLI2SM output by 8 */
1052 #define LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLI2S division factor for PLLI2SM output by 9 */
1053 #define LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLI2S division factor for PLLI2SM output by 10 */
1054 #define LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLI2S division factor for PLLI2SM output by 11 */
1055 #define LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLI2S division factor for PLLI2SM output by 12 */
1056 #define LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLI2S division factor for PLLI2SM output by 13 */
1057 #define LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLI2S division factor for PLLI2SM output by 14 */
1058 #define LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLI2S division factor for PLLI2SM output by 15 */
1059 #define LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLI2S division factor for PLLI2SM output by 16 */
1060 #define LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLI2S division factor for PLLI2SM output by 17 */
1061 #define LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLI2S division factor for PLLI2SM output by 18 */
1062 #define LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLI2S division factor for PLLI2SM output by 19 */
1063 #define LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLI2S division factor for PLLI2SM output by 20 */
1064 #define LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLI2S division factor for PLLI2SM output by 21 */
1065 #define LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLI2S division factor for PLLI2SM output by 22 */
1066 #define LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLI2S division factor for PLLI2SM output by 23 */
1067 #define LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLI2S division factor for PLLI2SM output by 24 */
1068 #define LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLI2S division factor for PLLI2SM output by 25 */
1069 #define LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLI2S division factor for PLLI2SM output by 26 */
1070 #define LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLI2S division factor for PLLI2SM output by 27 */
1071 #define LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLI2S division factor for PLLI2SM output by 28 */
1072 #define LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLI2S division factor for PLLI2SM output by 29 */
1073 #define LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLI2S division factor for PLLI2SM output by 30 */
1074 #define LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLI2S division factor for PLLI2SM output by 31 */
1075 #define LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLI2S division factor for PLLI2SM output by 32 */
1076 #define LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLI2S division factor for PLLI2SM output by 33 */
1077 #define LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLI2S division factor for PLLI2SM output by 34 */
1078 #define LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLI2S division factor for PLLI2SM output by 35 */
1079 #define LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLI2S division factor for PLLI2SM output by 36 */
1080 #define LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLI2S division factor for PLLI2SM output by 37 */
1081 #define LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLI2S division factor for PLLI2SM output by 38 */
1082 #define LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLI2S division factor for PLLI2SM output by 39 */
1083 #define LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLI2S division factor for PLLI2SM output by 40 */
1084 #define LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLI2S division factor for PLLI2SM output by 41 */
1085 #define LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLI2S division factor for PLLI2SM output by 42 */
1086 #define LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLI2S division factor for PLLI2SM output by 43 */
1087 #define LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLI2S division factor for PLLI2SM output by 44 */
1088 #define LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLI2S division factor for PLLI2SM output by 45 */
1089 #define LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLI2S division factor for PLLI2SM output by 46 */
1090 #define LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLI2S division factor for PLLI2SM output by 47 */
1091 #define LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLI2S division factor for PLLI2SM output by 48 */
1092 #define LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLI2S division factor for PLLI2SM output by 49 */
1093 #define LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLI2S division factor for PLLI2SM output by 50 */
1094 #define LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLI2S division factor for PLLI2SM output by 51 */
1095 #define LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLI2S division factor for PLLI2SM output by 52 */
1096 #define LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLI2S division factor for PLLI2SM output by 53 */
1097 #define LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLI2S division factor for PLLI2SM output by 54 */
1098 #define LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLI2S division factor for PLLI2SM output by 55 */
1099 #define LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLI2S division factor for PLLI2SM output by 56 */
1100 #define LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLI2S division factor for PLLI2SM output by 57 */
1101 #define LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLI2S division factor for PLLI2SM output by 58 */
1102 #define LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLI2S division factor for PLLI2SM output by 59 */
1103 #define LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLI2S division factor for PLLI2SM output by 60 */
1104 #define LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLI2S division factor for PLLI2SM output by 61 */
1105 #define LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLI2S division factor for PLLI2SM output by 62 */
1106 #define LL_RCC_PLLI2SM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLI2S division factor for PLLI2SM output by 63 */
1107 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
1108 /**
1109 * @}
1110 */
1111
1112 #if defined(RCC_PLLI2SCFGR_PLLI2SQ)
1113 /** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ)
1114 * @{
1115 */
1116 #define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division factor for PLLI2SQ output by 2 */
1117 #define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 3 */
1118 #define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division factor for PLLI2SQ output by 4 */
1119 #define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 5 */
1120 #define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 6 */
1121 #define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 7 */
1122 #define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division factor for PLLI2SQ output by 8 */
1123 #define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 9 */
1124 #define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 10 */
1125 #define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 11 */
1126 #define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) /*!< PLLI2S division factor for PLLI2SQ output by 12 */
1127 #define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 13 */
1128 #define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 14 */
1129 #define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 15 */
1130 /**
1131 * @}
1132 */
1133 #endif /* RCC_PLLI2SCFGR_PLLI2SQ */
1134
1135 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
1136 /** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ)
1137 * @{
1138 */
1139 #define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */
1140 #define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR_PLLI2SDIVQ_0 /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */
1141 #define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR_PLLI2SDIVQ_1 /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */
1142 #define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */
1143 #define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR_PLLI2SDIVQ_2 /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */
1144 #define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */
1145 #define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */
1146 #define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */
1147 #define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR_PLLI2SDIVQ_3 /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */
1148 #define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */
1149 #define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */
1150 #define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */
1151 #define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */
1152 #define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */
1153 #define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */
1154 #define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */
1155 #define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR_PLLI2SDIVQ_4 /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */
1156 #define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */
1157 #define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */
1158 #define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */
1159 #define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */
1160 #define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */
1161 #define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */
1162 #define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */
1163 #define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3) /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */
1164 #define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */
1165 #define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */
1166 #define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */
1167 #define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */
1168 #define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */
1169 #define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */
1170 #define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */
1171 /**
1172 * @}
1173 */
1174 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
1175
1176 #if defined(RCC_DCKCFGR_PLLI2SDIVR)
1177 /** @defgroup RCC_LL_EC_PLLI2SDIVR PLLI2SDIVR division factor (PLLI2SDIVR)
1178 * @{
1179 */
1180 #define LL_RCC_PLLI2SDIVR_DIV_1 (RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 1 */
1181 #define LL_RCC_PLLI2SDIVR_DIV_2 (RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 2 */
1182 #define LL_RCC_PLLI2SDIVR_DIV_3 (RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 3 */
1183 #define LL_RCC_PLLI2SDIVR_DIV_4 (RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 4 */
1184 #define LL_RCC_PLLI2SDIVR_DIV_5 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 5 */
1185 #define LL_RCC_PLLI2SDIVR_DIV_6 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 6 */
1186 #define LL_RCC_PLLI2SDIVR_DIV_7 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 7 */
1187 #define LL_RCC_PLLI2SDIVR_DIV_8 (RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 8 */
1188 #define LL_RCC_PLLI2SDIVR_DIV_9 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 9 */
1189 #define LL_RCC_PLLI2SDIVR_DIV_10 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 10 */
1190 #define LL_RCC_PLLI2SDIVR_DIV_11 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 11 */
1191 #define LL_RCC_PLLI2SDIVR_DIV_12 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 12 */
1192 #define LL_RCC_PLLI2SDIVR_DIV_13 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 13 */
1193 #define LL_RCC_PLLI2SDIVR_DIV_14 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 14 */
1194 #define LL_RCC_PLLI2SDIVR_DIV_15 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 15 */
1195 #define LL_RCC_PLLI2SDIVR_DIV_16 (RCC_DCKCFGR_PLLI2SDIVR_4) /*!< PLLI2S division factor for PLLI2SDIVR output by 16 */
1196 #define LL_RCC_PLLI2SDIVR_DIV_17 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 17 */
1197 #define LL_RCC_PLLI2SDIVR_DIV_18 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 18 */
1198 #define LL_RCC_PLLI2SDIVR_DIV_19 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 19 */
1199 #define LL_RCC_PLLI2SDIVR_DIV_20 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 20 */
1200 #define LL_RCC_PLLI2SDIVR_DIV_21 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 21 */
1201 #define LL_RCC_PLLI2SDIVR_DIV_22 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 22 */
1202 #define LL_RCC_PLLI2SDIVR_DIV_23 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 23 */
1203 #define LL_RCC_PLLI2SDIVR_DIV_24 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 24 */
1204 #define LL_RCC_PLLI2SDIVR_DIV_25 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 25 */
1205 #define LL_RCC_PLLI2SDIVR_DIV_26 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 26 */
1206 #define LL_RCC_PLLI2SDIVR_DIV_27 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 27 */
1207 #define LL_RCC_PLLI2SDIVR_DIV_28 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 28 */
1208 #define LL_RCC_PLLI2SDIVR_DIV_29 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 29 */
1209 #define LL_RCC_PLLI2SDIVR_DIV_30 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 30 */
1210 #define LL_RCC_PLLI2SDIVR_DIV_31 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 31 */
1211 /**
1212 * @}
1213 */
1214 #endif /* RCC_DCKCFGR_PLLI2SDIVR */
1215
1216 /** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
1217 * @{
1218 */
1219 #define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */
1220 #define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */
1221 #define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */
1222 #define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */
1223 #define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */
1224 #define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */
1225 /**
1226 * @}
1227 */
1228
1229 #if defined(RCC_PLLI2SCFGR_PLLI2SP)
1230 /** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP)
1231 * @{
1232 */
1233 #define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PLLI2SP output by 2 */
1234 #define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division factor for PLLI2SP output by 4 */
1235 #define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division factor for PLLI2SP output by 6 */
1236 #define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) /*!< PLLI2S division factor for PLLI2SP output by 8 */
1237 /**
1238 * @}
1239 */
1240 #endif /* RCC_PLLI2SCFGR_PLLI2SP */
1241 #endif /* RCC_PLLI2S_SUPPORT */
1242
1243 #if defined(RCC_PLLSAI_SUPPORT)
1244 /** @defgroup RCC_LL_EC_PLLSAIM PLLSAIM division factor (PLLSAIM or PLLM)
1245 * @{
1246 */
1247 #if defined(RCC_PLLSAICFGR_PLLSAIM)
1248 #define LL_RCC_PLLSAIM_DIV_2 (RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 2 */
1249 #define LL_RCC_PLLSAIM_DIV_3 (RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 3 */
1250 #define LL_RCC_PLLSAIM_DIV_4 (RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 4 */
1251 #define LL_RCC_PLLSAIM_DIV_5 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 5 */
1252 #define LL_RCC_PLLSAIM_DIV_6 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 6 */
1253 #define LL_RCC_PLLSAIM_DIV_7 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 7 */
1254 #define LL_RCC_PLLSAIM_DIV_8 (RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 8 */
1255 #define LL_RCC_PLLSAIM_DIV_9 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 9 */
1256 #define LL_RCC_PLLSAIM_DIV_10 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 10 */
1257 #define LL_RCC_PLLSAIM_DIV_11 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 11 */
1258 #define LL_RCC_PLLSAIM_DIV_12 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 12 */
1259 #define LL_RCC_PLLSAIM_DIV_13 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 13 */
1260 #define LL_RCC_PLLSAIM_DIV_14 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 14 */
1261 #define LL_RCC_PLLSAIM_DIV_15 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 15 */
1262 #define LL_RCC_PLLSAIM_DIV_16 (RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 16 */
1263 #define LL_RCC_PLLSAIM_DIV_17 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 17 */
1264 #define LL_RCC_PLLSAIM_DIV_18 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 18 */
1265 #define LL_RCC_PLLSAIM_DIV_19 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 19 */
1266 #define LL_RCC_PLLSAIM_DIV_20 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 20 */
1267 #define LL_RCC_PLLSAIM_DIV_21 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 21 */
1268 #define LL_RCC_PLLSAIM_DIV_22 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 22 */
1269 #define LL_RCC_PLLSAIM_DIV_23 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 23 */
1270 #define LL_RCC_PLLSAIM_DIV_24 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 24 */
1271 #define LL_RCC_PLLSAIM_DIV_25 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 25 */
1272 #define LL_RCC_PLLSAIM_DIV_26 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 26 */
1273 #define LL_RCC_PLLSAIM_DIV_27 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 27 */
1274 #define LL_RCC_PLLSAIM_DIV_28 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 28 */
1275 #define LL_RCC_PLLSAIM_DIV_29 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 29 */
1276 #define LL_RCC_PLLSAIM_DIV_30 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 30 */
1277 #define LL_RCC_PLLSAIM_DIV_31 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 31 */
1278 #define LL_RCC_PLLSAIM_DIV_32 (RCC_PLLSAICFGR_PLLSAIM_5) /*!< PLLSAI division factor for PLLSAIM output by 32 */
1279 #define LL_RCC_PLLSAIM_DIV_33 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 33 */
1280 #define LL_RCC_PLLSAIM_DIV_34 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 34 */
1281 #define LL_RCC_PLLSAIM_DIV_35 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 35 */
1282 #define LL_RCC_PLLSAIM_DIV_36 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 36 */
1283 #define LL_RCC_PLLSAIM_DIV_37 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 37 */
1284 #define LL_RCC_PLLSAIM_DIV_38 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 38 */
1285 #define LL_RCC_PLLSAIM_DIV_39 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 39 */
1286 #define LL_RCC_PLLSAIM_DIV_40 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 40 */
1287 #define LL_RCC_PLLSAIM_DIV_41 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 41 */
1288 #define LL_RCC_PLLSAIM_DIV_42 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 42 */
1289 #define LL_RCC_PLLSAIM_DIV_43 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 43 */
1290 #define LL_RCC_PLLSAIM_DIV_44 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 44 */
1291 #define LL_RCC_PLLSAIM_DIV_45 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 45 */
1292 #define LL_RCC_PLLSAIM_DIV_46 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 46 */
1293 #define LL_RCC_PLLSAIM_DIV_47 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 47 */
1294 #define LL_RCC_PLLSAIM_DIV_48 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 48 */
1295 #define LL_RCC_PLLSAIM_DIV_49 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 49 */
1296 #define LL_RCC_PLLSAIM_DIV_50 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 50 */
1297 #define LL_RCC_PLLSAIM_DIV_51 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 51 */
1298 #define LL_RCC_PLLSAIM_DIV_52 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 52 */
1299 #define LL_RCC_PLLSAIM_DIV_53 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 53 */
1300 #define LL_RCC_PLLSAIM_DIV_54 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 54 */
1301 #define LL_RCC_PLLSAIM_DIV_55 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 55 */
1302 #define LL_RCC_PLLSAIM_DIV_56 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 56 */
1303 #define LL_RCC_PLLSAIM_DIV_57 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 57 */
1304 #define LL_RCC_PLLSAIM_DIV_58 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 58 */
1305 #define LL_RCC_PLLSAIM_DIV_59 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 59 */
1306 #define LL_RCC_PLLSAIM_DIV_60 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 60 */
1307 #define LL_RCC_PLLSAIM_DIV_61 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 61 */
1308 #define LL_RCC_PLLSAIM_DIV_62 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 62 */
1309 #define LL_RCC_PLLSAIM_DIV_63 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 63 */
1310 #else
1311 #define LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLSAI division factor for PLLSAIM output by 2 */
1312 #define LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLSAI division factor for PLLSAIM output by 3 */
1313 #define LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLSAI division factor for PLLSAIM output by 4 */
1314 #define LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLSAI division factor for PLLSAIM output by 5 */
1315 #define LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLSAI division factor for PLLSAIM output by 6 */
1316 #define LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLSAI division factor for PLLSAIM output by 7 */
1317 #define LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLSAI division factor for PLLSAIM output by 8 */
1318 #define LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLSAI division factor for PLLSAIM output by 9 */
1319 #define LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLSAI division factor for PLLSAIM output by 10 */
1320 #define LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLSAI division factor for PLLSAIM output by 11 */
1321 #define LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLSAI division factor for PLLSAIM output by 12 */
1322 #define LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLSAI division factor for PLLSAIM output by 13 */
1323 #define LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLSAI division factor for PLLSAIM output by 14 */
1324 #define LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLSAI division factor for PLLSAIM output by 15 */
1325 #define LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLSAI division factor for PLLSAIM output by 16 */
1326 #define LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLSAI division factor for PLLSAIM output by 17 */
1327 #define LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLSAI division factor for PLLSAIM output by 18 */
1328 #define LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLSAI division factor for PLLSAIM output by 19 */
1329 #define LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLSAI division factor for PLLSAIM output by 20 */
1330 #define LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLSAI division factor for PLLSAIM output by 21 */
1331 #define LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLSAI division factor for PLLSAIM output by 22 */
1332 #define LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLSAI division factor for PLLSAIM output by 23 */
1333 #define LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLSAI division factor for PLLSAIM output by 24 */
1334 #define LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLSAI division factor for PLLSAIM output by 25 */
1335 #define LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLSAI division factor for PLLSAIM output by 26 */
1336 #define LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLSAI division factor for PLLSAIM output by 27 */
1337 #define LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLSAI division factor for PLLSAIM output by 28 */
1338 #define LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLSAI division factor for PLLSAIM output by 29 */
1339 #define LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLSAI division factor for PLLSAIM output by 30 */
1340 #define LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLSAI division factor for PLLSAIM output by 31 */
1341 #define LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLSAI division factor for PLLSAIM output by 32 */
1342 #define LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLSAI division factor for PLLSAIM output by 33 */
1343 #define LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLSAI division factor for PLLSAIM output by 34 */
1344 #define LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLSAI division factor for PLLSAIM output by 35 */
1345 #define LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLSAI division factor for PLLSAIM output by 36 */
1346 #define LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLSAI division factor for PLLSAIM output by 37 */
1347 #define LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLSAI division factor for PLLSAIM output by 38 */
1348 #define LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLSAI division factor for PLLSAIM output by 39 */
1349 #define LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLSAI division factor for PLLSAIM output by 40 */
1350 #define LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLSAI division factor for PLLSAIM output by 41 */
1351 #define LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLSAI division factor for PLLSAIM output by 42 */
1352 #define LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLSAI division factor for PLLSAIM output by 43 */
1353 #define LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLSAI division factor for PLLSAIM output by 44 */
1354 #define LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLSAI division factor for PLLSAIM output by 45 */
1355 #define LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLSAI division factor for PLLSAIM output by 46 */
1356 #define LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLSAI division factor for PLLSAIM output by 47 */
1357 #define LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLSAI division factor for PLLSAIM output by 48 */
1358 #define LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLSAI division factor for PLLSAIM output by 49 */
1359 #define LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLSAI division factor for PLLSAIM output by 50 */
1360 #define LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLSAI division factor for PLLSAIM output by 51 */
1361 #define LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLSAI division factor for PLLSAIM output by 52 */
1362 #define LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLSAI division factor for PLLSAIM output by 53 */
1363 #define LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLSAI division factor for PLLSAIM output by 54 */
1364 #define LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLSAI division factor for PLLSAIM output by 55 */
1365 #define LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLSAI division factor for PLLSAIM output by 56 */
1366 #define LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLSAI division factor for PLLSAIM output by 57 */
1367 #define LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLSAI division factor for PLLSAIM output by 58 */
1368 #define LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLSAI division factor for PLLSAIM output by 59 */
1369 #define LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLSAI division factor for PLLSAIM output by 60 */
1370 #define LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLSAI division factor for PLLSAIM output by 61 */
1371 #define LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLSAI division factor for PLLSAIM output by 62 */
1372 #define LL_RCC_PLLSAIM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLSAI division factor for PLLSAIM output by 63 */
1373 #endif /* RCC_PLLSAICFGR_PLLSAIM */
1374 /**
1375 * @}
1376 */
1377
1378 /** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ)
1379 * @{
1380 */
1381 #define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division factor for PLLSAIQ output by 2 */
1382 #define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 3 */
1383 #define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division factor for PLLSAIQ output by 4 */
1384 #define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 5 */
1385 #define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 6 */
1386 #define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 7 */
1387 #define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division factor for PLLSAIQ output by 8 */
1388 #define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 9 */
1389 #define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 10 */
1390 #define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 11 */
1391 #define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) /*!< PLLSAI division factor for PLLSAIQ output by 12 */
1392 #define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 13 */
1393 #define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 14 */
1394 #define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 15 */
1395 /**
1396 * @}
1397 */
1398
1399 #if defined(RCC_DCKCFGR_PLLSAIDIVQ)
1400 /** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ)
1401 * @{
1402 */
1403 #define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */
1404 #define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR_PLLSAIDIVQ_0 /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */
1405 #define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR_PLLSAIDIVQ_1 /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */
1406 #define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */
1407 #define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR_PLLSAIDIVQ_2 /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */
1408 #define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */
1409 #define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */
1410 #define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */
1411 #define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR_PLLSAIDIVQ_3 /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */
1412 #define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */
1413 #define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */
1414 #define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */
1415 #define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */
1416 #define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */
1417 #define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */
1418 #define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */
1419 #define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR_PLLSAIDIVQ_4 /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */
1420 #define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */
1421 #define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */
1422 #define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */
1423 #define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */
1424 #define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */
1425 #define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */
1426 #define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */
1427 #define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3) /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */
1428 #define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */
1429 #define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */
1430 #define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */
1431 #define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */
1432 #define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */
1433 #define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */
1434 #define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */
1435 /**
1436 * @}
1437 */
1438 #endif /* RCC_DCKCFGR_PLLSAIDIVQ */
1439
1440 #if defined(RCC_PLLSAICFGR_PLLSAIR)
1441 /** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR)
1442 * @{
1443 */
1444 #define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /*!< PLLSAI division factor for PLLSAIR output by 2 */
1445 #define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 3 */
1446 #define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /*!< PLLSAI division factor for PLLSAIR output by 4 */
1447 #define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 5 */
1448 #define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) /*!< PLLSAI division factor for PLLSAIR output by 6 */
1449 #define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 7 */
1450 /**
1451 * @}
1452 */
1453 #endif /* RCC_PLLSAICFGR_PLLSAIR */
1454
1455 #if defined(RCC_DCKCFGR_PLLSAIDIVR)
1456 /** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR)
1457 * @{
1458 */
1459 #define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */
1460 #define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR_PLLSAIDIVR_0 /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */
1461 #define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR_PLLSAIDIVR_1 /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */
1462 #define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0) /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */
1463 /**
1464 * @}
1465 */
1466 #endif /* RCC_DCKCFGR_PLLSAIDIVR */
1467
1468 #if defined(RCC_PLLSAICFGR_PLLSAIP)
1469 /** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP)
1470 * @{
1471 */
1472 #define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIP output by 2 */
1473 #define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division factor for PLLSAIP output by 4 */
1474 #define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division factor for PLLSAIP output by 6 */
1475 #define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) /*!< PLLSAI division factor for PLLSAIP output by 8 */
1476 /**
1477 * @}
1478 */
1479 #endif /* RCC_PLLSAICFGR_PLLSAIP */
1480 #endif /* RCC_PLLSAI_SUPPORT */
1481 /**
1482 * @}
1483 */
1484
1485 /* Exported macro ------------------------------------------------------------*/
1486 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1487 * @{
1488 */
1489
1490 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1491 * @{
1492 */
1493
1494 /**
1495 * @brief Write a value in RCC register
1496 * @param __REG__ Register to be written
1497 * @param __VALUE__ Value to be written in the register
1498 * @retval None
1499 */
1500 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1501
1502 /**
1503 * @brief Read a value in RCC register
1504 * @param __REG__ Register to be read
1505 * @retval Register value
1506 */
1507 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1508 /**
1509 * @}
1510 */
1511
1512 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1513 * @{
1514 */
1515
1516 /**
1517 * @brief Helper macro to calculate the PLLCLK frequency on system domain
1518 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1519 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
1520 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1521 * @param __PLLM__ This parameter can be one of the following values:
1522 * @arg @ref LL_RCC_PLLM_DIV_2
1523 * @arg @ref LL_RCC_PLLM_DIV_3
1524 * @arg @ref LL_RCC_PLLM_DIV_4
1525 * @arg @ref LL_RCC_PLLM_DIV_5
1526 * @arg @ref LL_RCC_PLLM_DIV_6
1527 * @arg @ref LL_RCC_PLLM_DIV_7
1528 * @arg @ref LL_RCC_PLLM_DIV_8
1529 * @arg @ref LL_RCC_PLLM_DIV_9
1530 * @arg @ref LL_RCC_PLLM_DIV_10
1531 * @arg @ref LL_RCC_PLLM_DIV_11
1532 * @arg @ref LL_RCC_PLLM_DIV_12
1533 * @arg @ref LL_RCC_PLLM_DIV_13
1534 * @arg @ref LL_RCC_PLLM_DIV_14
1535 * @arg @ref LL_RCC_PLLM_DIV_15
1536 * @arg @ref LL_RCC_PLLM_DIV_16
1537 * @arg @ref LL_RCC_PLLM_DIV_17
1538 * @arg @ref LL_RCC_PLLM_DIV_18
1539 * @arg @ref LL_RCC_PLLM_DIV_19
1540 * @arg @ref LL_RCC_PLLM_DIV_20
1541 * @arg @ref LL_RCC_PLLM_DIV_21
1542 * @arg @ref LL_RCC_PLLM_DIV_22
1543 * @arg @ref LL_RCC_PLLM_DIV_23
1544 * @arg @ref LL_RCC_PLLM_DIV_24
1545 * @arg @ref LL_RCC_PLLM_DIV_25
1546 * @arg @ref LL_RCC_PLLM_DIV_26
1547 * @arg @ref LL_RCC_PLLM_DIV_27
1548 * @arg @ref LL_RCC_PLLM_DIV_28
1549 * @arg @ref LL_RCC_PLLM_DIV_29
1550 * @arg @ref LL_RCC_PLLM_DIV_30
1551 * @arg @ref LL_RCC_PLLM_DIV_31
1552 * @arg @ref LL_RCC_PLLM_DIV_32
1553 * @arg @ref LL_RCC_PLLM_DIV_33
1554 * @arg @ref LL_RCC_PLLM_DIV_34
1555 * @arg @ref LL_RCC_PLLM_DIV_35
1556 * @arg @ref LL_RCC_PLLM_DIV_36
1557 * @arg @ref LL_RCC_PLLM_DIV_37
1558 * @arg @ref LL_RCC_PLLM_DIV_38
1559 * @arg @ref LL_RCC_PLLM_DIV_39
1560 * @arg @ref LL_RCC_PLLM_DIV_40
1561 * @arg @ref LL_RCC_PLLM_DIV_41
1562 * @arg @ref LL_RCC_PLLM_DIV_42
1563 * @arg @ref LL_RCC_PLLM_DIV_43
1564 * @arg @ref LL_RCC_PLLM_DIV_44
1565 * @arg @ref LL_RCC_PLLM_DIV_45
1566 * @arg @ref LL_RCC_PLLM_DIV_46
1567 * @arg @ref LL_RCC_PLLM_DIV_47
1568 * @arg @ref LL_RCC_PLLM_DIV_48
1569 * @arg @ref LL_RCC_PLLM_DIV_49
1570 * @arg @ref LL_RCC_PLLM_DIV_50
1571 * @arg @ref LL_RCC_PLLM_DIV_51
1572 * @arg @ref LL_RCC_PLLM_DIV_52
1573 * @arg @ref LL_RCC_PLLM_DIV_53
1574 * @arg @ref LL_RCC_PLLM_DIV_54
1575 * @arg @ref LL_RCC_PLLM_DIV_55
1576 * @arg @ref LL_RCC_PLLM_DIV_56
1577 * @arg @ref LL_RCC_PLLM_DIV_57
1578 * @arg @ref LL_RCC_PLLM_DIV_58
1579 * @arg @ref LL_RCC_PLLM_DIV_59
1580 * @arg @ref LL_RCC_PLLM_DIV_60
1581 * @arg @ref LL_RCC_PLLM_DIV_61
1582 * @arg @ref LL_RCC_PLLM_DIV_62
1583 * @arg @ref LL_RCC_PLLM_DIV_63
1584 * @param __PLLN__ Between 50/192(*) and 432
1585 *
1586 * (*) value not defined in all devices.
1587 * @param __PLLP__ This parameter can be one of the following values:
1588 * @arg @ref LL_RCC_PLLP_DIV_2
1589 * @arg @ref LL_RCC_PLLP_DIV_4
1590 * @arg @ref LL_RCC_PLLP_DIV_6
1591 * @arg @ref LL_RCC_PLLP_DIV_8
1592 * @retval PLL clock frequency (in Hz)
1593 */
1594 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1595 ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
1596
1597 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
1598 /**
1599 * @brief Helper macro to calculate the PLLRCLK frequency on system domain
1600 * @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1601 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1602 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1603 * @param __PLLM__ This parameter can be one of the following values:
1604 * @arg @ref LL_RCC_PLLM_DIV_2
1605 * @arg @ref LL_RCC_PLLM_DIV_3
1606 * @arg @ref LL_RCC_PLLM_DIV_4
1607 * @arg @ref LL_RCC_PLLM_DIV_5
1608 * @arg @ref LL_RCC_PLLM_DIV_6
1609 * @arg @ref LL_RCC_PLLM_DIV_7
1610 * @arg @ref LL_RCC_PLLM_DIV_8
1611 * @arg @ref LL_RCC_PLLM_DIV_9
1612 * @arg @ref LL_RCC_PLLM_DIV_10
1613 * @arg @ref LL_RCC_PLLM_DIV_11
1614 * @arg @ref LL_RCC_PLLM_DIV_12
1615 * @arg @ref LL_RCC_PLLM_DIV_13
1616 * @arg @ref LL_RCC_PLLM_DIV_14
1617 * @arg @ref LL_RCC_PLLM_DIV_15
1618 * @arg @ref LL_RCC_PLLM_DIV_16
1619 * @arg @ref LL_RCC_PLLM_DIV_17
1620 * @arg @ref LL_RCC_PLLM_DIV_18
1621 * @arg @ref LL_RCC_PLLM_DIV_19
1622 * @arg @ref LL_RCC_PLLM_DIV_20
1623 * @arg @ref LL_RCC_PLLM_DIV_21
1624 * @arg @ref LL_RCC_PLLM_DIV_22
1625 * @arg @ref LL_RCC_PLLM_DIV_23
1626 * @arg @ref LL_RCC_PLLM_DIV_24
1627 * @arg @ref LL_RCC_PLLM_DIV_25
1628 * @arg @ref LL_RCC_PLLM_DIV_26
1629 * @arg @ref LL_RCC_PLLM_DIV_27
1630 * @arg @ref LL_RCC_PLLM_DIV_28
1631 * @arg @ref LL_RCC_PLLM_DIV_29
1632 * @arg @ref LL_RCC_PLLM_DIV_30
1633 * @arg @ref LL_RCC_PLLM_DIV_31
1634 * @arg @ref LL_RCC_PLLM_DIV_32
1635 * @arg @ref LL_RCC_PLLM_DIV_33
1636 * @arg @ref LL_RCC_PLLM_DIV_34
1637 * @arg @ref LL_RCC_PLLM_DIV_35
1638 * @arg @ref LL_RCC_PLLM_DIV_36
1639 * @arg @ref LL_RCC_PLLM_DIV_37
1640 * @arg @ref LL_RCC_PLLM_DIV_38
1641 * @arg @ref LL_RCC_PLLM_DIV_39
1642 * @arg @ref LL_RCC_PLLM_DIV_40
1643 * @arg @ref LL_RCC_PLLM_DIV_41
1644 * @arg @ref LL_RCC_PLLM_DIV_42
1645 * @arg @ref LL_RCC_PLLM_DIV_43
1646 * @arg @ref LL_RCC_PLLM_DIV_44
1647 * @arg @ref LL_RCC_PLLM_DIV_45
1648 * @arg @ref LL_RCC_PLLM_DIV_46
1649 * @arg @ref LL_RCC_PLLM_DIV_47
1650 * @arg @ref LL_RCC_PLLM_DIV_48
1651 * @arg @ref LL_RCC_PLLM_DIV_49
1652 * @arg @ref LL_RCC_PLLM_DIV_50
1653 * @arg @ref LL_RCC_PLLM_DIV_51
1654 * @arg @ref LL_RCC_PLLM_DIV_52
1655 * @arg @ref LL_RCC_PLLM_DIV_53
1656 * @arg @ref LL_RCC_PLLM_DIV_54
1657 * @arg @ref LL_RCC_PLLM_DIV_55
1658 * @arg @ref LL_RCC_PLLM_DIV_56
1659 * @arg @ref LL_RCC_PLLM_DIV_57
1660 * @arg @ref LL_RCC_PLLM_DIV_58
1661 * @arg @ref LL_RCC_PLLM_DIV_59
1662 * @arg @ref LL_RCC_PLLM_DIV_60
1663 * @arg @ref LL_RCC_PLLM_DIV_61
1664 * @arg @ref LL_RCC_PLLM_DIV_62
1665 * @arg @ref LL_RCC_PLLM_DIV_63
1666 * @param __PLLN__ Between 50 and 432
1667 * @param __PLLR__ This parameter can be one of the following values:
1668 * @arg @ref LL_RCC_PLLR_DIV_2
1669 * @arg @ref LL_RCC_PLLR_DIV_3
1670 * @arg @ref LL_RCC_PLLR_DIV_4
1671 * @arg @ref LL_RCC_PLLR_DIV_5
1672 * @arg @ref LL_RCC_PLLR_DIV_6
1673 * @arg @ref LL_RCC_PLLR_DIV_7
1674 * @retval PLL clock frequency (in Hz)
1675 */
1676 #define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1677 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1678
1679 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
1680
1681 /**
1682 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
1683 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1684 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1685 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1686 * @param __PLLM__ This parameter can be one of the following values:
1687 * @arg @ref LL_RCC_PLLM_DIV_2
1688 * @arg @ref LL_RCC_PLLM_DIV_3
1689 * @arg @ref LL_RCC_PLLM_DIV_4
1690 * @arg @ref LL_RCC_PLLM_DIV_5
1691 * @arg @ref LL_RCC_PLLM_DIV_6
1692 * @arg @ref LL_RCC_PLLM_DIV_7
1693 * @arg @ref LL_RCC_PLLM_DIV_8
1694 * @arg @ref LL_RCC_PLLM_DIV_9
1695 * @arg @ref LL_RCC_PLLM_DIV_10
1696 * @arg @ref LL_RCC_PLLM_DIV_11
1697 * @arg @ref LL_RCC_PLLM_DIV_12
1698 * @arg @ref LL_RCC_PLLM_DIV_13
1699 * @arg @ref LL_RCC_PLLM_DIV_14
1700 * @arg @ref LL_RCC_PLLM_DIV_15
1701 * @arg @ref LL_RCC_PLLM_DIV_16
1702 * @arg @ref LL_RCC_PLLM_DIV_17
1703 * @arg @ref LL_RCC_PLLM_DIV_18
1704 * @arg @ref LL_RCC_PLLM_DIV_19
1705 * @arg @ref LL_RCC_PLLM_DIV_20
1706 * @arg @ref LL_RCC_PLLM_DIV_21
1707 * @arg @ref LL_RCC_PLLM_DIV_22
1708 * @arg @ref LL_RCC_PLLM_DIV_23
1709 * @arg @ref LL_RCC_PLLM_DIV_24
1710 * @arg @ref LL_RCC_PLLM_DIV_25
1711 * @arg @ref LL_RCC_PLLM_DIV_26
1712 * @arg @ref LL_RCC_PLLM_DIV_27
1713 * @arg @ref LL_RCC_PLLM_DIV_28
1714 * @arg @ref LL_RCC_PLLM_DIV_29
1715 * @arg @ref LL_RCC_PLLM_DIV_30
1716 * @arg @ref LL_RCC_PLLM_DIV_31
1717 * @arg @ref LL_RCC_PLLM_DIV_32
1718 * @arg @ref LL_RCC_PLLM_DIV_33
1719 * @arg @ref LL_RCC_PLLM_DIV_34
1720 * @arg @ref LL_RCC_PLLM_DIV_35
1721 * @arg @ref LL_RCC_PLLM_DIV_36
1722 * @arg @ref LL_RCC_PLLM_DIV_37
1723 * @arg @ref LL_RCC_PLLM_DIV_38
1724 * @arg @ref LL_RCC_PLLM_DIV_39
1725 * @arg @ref LL_RCC_PLLM_DIV_40
1726 * @arg @ref LL_RCC_PLLM_DIV_41
1727 * @arg @ref LL_RCC_PLLM_DIV_42
1728 * @arg @ref LL_RCC_PLLM_DIV_43
1729 * @arg @ref LL_RCC_PLLM_DIV_44
1730 * @arg @ref LL_RCC_PLLM_DIV_45
1731 * @arg @ref LL_RCC_PLLM_DIV_46
1732 * @arg @ref LL_RCC_PLLM_DIV_47
1733 * @arg @ref LL_RCC_PLLM_DIV_48
1734 * @arg @ref LL_RCC_PLLM_DIV_49
1735 * @arg @ref LL_RCC_PLLM_DIV_50
1736 * @arg @ref LL_RCC_PLLM_DIV_51
1737 * @arg @ref LL_RCC_PLLM_DIV_52
1738 * @arg @ref LL_RCC_PLLM_DIV_53
1739 * @arg @ref LL_RCC_PLLM_DIV_54
1740 * @arg @ref LL_RCC_PLLM_DIV_55
1741 * @arg @ref LL_RCC_PLLM_DIV_56
1742 * @arg @ref LL_RCC_PLLM_DIV_57
1743 * @arg @ref LL_RCC_PLLM_DIV_58
1744 * @arg @ref LL_RCC_PLLM_DIV_59
1745 * @arg @ref LL_RCC_PLLM_DIV_60
1746 * @arg @ref LL_RCC_PLLM_DIV_61
1747 * @arg @ref LL_RCC_PLLM_DIV_62
1748 * @arg @ref LL_RCC_PLLM_DIV_63
1749 * @param __PLLN__ Between 50/192(*) and 432
1750 *
1751 * (*) value not defined in all devices.
1752 * @param __PLLQ__ This parameter can be one of the following values:
1753 * @arg @ref LL_RCC_PLLQ_DIV_2
1754 * @arg @ref LL_RCC_PLLQ_DIV_3
1755 * @arg @ref LL_RCC_PLLQ_DIV_4
1756 * @arg @ref LL_RCC_PLLQ_DIV_5
1757 * @arg @ref LL_RCC_PLLQ_DIV_6
1758 * @arg @ref LL_RCC_PLLQ_DIV_7
1759 * @arg @ref LL_RCC_PLLQ_DIV_8
1760 * @arg @ref LL_RCC_PLLQ_DIV_9
1761 * @arg @ref LL_RCC_PLLQ_DIV_10
1762 * @arg @ref LL_RCC_PLLQ_DIV_11
1763 * @arg @ref LL_RCC_PLLQ_DIV_12
1764 * @arg @ref LL_RCC_PLLQ_DIV_13
1765 * @arg @ref LL_RCC_PLLQ_DIV_14
1766 * @arg @ref LL_RCC_PLLQ_DIV_15
1767 * @retval PLL clock frequency (in Hz)
1768 */
1769 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1770 ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
1771
1772 #if defined(DSI)
1773 /**
1774 * @brief Helper macro to calculate the PLLCLK frequency used on DSI
1775 * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
1776 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1777 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1778 * @param __PLLM__ This parameter can be one of the following values:
1779 * @arg @ref LL_RCC_PLLM_DIV_2
1780 * @arg @ref LL_RCC_PLLM_DIV_3
1781 * @arg @ref LL_RCC_PLLM_DIV_4
1782 * @arg @ref LL_RCC_PLLM_DIV_5
1783 * @arg @ref LL_RCC_PLLM_DIV_6
1784 * @arg @ref LL_RCC_PLLM_DIV_7
1785 * @arg @ref LL_RCC_PLLM_DIV_8
1786 * @arg @ref LL_RCC_PLLM_DIV_9
1787 * @arg @ref LL_RCC_PLLM_DIV_10
1788 * @arg @ref LL_RCC_PLLM_DIV_11
1789 * @arg @ref LL_RCC_PLLM_DIV_12
1790 * @arg @ref LL_RCC_PLLM_DIV_13
1791 * @arg @ref LL_RCC_PLLM_DIV_14
1792 * @arg @ref LL_RCC_PLLM_DIV_15
1793 * @arg @ref LL_RCC_PLLM_DIV_16
1794 * @arg @ref LL_RCC_PLLM_DIV_17
1795 * @arg @ref LL_RCC_PLLM_DIV_18
1796 * @arg @ref LL_RCC_PLLM_DIV_19
1797 * @arg @ref LL_RCC_PLLM_DIV_20
1798 * @arg @ref LL_RCC_PLLM_DIV_21
1799 * @arg @ref LL_RCC_PLLM_DIV_22
1800 * @arg @ref LL_RCC_PLLM_DIV_23
1801 * @arg @ref LL_RCC_PLLM_DIV_24
1802 * @arg @ref LL_RCC_PLLM_DIV_25
1803 * @arg @ref LL_RCC_PLLM_DIV_26
1804 * @arg @ref LL_RCC_PLLM_DIV_27
1805 * @arg @ref LL_RCC_PLLM_DIV_28
1806 * @arg @ref LL_RCC_PLLM_DIV_29
1807 * @arg @ref LL_RCC_PLLM_DIV_30
1808 * @arg @ref LL_RCC_PLLM_DIV_31
1809 * @arg @ref LL_RCC_PLLM_DIV_32
1810 * @arg @ref LL_RCC_PLLM_DIV_33
1811 * @arg @ref LL_RCC_PLLM_DIV_34
1812 * @arg @ref LL_RCC_PLLM_DIV_35
1813 * @arg @ref LL_RCC_PLLM_DIV_36
1814 * @arg @ref LL_RCC_PLLM_DIV_37
1815 * @arg @ref LL_RCC_PLLM_DIV_38
1816 * @arg @ref LL_RCC_PLLM_DIV_39
1817 * @arg @ref LL_RCC_PLLM_DIV_40
1818 * @arg @ref LL_RCC_PLLM_DIV_41
1819 * @arg @ref LL_RCC_PLLM_DIV_42
1820 * @arg @ref LL_RCC_PLLM_DIV_43
1821 * @arg @ref LL_RCC_PLLM_DIV_44
1822 * @arg @ref LL_RCC_PLLM_DIV_45
1823 * @arg @ref LL_RCC_PLLM_DIV_46
1824 * @arg @ref LL_RCC_PLLM_DIV_47
1825 * @arg @ref LL_RCC_PLLM_DIV_48
1826 * @arg @ref LL_RCC_PLLM_DIV_49
1827 * @arg @ref LL_RCC_PLLM_DIV_50
1828 * @arg @ref LL_RCC_PLLM_DIV_51
1829 * @arg @ref LL_RCC_PLLM_DIV_52
1830 * @arg @ref LL_RCC_PLLM_DIV_53
1831 * @arg @ref LL_RCC_PLLM_DIV_54
1832 * @arg @ref LL_RCC_PLLM_DIV_55
1833 * @arg @ref LL_RCC_PLLM_DIV_56
1834 * @arg @ref LL_RCC_PLLM_DIV_57
1835 * @arg @ref LL_RCC_PLLM_DIV_58
1836 * @arg @ref LL_RCC_PLLM_DIV_59
1837 * @arg @ref LL_RCC_PLLM_DIV_60
1838 * @arg @ref LL_RCC_PLLM_DIV_61
1839 * @arg @ref LL_RCC_PLLM_DIV_62
1840 * @arg @ref LL_RCC_PLLM_DIV_63
1841 * @param __PLLN__ Between 50 and 432
1842 * @param __PLLR__ This parameter can be one of the following values:
1843 * @arg @ref LL_RCC_PLLR_DIV_2
1844 * @arg @ref LL_RCC_PLLR_DIV_3
1845 * @arg @ref LL_RCC_PLLR_DIV_4
1846 * @arg @ref LL_RCC_PLLR_DIV_5
1847 * @arg @ref LL_RCC_PLLR_DIV_6
1848 * @arg @ref LL_RCC_PLLR_DIV_7
1849 * @retval PLL clock frequency (in Hz)
1850 */
1851 #define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1852 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1853 #endif /* DSI */
1854
1855 #if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
1856 /**
1857 * @brief Helper macro to calculate the PLLCLK frequency used on I2S
1858 * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
1859 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1860 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1861 * @param __PLLM__ This parameter can be one of the following values:
1862 * @arg @ref LL_RCC_PLLM_DIV_2
1863 * @arg @ref LL_RCC_PLLM_DIV_3
1864 * @arg @ref LL_RCC_PLLM_DIV_4
1865 * @arg @ref LL_RCC_PLLM_DIV_5
1866 * @arg @ref LL_RCC_PLLM_DIV_6
1867 * @arg @ref LL_RCC_PLLM_DIV_7
1868 * @arg @ref LL_RCC_PLLM_DIV_8
1869 * @arg @ref LL_RCC_PLLM_DIV_9
1870 * @arg @ref LL_RCC_PLLM_DIV_10
1871 * @arg @ref LL_RCC_PLLM_DIV_11
1872 * @arg @ref LL_RCC_PLLM_DIV_12
1873 * @arg @ref LL_RCC_PLLM_DIV_13
1874 * @arg @ref LL_RCC_PLLM_DIV_14
1875 * @arg @ref LL_RCC_PLLM_DIV_15
1876 * @arg @ref LL_RCC_PLLM_DIV_16
1877 * @arg @ref LL_RCC_PLLM_DIV_17
1878 * @arg @ref LL_RCC_PLLM_DIV_18
1879 * @arg @ref LL_RCC_PLLM_DIV_19
1880 * @arg @ref LL_RCC_PLLM_DIV_20
1881 * @arg @ref LL_RCC_PLLM_DIV_21
1882 * @arg @ref LL_RCC_PLLM_DIV_22
1883 * @arg @ref LL_RCC_PLLM_DIV_23
1884 * @arg @ref LL_RCC_PLLM_DIV_24
1885 * @arg @ref LL_RCC_PLLM_DIV_25
1886 * @arg @ref LL_RCC_PLLM_DIV_26
1887 * @arg @ref LL_RCC_PLLM_DIV_27
1888 * @arg @ref LL_RCC_PLLM_DIV_28
1889 * @arg @ref LL_RCC_PLLM_DIV_29
1890 * @arg @ref LL_RCC_PLLM_DIV_30
1891 * @arg @ref LL_RCC_PLLM_DIV_31
1892 * @arg @ref LL_RCC_PLLM_DIV_32
1893 * @arg @ref LL_RCC_PLLM_DIV_33
1894 * @arg @ref LL_RCC_PLLM_DIV_34
1895 * @arg @ref LL_RCC_PLLM_DIV_35
1896 * @arg @ref LL_RCC_PLLM_DIV_36
1897 * @arg @ref LL_RCC_PLLM_DIV_37
1898 * @arg @ref LL_RCC_PLLM_DIV_38
1899 * @arg @ref LL_RCC_PLLM_DIV_39
1900 * @arg @ref LL_RCC_PLLM_DIV_40
1901 * @arg @ref LL_RCC_PLLM_DIV_41
1902 * @arg @ref LL_RCC_PLLM_DIV_42
1903 * @arg @ref LL_RCC_PLLM_DIV_43
1904 * @arg @ref LL_RCC_PLLM_DIV_44
1905 * @arg @ref LL_RCC_PLLM_DIV_45
1906 * @arg @ref LL_RCC_PLLM_DIV_46
1907 * @arg @ref LL_RCC_PLLM_DIV_47
1908 * @arg @ref LL_RCC_PLLM_DIV_48
1909 * @arg @ref LL_RCC_PLLM_DIV_49
1910 * @arg @ref LL_RCC_PLLM_DIV_50
1911 * @arg @ref LL_RCC_PLLM_DIV_51
1912 * @arg @ref LL_RCC_PLLM_DIV_52
1913 * @arg @ref LL_RCC_PLLM_DIV_53
1914 * @arg @ref LL_RCC_PLLM_DIV_54
1915 * @arg @ref LL_RCC_PLLM_DIV_55
1916 * @arg @ref LL_RCC_PLLM_DIV_56
1917 * @arg @ref LL_RCC_PLLM_DIV_57
1918 * @arg @ref LL_RCC_PLLM_DIV_58
1919 * @arg @ref LL_RCC_PLLM_DIV_59
1920 * @arg @ref LL_RCC_PLLM_DIV_60
1921 * @arg @ref LL_RCC_PLLM_DIV_61
1922 * @arg @ref LL_RCC_PLLM_DIV_62
1923 * @arg @ref LL_RCC_PLLM_DIV_63
1924 * @param __PLLN__ Between 50 and 432
1925 * @param __PLLR__ This parameter can be one of the following values:
1926 * @arg @ref LL_RCC_PLLR_DIV_2
1927 * @arg @ref LL_RCC_PLLR_DIV_3
1928 * @arg @ref LL_RCC_PLLR_DIV_4
1929 * @arg @ref LL_RCC_PLLR_DIV_5
1930 * @arg @ref LL_RCC_PLLR_DIV_6
1931 * @arg @ref LL_RCC_PLLR_DIV_7
1932 * @retval PLL clock frequency (in Hz)
1933 */
1934 #define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1935 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1936 #endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
1937
1938 #if defined(SPDIFRX)
1939 /**
1940 * @brief Helper macro to calculate the PLLCLK frequency used on SPDIFRX
1941 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
1942 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1943 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1944 * @param __PLLM__ This parameter can be one of the following values:
1945 * @arg @ref LL_RCC_PLLM_DIV_2
1946 * @arg @ref LL_RCC_PLLM_DIV_3
1947 * @arg @ref LL_RCC_PLLM_DIV_4
1948 * @arg @ref LL_RCC_PLLM_DIV_5
1949 * @arg @ref LL_RCC_PLLM_DIV_6
1950 * @arg @ref LL_RCC_PLLM_DIV_7
1951 * @arg @ref LL_RCC_PLLM_DIV_8
1952 * @arg @ref LL_RCC_PLLM_DIV_9
1953 * @arg @ref LL_RCC_PLLM_DIV_10
1954 * @arg @ref LL_RCC_PLLM_DIV_11
1955 * @arg @ref LL_RCC_PLLM_DIV_12
1956 * @arg @ref LL_RCC_PLLM_DIV_13
1957 * @arg @ref LL_RCC_PLLM_DIV_14
1958 * @arg @ref LL_RCC_PLLM_DIV_15
1959 * @arg @ref LL_RCC_PLLM_DIV_16
1960 * @arg @ref LL_RCC_PLLM_DIV_17
1961 * @arg @ref LL_RCC_PLLM_DIV_18
1962 * @arg @ref LL_RCC_PLLM_DIV_19
1963 * @arg @ref LL_RCC_PLLM_DIV_20
1964 * @arg @ref LL_RCC_PLLM_DIV_21
1965 * @arg @ref LL_RCC_PLLM_DIV_22
1966 * @arg @ref LL_RCC_PLLM_DIV_23
1967 * @arg @ref LL_RCC_PLLM_DIV_24
1968 * @arg @ref LL_RCC_PLLM_DIV_25
1969 * @arg @ref LL_RCC_PLLM_DIV_26
1970 * @arg @ref LL_RCC_PLLM_DIV_27
1971 * @arg @ref LL_RCC_PLLM_DIV_28
1972 * @arg @ref LL_RCC_PLLM_DIV_29
1973 * @arg @ref LL_RCC_PLLM_DIV_30
1974 * @arg @ref LL_RCC_PLLM_DIV_31
1975 * @arg @ref LL_RCC_PLLM_DIV_32
1976 * @arg @ref LL_RCC_PLLM_DIV_33
1977 * @arg @ref LL_RCC_PLLM_DIV_34
1978 * @arg @ref LL_RCC_PLLM_DIV_35
1979 * @arg @ref LL_RCC_PLLM_DIV_36
1980 * @arg @ref LL_RCC_PLLM_DIV_37
1981 * @arg @ref LL_RCC_PLLM_DIV_38
1982 * @arg @ref LL_RCC_PLLM_DIV_39
1983 * @arg @ref LL_RCC_PLLM_DIV_40
1984 * @arg @ref LL_RCC_PLLM_DIV_41
1985 * @arg @ref LL_RCC_PLLM_DIV_42
1986 * @arg @ref LL_RCC_PLLM_DIV_43
1987 * @arg @ref LL_RCC_PLLM_DIV_44
1988 * @arg @ref LL_RCC_PLLM_DIV_45
1989 * @arg @ref LL_RCC_PLLM_DIV_46
1990 * @arg @ref LL_RCC_PLLM_DIV_47
1991 * @arg @ref LL_RCC_PLLM_DIV_48
1992 * @arg @ref LL_RCC_PLLM_DIV_49
1993 * @arg @ref LL_RCC_PLLM_DIV_50
1994 * @arg @ref LL_RCC_PLLM_DIV_51
1995 * @arg @ref LL_RCC_PLLM_DIV_52
1996 * @arg @ref LL_RCC_PLLM_DIV_53
1997 * @arg @ref LL_RCC_PLLM_DIV_54
1998 * @arg @ref LL_RCC_PLLM_DIV_55
1999 * @arg @ref LL_RCC_PLLM_DIV_56
2000 * @arg @ref LL_RCC_PLLM_DIV_57
2001 * @arg @ref LL_RCC_PLLM_DIV_58
2002 * @arg @ref LL_RCC_PLLM_DIV_59
2003 * @arg @ref LL_RCC_PLLM_DIV_60
2004 * @arg @ref LL_RCC_PLLM_DIV_61
2005 * @arg @ref LL_RCC_PLLM_DIV_62
2006 * @arg @ref LL_RCC_PLLM_DIV_63
2007 * @param __PLLN__ Between 50 and 432
2008 * @param __PLLR__ This parameter can be one of the following values:
2009 * @arg @ref LL_RCC_PLLR_DIV_2
2010 * @arg @ref LL_RCC_PLLR_DIV_3
2011 * @arg @ref LL_RCC_PLLR_DIV_4
2012 * @arg @ref LL_RCC_PLLR_DIV_5
2013 * @arg @ref LL_RCC_PLLR_DIV_6
2014 * @arg @ref LL_RCC_PLLR_DIV_7
2015 * @retval PLL clock frequency (in Hz)
2016 */
2017 #define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
2018 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
2019 #endif /* SPDIFRX */
2020
2021 #if defined(RCC_PLLCFGR_PLLR)
2022 #if defined(SAI1)
2023 /**
2024 * @brief Helper macro to calculate the PLLCLK frequency used on SAI
2025 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
2026 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ());
2027 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2028 * @param __PLLM__ This parameter can be one of the following values:
2029 * @arg @ref LL_RCC_PLLM_DIV_2
2030 * @arg @ref LL_RCC_PLLM_DIV_3
2031 * @arg @ref LL_RCC_PLLM_DIV_4
2032 * @arg @ref LL_RCC_PLLM_DIV_5
2033 * @arg @ref LL_RCC_PLLM_DIV_6
2034 * @arg @ref LL_RCC_PLLM_DIV_7
2035 * @arg @ref LL_RCC_PLLM_DIV_8
2036 * @arg @ref LL_RCC_PLLM_DIV_9
2037 * @arg @ref LL_RCC_PLLM_DIV_10
2038 * @arg @ref LL_RCC_PLLM_DIV_11
2039 * @arg @ref LL_RCC_PLLM_DIV_12
2040 * @arg @ref LL_RCC_PLLM_DIV_13
2041 * @arg @ref LL_RCC_PLLM_DIV_14
2042 * @arg @ref LL_RCC_PLLM_DIV_15
2043 * @arg @ref LL_RCC_PLLM_DIV_16
2044 * @arg @ref LL_RCC_PLLM_DIV_17
2045 * @arg @ref LL_RCC_PLLM_DIV_18
2046 * @arg @ref LL_RCC_PLLM_DIV_19
2047 * @arg @ref LL_RCC_PLLM_DIV_20
2048 * @arg @ref LL_RCC_PLLM_DIV_21
2049 * @arg @ref LL_RCC_PLLM_DIV_22
2050 * @arg @ref LL_RCC_PLLM_DIV_23
2051 * @arg @ref LL_RCC_PLLM_DIV_24
2052 * @arg @ref LL_RCC_PLLM_DIV_25
2053 * @arg @ref LL_RCC_PLLM_DIV_26
2054 * @arg @ref LL_RCC_PLLM_DIV_27
2055 * @arg @ref LL_RCC_PLLM_DIV_28
2056 * @arg @ref LL_RCC_PLLM_DIV_29
2057 * @arg @ref LL_RCC_PLLM_DIV_30
2058 * @arg @ref LL_RCC_PLLM_DIV_31
2059 * @arg @ref LL_RCC_PLLM_DIV_32
2060 * @arg @ref LL_RCC_PLLM_DIV_33
2061 * @arg @ref LL_RCC_PLLM_DIV_34
2062 * @arg @ref LL_RCC_PLLM_DIV_35
2063 * @arg @ref LL_RCC_PLLM_DIV_36
2064 * @arg @ref LL_RCC_PLLM_DIV_37
2065 * @arg @ref LL_RCC_PLLM_DIV_38
2066 * @arg @ref LL_RCC_PLLM_DIV_39
2067 * @arg @ref LL_RCC_PLLM_DIV_40
2068 * @arg @ref LL_RCC_PLLM_DIV_41
2069 * @arg @ref LL_RCC_PLLM_DIV_42
2070 * @arg @ref LL_RCC_PLLM_DIV_43
2071 * @arg @ref LL_RCC_PLLM_DIV_44
2072 * @arg @ref LL_RCC_PLLM_DIV_45
2073 * @arg @ref LL_RCC_PLLM_DIV_46
2074 * @arg @ref LL_RCC_PLLM_DIV_47
2075 * @arg @ref LL_RCC_PLLM_DIV_48
2076 * @arg @ref LL_RCC_PLLM_DIV_49
2077 * @arg @ref LL_RCC_PLLM_DIV_50
2078 * @arg @ref LL_RCC_PLLM_DIV_51
2079 * @arg @ref LL_RCC_PLLM_DIV_52
2080 * @arg @ref LL_RCC_PLLM_DIV_53
2081 * @arg @ref LL_RCC_PLLM_DIV_54
2082 * @arg @ref LL_RCC_PLLM_DIV_55
2083 * @arg @ref LL_RCC_PLLM_DIV_56
2084 * @arg @ref LL_RCC_PLLM_DIV_57
2085 * @arg @ref LL_RCC_PLLM_DIV_58
2086 * @arg @ref LL_RCC_PLLM_DIV_59
2087 * @arg @ref LL_RCC_PLLM_DIV_60
2088 * @arg @ref LL_RCC_PLLM_DIV_61
2089 * @arg @ref LL_RCC_PLLM_DIV_62
2090 * @arg @ref LL_RCC_PLLM_DIV_63
2091 * @param __PLLN__ Between 50 and 432
2092 * @param __PLLR__ This parameter can be one of the following values:
2093 * @arg @ref LL_RCC_PLLR_DIV_2
2094 * @arg @ref LL_RCC_PLLR_DIV_3
2095 * @arg @ref LL_RCC_PLLR_DIV_4
2096 * @arg @ref LL_RCC_PLLR_DIV_5
2097 * @arg @ref LL_RCC_PLLR_DIV_6
2098 * @arg @ref LL_RCC_PLLR_DIV_7
2099 * @param __PLLDIVR__ This parameter can be one of the following values:
2100 * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
2101 * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
2102 * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
2103 * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
2104 * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
2105 * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
2106 * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
2107 * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
2108 * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
2109 * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
2110 * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
2111 * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
2112 * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
2113 * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
2114 * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
2115 * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
2116 * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
2117 * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
2118 * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
2119 * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
2120 * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
2121 * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
2122 * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
2123 * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
2124 * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
2125 * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
2126 * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
2127 * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
2128 * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
2129 * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
2130 * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
2131 *
2132 * (*) value not defined in all devices.
2133 * @retval PLL clock frequency (in Hz)
2134 */
2135 #if defined(RCC_DCKCFGR_PLLDIVR)
2136 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
2137 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos ))
2138 #else
2139 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
2140 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
2141 #endif /* RCC_DCKCFGR_PLLDIVR */
2142 #endif /* SAI1 */
2143 #endif /* RCC_PLLCFGR_PLLR */
2144
2145 #if defined(RCC_PLLSAI_SUPPORT)
2146 /**
2147 * @brief Helper macro to calculate the PLLSAI frequency used for SAI domain
2148 * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
2149 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
2150 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2151 * @param __PLLM__ This parameter can be one of the following values:
2152 * @arg @ref LL_RCC_PLLSAIM_DIV_2
2153 * @arg @ref LL_RCC_PLLSAIM_DIV_3
2154 * @arg @ref LL_RCC_PLLSAIM_DIV_4
2155 * @arg @ref LL_RCC_PLLSAIM_DIV_5
2156 * @arg @ref LL_RCC_PLLSAIM_DIV_6
2157 * @arg @ref LL_RCC_PLLSAIM_DIV_7
2158 * @arg @ref LL_RCC_PLLSAIM_DIV_8
2159 * @arg @ref LL_RCC_PLLSAIM_DIV_9
2160 * @arg @ref LL_RCC_PLLSAIM_DIV_10
2161 * @arg @ref LL_RCC_PLLSAIM_DIV_11
2162 * @arg @ref LL_RCC_PLLSAIM_DIV_12
2163 * @arg @ref LL_RCC_PLLSAIM_DIV_13
2164 * @arg @ref LL_RCC_PLLSAIM_DIV_14
2165 * @arg @ref LL_RCC_PLLSAIM_DIV_15
2166 * @arg @ref LL_RCC_PLLSAIM_DIV_16
2167 * @arg @ref LL_RCC_PLLSAIM_DIV_17
2168 * @arg @ref LL_RCC_PLLSAIM_DIV_18
2169 * @arg @ref LL_RCC_PLLSAIM_DIV_19
2170 * @arg @ref LL_RCC_PLLSAIM_DIV_20
2171 * @arg @ref LL_RCC_PLLSAIM_DIV_21
2172 * @arg @ref LL_RCC_PLLSAIM_DIV_22
2173 * @arg @ref LL_RCC_PLLSAIM_DIV_23
2174 * @arg @ref LL_RCC_PLLSAIM_DIV_24
2175 * @arg @ref LL_RCC_PLLSAIM_DIV_25
2176 * @arg @ref LL_RCC_PLLSAIM_DIV_26
2177 * @arg @ref LL_RCC_PLLSAIM_DIV_27
2178 * @arg @ref LL_RCC_PLLSAIM_DIV_28
2179 * @arg @ref LL_RCC_PLLSAIM_DIV_29
2180 * @arg @ref LL_RCC_PLLSAIM_DIV_30
2181 * @arg @ref LL_RCC_PLLSAIM_DIV_31
2182 * @arg @ref LL_RCC_PLLSAIM_DIV_32
2183 * @arg @ref LL_RCC_PLLSAIM_DIV_33
2184 * @arg @ref LL_RCC_PLLSAIM_DIV_34
2185 * @arg @ref LL_RCC_PLLSAIM_DIV_35
2186 * @arg @ref LL_RCC_PLLSAIM_DIV_36
2187 * @arg @ref LL_RCC_PLLSAIM_DIV_37
2188 * @arg @ref LL_RCC_PLLSAIM_DIV_38
2189 * @arg @ref LL_RCC_PLLSAIM_DIV_39
2190 * @arg @ref LL_RCC_PLLSAIM_DIV_40
2191 * @arg @ref LL_RCC_PLLSAIM_DIV_41
2192 * @arg @ref LL_RCC_PLLSAIM_DIV_42
2193 * @arg @ref LL_RCC_PLLSAIM_DIV_43
2194 * @arg @ref LL_RCC_PLLSAIM_DIV_44
2195 * @arg @ref LL_RCC_PLLSAIM_DIV_45
2196 * @arg @ref LL_RCC_PLLSAIM_DIV_46
2197 * @arg @ref LL_RCC_PLLSAIM_DIV_47
2198 * @arg @ref LL_RCC_PLLSAIM_DIV_48
2199 * @arg @ref LL_RCC_PLLSAIM_DIV_49
2200 * @arg @ref LL_RCC_PLLSAIM_DIV_50
2201 * @arg @ref LL_RCC_PLLSAIM_DIV_51
2202 * @arg @ref LL_RCC_PLLSAIM_DIV_52
2203 * @arg @ref LL_RCC_PLLSAIM_DIV_53
2204 * @arg @ref LL_RCC_PLLSAIM_DIV_54
2205 * @arg @ref LL_RCC_PLLSAIM_DIV_55
2206 * @arg @ref LL_RCC_PLLSAIM_DIV_56
2207 * @arg @ref LL_RCC_PLLSAIM_DIV_57
2208 * @arg @ref LL_RCC_PLLSAIM_DIV_58
2209 * @arg @ref LL_RCC_PLLSAIM_DIV_59
2210 * @arg @ref LL_RCC_PLLSAIM_DIV_60
2211 * @arg @ref LL_RCC_PLLSAIM_DIV_61
2212 * @arg @ref LL_RCC_PLLSAIM_DIV_62
2213 * @arg @ref LL_RCC_PLLSAIM_DIV_63
2214 * @param __PLLSAIN__ Between 49/50(*) and 432
2215 *
2216 * (*) value not defined in all devices.
2217 * @param __PLLSAIQ__ This parameter can be one of the following values:
2218 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
2219 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
2220 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
2221 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
2222 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
2223 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
2224 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
2225 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
2226 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
2227 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
2228 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
2229 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
2230 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
2231 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
2232 * @param __PLLSAIDIVQ__ This parameter can be one of the following values:
2233 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
2234 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
2235 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
2236 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
2237 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
2238 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
2239 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
2240 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
2241 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
2242 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
2243 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
2244 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
2245 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
2246 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
2247 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
2248 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
2249 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
2250 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
2251 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
2252 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
2253 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
2254 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
2255 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
2256 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
2257 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
2258 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
2259 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
2260 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
2261 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
2262 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
2263 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
2264 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
2265 * @retval PLLSAI clock frequency (in Hz)
2266 */
2267 #define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
2268 (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U)))
2269
2270 #if defined(RCC_PLLSAICFGR_PLLSAIP)
2271 /**
2272 * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
2273 * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
2274 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
2275 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2276 * @param __PLLM__ This parameter can be one of the following values:
2277 * @arg @ref LL_RCC_PLLSAIM_DIV_2
2278 * @arg @ref LL_RCC_PLLSAIM_DIV_3
2279 * @arg @ref LL_RCC_PLLSAIM_DIV_4
2280 * @arg @ref LL_RCC_PLLSAIM_DIV_5
2281 * @arg @ref LL_RCC_PLLSAIM_DIV_6
2282 * @arg @ref LL_RCC_PLLSAIM_DIV_7
2283 * @arg @ref LL_RCC_PLLSAIM_DIV_8
2284 * @arg @ref LL_RCC_PLLSAIM_DIV_9
2285 * @arg @ref LL_RCC_PLLSAIM_DIV_10
2286 * @arg @ref LL_RCC_PLLSAIM_DIV_11
2287 * @arg @ref LL_RCC_PLLSAIM_DIV_12
2288 * @arg @ref LL_RCC_PLLSAIM_DIV_13
2289 * @arg @ref LL_RCC_PLLSAIM_DIV_14
2290 * @arg @ref LL_RCC_PLLSAIM_DIV_15
2291 * @arg @ref LL_RCC_PLLSAIM_DIV_16
2292 * @arg @ref LL_RCC_PLLSAIM_DIV_17
2293 * @arg @ref LL_RCC_PLLSAIM_DIV_18
2294 * @arg @ref LL_RCC_PLLSAIM_DIV_19
2295 * @arg @ref LL_RCC_PLLSAIM_DIV_20
2296 * @arg @ref LL_RCC_PLLSAIM_DIV_21
2297 * @arg @ref LL_RCC_PLLSAIM_DIV_22
2298 * @arg @ref LL_RCC_PLLSAIM_DIV_23
2299 * @arg @ref LL_RCC_PLLSAIM_DIV_24
2300 * @arg @ref LL_RCC_PLLSAIM_DIV_25
2301 * @arg @ref LL_RCC_PLLSAIM_DIV_26
2302 * @arg @ref LL_RCC_PLLSAIM_DIV_27
2303 * @arg @ref LL_RCC_PLLSAIM_DIV_28
2304 * @arg @ref LL_RCC_PLLSAIM_DIV_29
2305 * @arg @ref LL_RCC_PLLSAIM_DIV_30
2306 * @arg @ref LL_RCC_PLLSAIM_DIV_31
2307 * @arg @ref LL_RCC_PLLSAIM_DIV_32
2308 * @arg @ref LL_RCC_PLLSAIM_DIV_33
2309 * @arg @ref LL_RCC_PLLSAIM_DIV_34
2310 * @arg @ref LL_RCC_PLLSAIM_DIV_35
2311 * @arg @ref LL_RCC_PLLSAIM_DIV_36
2312 * @arg @ref LL_RCC_PLLSAIM_DIV_37
2313 * @arg @ref LL_RCC_PLLSAIM_DIV_38
2314 * @arg @ref LL_RCC_PLLSAIM_DIV_39
2315 * @arg @ref LL_RCC_PLLSAIM_DIV_40
2316 * @arg @ref LL_RCC_PLLSAIM_DIV_41
2317 * @arg @ref LL_RCC_PLLSAIM_DIV_42
2318 * @arg @ref LL_RCC_PLLSAIM_DIV_43
2319 * @arg @ref LL_RCC_PLLSAIM_DIV_44
2320 * @arg @ref LL_RCC_PLLSAIM_DIV_45
2321 * @arg @ref LL_RCC_PLLSAIM_DIV_46
2322 * @arg @ref LL_RCC_PLLSAIM_DIV_47
2323 * @arg @ref LL_RCC_PLLSAIM_DIV_48
2324 * @arg @ref LL_RCC_PLLSAIM_DIV_49
2325 * @arg @ref LL_RCC_PLLSAIM_DIV_50
2326 * @arg @ref LL_RCC_PLLSAIM_DIV_51
2327 * @arg @ref LL_RCC_PLLSAIM_DIV_52
2328 * @arg @ref LL_RCC_PLLSAIM_DIV_53
2329 * @arg @ref LL_RCC_PLLSAIM_DIV_54
2330 * @arg @ref LL_RCC_PLLSAIM_DIV_55
2331 * @arg @ref LL_RCC_PLLSAIM_DIV_56
2332 * @arg @ref LL_RCC_PLLSAIM_DIV_57
2333 * @arg @ref LL_RCC_PLLSAIM_DIV_58
2334 * @arg @ref LL_RCC_PLLSAIM_DIV_59
2335 * @arg @ref LL_RCC_PLLSAIM_DIV_60
2336 * @arg @ref LL_RCC_PLLSAIM_DIV_61
2337 * @arg @ref LL_RCC_PLLSAIM_DIV_62
2338 * @arg @ref LL_RCC_PLLSAIM_DIV_63
2339 * @param __PLLSAIN__ Between 50 and 432
2340 * @param __PLLSAIP__ This parameter can be one of the following values:
2341 * @arg @ref LL_RCC_PLLSAIP_DIV_2
2342 * @arg @ref LL_RCC_PLLSAIP_DIV_4
2343 * @arg @ref LL_RCC_PLLSAIP_DIV_6
2344 * @arg @ref LL_RCC_PLLSAIP_DIV_8
2345 * @retval PLLSAI clock frequency (in Hz)
2346 */
2347 #define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
2348 ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U))
2349 #endif /* RCC_PLLSAICFGR_PLLSAIP */
2350
2351 #if defined(LTDC)
2352 /**
2353 * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain
2354 * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
2355 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
2356 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2357 * @param __PLLM__ This parameter can be one of the following values:
2358 * @arg @ref LL_RCC_PLLSAIM_DIV_2
2359 * @arg @ref LL_RCC_PLLSAIM_DIV_3
2360 * @arg @ref LL_RCC_PLLSAIM_DIV_4
2361 * @arg @ref LL_RCC_PLLSAIM_DIV_5
2362 * @arg @ref LL_RCC_PLLSAIM_DIV_6
2363 * @arg @ref LL_RCC_PLLSAIM_DIV_7
2364 * @arg @ref LL_RCC_PLLSAIM_DIV_8
2365 * @arg @ref LL_RCC_PLLSAIM_DIV_9
2366 * @arg @ref LL_RCC_PLLSAIM_DIV_10
2367 * @arg @ref LL_RCC_PLLSAIM_DIV_11
2368 * @arg @ref LL_RCC_PLLSAIM_DIV_12
2369 * @arg @ref LL_RCC_PLLSAIM_DIV_13
2370 * @arg @ref LL_RCC_PLLSAIM_DIV_14
2371 * @arg @ref LL_RCC_PLLSAIM_DIV_15
2372 * @arg @ref LL_RCC_PLLSAIM_DIV_16
2373 * @arg @ref LL_RCC_PLLSAIM_DIV_17
2374 * @arg @ref LL_RCC_PLLSAIM_DIV_18
2375 * @arg @ref LL_RCC_PLLSAIM_DIV_19
2376 * @arg @ref LL_RCC_PLLSAIM_DIV_20
2377 * @arg @ref LL_RCC_PLLSAIM_DIV_21
2378 * @arg @ref LL_RCC_PLLSAIM_DIV_22
2379 * @arg @ref LL_RCC_PLLSAIM_DIV_23
2380 * @arg @ref LL_RCC_PLLSAIM_DIV_24
2381 * @arg @ref LL_RCC_PLLSAIM_DIV_25
2382 * @arg @ref LL_RCC_PLLSAIM_DIV_26
2383 * @arg @ref LL_RCC_PLLSAIM_DIV_27
2384 * @arg @ref LL_RCC_PLLSAIM_DIV_28
2385 * @arg @ref LL_RCC_PLLSAIM_DIV_29
2386 * @arg @ref LL_RCC_PLLSAIM_DIV_30
2387 * @arg @ref LL_RCC_PLLSAIM_DIV_31
2388 * @arg @ref LL_RCC_PLLSAIM_DIV_32
2389 * @arg @ref LL_RCC_PLLSAIM_DIV_33
2390 * @arg @ref LL_RCC_PLLSAIM_DIV_34
2391 * @arg @ref LL_RCC_PLLSAIM_DIV_35
2392 * @arg @ref LL_RCC_PLLSAIM_DIV_36
2393 * @arg @ref LL_RCC_PLLSAIM_DIV_37
2394 * @arg @ref LL_RCC_PLLSAIM_DIV_38
2395 * @arg @ref LL_RCC_PLLSAIM_DIV_39
2396 * @arg @ref LL_RCC_PLLSAIM_DIV_40
2397 * @arg @ref LL_RCC_PLLSAIM_DIV_41
2398 * @arg @ref LL_RCC_PLLSAIM_DIV_42
2399 * @arg @ref LL_RCC_PLLSAIM_DIV_43
2400 * @arg @ref LL_RCC_PLLSAIM_DIV_44
2401 * @arg @ref LL_RCC_PLLSAIM_DIV_45
2402 * @arg @ref LL_RCC_PLLSAIM_DIV_46
2403 * @arg @ref LL_RCC_PLLSAIM_DIV_47
2404 * @arg @ref LL_RCC_PLLSAIM_DIV_48
2405 * @arg @ref LL_RCC_PLLSAIM_DIV_49
2406 * @arg @ref LL_RCC_PLLSAIM_DIV_50
2407 * @arg @ref LL_RCC_PLLSAIM_DIV_51
2408 * @arg @ref LL_RCC_PLLSAIM_DIV_52
2409 * @arg @ref LL_RCC_PLLSAIM_DIV_53
2410 * @arg @ref LL_RCC_PLLSAIM_DIV_54
2411 * @arg @ref LL_RCC_PLLSAIM_DIV_55
2412 * @arg @ref LL_RCC_PLLSAIM_DIV_56
2413 * @arg @ref LL_RCC_PLLSAIM_DIV_57
2414 * @arg @ref LL_RCC_PLLSAIM_DIV_58
2415 * @arg @ref LL_RCC_PLLSAIM_DIV_59
2416 * @arg @ref LL_RCC_PLLSAIM_DIV_60
2417 * @arg @ref LL_RCC_PLLSAIM_DIV_61
2418 * @arg @ref LL_RCC_PLLSAIM_DIV_62
2419 * @arg @ref LL_RCC_PLLSAIM_DIV_63
2420 * @param __PLLSAIN__ Between 49/50(*) and 432
2421 *
2422 * (*) value not defined in all devices.
2423 * @param __PLLSAIR__ This parameter can be one of the following values:
2424 * @arg @ref LL_RCC_PLLSAIR_DIV_2
2425 * @arg @ref LL_RCC_PLLSAIR_DIV_3
2426 * @arg @ref LL_RCC_PLLSAIR_DIV_4
2427 * @arg @ref LL_RCC_PLLSAIR_DIV_5
2428 * @arg @ref LL_RCC_PLLSAIR_DIV_6
2429 * @arg @ref LL_RCC_PLLSAIR_DIV_7
2430 * @param __PLLSAIDIVR__ This parameter can be one of the following values:
2431 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
2432 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
2433 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
2434 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
2435 * @retval PLLSAI clock frequency (in Hz)
2436 */
2437 #define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
2438 (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos])))
2439 #endif /* LTDC */
2440 #endif /* RCC_PLLSAI_SUPPORT */
2441
2442 #if defined(RCC_PLLI2S_SUPPORT)
2443 #if defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR)
2444 /**
2445 * @brief Helper macro to calculate the PLLI2S frequency used for SAI domain
2446 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2447 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
2448 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2449 * @param __PLLM__ This parameter can be one of the following values:
2450 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2451 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2452 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2453 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2454 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2455 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2456 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2457 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2458 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2459 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2460 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2461 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2462 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2463 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2464 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2465 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2466 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2467 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2468 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2469 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2470 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2471 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2472 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2473 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2474 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2475 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2476 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2477 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2478 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2479 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2480 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2481 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2482 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2483 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2484 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2485 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2486 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2487 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2488 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2489 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2490 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2491 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2492 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2493 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2494 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2495 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2496 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2497 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2498 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2499 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2500 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2501 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2502 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2503 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2504 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2505 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2506 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2507 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2508 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2509 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2510 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2511 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2512 * @param __PLLI2SN__ Between 50/192(*) and 432
2513 *
2514 * (*) value not defined in all devices.
2515 * @param __PLLI2SQ_R__ This parameter can be one of the following values:
2516 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
2517 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
2518 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
2519 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
2520 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
2521 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
2522 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
2523 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
2524 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
2525 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
2526 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
2527 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
2528 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
2529 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
2530 * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
2531 * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
2532 * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
2533 * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
2534 * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
2535 * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
2536 *
2537 * (*) value not defined in all devices.
2538 * @param __PLLI2SDIVQ_R__ This parameter can be one of the following values:
2539 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
2540 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
2541 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
2542 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
2543 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
2544 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
2545 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
2546 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
2547 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
2548 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
2549 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
2550 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
2551 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
2552 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
2553 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
2554 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
2555 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
2556 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
2557 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
2558 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
2559 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
2560 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
2561 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
2562 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
2563 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
2564 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
2565 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
2566 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
2567 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
2568 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
2569 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
2570 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
2571 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
2572 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
2573 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
2574 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
2575 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
2576 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
2577 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
2578 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
2579 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
2580 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
2581 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
2582 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
2583 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
2584 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
2585 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
2586 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
2587 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
2588 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
2589 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
2590 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
2591 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
2592 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
2593 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
2594 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
2595 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
2596 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
2597 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
2598 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
2599 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
2600 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
2601 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
2602 *
2603 * (*) value not defined in all devices.
2604 * @retval PLLI2S clock frequency (in Hz)
2605 */
2606 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
2607 #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2608 (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U)))
2609 #else
2610 #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2611 (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos)))
2612
2613 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
2614 #endif /* RCC_DCKCFGR_PLLI2SDIVQ || RCC_DCKCFGR_PLLI2SDIVR */
2615
2616 #if defined(SPDIFRX)
2617 /**
2618 * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
2619 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2620 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
2621 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2622 * @param __PLLM__ This parameter can be one of the following values:
2623 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2624 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2625 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2626 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2627 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2628 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2629 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2630 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2631 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2632 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2633 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2634 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2635 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2636 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2637 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2638 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2639 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2640 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2641 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2642 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2643 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2644 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2645 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2646 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2647 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2648 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2649 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2650 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2651 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2652 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2653 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2654 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2655 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2656 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2657 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2658 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2659 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2660 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2661 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2662 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2663 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2664 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2665 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2666 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2667 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2668 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2669 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2670 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2671 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2672 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2673 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2674 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2675 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2676 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2677 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2678 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2679 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2680 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2681 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2682 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2683 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2684 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2685 * @param __PLLI2SN__ Between 50 and 432
2686 * @param __PLLI2SP__ This parameter can be one of the following values:
2687 * @arg @ref LL_RCC_PLLI2SP_DIV_2
2688 * @arg @ref LL_RCC_PLLI2SP_DIV_4
2689 * @arg @ref LL_RCC_PLLI2SP_DIV_6
2690 * @arg @ref LL_RCC_PLLI2SP_DIV_8
2691 * @retval PLLI2S clock frequency (in Hz)
2692 */
2693 #define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2694 ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
2695
2696 #endif /* SPDIFRX */
2697
2698 /**
2699 * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
2700 * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2701 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
2702 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2703 * @param __PLLM__ This parameter can be one of the following values:
2704 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2705 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2706 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2707 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2708 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2709 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2710 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2711 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2712 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2713 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2714 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2715 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2716 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2717 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2718 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2719 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2720 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2721 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2722 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2723 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2724 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2725 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2726 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2727 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2728 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2729 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2730 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2731 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2732 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2733 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2734 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2735 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2736 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2737 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2738 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2739 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2740 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2741 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2742 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2743 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2744 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2745 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2746 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2747 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2748 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2749 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2750 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2751 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2752 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2753 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2754 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2755 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2756 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2757 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2758 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2759 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2760 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2761 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2762 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2763 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2764 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2765 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2766 * @param __PLLI2SN__ Between 50/192(*) and 432
2767 *
2768 * (*) value not defined in all devices.
2769 * @param __PLLI2SR__ This parameter can be one of the following values:
2770 * @arg @ref LL_RCC_PLLI2SR_DIV_2
2771 * @arg @ref LL_RCC_PLLI2SR_DIV_3
2772 * @arg @ref LL_RCC_PLLI2SR_DIV_4
2773 * @arg @ref LL_RCC_PLLI2SR_DIV_5
2774 * @arg @ref LL_RCC_PLLI2SR_DIV_6
2775 * @arg @ref LL_RCC_PLLI2SR_DIV_7
2776 * @retval PLLI2S clock frequency (in Hz)
2777 */
2778 #define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2779 ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
2780
2781 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
2782 /**
2783 * @brief Helper macro to calculate the PLLI2S frequency used for 48Mhz domain
2784 * @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2785 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ());
2786 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2787 * @param __PLLM__ This parameter can be one of the following values:
2788 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2789 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2790 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2791 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2792 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2793 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2794 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2795 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2796 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2797 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2798 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2799 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2800 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2801 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2802 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2803 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2804 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2805 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2806 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2807 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2808 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2809 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2810 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2811 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2812 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2813 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2814 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2815 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2816 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2817 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2818 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2819 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2820 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2821 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2822 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2823 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2824 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2825 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2826 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2827 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2828 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2829 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2830 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2831 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2832 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2833 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2834 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2835 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2836 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2837 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2838 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2839 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2840 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2841 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2842 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2843 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2844 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2845 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2846 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2847 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2848 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2849 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2850 * @param __PLLI2SN__ Between 50 and 432
2851 * @param __PLLI2SQ__ This parameter can be one of the following values:
2852 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
2853 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
2854 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
2855 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
2856 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
2857 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
2858 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
2859 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
2860 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
2861 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
2862 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
2863 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
2864 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
2865 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
2866 * @retval PLLI2S clock frequency (in Hz)
2867 */
2868 #define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2869 ((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos))
2870
2871 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
2872 #endif /* RCC_PLLI2S_SUPPORT */
2873
2874 /**
2875 * @brief Helper macro to calculate the HCLK frequency
2876 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
2877 * @param __AHBPRESCALER__ This parameter can be one of the following values:
2878 * @arg @ref LL_RCC_SYSCLK_DIV_1
2879 * @arg @ref LL_RCC_SYSCLK_DIV_2
2880 * @arg @ref LL_RCC_SYSCLK_DIV_4
2881 * @arg @ref LL_RCC_SYSCLK_DIV_8
2882 * @arg @ref LL_RCC_SYSCLK_DIV_16
2883 * @arg @ref LL_RCC_SYSCLK_DIV_64
2884 * @arg @ref LL_RCC_SYSCLK_DIV_128
2885 * @arg @ref LL_RCC_SYSCLK_DIV_256
2886 * @arg @ref LL_RCC_SYSCLK_DIV_512
2887 * @retval HCLK clock frequency (in Hz)
2888 */
2889 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
2890
2891 /**
2892 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
2893 * @param __HCLKFREQ__ HCLK frequency
2894 * @param __APB1PRESCALER__ This parameter can be one of the following values:
2895 * @arg @ref LL_RCC_APB1_DIV_1
2896 * @arg @ref LL_RCC_APB1_DIV_2
2897 * @arg @ref LL_RCC_APB1_DIV_4
2898 * @arg @ref LL_RCC_APB1_DIV_8
2899 * @arg @ref LL_RCC_APB1_DIV_16
2900 * @retval PCLK1 clock frequency (in Hz)
2901 */
2902 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
2903
2904 /**
2905 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
2906 * @param __HCLKFREQ__ HCLK frequency
2907 * @param __APB2PRESCALER__ This parameter can be one of the following values:
2908 * @arg @ref LL_RCC_APB2_DIV_1
2909 * @arg @ref LL_RCC_APB2_DIV_2
2910 * @arg @ref LL_RCC_APB2_DIV_4
2911 * @arg @ref LL_RCC_APB2_DIV_8
2912 * @arg @ref LL_RCC_APB2_DIV_16
2913 * @retval PCLK2 clock frequency (in Hz)
2914 */
2915 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
2916
2917 /**
2918 * @}
2919 */
2920
2921 /**
2922 * @}
2923 */
2924
2925 /* Exported functions --------------------------------------------------------*/
2926 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
2927 * @{
2928 */
2929
2930 /** @defgroup RCC_LL_EF_HSE HSE
2931 * @{
2932 */
2933
2934 /**
2935 * @brief Enable the Clock Security System.
2936 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
2937 * @retval None
2938 */
2939 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
2940 {
2941 SET_BIT(RCC->CR, RCC_CR_CSSON);
2942 }
2943
2944 /**
2945 * @brief Enable HSE external oscillator (HSE Bypass)
2946 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
2947 * @retval None
2948 */
2949 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
2950 {
2951 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
2952 }
2953
2954 /**
2955 * @brief Disable HSE external oscillator (HSE Bypass)
2956 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
2957 * @retval None
2958 */
2959 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
2960 {
2961 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
2962 }
2963
2964 /**
2965 * @brief Enable HSE crystal oscillator (HSE ON)
2966 * @rmtoll CR HSEON LL_RCC_HSE_Enable
2967 * @retval None
2968 */
2969 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
2970 {
2971 SET_BIT(RCC->CR, RCC_CR_HSEON);
2972 }
2973
2974 /**
2975 * @brief Disable HSE crystal oscillator (HSE ON)
2976 * @rmtoll CR HSEON LL_RCC_HSE_Disable
2977 * @retval None
2978 */
2979 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
2980 {
2981 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
2982 }
2983
2984 /**
2985 * @brief Check if HSE oscillator Ready
2986 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
2987 * @retval State of bit (1 or 0).
2988 */
2989 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
2990 {
2991 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
2992 }
2993
2994 /**
2995 * @}
2996 */
2997
2998 /** @defgroup RCC_LL_EF_HSI HSI
2999 * @{
3000 */
3001
3002 /**
3003 * @brief Enable HSI oscillator
3004 * @rmtoll CR HSION LL_RCC_HSI_Enable
3005 * @retval None
3006 */
3007 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
3008 {
3009 SET_BIT(RCC->CR, RCC_CR_HSION);
3010 }
3011
3012 /**
3013 * @brief Disable HSI oscillator
3014 * @rmtoll CR HSION LL_RCC_HSI_Disable
3015 * @retval None
3016 */
3017 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
3018 {
3019 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
3020 }
3021
3022 /**
3023 * @brief Check if HSI clock is ready
3024 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
3025 * @retval State of bit (1 or 0).
3026 */
3027 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
3028 {
3029 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
3030 }
3031
3032 /**
3033 * @brief Get HSI Calibration value
3034 * @note When HSITRIM is written, HSICAL is updated with the sum of
3035 * HSITRIM and the factory trim value
3036 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
3037 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
3038 */
3039 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
3040 {
3041 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
3042 }
3043
3044 /**
3045 * @brief Set HSI Calibration trimming
3046 * @note user-programmable trimming value that is added to the HSICAL
3047 * @note Default value is 16, which, when added to the HSICAL value,
3048 * should trim the HSI to 16 MHz +/- 1 %
3049 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
3050 * @param Value Between Min_Data = 0 and Max_Data = 31
3051 * @retval None
3052 */
3053 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
3054 {
3055 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
3056 }
3057
3058 /**
3059 * @brief Get HSI Calibration trimming
3060 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
3061 * @retval Between Min_Data = 0 and Max_Data = 31
3062 */
3063 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
3064 {
3065 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
3066 }
3067
3068 /**
3069 * @}
3070 */
3071
3072 /** @defgroup RCC_LL_EF_LSE LSE
3073 * @{
3074 */
3075
3076 /**
3077 * @brief Enable Low Speed External (LSE) crystal.
3078 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
3079 * @retval None
3080 */
3081 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
3082 {
3083 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
3084 }
3085
3086 /**
3087 * @brief Disable Low Speed External (LSE) crystal.
3088 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
3089 * @retval None
3090 */
3091 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
3092 {
3093 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
3094 }
3095
3096 /**
3097 * @brief Enable external clock source (LSE bypass).
3098 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
3099 * @retval None
3100 */
3101 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
3102 {
3103 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
3104 }
3105
3106 /**
3107 * @brief Disable external clock source (LSE bypass).
3108 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
3109 * @retval None
3110 */
3111 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
3112 {
3113 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
3114 }
3115
3116 /**
3117 * @brief Check if LSE oscillator Ready
3118 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
3119 * @retval State of bit (1 or 0).
3120 */
3121 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
3122 {
3123 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
3124 }
3125
3126 #if defined(RCC_BDCR_LSEMOD)
3127 /**
3128 * @brief Enable LSE high drive mode.
3129 * @note LSE high drive mode can be enabled only when the LSE clock is disabled
3130 * @rmtoll BDCR LSEMOD LL_RCC_LSE_EnableHighDriveMode
3131 * @retval None
3132 */
3133 __STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void)
3134 {
3135 SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
3136 }
3137
3138 /**
3139 * @brief Disable LSE high drive mode.
3140 * @note LSE high drive mode can be disabled only when the LSE clock is disabled
3141 * @rmtoll BDCR LSEMOD LL_RCC_LSE_DisableHighDriveMode
3142 * @retval None
3143 */
3144 __STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void)
3145 {
3146 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
3147 }
3148 #endif /* RCC_BDCR_LSEMOD */
3149
3150 /**
3151 * @}
3152 */
3153
3154 /** @defgroup RCC_LL_EF_LSI LSI
3155 * @{
3156 */
3157
3158 /**
3159 * @brief Enable LSI Oscillator
3160 * @rmtoll CSR LSION LL_RCC_LSI_Enable
3161 * @retval None
3162 */
3163 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
3164 {
3165 SET_BIT(RCC->CSR, RCC_CSR_LSION);
3166 }
3167
3168 /**
3169 * @brief Disable LSI Oscillator
3170 * @rmtoll CSR LSION LL_RCC_LSI_Disable
3171 * @retval None
3172 */
3173 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
3174 {
3175 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
3176 }
3177
3178 /**
3179 * @brief Check if LSI is Ready
3180 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
3181 * @retval State of bit (1 or 0).
3182 */
3183 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
3184 {
3185 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
3186 }
3187
3188 /**
3189 * @}
3190 */
3191
3192 /** @defgroup RCC_LL_EF_System System
3193 * @{
3194 */
3195
3196 /**
3197 * @brief Configure the system clock source
3198 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
3199 * @param Source This parameter can be one of the following values:
3200 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
3201 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
3202 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
3203 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*)
3204 *
3205 * (*) value not defined in all devices.
3206 * @retval None
3207 */
3208 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
3209 {
3210 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
3211 }
3212
3213 /**
3214 * @brief Get the system clock source
3215 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
3216 * @retval Returned value can be one of the following values:
3217 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
3218 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
3219 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
3220 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*)
3221 *
3222 * (*) value not defined in all devices.
3223 */
3224 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
3225 {
3226 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
3227 }
3228
3229 /**
3230 * @brief Set AHB prescaler
3231 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
3232 * @param Prescaler This parameter can be one of the following values:
3233 * @arg @ref LL_RCC_SYSCLK_DIV_1
3234 * @arg @ref LL_RCC_SYSCLK_DIV_2
3235 * @arg @ref LL_RCC_SYSCLK_DIV_4
3236 * @arg @ref LL_RCC_SYSCLK_DIV_8
3237 * @arg @ref LL_RCC_SYSCLK_DIV_16
3238 * @arg @ref LL_RCC_SYSCLK_DIV_64
3239 * @arg @ref LL_RCC_SYSCLK_DIV_128
3240 * @arg @ref LL_RCC_SYSCLK_DIV_256
3241 * @arg @ref LL_RCC_SYSCLK_DIV_512
3242 * @retval None
3243 */
3244 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
3245 {
3246 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
3247 }
3248
3249 /**
3250 * @brief Set APB1 prescaler
3251 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
3252 * @param Prescaler This parameter can be one of the following values:
3253 * @arg @ref LL_RCC_APB1_DIV_1
3254 * @arg @ref LL_RCC_APB1_DIV_2
3255 * @arg @ref LL_RCC_APB1_DIV_4
3256 * @arg @ref LL_RCC_APB1_DIV_8
3257 * @arg @ref LL_RCC_APB1_DIV_16
3258 * @retval None
3259 */
3260 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
3261 {
3262 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
3263 }
3264
3265 /**
3266 * @brief Set APB2 prescaler
3267 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
3268 * @param Prescaler This parameter can be one of the following values:
3269 * @arg @ref LL_RCC_APB2_DIV_1
3270 * @arg @ref LL_RCC_APB2_DIV_2
3271 * @arg @ref LL_RCC_APB2_DIV_4
3272 * @arg @ref LL_RCC_APB2_DIV_8
3273 * @arg @ref LL_RCC_APB2_DIV_16
3274 * @retval None
3275 */
3276 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
3277 {
3278 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
3279 }
3280
3281 /**
3282 * @brief Get AHB prescaler
3283 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
3284 * @retval Returned value can be one of the following values:
3285 * @arg @ref LL_RCC_SYSCLK_DIV_1
3286 * @arg @ref LL_RCC_SYSCLK_DIV_2
3287 * @arg @ref LL_RCC_SYSCLK_DIV_4
3288 * @arg @ref LL_RCC_SYSCLK_DIV_8
3289 * @arg @ref LL_RCC_SYSCLK_DIV_16
3290 * @arg @ref LL_RCC_SYSCLK_DIV_64
3291 * @arg @ref LL_RCC_SYSCLK_DIV_128
3292 * @arg @ref LL_RCC_SYSCLK_DIV_256
3293 * @arg @ref LL_RCC_SYSCLK_DIV_512
3294 */
3295 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
3296 {
3297 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
3298 }
3299
3300 /**
3301 * @brief Get APB1 prescaler
3302 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
3303 * @retval Returned value can be one of the following values:
3304 * @arg @ref LL_RCC_APB1_DIV_1
3305 * @arg @ref LL_RCC_APB1_DIV_2
3306 * @arg @ref LL_RCC_APB1_DIV_4
3307 * @arg @ref LL_RCC_APB1_DIV_8
3308 * @arg @ref LL_RCC_APB1_DIV_16
3309 */
3310 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
3311 {
3312 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
3313 }
3314
3315 /**
3316 * @brief Get APB2 prescaler
3317 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
3318 * @retval Returned value can be one of the following values:
3319 * @arg @ref LL_RCC_APB2_DIV_1
3320 * @arg @ref LL_RCC_APB2_DIV_2
3321 * @arg @ref LL_RCC_APB2_DIV_4
3322 * @arg @ref LL_RCC_APB2_DIV_8
3323 * @arg @ref LL_RCC_APB2_DIV_16
3324 */
3325 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
3326 {
3327 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
3328 }
3329
3330 /**
3331 * @}
3332 */
3333
3334 /** @defgroup RCC_LL_EF_MCO MCO
3335 * @{
3336 */
3337
3338 #if defined(RCC_CFGR_MCO1EN)
3339 /**
3340 * @brief Enable MCO1 output
3341 * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Enable
3342 * @retval None
3343 */
3344 __STATIC_INLINE void LL_RCC_MCO1_Enable(void)
3345 {
3346 SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
3347 }
3348
3349 /**
3350 * @brief Disable MCO1 output
3351 * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Disable
3352 * @retval None
3353 */
3354 __STATIC_INLINE void LL_RCC_MCO1_Disable(void)
3355 {
3356 CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
3357 }
3358 #endif /* RCC_CFGR_MCO1EN */
3359
3360 #if defined(RCC_CFGR_MCO2EN)
3361 /**
3362 * @brief Enable MCO2 output
3363 * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Enable
3364 * @retval None
3365 */
3366 __STATIC_INLINE void LL_RCC_MCO2_Enable(void)
3367 {
3368 SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
3369 }
3370
3371 /**
3372 * @brief Disable MCO2 output
3373 * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Disable
3374 * @retval None
3375 */
3376 __STATIC_INLINE void LL_RCC_MCO2_Disable(void)
3377 {
3378 CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
3379 }
3380 #endif /* RCC_CFGR_MCO2EN */
3381
3382 /**
3383 * @brief Configure MCOx
3384 * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
3385 * CFGR MCO1PRE LL_RCC_ConfigMCO\n
3386 * CFGR MCO2 LL_RCC_ConfigMCO\n
3387 * CFGR MCO2PRE LL_RCC_ConfigMCO
3388 * @param MCOxSource This parameter can be one of the following values:
3389 * @arg @ref LL_RCC_MCO1SOURCE_HSI
3390 * @arg @ref LL_RCC_MCO1SOURCE_LSE
3391 * @arg @ref LL_RCC_MCO1SOURCE_HSE
3392 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
3393 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
3394 * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
3395 * @arg @ref LL_RCC_MCO2SOURCE_HSE
3396 * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
3397 * @param MCOxPrescaler This parameter can be one of the following values:
3398 * @arg @ref LL_RCC_MCO1_DIV_1
3399 * @arg @ref LL_RCC_MCO1_DIV_2
3400 * @arg @ref LL_RCC_MCO1_DIV_3
3401 * @arg @ref LL_RCC_MCO1_DIV_4
3402 * @arg @ref LL_RCC_MCO1_DIV_5
3403 * @arg @ref LL_RCC_MCO2_DIV_1
3404 * @arg @ref LL_RCC_MCO2_DIV_2
3405 * @arg @ref LL_RCC_MCO2_DIV_3
3406 * @arg @ref LL_RCC_MCO2_DIV_4
3407 * @arg @ref LL_RCC_MCO2_DIV_5
3408 * @retval None
3409 */
3410 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
3411 {
3412 MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U));
3413 }
3414
3415 /**
3416 * @}
3417 */
3418
3419 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
3420 * @{
3421 */
3422 #if defined(FMPI2C1)
3423 /**
3424 * @brief Configure FMPI2C clock source
3425 * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_SetFMPI2CClockSource
3426 * @param FMPI2CxSource This parameter can be one of the following values:
3427 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
3428 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
3429 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
3430 * @retval None
3431 */
3432 __STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)
3433 {
3434 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource);
3435 }
3436 #endif /* FMPI2C1 */
3437
3438 #if defined(LPTIM1)
3439 /**
3440 * @brief Configure LPTIMx clock source
3441 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource
3442 * @param LPTIMxSource This parameter can be one of the following values:
3443 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3444 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
3445 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3446 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3447 * @retval None
3448 */
3449 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
3450 {
3451 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
3452 }
3453 #endif /* LPTIM1 */
3454
3455 #if defined(SAI1)
3456 /**
3457 * @brief Configure SAIx clock source
3458 * @rmtoll DCKCFGR SAI1SRC LL_RCC_SetSAIClockSource\n
3459 * DCKCFGR SAI2SRC LL_RCC_SetSAIClockSource\n
3460 * DCKCFGR SAI1ASRC LL_RCC_SetSAIClockSource\n
3461 * DCKCFGR SAI1BSRC LL_RCC_SetSAIClockSource
3462 * @param SAIxSource This parameter can be one of the following values:
3463 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
3464 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
3465 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
3466 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
3467 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
3468 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
3469 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
3470 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
3471 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
3472 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
3473 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
3474 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
3475 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
3476 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
3477 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
3478 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
3479 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
3480 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
3481 *
3482 * (*) value not defined in all devices.
3483 * @retval None
3484 */
3485 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
3486 {
3487 MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
3488 }
3489 #endif /* SAI1 */
3490
3491 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
3492 /**
3493 * @brief Configure SDIO clock source
3494 * @rmtoll DCKCFGR SDIOSEL LL_RCC_SetSDIOClockSource\n
3495 * DCKCFGR2 SDIOSEL LL_RCC_SetSDIOClockSource
3496 * @param SDIOxSource This parameter can be one of the following values:
3497 * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
3498 * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
3499 * @retval None
3500 */
3501 __STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)
3502 {
3503 #if defined(RCC_DCKCFGR_SDIOSEL)
3504 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource);
3505 #else
3506 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource);
3507 #endif /* RCC_DCKCFGR_SDIOSEL */
3508 }
3509 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
3510
3511 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
3512 /**
3513 * @brief Configure 48Mhz domain clock source
3514 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetCK48MClockSource\n
3515 * DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource
3516 * @param CK48MxSource This parameter can be one of the following values:
3517 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
3518 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
3519 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
3520 *
3521 * (*) value not defined in all devices.
3522 * @retval None
3523 */
3524 __STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
3525 {
3526 #if defined(RCC_DCKCFGR_CK48MSEL)
3527 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource);
3528 #else
3529 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
3530 #endif /* RCC_DCKCFGR_CK48MSEL */
3531 }
3532
3533 #if defined(RNG)
3534 /**
3535 * @brief Configure RNG clock source
3536 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetRNGClockSource\n
3537 * DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource
3538 * @param RNGxSource This parameter can be one of the following values:
3539 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
3540 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
3541 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
3542 *
3543 * (*) value not defined in all devices.
3544 * @retval None
3545 */
3546 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
3547 {
3548 #if defined(RCC_DCKCFGR_CK48MSEL)
3549 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource);
3550 #else
3551 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
3552 #endif /* RCC_DCKCFGR_CK48MSEL */
3553 }
3554 #endif /* RNG */
3555
3556 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
3557 /**
3558 * @brief Configure USB clock source
3559 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetUSBClockSource\n
3560 * DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource
3561 * @param USBxSource This parameter can be one of the following values:
3562 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
3563 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
3564 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
3565 *
3566 * (*) value not defined in all devices.
3567 * @retval None
3568 */
3569 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
3570 {
3571 #if defined(RCC_DCKCFGR_CK48MSEL)
3572 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource);
3573 #else
3574 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
3575 #endif /* RCC_DCKCFGR_CK48MSEL */
3576 }
3577 #endif /* USB_OTG_FS || USB_OTG_HS */
3578 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
3579
3580 #if defined(CEC)
3581 /**
3582 * @brief Configure CEC clock source
3583 * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource
3584 * @param Source This parameter can be one of the following values:
3585 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
3586 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3587 * @retval None
3588 */
3589 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
3590 {
3591 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
3592 }
3593 #endif /* CEC */
3594
3595 /**
3596 * @brief Configure I2S clock source
3597 * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource\n
3598 * DCKCFGR I2SSRC LL_RCC_SetI2SClockSource\n
3599 * DCKCFGR I2S1SRC LL_RCC_SetI2SClockSource\n
3600 * DCKCFGR I2S2SRC LL_RCC_SetI2SClockSource
3601 * @param Source This parameter can be one of the following values:
3602 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
3603 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
3604 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
3605 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
3606 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
3607 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
3608 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
3609 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
3610 *
3611 * (*) value not defined in all devices.
3612 * @retval None
3613 */
3614 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
3615 {
3616 #if defined(RCC_CFGR_I2SSRC)
3617 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
3618 #else
3619 MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U));
3620 #endif /* RCC_CFGR_I2SSRC */
3621 }
3622
3623 #if defined(DSI)
3624 /**
3625 * @brief Configure DSI clock source
3626 * @rmtoll DCKCFGR DSISEL LL_RCC_SetDSIClockSource
3627 * @param Source This parameter can be one of the following values:
3628 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3629 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
3630 * @retval None
3631 */
3632 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
3633 {
3634 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source);
3635 }
3636 #endif /* DSI */
3637
3638 #if defined(DFSDM1_Channel0)
3639 /**
3640 * @brief Configure DFSDM Audio clock source
3641 * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_SetDFSDMAudioClockSource\n
3642 * DCKCFGR CKDFSDM2ASEL LL_RCC_SetDFSDMAudioClockSource
3643 * @param Source This parameter can be one of the following values:
3644 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
3645 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
3646 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
3647 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
3648 *
3649 * (*) value not defined in all devices.
3650 * @retval None
3651 */
3652 __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
3653 {
3654 MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U));
3655 }
3656
3657 /**
3658 * @brief Configure DFSDM Kernel clock source
3659 * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_SetDFSDMClockSource
3660 * @param Source This parameter can be one of the following values:
3661 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3662 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3663 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
3664 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
3665 *
3666 * (*) value not defined in all devices.
3667 * @retval None
3668 */
3669 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
3670 {
3671 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source);
3672 }
3673 #endif /* DFSDM1_Channel0 */
3674
3675 #if defined(SPDIFRX)
3676 /**
3677 * @brief Configure SPDIFRX clock source
3678 * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_SetSPDIFRXClockSource
3679 * @param SPDIFRXxSource This parameter can be one of the following values:
3680 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
3681 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
3682 *
3683 * (*) value not defined in all devices.
3684 * @retval None
3685 */
3686 __STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)
3687 {
3688 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource);
3689 }
3690 #endif /* SPDIFRX */
3691
3692 #if defined(FMPI2C1)
3693 /**
3694 * @brief Get FMPI2C clock source
3695 * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_GetFMPI2CClockSource
3696 * @param FMPI2Cx This parameter can be one of the following values:
3697 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
3698 * @retval Returned value can be one of the following values:
3699 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
3700 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
3701 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
3702 */
3703 __STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)
3704 {
3705 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx));
3706 }
3707 #endif /* FMPI2C1 */
3708
3709 #if defined(LPTIM1)
3710 /**
3711 * @brief Get LPTIMx clock source
3712 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource
3713 * @param LPTIMx This parameter can be one of the following values:
3714 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3715 * @retval Returned value can be one of the following values:
3716 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3717 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
3718 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3719 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3720 */
3721 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
3722 {
3723 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
3724 }
3725 #endif /* LPTIM1 */
3726
3727 #if defined(SAI1)
3728 /**
3729 * @brief Get SAIx clock source
3730 * @rmtoll DCKCFGR SAI1SEL LL_RCC_GetSAIClockSource\n
3731 * DCKCFGR SAI2SEL LL_RCC_GetSAIClockSource\n
3732 * DCKCFGR SAI1ASRC LL_RCC_GetSAIClockSource\n
3733 * DCKCFGR SAI1BSRC LL_RCC_GetSAIClockSource
3734 * @param SAIx This parameter can be one of the following values:
3735 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
3736 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
3737 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
3738 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
3739 *
3740 * (*) value not defined in all devices.
3741 * @retval Returned value can be one of the following values:
3742 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
3743 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
3744 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
3745 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
3746 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
3747 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
3748 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
3749 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
3750 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
3751 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
3752 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
3753 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
3754 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
3755 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
3756 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
3757 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
3758 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
3759 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
3760 *
3761 * (*) value not defined in all devices.
3762 */
3763 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
3764 {
3765 return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U | SAIx);
3766 }
3767 #endif /* SAI1 */
3768
3769 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
3770 /**
3771 * @brief Get SDIOx clock source
3772 * @rmtoll DCKCFGR SDIOSEL LL_RCC_GetSDIOClockSource\n
3773 * DCKCFGR2 SDIOSEL LL_RCC_GetSDIOClockSource
3774 * @param SDIOx This parameter can be one of the following values:
3775 * @arg @ref LL_RCC_SDIO_CLKSOURCE
3776 * @retval Returned value can be one of the following values:
3777 * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
3778 * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
3779 */
3780 __STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx)
3781 {
3782 #if defined(RCC_DCKCFGR_SDIOSEL)
3783 return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx));
3784 #else
3785 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx));
3786 #endif /* RCC_DCKCFGR_SDIOSEL */
3787 }
3788 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
3789
3790 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
3791 /**
3792 * @brief Get 48Mhz domain clock source
3793 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetCK48MClockSource\n
3794 * DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource
3795 * @param CK48Mx This parameter can be one of the following values:
3796 * @arg @ref LL_RCC_CK48M_CLKSOURCE
3797 * @retval Returned value can be one of the following values:
3798 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
3799 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
3800 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
3801 *
3802 * (*) value not defined in all devices.
3803 */
3804 __STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
3805 {
3806 #if defined(RCC_DCKCFGR_CK48MSEL)
3807 return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx));
3808 #else
3809 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
3810 #endif /* RCC_DCKCFGR_CK48MSEL */
3811 }
3812
3813 #if defined(RNG)
3814 /**
3815 * @brief Get RNGx clock source
3816 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetRNGClockSource\n
3817 * DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource
3818 * @param RNGx This parameter can be one of the following values:
3819 * @arg @ref LL_RCC_RNG_CLKSOURCE
3820 * @retval Returned value can be one of the following values:
3821 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
3822 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
3823 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
3824 *
3825 * (*) value not defined in all devices.
3826 */
3827 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
3828 {
3829 #if defined(RCC_DCKCFGR_CK48MSEL)
3830 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx));
3831 #else
3832 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
3833 #endif /* RCC_DCKCFGR_CK48MSEL */
3834 }
3835 #endif /* RNG */
3836
3837 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
3838 /**
3839 * @brief Get USBx clock source
3840 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetUSBClockSource\n
3841 * DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource
3842 * @param USBx This parameter can be one of the following values:
3843 * @arg @ref LL_RCC_USB_CLKSOURCE
3844 * @retval Returned value can be one of the following values:
3845 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
3846 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
3847 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
3848 *
3849 * (*) value not defined in all devices.
3850 */
3851 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
3852 {
3853 #if defined(RCC_DCKCFGR_CK48MSEL)
3854 return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx));
3855 #else
3856 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
3857 #endif /* RCC_DCKCFGR_CK48MSEL */
3858 }
3859 #endif /* USB_OTG_FS || USB_OTG_HS */
3860 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
3861
3862 #if defined(CEC)
3863 /**
3864 * @brief Get CEC Clock Source
3865 * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource
3866 * @param CECx This parameter can be one of the following values:
3867 * @arg @ref LL_RCC_CEC_CLKSOURCE
3868 * @retval Returned value can be one of the following values:
3869 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
3870 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3871 */
3872 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
3873 {
3874 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
3875 }
3876 #endif /* CEC */
3877
3878 /**
3879 * @brief Get I2S Clock Source
3880 * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource\n
3881 * DCKCFGR I2SSRC LL_RCC_GetI2SClockSource\n
3882 * DCKCFGR I2S1SRC LL_RCC_GetI2SClockSource\n
3883 * DCKCFGR I2S2SRC LL_RCC_GetI2SClockSource
3884 * @param I2Sx This parameter can be one of the following values:
3885 * @arg @ref LL_RCC_I2S1_CLKSOURCE
3886 * @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
3887 * @retval Returned value can be one of the following values:
3888 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
3889 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
3890 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
3891 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
3892 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
3893 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
3894 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
3895 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
3896 *
3897 * (*) value not defined in all devices.
3898 */
3899 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
3900 {
3901 #if defined(RCC_CFGR_I2SSRC)
3902 return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
3903 #else
3904 return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U | I2Sx);
3905 #endif /* RCC_CFGR_I2SSRC */
3906 }
3907
3908 #if defined(DFSDM1_Channel0)
3909 /**
3910 * @brief Get DFSDM Audio Clock Source
3911 * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_GetDFSDMAudioClockSource\n
3912 * DCKCFGR CKDFSDM2ASEL LL_RCC_GetDFSDMAudioClockSource
3913 * @param DFSDMx This parameter can be one of the following values:
3914 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
3915 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
3916 * @retval Returned value can be one of the following values:
3917 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
3918 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
3919 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
3920 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
3921 *
3922 * (*) value not defined in all devices.
3923 */
3924 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
3925 {
3926 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U | DFSDMx);
3927 }
3928
3929 /**
3930 * @brief Get DFSDM Audio Clock Source
3931 * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_GetDFSDMClockSource
3932 * @param DFSDMx This parameter can be one of the following values:
3933 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
3934 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
3935 * @retval Returned value can be one of the following values:
3936 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3937 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3938 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
3939 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
3940 *
3941 * (*) value not defined in all devices.
3942 */
3943 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
3944 {
3945 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx));
3946 }
3947 #endif /* DFSDM1_Channel0 */
3948
3949 #if defined(SPDIFRX)
3950 /**
3951 * @brief Get SPDIFRX clock source
3952 * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_GetSPDIFRXClockSource
3953 * @param SPDIFRXx This parameter can be one of the following values:
3954 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
3955 * @retval Returned value can be one of the following values:
3956 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
3957 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
3958 *
3959 * (*) value not defined in all devices.
3960 */
3961 __STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)
3962 {
3963 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx));
3964 }
3965 #endif /* SPDIFRX */
3966
3967 #if defined(DSI)
3968 /**
3969 * @brief Get DSI Clock Source
3970 * @rmtoll DCKCFGR DSISEL LL_RCC_GetDSIClockSource
3971 * @param DSIx This parameter can be one of the following values:
3972 * @arg @ref LL_RCC_DSI_CLKSOURCE
3973 * @retval Returned value can be one of the following values:
3974 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3975 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
3976 */
3977 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
3978 {
3979 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx));
3980 }
3981 #endif /* DSI */
3982
3983 /**
3984 * @}
3985 */
3986
3987 /** @defgroup RCC_LL_EF_RTC RTC
3988 * @{
3989 */
3990
3991 /**
3992 * @brief Set RTC Clock Source
3993 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
3994 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
3995 * set). The BDRST bit can be used to reset them.
3996 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
3997 * @param Source This parameter can be one of the following values:
3998 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3999 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
4000 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
4001 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
4002 * @retval None
4003 */
4004 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
4005 {
4006 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
4007 }
4008
4009 /**
4010 * @brief Get RTC Clock Source
4011 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
4012 * @retval Returned value can be one of the following values:
4013 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
4014 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
4015 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
4016 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
4017 */
4018 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
4019 {
4020 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
4021 }
4022
4023 /**
4024 * @brief Enable RTC
4025 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
4026 * @retval None
4027 */
4028 __STATIC_INLINE void LL_RCC_EnableRTC(void)
4029 {
4030 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
4031 }
4032
4033 /**
4034 * @brief Disable RTC
4035 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
4036 * @retval None
4037 */
4038 __STATIC_INLINE void LL_RCC_DisableRTC(void)
4039 {
4040 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
4041 }
4042
4043 /**
4044 * @brief Check if RTC has been enabled or not
4045 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
4046 * @retval State of bit (1 or 0).
4047 */
4048 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
4049 {
4050 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
4051 }
4052
4053 /**
4054 * @brief Force the Backup domain reset
4055 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
4056 * @retval None
4057 */
4058 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
4059 {
4060 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
4061 }
4062
4063 /**
4064 * @brief Release the Backup domain reset
4065 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
4066 * @retval None
4067 */
4068 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
4069 {
4070 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
4071 }
4072
4073 /**
4074 * @brief Set HSE Prescalers for RTC Clock
4075 * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
4076 * @param Prescaler This parameter can be one of the following values:
4077 * @arg @ref LL_RCC_RTC_NOCLOCK
4078 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4079 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4080 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4081 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4082 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4083 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4084 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4085 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4086 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4087 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4088 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4089 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4090 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4091 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4092 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4093 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4094 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4095 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4096 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4097 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4098 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4099 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4100 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4101 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4102 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4103 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4104 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4105 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4106 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4107 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4108 * @retval None
4109 */
4110 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
4111 {
4112 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
4113 }
4114
4115 /**
4116 * @brief Get HSE Prescalers for RTC Clock
4117 * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
4118 * @retval Returned value can be one of the following values:
4119 * @arg @ref LL_RCC_RTC_NOCLOCK
4120 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4121 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4122 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4123 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4124 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4125 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4126 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4127 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4128 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4129 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4130 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4131 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4132 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4133 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4134 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4135 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4136 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4137 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4138 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4139 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4140 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4141 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4142 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4143 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4144 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4145 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4146 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4147 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4148 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4149 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4150 */
4151 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
4152 {
4153 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
4154 }
4155
4156 /**
4157 * @}
4158 */
4159
4160 #if defined(RCC_DCKCFGR_TIMPRE)
4161 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
4162 * @{
4163 */
4164
4165 /**
4166 * @brief Set Timers Clock Prescalers
4167 * @rmtoll DCKCFGR TIMPRE LL_RCC_SetTIMPrescaler
4168 * @param Prescaler This parameter can be one of the following values:
4169 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4170 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4171 * @retval None
4172 */
4173 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
4174 {
4175 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler);
4176 }
4177
4178 /**
4179 * @brief Get Timers Clock Prescalers
4180 * @rmtoll DCKCFGR TIMPRE LL_RCC_GetTIMPrescaler
4181 * @retval Returned value can be one of the following values:
4182 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4183 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4184 */
4185 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
4186 {
4187 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE));
4188 }
4189
4190 /**
4191 * @}
4192 */
4193 #endif /* RCC_DCKCFGR_TIMPRE */
4194
4195 /** @defgroup RCC_LL_EF_PLL PLL
4196 * @{
4197 */
4198
4199 /**
4200 * @brief Enable PLL
4201 * @rmtoll CR PLLON LL_RCC_PLL_Enable
4202 * @retval None
4203 */
4204 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
4205 {
4206 SET_BIT(RCC->CR, RCC_CR_PLLON);
4207 }
4208
4209 /**
4210 * @brief Disable PLL
4211 * @note Cannot be disabled if the PLL clock is used as the system clock
4212 * @rmtoll CR PLLON LL_RCC_PLL_Disable
4213 * @retval None
4214 */
4215 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
4216 {
4217 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
4218 }
4219
4220 /**
4221 * @brief Check if PLL Ready
4222 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
4223 * @retval State of bit (1 or 0).
4224 */
4225 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
4226 {
4227 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
4228 }
4229
4230 /**
4231 * @brief Configure PLL used for SYSCLK Domain
4232 * @note PLL Source and PLLM Divider can be written only when PLL,
4233 * PLLI2S and PLLSAI(*) are disabled
4234 * @note PLLN/PLLP can be written only when PLL is disabled
4235 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
4236 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
4237 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
4238 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS\n
4239 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
4240 * @param Source This parameter can be one of the following values:
4241 * @arg @ref LL_RCC_PLLSOURCE_HSI
4242 * @arg @ref LL_RCC_PLLSOURCE_HSE
4243 * @param PLLM This parameter can be one of the following values:
4244 * @arg @ref LL_RCC_PLLM_DIV_2
4245 * @arg @ref LL_RCC_PLLM_DIV_3
4246 * @arg @ref LL_RCC_PLLM_DIV_4
4247 * @arg @ref LL_RCC_PLLM_DIV_5
4248 * @arg @ref LL_RCC_PLLM_DIV_6
4249 * @arg @ref LL_RCC_PLLM_DIV_7
4250 * @arg @ref LL_RCC_PLLM_DIV_8
4251 * @arg @ref LL_RCC_PLLM_DIV_9
4252 * @arg @ref LL_RCC_PLLM_DIV_10
4253 * @arg @ref LL_RCC_PLLM_DIV_11
4254 * @arg @ref LL_RCC_PLLM_DIV_12
4255 * @arg @ref LL_RCC_PLLM_DIV_13
4256 * @arg @ref LL_RCC_PLLM_DIV_14
4257 * @arg @ref LL_RCC_PLLM_DIV_15
4258 * @arg @ref LL_RCC_PLLM_DIV_16
4259 * @arg @ref LL_RCC_PLLM_DIV_17
4260 * @arg @ref LL_RCC_PLLM_DIV_18
4261 * @arg @ref LL_RCC_PLLM_DIV_19
4262 * @arg @ref LL_RCC_PLLM_DIV_20
4263 * @arg @ref LL_RCC_PLLM_DIV_21
4264 * @arg @ref LL_RCC_PLLM_DIV_22
4265 * @arg @ref LL_RCC_PLLM_DIV_23
4266 * @arg @ref LL_RCC_PLLM_DIV_24
4267 * @arg @ref LL_RCC_PLLM_DIV_25
4268 * @arg @ref LL_RCC_PLLM_DIV_26
4269 * @arg @ref LL_RCC_PLLM_DIV_27
4270 * @arg @ref LL_RCC_PLLM_DIV_28
4271 * @arg @ref LL_RCC_PLLM_DIV_29
4272 * @arg @ref LL_RCC_PLLM_DIV_30
4273 * @arg @ref LL_RCC_PLLM_DIV_31
4274 * @arg @ref LL_RCC_PLLM_DIV_32
4275 * @arg @ref LL_RCC_PLLM_DIV_33
4276 * @arg @ref LL_RCC_PLLM_DIV_34
4277 * @arg @ref LL_RCC_PLLM_DIV_35
4278 * @arg @ref LL_RCC_PLLM_DIV_36
4279 * @arg @ref LL_RCC_PLLM_DIV_37
4280 * @arg @ref LL_RCC_PLLM_DIV_38
4281 * @arg @ref LL_RCC_PLLM_DIV_39
4282 * @arg @ref LL_RCC_PLLM_DIV_40
4283 * @arg @ref LL_RCC_PLLM_DIV_41
4284 * @arg @ref LL_RCC_PLLM_DIV_42
4285 * @arg @ref LL_RCC_PLLM_DIV_43
4286 * @arg @ref LL_RCC_PLLM_DIV_44
4287 * @arg @ref LL_RCC_PLLM_DIV_45
4288 * @arg @ref LL_RCC_PLLM_DIV_46
4289 * @arg @ref LL_RCC_PLLM_DIV_47
4290 * @arg @ref LL_RCC_PLLM_DIV_48
4291 * @arg @ref LL_RCC_PLLM_DIV_49
4292 * @arg @ref LL_RCC_PLLM_DIV_50
4293 * @arg @ref LL_RCC_PLLM_DIV_51
4294 * @arg @ref LL_RCC_PLLM_DIV_52
4295 * @arg @ref LL_RCC_PLLM_DIV_53
4296 * @arg @ref LL_RCC_PLLM_DIV_54
4297 * @arg @ref LL_RCC_PLLM_DIV_55
4298 * @arg @ref LL_RCC_PLLM_DIV_56
4299 * @arg @ref LL_RCC_PLLM_DIV_57
4300 * @arg @ref LL_RCC_PLLM_DIV_58
4301 * @arg @ref LL_RCC_PLLM_DIV_59
4302 * @arg @ref LL_RCC_PLLM_DIV_60
4303 * @arg @ref LL_RCC_PLLM_DIV_61
4304 * @arg @ref LL_RCC_PLLM_DIV_62
4305 * @arg @ref LL_RCC_PLLM_DIV_63
4306 * @param PLLN Between 50/192(*) and 432
4307 *
4308 * (*) value not defined in all devices.
4309 * @param PLLP_R This parameter can be one of the following values:
4310 * @arg @ref LL_RCC_PLLP_DIV_2
4311 * @arg @ref LL_RCC_PLLP_DIV_4
4312 * @arg @ref LL_RCC_PLLP_DIV_6
4313 * @arg @ref LL_RCC_PLLP_DIV_8
4314 * @arg @ref LL_RCC_PLLR_DIV_2 (*)
4315 * @arg @ref LL_RCC_PLLR_DIV_3 (*)
4316 * @arg @ref LL_RCC_PLLR_DIV_4 (*)
4317 * @arg @ref LL_RCC_PLLR_DIV_5 (*)
4318 * @arg @ref LL_RCC_PLLR_DIV_6 (*)
4319 * @arg @ref LL_RCC_PLLR_DIV_7 (*)
4320 *
4321 * (*) value not defined in all devices.
4322 * @retval None
4323 */
4324 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R)
4325 {
4326 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN,
4327 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos);
4328 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R);
4329 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
4330 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R);
4331 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
4332 }
4333
4334 /**
4335 * @brief Configure PLL used for 48Mhz domain clock
4336 * @note PLL Source and PLLM Divider can be written only when PLL,
4337 * PLLI2S and PLLSAI(*) are disabled
4338 * @note PLLN/PLLQ can be written only when PLL is disabled
4339 * @note This can be selected for USB, RNG, SDIO
4340 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
4341 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
4342 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
4343 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
4344 * @param Source This parameter can be one of the following values:
4345 * @arg @ref LL_RCC_PLLSOURCE_HSI
4346 * @arg @ref LL_RCC_PLLSOURCE_HSE
4347 * @param PLLM This parameter can be one of the following values:
4348 * @arg @ref LL_RCC_PLLM_DIV_2
4349 * @arg @ref LL_RCC_PLLM_DIV_3
4350 * @arg @ref LL_RCC_PLLM_DIV_4
4351 * @arg @ref LL_RCC_PLLM_DIV_5
4352 * @arg @ref LL_RCC_PLLM_DIV_6
4353 * @arg @ref LL_RCC_PLLM_DIV_7
4354 * @arg @ref LL_RCC_PLLM_DIV_8
4355 * @arg @ref LL_RCC_PLLM_DIV_9
4356 * @arg @ref LL_RCC_PLLM_DIV_10
4357 * @arg @ref LL_RCC_PLLM_DIV_11
4358 * @arg @ref LL_RCC_PLLM_DIV_12
4359 * @arg @ref LL_RCC_PLLM_DIV_13
4360 * @arg @ref LL_RCC_PLLM_DIV_14
4361 * @arg @ref LL_RCC_PLLM_DIV_15
4362 * @arg @ref LL_RCC_PLLM_DIV_16
4363 * @arg @ref LL_RCC_PLLM_DIV_17
4364 * @arg @ref LL_RCC_PLLM_DIV_18
4365 * @arg @ref LL_RCC_PLLM_DIV_19
4366 * @arg @ref LL_RCC_PLLM_DIV_20
4367 * @arg @ref LL_RCC_PLLM_DIV_21
4368 * @arg @ref LL_RCC_PLLM_DIV_22
4369 * @arg @ref LL_RCC_PLLM_DIV_23
4370 * @arg @ref LL_RCC_PLLM_DIV_24
4371 * @arg @ref LL_RCC_PLLM_DIV_25
4372 * @arg @ref LL_RCC_PLLM_DIV_26
4373 * @arg @ref LL_RCC_PLLM_DIV_27
4374 * @arg @ref LL_RCC_PLLM_DIV_28
4375 * @arg @ref LL_RCC_PLLM_DIV_29
4376 * @arg @ref LL_RCC_PLLM_DIV_30
4377 * @arg @ref LL_RCC_PLLM_DIV_31
4378 * @arg @ref LL_RCC_PLLM_DIV_32
4379 * @arg @ref LL_RCC_PLLM_DIV_33
4380 * @arg @ref LL_RCC_PLLM_DIV_34
4381 * @arg @ref LL_RCC_PLLM_DIV_35
4382 * @arg @ref LL_RCC_PLLM_DIV_36
4383 * @arg @ref LL_RCC_PLLM_DIV_37
4384 * @arg @ref LL_RCC_PLLM_DIV_38
4385 * @arg @ref LL_RCC_PLLM_DIV_39
4386 * @arg @ref LL_RCC_PLLM_DIV_40
4387 * @arg @ref LL_RCC_PLLM_DIV_41
4388 * @arg @ref LL_RCC_PLLM_DIV_42
4389 * @arg @ref LL_RCC_PLLM_DIV_43
4390 * @arg @ref LL_RCC_PLLM_DIV_44
4391 * @arg @ref LL_RCC_PLLM_DIV_45
4392 * @arg @ref LL_RCC_PLLM_DIV_46
4393 * @arg @ref LL_RCC_PLLM_DIV_47
4394 * @arg @ref LL_RCC_PLLM_DIV_48
4395 * @arg @ref LL_RCC_PLLM_DIV_49
4396 * @arg @ref LL_RCC_PLLM_DIV_50
4397 * @arg @ref LL_RCC_PLLM_DIV_51
4398 * @arg @ref LL_RCC_PLLM_DIV_52
4399 * @arg @ref LL_RCC_PLLM_DIV_53
4400 * @arg @ref LL_RCC_PLLM_DIV_54
4401 * @arg @ref LL_RCC_PLLM_DIV_55
4402 * @arg @ref LL_RCC_PLLM_DIV_56
4403 * @arg @ref LL_RCC_PLLM_DIV_57
4404 * @arg @ref LL_RCC_PLLM_DIV_58
4405 * @arg @ref LL_RCC_PLLM_DIV_59
4406 * @arg @ref LL_RCC_PLLM_DIV_60
4407 * @arg @ref LL_RCC_PLLM_DIV_61
4408 * @arg @ref LL_RCC_PLLM_DIV_62
4409 * @arg @ref LL_RCC_PLLM_DIV_63
4410 * @param PLLN Between 50/192(*) and 432
4411 *
4412 * (*) value not defined in all devices.
4413 * @param PLLQ This parameter can be one of the following values:
4414 * @arg @ref LL_RCC_PLLQ_DIV_2
4415 * @arg @ref LL_RCC_PLLQ_DIV_3
4416 * @arg @ref LL_RCC_PLLQ_DIV_4
4417 * @arg @ref LL_RCC_PLLQ_DIV_5
4418 * @arg @ref LL_RCC_PLLQ_DIV_6
4419 * @arg @ref LL_RCC_PLLQ_DIV_7
4420 * @arg @ref LL_RCC_PLLQ_DIV_8
4421 * @arg @ref LL_RCC_PLLQ_DIV_9
4422 * @arg @ref LL_RCC_PLLQ_DIV_10
4423 * @arg @ref LL_RCC_PLLQ_DIV_11
4424 * @arg @ref LL_RCC_PLLQ_DIV_12
4425 * @arg @ref LL_RCC_PLLQ_DIV_13
4426 * @arg @ref LL_RCC_PLLQ_DIV_14
4427 * @arg @ref LL_RCC_PLLQ_DIV_15
4428 * @retval None
4429 */
4430 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
4431 {
4432 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
4433 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
4434 }
4435
4436 #if defined(DSI)
4437 /**
4438 * @brief Configure PLL used for DSI clock
4439 * @note PLL Source and PLLM Divider can be written only when PLL,
4440 * PLLI2S and PLLSAI are disabled
4441 * @note PLLN/PLLR can be written only when PLL is disabled
4442 * @note This can be selected for DSI
4443 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n
4444 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n
4445 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n
4446 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI
4447 * @param Source This parameter can be one of the following values:
4448 * @arg @ref LL_RCC_PLLSOURCE_HSI
4449 * @arg @ref LL_RCC_PLLSOURCE_HSE
4450 * @param PLLM This parameter can be one of the following values:
4451 * @arg @ref LL_RCC_PLLM_DIV_2
4452 * @arg @ref LL_RCC_PLLM_DIV_3
4453 * @arg @ref LL_RCC_PLLM_DIV_4
4454 * @arg @ref LL_RCC_PLLM_DIV_5
4455 * @arg @ref LL_RCC_PLLM_DIV_6
4456 * @arg @ref LL_RCC_PLLM_DIV_7
4457 * @arg @ref LL_RCC_PLLM_DIV_8
4458 * @arg @ref LL_RCC_PLLM_DIV_9
4459 * @arg @ref LL_RCC_PLLM_DIV_10
4460 * @arg @ref LL_RCC_PLLM_DIV_11
4461 * @arg @ref LL_RCC_PLLM_DIV_12
4462 * @arg @ref LL_RCC_PLLM_DIV_13
4463 * @arg @ref LL_RCC_PLLM_DIV_14
4464 * @arg @ref LL_RCC_PLLM_DIV_15
4465 * @arg @ref LL_RCC_PLLM_DIV_16
4466 * @arg @ref LL_RCC_PLLM_DIV_17
4467 * @arg @ref LL_RCC_PLLM_DIV_18
4468 * @arg @ref LL_RCC_PLLM_DIV_19
4469 * @arg @ref LL_RCC_PLLM_DIV_20
4470 * @arg @ref LL_RCC_PLLM_DIV_21
4471 * @arg @ref LL_RCC_PLLM_DIV_22
4472 * @arg @ref LL_RCC_PLLM_DIV_23
4473 * @arg @ref LL_RCC_PLLM_DIV_24
4474 * @arg @ref LL_RCC_PLLM_DIV_25
4475 * @arg @ref LL_RCC_PLLM_DIV_26
4476 * @arg @ref LL_RCC_PLLM_DIV_27
4477 * @arg @ref LL_RCC_PLLM_DIV_28
4478 * @arg @ref LL_RCC_PLLM_DIV_29
4479 * @arg @ref LL_RCC_PLLM_DIV_30
4480 * @arg @ref LL_RCC_PLLM_DIV_31
4481 * @arg @ref LL_RCC_PLLM_DIV_32
4482 * @arg @ref LL_RCC_PLLM_DIV_33
4483 * @arg @ref LL_RCC_PLLM_DIV_34
4484 * @arg @ref LL_RCC_PLLM_DIV_35
4485 * @arg @ref LL_RCC_PLLM_DIV_36
4486 * @arg @ref LL_RCC_PLLM_DIV_37
4487 * @arg @ref LL_RCC_PLLM_DIV_38
4488 * @arg @ref LL_RCC_PLLM_DIV_39
4489 * @arg @ref LL_RCC_PLLM_DIV_40
4490 * @arg @ref LL_RCC_PLLM_DIV_41
4491 * @arg @ref LL_RCC_PLLM_DIV_42
4492 * @arg @ref LL_RCC_PLLM_DIV_43
4493 * @arg @ref LL_RCC_PLLM_DIV_44
4494 * @arg @ref LL_RCC_PLLM_DIV_45
4495 * @arg @ref LL_RCC_PLLM_DIV_46
4496 * @arg @ref LL_RCC_PLLM_DIV_47
4497 * @arg @ref LL_RCC_PLLM_DIV_48
4498 * @arg @ref LL_RCC_PLLM_DIV_49
4499 * @arg @ref LL_RCC_PLLM_DIV_50
4500 * @arg @ref LL_RCC_PLLM_DIV_51
4501 * @arg @ref LL_RCC_PLLM_DIV_52
4502 * @arg @ref LL_RCC_PLLM_DIV_53
4503 * @arg @ref LL_RCC_PLLM_DIV_54
4504 * @arg @ref LL_RCC_PLLM_DIV_55
4505 * @arg @ref LL_RCC_PLLM_DIV_56
4506 * @arg @ref LL_RCC_PLLM_DIV_57
4507 * @arg @ref LL_RCC_PLLM_DIV_58
4508 * @arg @ref LL_RCC_PLLM_DIV_59
4509 * @arg @ref LL_RCC_PLLM_DIV_60
4510 * @arg @ref LL_RCC_PLLM_DIV_61
4511 * @arg @ref LL_RCC_PLLM_DIV_62
4512 * @arg @ref LL_RCC_PLLM_DIV_63
4513 * @param PLLN Between 50 and 432
4514 * @param PLLR This parameter can be one of the following values:
4515 * @arg @ref LL_RCC_PLLR_DIV_2
4516 * @arg @ref LL_RCC_PLLR_DIV_3
4517 * @arg @ref LL_RCC_PLLR_DIV_4
4518 * @arg @ref LL_RCC_PLLR_DIV_5
4519 * @arg @ref LL_RCC_PLLR_DIV_6
4520 * @arg @ref LL_RCC_PLLR_DIV_7
4521 * @retval None
4522 */
4523 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4524 {
4525 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4526 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4527 }
4528 #endif /* DSI */
4529
4530 #if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
4531 /**
4532 * @brief Configure PLL used for I2S clock
4533 * @note PLL Source and PLLM Divider can be written only when PLL,
4534 * PLLI2S and PLLSAI are disabled
4535 * @note PLLN/PLLR can be written only when PLL is disabled
4536 * @note This can be selected for I2S
4537 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S\n
4538 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S\n
4539 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S\n
4540 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_I2S
4541 * @param Source This parameter can be one of the following values:
4542 * @arg @ref LL_RCC_PLLSOURCE_HSI
4543 * @arg @ref LL_RCC_PLLSOURCE_HSE
4544 * @param PLLM This parameter can be one of the following values:
4545 * @arg @ref LL_RCC_PLLM_DIV_2
4546 * @arg @ref LL_RCC_PLLM_DIV_3
4547 * @arg @ref LL_RCC_PLLM_DIV_4
4548 * @arg @ref LL_RCC_PLLM_DIV_5
4549 * @arg @ref LL_RCC_PLLM_DIV_6
4550 * @arg @ref LL_RCC_PLLM_DIV_7
4551 * @arg @ref LL_RCC_PLLM_DIV_8
4552 * @arg @ref LL_RCC_PLLM_DIV_9
4553 * @arg @ref LL_RCC_PLLM_DIV_10
4554 * @arg @ref LL_RCC_PLLM_DIV_11
4555 * @arg @ref LL_RCC_PLLM_DIV_12
4556 * @arg @ref LL_RCC_PLLM_DIV_13
4557 * @arg @ref LL_RCC_PLLM_DIV_14
4558 * @arg @ref LL_RCC_PLLM_DIV_15
4559 * @arg @ref LL_RCC_PLLM_DIV_16
4560 * @arg @ref LL_RCC_PLLM_DIV_17
4561 * @arg @ref LL_RCC_PLLM_DIV_18
4562 * @arg @ref LL_RCC_PLLM_DIV_19
4563 * @arg @ref LL_RCC_PLLM_DIV_20
4564 * @arg @ref LL_RCC_PLLM_DIV_21
4565 * @arg @ref LL_RCC_PLLM_DIV_22
4566 * @arg @ref LL_RCC_PLLM_DIV_23
4567 * @arg @ref LL_RCC_PLLM_DIV_24
4568 * @arg @ref LL_RCC_PLLM_DIV_25
4569 * @arg @ref LL_RCC_PLLM_DIV_26
4570 * @arg @ref LL_RCC_PLLM_DIV_27
4571 * @arg @ref LL_RCC_PLLM_DIV_28
4572 * @arg @ref LL_RCC_PLLM_DIV_29
4573 * @arg @ref LL_RCC_PLLM_DIV_30
4574 * @arg @ref LL_RCC_PLLM_DIV_31
4575 * @arg @ref LL_RCC_PLLM_DIV_32
4576 * @arg @ref LL_RCC_PLLM_DIV_33
4577 * @arg @ref LL_RCC_PLLM_DIV_34
4578 * @arg @ref LL_RCC_PLLM_DIV_35
4579 * @arg @ref LL_RCC_PLLM_DIV_36
4580 * @arg @ref LL_RCC_PLLM_DIV_37
4581 * @arg @ref LL_RCC_PLLM_DIV_38
4582 * @arg @ref LL_RCC_PLLM_DIV_39
4583 * @arg @ref LL_RCC_PLLM_DIV_40
4584 * @arg @ref LL_RCC_PLLM_DIV_41
4585 * @arg @ref LL_RCC_PLLM_DIV_42
4586 * @arg @ref LL_RCC_PLLM_DIV_43
4587 * @arg @ref LL_RCC_PLLM_DIV_44
4588 * @arg @ref LL_RCC_PLLM_DIV_45
4589 * @arg @ref LL_RCC_PLLM_DIV_46
4590 * @arg @ref LL_RCC_PLLM_DIV_47
4591 * @arg @ref LL_RCC_PLLM_DIV_48
4592 * @arg @ref LL_RCC_PLLM_DIV_49
4593 * @arg @ref LL_RCC_PLLM_DIV_50
4594 * @arg @ref LL_RCC_PLLM_DIV_51
4595 * @arg @ref LL_RCC_PLLM_DIV_52
4596 * @arg @ref LL_RCC_PLLM_DIV_53
4597 * @arg @ref LL_RCC_PLLM_DIV_54
4598 * @arg @ref LL_RCC_PLLM_DIV_55
4599 * @arg @ref LL_RCC_PLLM_DIV_56
4600 * @arg @ref LL_RCC_PLLM_DIV_57
4601 * @arg @ref LL_RCC_PLLM_DIV_58
4602 * @arg @ref LL_RCC_PLLM_DIV_59
4603 * @arg @ref LL_RCC_PLLM_DIV_60
4604 * @arg @ref LL_RCC_PLLM_DIV_61
4605 * @arg @ref LL_RCC_PLLM_DIV_62
4606 * @arg @ref LL_RCC_PLLM_DIV_63
4607 * @param PLLN Between 50 and 432
4608 * @param PLLR This parameter can be one of the following values:
4609 * @arg @ref LL_RCC_PLLR_DIV_2
4610 * @arg @ref LL_RCC_PLLR_DIV_3
4611 * @arg @ref LL_RCC_PLLR_DIV_4
4612 * @arg @ref LL_RCC_PLLR_DIV_5
4613 * @arg @ref LL_RCC_PLLR_DIV_6
4614 * @arg @ref LL_RCC_PLLR_DIV_7
4615 * @retval None
4616 */
4617 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4618 {
4619 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4620 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4621 }
4622 #endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
4623
4624 #if defined(SPDIFRX)
4625 /**
4626 * @brief Configure PLL used for SPDIFRX clock
4627 * @note PLL Source and PLLM Divider can be written only when PLL,
4628 * PLLI2S and PLLSAI are disabled
4629 * @note PLLN/PLLR can be written only when PLL is disabled
4630 * @note This can be selected for SPDIFRX
4631 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SPDIFRX\n
4632 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SPDIFRX\n
4633 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SPDIFRX\n
4634 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SPDIFRX
4635 * @param Source This parameter can be one of the following values:
4636 * @arg @ref LL_RCC_PLLSOURCE_HSI
4637 * @arg @ref LL_RCC_PLLSOURCE_HSE
4638 * @param PLLM This parameter can be one of the following values:
4639 * @arg @ref LL_RCC_PLLM_DIV_2
4640 * @arg @ref LL_RCC_PLLM_DIV_3
4641 * @arg @ref LL_RCC_PLLM_DIV_4
4642 * @arg @ref LL_RCC_PLLM_DIV_5
4643 * @arg @ref LL_RCC_PLLM_DIV_6
4644 * @arg @ref LL_RCC_PLLM_DIV_7
4645 * @arg @ref LL_RCC_PLLM_DIV_8
4646 * @arg @ref LL_RCC_PLLM_DIV_9
4647 * @arg @ref LL_RCC_PLLM_DIV_10
4648 * @arg @ref LL_RCC_PLLM_DIV_11
4649 * @arg @ref LL_RCC_PLLM_DIV_12
4650 * @arg @ref LL_RCC_PLLM_DIV_13
4651 * @arg @ref LL_RCC_PLLM_DIV_14
4652 * @arg @ref LL_RCC_PLLM_DIV_15
4653 * @arg @ref LL_RCC_PLLM_DIV_16
4654 * @arg @ref LL_RCC_PLLM_DIV_17
4655 * @arg @ref LL_RCC_PLLM_DIV_18
4656 * @arg @ref LL_RCC_PLLM_DIV_19
4657 * @arg @ref LL_RCC_PLLM_DIV_20
4658 * @arg @ref LL_RCC_PLLM_DIV_21
4659 * @arg @ref LL_RCC_PLLM_DIV_22
4660 * @arg @ref LL_RCC_PLLM_DIV_23
4661 * @arg @ref LL_RCC_PLLM_DIV_24
4662 * @arg @ref LL_RCC_PLLM_DIV_25
4663 * @arg @ref LL_RCC_PLLM_DIV_26
4664 * @arg @ref LL_RCC_PLLM_DIV_27
4665 * @arg @ref LL_RCC_PLLM_DIV_28
4666 * @arg @ref LL_RCC_PLLM_DIV_29
4667 * @arg @ref LL_RCC_PLLM_DIV_30
4668 * @arg @ref LL_RCC_PLLM_DIV_31
4669 * @arg @ref LL_RCC_PLLM_DIV_32
4670 * @arg @ref LL_RCC_PLLM_DIV_33
4671 * @arg @ref LL_RCC_PLLM_DIV_34
4672 * @arg @ref LL_RCC_PLLM_DIV_35
4673 * @arg @ref LL_RCC_PLLM_DIV_36
4674 * @arg @ref LL_RCC_PLLM_DIV_37
4675 * @arg @ref LL_RCC_PLLM_DIV_38
4676 * @arg @ref LL_RCC_PLLM_DIV_39
4677 * @arg @ref LL_RCC_PLLM_DIV_40
4678 * @arg @ref LL_RCC_PLLM_DIV_41
4679 * @arg @ref LL_RCC_PLLM_DIV_42
4680 * @arg @ref LL_RCC_PLLM_DIV_43
4681 * @arg @ref LL_RCC_PLLM_DIV_44
4682 * @arg @ref LL_RCC_PLLM_DIV_45
4683 * @arg @ref LL_RCC_PLLM_DIV_46
4684 * @arg @ref LL_RCC_PLLM_DIV_47
4685 * @arg @ref LL_RCC_PLLM_DIV_48
4686 * @arg @ref LL_RCC_PLLM_DIV_49
4687 * @arg @ref LL_RCC_PLLM_DIV_50
4688 * @arg @ref LL_RCC_PLLM_DIV_51
4689 * @arg @ref LL_RCC_PLLM_DIV_52
4690 * @arg @ref LL_RCC_PLLM_DIV_53
4691 * @arg @ref LL_RCC_PLLM_DIV_54
4692 * @arg @ref LL_RCC_PLLM_DIV_55
4693 * @arg @ref LL_RCC_PLLM_DIV_56
4694 * @arg @ref LL_RCC_PLLM_DIV_57
4695 * @arg @ref LL_RCC_PLLM_DIV_58
4696 * @arg @ref LL_RCC_PLLM_DIV_59
4697 * @arg @ref LL_RCC_PLLM_DIV_60
4698 * @arg @ref LL_RCC_PLLM_DIV_61
4699 * @arg @ref LL_RCC_PLLM_DIV_62
4700 * @arg @ref LL_RCC_PLLM_DIV_63
4701 * @param PLLN Between 50 and 432
4702 * @param PLLR This parameter can be one of the following values:
4703 * @arg @ref LL_RCC_PLLR_DIV_2
4704 * @arg @ref LL_RCC_PLLR_DIV_3
4705 * @arg @ref LL_RCC_PLLR_DIV_4
4706 * @arg @ref LL_RCC_PLLR_DIV_5
4707 * @arg @ref LL_RCC_PLLR_DIV_6
4708 * @arg @ref LL_RCC_PLLR_DIV_7
4709 * @retval None
4710 */
4711 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4712 {
4713 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4714 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4715 }
4716 #endif /* SPDIFRX */
4717
4718 #if defined(RCC_PLLCFGR_PLLR)
4719 #if defined(SAI1)
4720 /**
4721 * @brief Configure PLL used for SAI clock
4722 * @note PLL Source and PLLM Divider can be written only when PLL,
4723 * PLLI2S and PLLSAI are disabled
4724 * @note PLLN/PLLR can be written only when PLL is disabled
4725 * @note This can be selected for SAI
4726 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
4727 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
4728 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
4729 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SAI\n
4730 * DCKCFGR PLLDIVR LL_RCC_PLL_ConfigDomain_SAI
4731 * @param Source This parameter can be one of the following values:
4732 * @arg @ref LL_RCC_PLLSOURCE_HSI
4733 * @arg @ref LL_RCC_PLLSOURCE_HSE
4734 * @param PLLM This parameter can be one of the following values:
4735 * @arg @ref LL_RCC_PLLM_DIV_2
4736 * @arg @ref LL_RCC_PLLM_DIV_3
4737 * @arg @ref LL_RCC_PLLM_DIV_4
4738 * @arg @ref LL_RCC_PLLM_DIV_5
4739 * @arg @ref LL_RCC_PLLM_DIV_6
4740 * @arg @ref LL_RCC_PLLM_DIV_7
4741 * @arg @ref LL_RCC_PLLM_DIV_8
4742 * @arg @ref LL_RCC_PLLM_DIV_9
4743 * @arg @ref LL_RCC_PLLM_DIV_10
4744 * @arg @ref LL_RCC_PLLM_DIV_11
4745 * @arg @ref LL_RCC_PLLM_DIV_12
4746 * @arg @ref LL_RCC_PLLM_DIV_13
4747 * @arg @ref LL_RCC_PLLM_DIV_14
4748 * @arg @ref LL_RCC_PLLM_DIV_15
4749 * @arg @ref LL_RCC_PLLM_DIV_16
4750 * @arg @ref LL_RCC_PLLM_DIV_17
4751 * @arg @ref LL_RCC_PLLM_DIV_18
4752 * @arg @ref LL_RCC_PLLM_DIV_19
4753 * @arg @ref LL_RCC_PLLM_DIV_20
4754 * @arg @ref LL_RCC_PLLM_DIV_21
4755 * @arg @ref LL_RCC_PLLM_DIV_22
4756 * @arg @ref LL_RCC_PLLM_DIV_23
4757 * @arg @ref LL_RCC_PLLM_DIV_24
4758 * @arg @ref LL_RCC_PLLM_DIV_25
4759 * @arg @ref LL_RCC_PLLM_DIV_26
4760 * @arg @ref LL_RCC_PLLM_DIV_27
4761 * @arg @ref LL_RCC_PLLM_DIV_28
4762 * @arg @ref LL_RCC_PLLM_DIV_29
4763 * @arg @ref LL_RCC_PLLM_DIV_30
4764 * @arg @ref LL_RCC_PLLM_DIV_31
4765 * @arg @ref LL_RCC_PLLM_DIV_32
4766 * @arg @ref LL_RCC_PLLM_DIV_33
4767 * @arg @ref LL_RCC_PLLM_DIV_34
4768 * @arg @ref LL_RCC_PLLM_DIV_35
4769 * @arg @ref LL_RCC_PLLM_DIV_36
4770 * @arg @ref LL_RCC_PLLM_DIV_37
4771 * @arg @ref LL_RCC_PLLM_DIV_38
4772 * @arg @ref LL_RCC_PLLM_DIV_39
4773 * @arg @ref LL_RCC_PLLM_DIV_40
4774 * @arg @ref LL_RCC_PLLM_DIV_41
4775 * @arg @ref LL_RCC_PLLM_DIV_42
4776 * @arg @ref LL_RCC_PLLM_DIV_43
4777 * @arg @ref LL_RCC_PLLM_DIV_44
4778 * @arg @ref LL_RCC_PLLM_DIV_45
4779 * @arg @ref LL_RCC_PLLM_DIV_46
4780 * @arg @ref LL_RCC_PLLM_DIV_47
4781 * @arg @ref LL_RCC_PLLM_DIV_48
4782 * @arg @ref LL_RCC_PLLM_DIV_49
4783 * @arg @ref LL_RCC_PLLM_DIV_50
4784 * @arg @ref LL_RCC_PLLM_DIV_51
4785 * @arg @ref LL_RCC_PLLM_DIV_52
4786 * @arg @ref LL_RCC_PLLM_DIV_53
4787 * @arg @ref LL_RCC_PLLM_DIV_54
4788 * @arg @ref LL_RCC_PLLM_DIV_55
4789 * @arg @ref LL_RCC_PLLM_DIV_56
4790 * @arg @ref LL_RCC_PLLM_DIV_57
4791 * @arg @ref LL_RCC_PLLM_DIV_58
4792 * @arg @ref LL_RCC_PLLM_DIV_59
4793 * @arg @ref LL_RCC_PLLM_DIV_60
4794 * @arg @ref LL_RCC_PLLM_DIV_61
4795 * @arg @ref LL_RCC_PLLM_DIV_62
4796 * @arg @ref LL_RCC_PLLM_DIV_63
4797 * @param PLLN Between 50 and 432
4798 * @param PLLR This parameter can be one of the following values:
4799 * @arg @ref LL_RCC_PLLR_DIV_2
4800 * @arg @ref LL_RCC_PLLR_DIV_3
4801 * @arg @ref LL_RCC_PLLR_DIV_4
4802 * @arg @ref LL_RCC_PLLR_DIV_5
4803 * @arg @ref LL_RCC_PLLR_DIV_6
4804 * @arg @ref LL_RCC_PLLR_DIV_7
4805 * @param PLLDIVR This parameter can be one of the following values:
4806 * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
4807 * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
4808 * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
4809 * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
4810 * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
4811 * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
4812 * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
4813 * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
4814 * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
4815 * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
4816 * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
4817 * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
4818 * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
4819 * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
4820 * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
4821 * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
4822 * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
4823 * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
4824 * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
4825 * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
4826 * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
4827 * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
4828 * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
4829 * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
4830 * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
4831 * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
4832 * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
4833 * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
4834 * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
4835 * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
4836 * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
4837 *
4838 * (*) value not defined in all devices.
4839 * @retval None
4840 */
4841 #if defined(RCC_DCKCFGR_PLLDIVR)
4842 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
4843 #else
4844 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4845 #endif /* RCC_DCKCFGR_PLLDIVR */
4846 {
4847 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4848 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4849 #if defined(RCC_DCKCFGR_PLLDIVR)
4850 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR);
4851 #endif /* RCC_DCKCFGR_PLLDIVR */
4852 }
4853 #endif /* SAI1 */
4854 #endif /* RCC_PLLCFGR_PLLR */
4855
4856 /**
4857 * @brief Get Main PLL multiplication factor for VCO
4858 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
4859 * @retval Between 50/192(*) and 432
4860 *
4861 * (*) value not defined in all devices.
4862 */
4863 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
4864 {
4865 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
4866 }
4867
4868 /**
4869 * @brief Get Main PLL division factor for PLLP
4870 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
4871 * @retval Returned value can be one of the following values:
4872 * @arg @ref LL_RCC_PLLP_DIV_2
4873 * @arg @ref LL_RCC_PLLP_DIV_4
4874 * @arg @ref LL_RCC_PLLP_DIV_6
4875 * @arg @ref LL_RCC_PLLP_DIV_8
4876 */
4877 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
4878 {
4879 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
4880 }
4881
4882 /**
4883 * @brief Get Main PLL division factor for PLLQ
4884 * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)
4885 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
4886 * @retval Returned value can be one of the following values:
4887 * @arg @ref LL_RCC_PLLQ_DIV_2
4888 * @arg @ref LL_RCC_PLLQ_DIV_3
4889 * @arg @ref LL_RCC_PLLQ_DIV_4
4890 * @arg @ref LL_RCC_PLLQ_DIV_5
4891 * @arg @ref LL_RCC_PLLQ_DIV_6
4892 * @arg @ref LL_RCC_PLLQ_DIV_7
4893 * @arg @ref LL_RCC_PLLQ_DIV_8
4894 * @arg @ref LL_RCC_PLLQ_DIV_9
4895 * @arg @ref LL_RCC_PLLQ_DIV_10
4896 * @arg @ref LL_RCC_PLLQ_DIV_11
4897 * @arg @ref LL_RCC_PLLQ_DIV_12
4898 * @arg @ref LL_RCC_PLLQ_DIV_13
4899 * @arg @ref LL_RCC_PLLQ_DIV_14
4900 * @arg @ref LL_RCC_PLLQ_DIV_15
4901 */
4902 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
4903 {
4904 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
4905 }
4906
4907 #if defined(RCC_PLLCFGR_PLLR)
4908 /**
4909 * @brief Get Main PLL division factor for PLLR
4910 * @note used for PLLCLK (system clock)
4911 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
4912 * @retval Returned value can be one of the following values:
4913 * @arg @ref LL_RCC_PLLR_DIV_2
4914 * @arg @ref LL_RCC_PLLR_DIV_3
4915 * @arg @ref LL_RCC_PLLR_DIV_4
4916 * @arg @ref LL_RCC_PLLR_DIV_5
4917 * @arg @ref LL_RCC_PLLR_DIV_6
4918 * @arg @ref LL_RCC_PLLR_DIV_7
4919 */
4920 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
4921 {
4922 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
4923 }
4924 #endif /* RCC_PLLCFGR_PLLR */
4925
4926 #if defined(RCC_DCKCFGR_PLLDIVR)
4927 /**
4928 * @brief Get Main PLL division factor for PLLDIVR
4929 * @note used for PLLSAICLK (SAI1 and SAI2 clock)
4930 * @rmtoll DCKCFGR PLLDIVR LL_RCC_PLL_GetDIVR
4931 * @retval Returned value can be one of the following values:
4932 * @arg @ref LL_RCC_PLLDIVR_DIV_1
4933 * @arg @ref LL_RCC_PLLDIVR_DIV_2
4934 * @arg @ref LL_RCC_PLLDIVR_DIV_3
4935 * @arg @ref LL_RCC_PLLDIVR_DIV_4
4936 * @arg @ref LL_RCC_PLLDIVR_DIV_5
4937 * @arg @ref LL_RCC_PLLDIVR_DIV_6
4938 * @arg @ref LL_RCC_PLLDIVR_DIV_7
4939 * @arg @ref LL_RCC_PLLDIVR_DIV_8
4940 * @arg @ref LL_RCC_PLLDIVR_DIV_9
4941 * @arg @ref LL_RCC_PLLDIVR_DIV_10
4942 * @arg @ref LL_RCC_PLLDIVR_DIV_11
4943 * @arg @ref LL_RCC_PLLDIVR_DIV_12
4944 * @arg @ref LL_RCC_PLLDIVR_DIV_13
4945 * @arg @ref LL_RCC_PLLDIVR_DIV_14
4946 * @arg @ref LL_RCC_PLLDIVR_DIV_15
4947 * @arg @ref LL_RCC_PLLDIVR_DIV_16
4948 * @arg @ref LL_RCC_PLLDIVR_DIV_17
4949 * @arg @ref LL_RCC_PLLDIVR_DIV_18
4950 * @arg @ref LL_RCC_PLLDIVR_DIV_19
4951 * @arg @ref LL_RCC_PLLDIVR_DIV_20
4952 * @arg @ref LL_RCC_PLLDIVR_DIV_21
4953 * @arg @ref LL_RCC_PLLDIVR_DIV_22
4954 * @arg @ref LL_RCC_PLLDIVR_DIV_23
4955 * @arg @ref LL_RCC_PLLDIVR_DIV_24
4956 * @arg @ref LL_RCC_PLLDIVR_DIV_25
4957 * @arg @ref LL_RCC_PLLDIVR_DIV_26
4958 * @arg @ref LL_RCC_PLLDIVR_DIV_27
4959 * @arg @ref LL_RCC_PLLDIVR_DIV_28
4960 * @arg @ref LL_RCC_PLLDIVR_DIV_29
4961 * @arg @ref LL_RCC_PLLDIVR_DIV_30
4962 * @arg @ref LL_RCC_PLLDIVR_DIV_31
4963 */
4964 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void)
4965 {
4966 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR));
4967 }
4968 #endif /* RCC_DCKCFGR_PLLDIVR */
4969
4970 /**
4971 * @brief Get the oscillator used as PLL clock source.
4972 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
4973 * @retval Returned value can be one of the following values:
4974 * @arg @ref LL_RCC_PLLSOURCE_HSI
4975 * @arg @ref LL_RCC_PLLSOURCE_HSE
4976 */
4977 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
4978 {
4979 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
4980 }
4981
4982 /**
4983 * @brief Get Division factor for the main PLL and other PLL
4984 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
4985 * @retval Returned value can be one of the following values:
4986 * @arg @ref LL_RCC_PLLM_DIV_2
4987 * @arg @ref LL_RCC_PLLM_DIV_3
4988 * @arg @ref LL_RCC_PLLM_DIV_4
4989 * @arg @ref LL_RCC_PLLM_DIV_5
4990 * @arg @ref LL_RCC_PLLM_DIV_6
4991 * @arg @ref LL_RCC_PLLM_DIV_7
4992 * @arg @ref LL_RCC_PLLM_DIV_8
4993 * @arg @ref LL_RCC_PLLM_DIV_9
4994 * @arg @ref LL_RCC_PLLM_DIV_10
4995 * @arg @ref LL_RCC_PLLM_DIV_11
4996 * @arg @ref LL_RCC_PLLM_DIV_12
4997 * @arg @ref LL_RCC_PLLM_DIV_13
4998 * @arg @ref LL_RCC_PLLM_DIV_14
4999 * @arg @ref LL_RCC_PLLM_DIV_15
5000 * @arg @ref LL_RCC_PLLM_DIV_16
5001 * @arg @ref LL_RCC_PLLM_DIV_17
5002 * @arg @ref LL_RCC_PLLM_DIV_18
5003 * @arg @ref LL_RCC_PLLM_DIV_19
5004 * @arg @ref LL_RCC_PLLM_DIV_20
5005 * @arg @ref LL_RCC_PLLM_DIV_21
5006 * @arg @ref LL_RCC_PLLM_DIV_22
5007 * @arg @ref LL_RCC_PLLM_DIV_23
5008 * @arg @ref LL_RCC_PLLM_DIV_24
5009 * @arg @ref LL_RCC_PLLM_DIV_25
5010 * @arg @ref LL_RCC_PLLM_DIV_26
5011 * @arg @ref LL_RCC_PLLM_DIV_27
5012 * @arg @ref LL_RCC_PLLM_DIV_28
5013 * @arg @ref LL_RCC_PLLM_DIV_29
5014 * @arg @ref LL_RCC_PLLM_DIV_30
5015 * @arg @ref LL_RCC_PLLM_DIV_31
5016 * @arg @ref LL_RCC_PLLM_DIV_32
5017 * @arg @ref LL_RCC_PLLM_DIV_33
5018 * @arg @ref LL_RCC_PLLM_DIV_34
5019 * @arg @ref LL_RCC_PLLM_DIV_35
5020 * @arg @ref LL_RCC_PLLM_DIV_36
5021 * @arg @ref LL_RCC_PLLM_DIV_37
5022 * @arg @ref LL_RCC_PLLM_DIV_38
5023 * @arg @ref LL_RCC_PLLM_DIV_39
5024 * @arg @ref LL_RCC_PLLM_DIV_40
5025 * @arg @ref LL_RCC_PLLM_DIV_41
5026 * @arg @ref LL_RCC_PLLM_DIV_42
5027 * @arg @ref LL_RCC_PLLM_DIV_43
5028 * @arg @ref LL_RCC_PLLM_DIV_44
5029 * @arg @ref LL_RCC_PLLM_DIV_45
5030 * @arg @ref LL_RCC_PLLM_DIV_46
5031 * @arg @ref LL_RCC_PLLM_DIV_47
5032 * @arg @ref LL_RCC_PLLM_DIV_48
5033 * @arg @ref LL_RCC_PLLM_DIV_49
5034 * @arg @ref LL_RCC_PLLM_DIV_50
5035 * @arg @ref LL_RCC_PLLM_DIV_51
5036 * @arg @ref LL_RCC_PLLM_DIV_52
5037 * @arg @ref LL_RCC_PLLM_DIV_53
5038 * @arg @ref LL_RCC_PLLM_DIV_54
5039 * @arg @ref LL_RCC_PLLM_DIV_55
5040 * @arg @ref LL_RCC_PLLM_DIV_56
5041 * @arg @ref LL_RCC_PLLM_DIV_57
5042 * @arg @ref LL_RCC_PLLM_DIV_58
5043 * @arg @ref LL_RCC_PLLM_DIV_59
5044 * @arg @ref LL_RCC_PLLM_DIV_60
5045 * @arg @ref LL_RCC_PLLM_DIV_61
5046 * @arg @ref LL_RCC_PLLM_DIV_62
5047 * @arg @ref LL_RCC_PLLM_DIV_63
5048 */
5049 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
5050 {
5051 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
5052 }
5053
5054 /**
5055 * @brief Configure Spread Spectrum used for PLL
5056 * @note These bits must be written before enabling PLL
5057 * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
5058 * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
5059 * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
5060 * @param Mod Between Min_Data=0 and Max_Data=8191
5061 * @param Inc Between Min_Data=0 and Max_Data=32767
5062 * @param Sel This parameter can be one of the following values:
5063 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
5064 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
5065 * @retval None
5066 */
5067 __STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
5068 {
5069 MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);
5070 }
5071
5072 /**
5073 * @brief Get Spread Spectrum Modulation Period for PLL
5074 * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
5075 * @retval Between Min_Data=0 and Max_Data=8191
5076 */
5077 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
5078 {
5079 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
5080 }
5081
5082 /**
5083 * @brief Get Spread Spectrum Incrementation Step for PLL
5084 * @note Must be written before enabling PLL
5085 * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
5086 * @retval Between Min_Data=0 and Max_Data=32767
5087 */
5088 __STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
5089 {
5090 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
5091 }
5092
5093 /**
5094 * @brief Get Spread Spectrum Selection for PLL
5095 * @note Must be written before enabling PLL
5096 * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
5097 * @retval Returned value can be one of the following values:
5098 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
5099 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
5100 */
5101 __STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
5102 {
5103 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
5104 }
5105
5106 /**
5107 * @brief Enable Spread Spectrum for PLL.
5108 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
5109 * @retval None
5110 */
5111 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
5112 {
5113 SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
5114 }
5115
5116 /**
5117 * @brief Disable Spread Spectrum for PLL.
5118 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
5119 * @retval None
5120 */
5121 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
5122 {
5123 CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
5124 }
5125
5126 /**
5127 * @}
5128 */
5129
5130 #if defined(RCC_PLLI2S_SUPPORT)
5131 /** @defgroup RCC_LL_EF_PLLI2S PLLI2S
5132 * @{
5133 */
5134
5135 /**
5136 * @brief Enable PLLI2S
5137 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
5138 * @retval None
5139 */
5140 __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
5141 {
5142 SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
5143 }
5144
5145 /**
5146 * @brief Disable PLLI2S
5147 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
5148 * @retval None
5149 */
5150 __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
5151 {
5152 CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
5153 }
5154
5155 /**
5156 * @brief Check if PLLI2S Ready
5157 * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
5158 * @retval State of bit (1 or 0).
5159 */
5160 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
5161 {
5162 return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
5163 }
5164
5165 #if (defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR))
5166 /**
5167 * @brief Configure PLLI2S used for SAI domain clock
5168 * @note PLL Source and PLLM Divider can be written only when PLL,
5169 * PLLI2S and PLLSAI(*) are disabled
5170 * @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled
5171 * @note This can be selected for SAI
5172 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
5173 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
5174 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n
5175 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SAI\n
5176 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n
5177 * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
5178 * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_SAI\n
5179 * DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
5180 * DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_ConfigDomain_SAI
5181 * @param Source This parameter can be one of the following values:
5182 * @arg @ref LL_RCC_PLLSOURCE_HSI
5183 * @arg @ref LL_RCC_PLLSOURCE_HSE
5184 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5185 *
5186 * (*) value not defined in all devices.
5187 * @param PLLM This parameter can be one of the following values:
5188 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5189 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5190 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5191 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5192 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5193 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5194 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5195 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5196 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5197 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5198 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5199 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5200 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5201 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5202 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5203 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5204 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5205 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5206 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5207 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5208 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5209 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5210 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5211 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5212 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5213 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5214 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5215 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5216 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5217 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5218 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5219 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5220 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5221 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5222 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5223 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5224 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5225 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5226 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5227 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5228 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5229 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5230 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5231 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5232 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5233 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5234 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5235 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5236 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5237 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5238 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5239 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5240 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5241 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5242 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5243 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5244 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5245 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5246 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5247 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5248 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5249 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5250 * @param PLLN Between 50/192(*) and 432
5251 *
5252 * (*) value not defined in all devices.
5253 * @param PLLQ_R This parameter can be one of the following values:
5254 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
5255 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
5256 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
5257 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
5258 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
5259 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
5260 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
5261 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
5262 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
5263 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
5264 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
5265 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
5266 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
5267 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
5268 * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
5269 * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
5270 * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
5271 * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
5272 * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
5273 * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
5274 *
5275 * (*) value not defined in all devices.
5276 * @param PLLDIVQ_R This parameter can be one of the following values:
5277 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
5278 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
5279 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
5280 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
5281 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
5282 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
5283 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
5284 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
5285 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
5286 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
5287 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
5288 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
5289 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
5290 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
5291 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
5292 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
5293 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
5294 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
5295 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
5296 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
5297 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
5298 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
5299 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
5300 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
5301 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
5302 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
5303 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
5304 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
5305 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
5306 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
5307 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
5308 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
5309 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
5310 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
5311 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
5312 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
5313 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
5314 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
5315 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
5316 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
5317 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
5318 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
5319 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
5320 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
5321 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
5322 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
5323 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
5324 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
5325 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
5326 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
5327 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
5328 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
5329 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
5330 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
5331 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
5332 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
5333 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
5334 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
5335 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
5336 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
5337 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
5338 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
5339 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
5340 *
5341 * (*) value not defined in all devices.
5342 * @retval None
5343 */
5344 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)
5345 {
5346 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
5347 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
5348 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5349 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5350 #else
5351 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5352 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5353 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos);
5354 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
5355 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R);
5356 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R);
5357 #else
5358 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R);
5359 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R);
5360 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
5361 }
5362 #endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */
5363
5364 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
5365 /**
5366 * @brief Configure PLLI2S used for 48Mhz domain clock
5367 * @note PLL Source and PLLM Divider can be written only when PLL,
5368 * PLLI2S and PLLSAI(*) are disabled
5369 * @note PLLN/PLLQ can be written only when PLLI2S is disabled
5370 * @note This can be selected for RNG, USB, SDIO
5371 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
5372 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
5373 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_48M\n
5374 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_48M\n
5375 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_48M\n
5376 * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_48M
5377 * @param Source This parameter can be one of the following values:
5378 * @arg @ref LL_RCC_PLLSOURCE_HSI
5379 * @arg @ref LL_RCC_PLLSOURCE_HSE
5380 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5381 *
5382 * (*) value not defined in all devices.
5383 * @param PLLM This parameter can be one of the following values:
5384 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5385 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5386 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5387 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5388 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5389 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5390 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5391 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5392 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5393 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5394 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5395 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5396 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5397 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5398 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5399 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5400 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5401 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5402 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5403 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5404 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5405 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5406 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5407 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5408 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5409 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5410 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5411 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5412 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5413 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5414 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5415 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5416 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5417 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5418 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5419 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5420 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5421 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5422 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5423 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5424 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5425 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5426 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5427 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5428 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5429 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5430 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5431 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5432 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5433 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5434 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5435 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5436 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5437 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5438 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5439 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5440 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5441 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5442 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5443 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5444 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5445 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5446 * @param PLLN Between 50 and 432
5447 * @param PLLQ This parameter can be one of the following values:
5448 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
5449 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
5450 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
5451 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
5452 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
5453 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
5454 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
5455 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
5456 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
5457 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
5458 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
5459 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
5460 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
5461 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
5462 * @retval None
5463 */
5464 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
5465 {
5466 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
5467 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
5468 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5469 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5470 #else
5471 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5472 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5473 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ);
5474 }
5475 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
5476
5477 #if defined(SPDIFRX)
5478 /**
5479 * @brief Configure PLLI2S used for SPDIFRX domain clock
5480 * @note PLL Source and PLLM Divider can be written only when PLL,
5481 * PLLI2S and PLLSAI(*) are disabled
5482 * @note PLLN/PLLP can be written only when PLLI2S is disabled
5483 * @note This can be selected for SPDIFRX
5484 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5485 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5486 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5487 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5488 * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
5489 * @param Source This parameter can be one of the following values:
5490 * @arg @ref LL_RCC_PLLSOURCE_HSI
5491 * @arg @ref LL_RCC_PLLSOURCE_HSE
5492 * @param PLLM This parameter can be one of the following values:
5493 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5494 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5495 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5496 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5497 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5498 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5499 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5500 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5501 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5502 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5503 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5504 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5505 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5506 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5507 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5508 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5509 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5510 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5511 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5512 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5513 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5514 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5515 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5516 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5517 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5518 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5519 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5520 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5521 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5522 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5523 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5524 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5525 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5526 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5527 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5528 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5529 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5530 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5531 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5532 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5533 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5534 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5535 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5536 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5537 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5538 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5539 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5540 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5541 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5542 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5543 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5544 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5545 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5546 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5547 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5548 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5549 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5550 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5551 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5552 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5553 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5554 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5555 * @param PLLN Between 50 and 432
5556 * @param PLLP This parameter can be one of the following values:
5557 * @arg @ref LL_RCC_PLLI2SP_DIV_2
5558 * @arg @ref LL_RCC_PLLI2SP_DIV_4
5559 * @arg @ref LL_RCC_PLLI2SP_DIV_6
5560 * @arg @ref LL_RCC_PLLI2SP_DIV_8
5561 * @retval None
5562 */
5563 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
5564 {
5565 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
5566 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5567 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5568 #else
5569 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5570 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5571 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP);
5572 }
5573 #endif /* SPDIFRX */
5574
5575 /**
5576 * @brief Configure PLLI2S used for I2S1 domain clock
5577 * @note PLL Source and PLLM Divider can be written only when PLL,
5578 * PLLI2S and PLLSAI(*) are disabled
5579 * @note PLLN/PLLR can be written only when PLLI2S is disabled
5580 * @note This can be selected for I2S
5581 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
5582 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
5583 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
5584 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_I2S\n
5585 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
5586 * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
5587 * @param Source This parameter can be one of the following values:
5588 * @arg @ref LL_RCC_PLLSOURCE_HSI
5589 * @arg @ref LL_RCC_PLLSOURCE_HSE
5590 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5591 *
5592 * (*) value not defined in all devices.
5593 * @param PLLM This parameter can be one of the following values:
5594 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5595 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5596 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5597 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5598 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5599 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5600 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5601 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5602 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5603 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5604 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5605 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5606 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5607 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5608 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5609 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5610 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5611 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5612 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5613 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5614 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5615 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5616 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5617 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5618 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5619 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5620 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5621 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5622 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5623 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5624 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5625 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5626 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5627 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5628 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5629 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5630 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5631 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5632 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5633 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5634 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5635 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5636 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5637 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5638 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5639 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5640 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5641 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5642 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5643 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5644 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5645 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5646 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5647 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5648 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5649 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5650 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5651 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5652 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5653 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5654 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5655 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5656 * @param PLLN Between 50/192(*) and 432
5657 *
5658 * (*) value not defined in all devices.
5659 * @param PLLR This parameter can be one of the following values:
5660 * @arg @ref LL_RCC_PLLI2SR_DIV_2
5661 * @arg @ref LL_RCC_PLLI2SR_DIV_3
5662 * @arg @ref LL_RCC_PLLI2SR_DIV_4
5663 * @arg @ref LL_RCC_PLLI2SR_DIV_5
5664 * @arg @ref LL_RCC_PLLI2SR_DIV_6
5665 * @arg @ref LL_RCC_PLLI2SR_DIV_7
5666 * @retval None
5667 */
5668 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
5669 {
5670 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
5671 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
5672 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5673 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5674 #else
5675 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5676 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5677 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);
5678 }
5679
5680 /**
5681 * @brief Get I2SPLL multiplication factor for VCO
5682 * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
5683 * @retval Between 50/192(*) and 432
5684 *
5685 * (*) value not defined in all devices.
5686 */
5687 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
5688 {
5689 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
5690 }
5691
5692 #if defined(RCC_PLLI2SCFGR_PLLI2SQ)
5693 /**
5694 * @brief Get I2SPLL division factor for PLLI2SQ
5695 * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ
5696 * @retval Returned value can be one of the following values:
5697 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
5698 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
5699 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
5700 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
5701 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
5702 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
5703 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
5704 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
5705 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
5706 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
5707 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
5708 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
5709 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
5710 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
5711 */
5712 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
5713 {
5714 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
5715 }
5716 #endif /* RCC_PLLI2SCFGR_PLLI2SQ */
5717
5718 /**
5719 * @brief Get I2SPLL division factor for PLLI2SR
5720 * @note used for PLLI2SCLK (I2S clock)
5721 * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
5722 * @retval Returned value can be one of the following values:
5723 * @arg @ref LL_RCC_PLLI2SR_DIV_2
5724 * @arg @ref LL_RCC_PLLI2SR_DIV_3
5725 * @arg @ref LL_RCC_PLLI2SR_DIV_4
5726 * @arg @ref LL_RCC_PLLI2SR_DIV_5
5727 * @arg @ref LL_RCC_PLLI2SR_DIV_6
5728 * @arg @ref LL_RCC_PLLI2SR_DIV_7
5729 */
5730 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
5731 {
5732 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
5733 }
5734
5735 #if defined(RCC_PLLI2SCFGR_PLLI2SP)
5736 /**
5737 * @brief Get I2SPLL division factor for PLLI2SP
5738 * @note used for PLLSPDIFRXCLK (SPDIFRX clock)
5739 * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP
5740 * @retval Returned value can be one of the following values:
5741 * @arg @ref LL_RCC_PLLI2SP_DIV_2
5742 * @arg @ref LL_RCC_PLLI2SP_DIV_4
5743 * @arg @ref LL_RCC_PLLI2SP_DIV_6
5744 * @arg @ref LL_RCC_PLLI2SP_DIV_8
5745 */
5746 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
5747 {
5748 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
5749 }
5750 #endif /* RCC_PLLI2SCFGR_PLLI2SP */
5751
5752 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
5753 /**
5754 * @brief Get I2SPLL division factor for PLLI2SDIVQ
5755 * @note used PLLSAICLK selected (SAI clock)
5756 * @rmtoll DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ
5757 * @retval Returned value can be one of the following values:
5758 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
5759 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
5760 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
5761 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
5762 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
5763 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
5764 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
5765 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
5766 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
5767 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
5768 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
5769 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
5770 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
5771 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
5772 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
5773 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
5774 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
5775 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
5776 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
5777 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
5778 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
5779 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
5780 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
5781 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
5782 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
5783 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
5784 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
5785 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
5786 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
5787 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
5788 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
5789 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
5790 */
5791 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
5792 {
5793 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ));
5794 }
5795 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
5796
5797 #if defined(RCC_DCKCFGR_PLLI2SDIVR)
5798 /**
5799 * @brief Get I2SPLL division factor for PLLI2SDIVR
5800 * @note used PLLSAICLK selected (SAI clock)
5801 * @rmtoll DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_GetDIVR
5802 * @retval Returned value can be one of the following values:
5803 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1
5804 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2
5805 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3
5806 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4
5807 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5
5808 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6
5809 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7
5810 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8
5811 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9
5812 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10
5813 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11
5814 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12
5815 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13
5816 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14
5817 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15
5818 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16
5819 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17
5820 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18
5821 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19
5822 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20
5823 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21
5824 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22
5825 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23
5826 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24
5827 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25
5828 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26
5829 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27
5830 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28
5831 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29
5832 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30
5833 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31
5834 */
5835 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void)
5836 {
5837 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR));
5838 }
5839 #endif /* RCC_DCKCFGR_PLLI2SDIVR */
5840
5841 /**
5842 * @brief Get division factor for PLLI2S input clock
5843 * @rmtoll PLLCFGR PLLM LL_RCC_PLLI2S_GetDivider\n
5844 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_GetDivider
5845 * @retval Returned value can be one of the following values:
5846 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5847 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5848 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5849 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5850 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5851 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5852 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5853 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5854 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5855 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5856 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5857 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5858 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5859 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5860 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5861 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5862 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5863 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5864 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5865 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5866 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5867 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5868 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5869 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5870 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5871 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5872 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5873 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5874 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5875 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5876 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5877 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5878 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5879 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5880 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5881 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5882 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5883 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5884 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5885 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5886 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5887 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5888 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5889 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5890 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5891 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5892 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5893 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5894 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5895 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5896 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5897 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5898 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5899 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5900 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5901 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5902 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5903 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5904 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5905 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5906 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5907 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5908 */
5909 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void)
5910 {
5911 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5912 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM));
5913 #else
5914 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
5915 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5916 }
5917
5918 /**
5919 * @brief Get the oscillator used as PLL clock source.
5920 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_GetMainSource\n
5921 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_GetMainSource
5922 * @retval Returned value can be one of the following values:
5923 * @arg @ref LL_RCC_PLLSOURCE_HSI
5924 * @arg @ref LL_RCC_PLLSOURCE_HSE
5925 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5926 *
5927 * (*) value not defined in all devices.
5928 */
5929 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void)
5930 {
5931 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
5932 register uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
5933 register uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);
5934 register uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;
5935 return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1);
5936 #else
5937 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
5938 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
5939 }
5940
5941 /**
5942 * @}
5943 */
5944 #endif /* RCC_PLLI2S_SUPPORT */
5945
5946 #if defined(RCC_PLLSAI_SUPPORT)
5947 /** @defgroup RCC_LL_EF_PLLSAI PLLSAI
5948 * @{
5949 */
5950
5951 /**
5952 * @brief Enable PLLSAI
5953 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable
5954 * @retval None
5955 */
5956 __STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
5957 {
5958 SET_BIT(RCC->CR, RCC_CR_PLLSAION);
5959 }
5960
5961 /**
5962 * @brief Disable PLLSAI
5963 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable
5964 * @retval None
5965 */
5966 __STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
5967 {
5968 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
5969 }
5970
5971 /**
5972 * @brief Check if PLLSAI Ready
5973 * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady
5974 * @retval State of bit (1 or 0).
5975 */
5976 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
5977 {
5978 return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
5979 }
5980
5981 /**
5982 * @brief Configure PLLSAI used for SAI domain clock
5983 * @note PLL Source and PLLM Divider can be written only when PLL,
5984 * PLLI2S and PLLSAI(*) are disabled
5985 * @note PLLN/PLLQ can be written only when PLLSAI is disabled
5986 * @note This can be selected for SAI
5987 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n
5988 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n
5989 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_SAI\n
5990 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n
5991 * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n
5992 * DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI
5993 * @param Source This parameter can be one of the following values:
5994 * @arg @ref LL_RCC_PLLSOURCE_HSI
5995 * @arg @ref LL_RCC_PLLSOURCE_HSE
5996 * @param PLLM This parameter can be one of the following values:
5997 * @arg @ref LL_RCC_PLLSAIM_DIV_2
5998 * @arg @ref LL_RCC_PLLSAIM_DIV_3
5999 * @arg @ref LL_RCC_PLLSAIM_DIV_4
6000 * @arg @ref LL_RCC_PLLSAIM_DIV_5
6001 * @arg @ref LL_RCC_PLLSAIM_DIV_6
6002 * @arg @ref LL_RCC_PLLSAIM_DIV_7
6003 * @arg @ref LL_RCC_PLLSAIM_DIV_8
6004 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6005 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6006 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6007 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6008 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6009 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6010 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6011 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6012 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6013 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6014 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6015 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6016 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6017 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6018 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6019 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6020 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6021 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6022 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6023 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6024 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6025 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6026 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6027 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6028 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6029 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6030 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6031 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6032 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6033 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6034 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6035 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6036 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6037 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6038 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6039 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6040 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6041 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6042 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6043 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6044 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6045 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6046 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6047 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6048 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6049 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6050 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6051 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6052 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6053 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6054 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6055 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6056 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6057 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6058 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6059 * @param PLLN Between 49/50(*) and 432
6060 *
6061 * (*) value not defined in all devices.
6062 * @param PLLQ This parameter can be one of the following values:
6063 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
6064 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
6065 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
6066 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
6067 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
6068 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
6069 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
6070 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
6071 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
6072 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
6073 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
6074 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
6075 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
6076 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
6077 * @param PLLDIVQ This parameter can be one of the following values:
6078 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
6079 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
6080 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
6081 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
6082 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
6083 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
6084 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
6085 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
6086 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
6087 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
6088 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
6089 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
6090 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
6091 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
6092 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
6093 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
6094 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
6095 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
6096 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
6097 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
6098 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
6099 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
6100 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
6101 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
6102 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
6103 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
6104 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
6105 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
6106 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
6107 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
6108 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
6109 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
6110 * @retval None
6111 */
6112 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
6113 {
6114 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
6115 #if defined(RCC_PLLSAICFGR_PLLSAIM)
6116 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
6117 #else
6118 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
6119 #endif /* RCC_PLLSAICFGR_PLLSAIM */
6120 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ);
6121 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ);
6122 }
6123
6124 #if defined(RCC_PLLSAICFGR_PLLSAIP)
6125 /**
6126 * @brief Configure PLLSAI used for 48Mhz domain clock
6127 * @note PLL Source and PLLM Divider can be written only when PLL,
6128 * PLLI2S and PLLSAI(*) are disabled
6129 * @note PLLN/PLLP can be written only when PLLSAI is disabled
6130 * @note This can be selected for USB, RNG, SDIO
6131 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n
6132 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n
6133 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_48M\n
6134 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n
6135 * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M
6136 * @param Source This parameter can be one of the following values:
6137 * @arg @ref LL_RCC_PLLSOURCE_HSI
6138 * @arg @ref LL_RCC_PLLSOURCE_HSE
6139 * @param PLLM This parameter can be one of the following values:
6140 * @arg @ref LL_RCC_PLLSAIM_DIV_2
6141 * @arg @ref LL_RCC_PLLSAIM_DIV_3
6142 * @arg @ref LL_RCC_PLLSAIM_DIV_4
6143 * @arg @ref LL_RCC_PLLSAIM_DIV_5
6144 * @arg @ref LL_RCC_PLLSAIM_DIV_6
6145 * @arg @ref LL_RCC_PLLSAIM_DIV_7
6146 * @arg @ref LL_RCC_PLLSAIM_DIV_8
6147 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6148 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6149 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6150 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6151 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6152 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6153 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6154 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6155 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6156 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6157 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6158 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6159 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6160 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6161 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6162 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6163 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6164 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6165 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6166 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6167 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6168 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6169 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6170 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6171 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6172 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6173 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6174 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6175 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6176 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6177 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6178 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6179 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6180 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6181 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6182 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6183 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6184 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6185 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6186 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6187 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6188 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6189 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6190 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6191 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6192 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6193 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6194 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6195 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6196 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6197 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6198 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6199 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6200 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6201 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6202 * @param PLLN Between 50 and 432
6203 * @param PLLP This parameter can be one of the following values:
6204 * @arg @ref LL_RCC_PLLSAIP_DIV_2
6205 * @arg @ref LL_RCC_PLLSAIP_DIV_4
6206 * @arg @ref LL_RCC_PLLSAIP_DIV_6
6207 * @arg @ref LL_RCC_PLLSAIP_DIV_8
6208 * @retval None
6209 */
6210 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
6211 {
6212 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
6213 #if defined(RCC_PLLSAICFGR_PLLSAIM)
6214 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
6215 #else
6216 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
6217 #endif /* RCC_PLLSAICFGR_PLLSAIM */
6218 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP);
6219 }
6220 #endif /* RCC_PLLSAICFGR_PLLSAIP */
6221
6222 #if defined(LTDC)
6223 /**
6224 * @brief Configure PLLSAI used for LTDC domain clock
6225 * @note PLL Source and PLLM Divider can be written only when PLL,
6226 * PLLI2S and PLLSAI(*) are disabled
6227 * @note PLLN/PLLR can be written only when PLLSAI is disabled
6228 * @note This can be selected for LTDC
6229 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6230 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6231 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6232 * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6233 * DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC
6234 * @param Source This parameter can be one of the following values:
6235 * @arg @ref LL_RCC_PLLSOURCE_HSI
6236 * @arg @ref LL_RCC_PLLSOURCE_HSE
6237 * @param PLLM This parameter can be one of the following values:
6238 * @arg @ref LL_RCC_PLLSAIM_DIV_2
6239 * @arg @ref LL_RCC_PLLSAIM_DIV_3
6240 * @arg @ref LL_RCC_PLLSAIM_DIV_4
6241 * @arg @ref LL_RCC_PLLSAIM_DIV_5
6242 * @arg @ref LL_RCC_PLLSAIM_DIV_6
6243 * @arg @ref LL_RCC_PLLSAIM_DIV_7
6244 * @arg @ref LL_RCC_PLLSAIM_DIV_8
6245 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6246 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6247 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6248 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6249 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6250 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6251 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6252 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6253 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6254 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6255 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6256 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6257 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6258 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6259 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6260 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6261 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6262 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6263 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6264 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6265 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6266 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6267 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6268 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6269 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6270 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6271 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6272 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6273 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6274 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6275 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6276 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6277 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6278 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6279 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6280 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6281 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6282 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6283 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6284 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6285 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6286 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6287 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6288 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6289 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6290 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6291 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6292 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6293 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6294 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6295 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6296 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6297 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6298 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6299 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6300 * @param PLLN Between 49/50(*) and 432
6301 *
6302 * (*) value not defined in all devices.
6303 * @param PLLR This parameter can be one of the following values:
6304 * @arg @ref LL_RCC_PLLSAIR_DIV_2
6305 * @arg @ref LL_RCC_PLLSAIR_DIV_3
6306 * @arg @ref LL_RCC_PLLSAIR_DIV_4
6307 * @arg @ref LL_RCC_PLLSAIR_DIV_5
6308 * @arg @ref LL_RCC_PLLSAIR_DIV_6
6309 * @arg @ref LL_RCC_PLLSAIR_DIV_7
6310 * @param PLLDIVR This parameter can be one of the following values:
6311 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
6312 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
6313 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
6314 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
6315 * @retval None
6316 */
6317 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
6318 {
6319 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
6320 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR);
6321 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR);
6322 }
6323 #endif /* LTDC */
6324
6325 /**
6326 * @brief Get division factor for PLLSAI input clock
6327 * @rmtoll PLLCFGR PLLM LL_RCC_PLLSAI_GetDivider\n
6328 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_GetDivider
6329 * @retval Returned value can be one of the following values:
6330 * @arg @ref LL_RCC_PLLSAIM_DIV_2
6331 * @arg @ref LL_RCC_PLLSAIM_DIV_3
6332 * @arg @ref LL_RCC_PLLSAIM_DIV_4
6333 * @arg @ref LL_RCC_PLLSAIM_DIV_5
6334 * @arg @ref LL_RCC_PLLSAIM_DIV_6
6335 * @arg @ref LL_RCC_PLLSAIM_DIV_7
6336 * @arg @ref LL_RCC_PLLSAIM_DIV_8
6337 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6338 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6339 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6340 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6341 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6342 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6343 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6344 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6345 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6346 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6347 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6348 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6349 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6350 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6351 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6352 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6353 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6354 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6355 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6356 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6357 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6358 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6359 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6360 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6361 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6362 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6363 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6364 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6365 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6366 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6367 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6368 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6369 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6370 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6371 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6372 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6373 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6374 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6375 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6376 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6377 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6378 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6379 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6380 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6381 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6382 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6383 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6384 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6385 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6386 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6387 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6388 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6389 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6390 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6391 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6392 */
6393 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void)
6394 {
6395 #if defined(RCC_PLLSAICFGR_PLLSAIM)
6396 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM));
6397 #else
6398 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
6399 #endif /* RCC_PLLSAICFGR_PLLSAIM */
6400 }
6401
6402 /**
6403 * @brief Get SAIPLL multiplication factor for VCO
6404 * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN
6405 * @retval Between 49/50(*) and 432
6406 *
6407 * (*) value not defined in all devices.
6408 */
6409 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
6410 {
6411 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
6412 }
6413
6414 /**
6415 * @brief Get SAIPLL division factor for PLLSAIQ
6416 * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ
6417 * @retval Returned value can be one of the following values:
6418 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
6419 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
6420 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
6421 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
6422 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
6423 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
6424 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
6425 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
6426 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
6427 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
6428 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
6429 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
6430 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
6431 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
6432 */
6433 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
6434 {
6435 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
6436 }
6437
6438 #if defined(RCC_PLLSAICFGR_PLLSAIR)
6439 /**
6440 * @brief Get SAIPLL division factor for PLLSAIR
6441 * @note used for PLLSAICLK (SAI clock)
6442 * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR
6443 * @retval Returned value can be one of the following values:
6444 * @arg @ref LL_RCC_PLLSAIR_DIV_2
6445 * @arg @ref LL_RCC_PLLSAIR_DIV_3
6446 * @arg @ref LL_RCC_PLLSAIR_DIV_4
6447 * @arg @ref LL_RCC_PLLSAIR_DIV_5
6448 * @arg @ref LL_RCC_PLLSAIR_DIV_6
6449 * @arg @ref LL_RCC_PLLSAIR_DIV_7
6450 */
6451 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
6452 {
6453 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
6454 }
6455 #endif /* RCC_PLLSAICFGR_PLLSAIR */
6456
6457 #if defined(RCC_PLLSAICFGR_PLLSAIP)
6458 /**
6459 * @brief Get SAIPLL division factor for PLLSAIP
6460 * @note used for PLL48MCLK (48M domain clock)
6461 * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP
6462 * @retval Returned value can be one of the following values:
6463 * @arg @ref LL_RCC_PLLSAIP_DIV_2
6464 * @arg @ref LL_RCC_PLLSAIP_DIV_4
6465 * @arg @ref LL_RCC_PLLSAIP_DIV_6
6466 * @arg @ref LL_RCC_PLLSAIP_DIV_8
6467 */
6468 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
6469 {
6470 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
6471 }
6472 #endif /* RCC_PLLSAICFGR_PLLSAIP */
6473
6474 /**
6475 * @brief Get SAIPLL division factor for PLLSAIDIVQ
6476 * @note used PLLSAICLK selected (SAI clock)
6477 * @rmtoll DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ
6478 * @retval Returned value can be one of the following values:
6479 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
6480 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
6481 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
6482 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
6483 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
6484 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
6485 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
6486 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
6487 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
6488 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
6489 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
6490 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
6491 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
6492 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
6493 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
6494 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
6495 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
6496 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
6497 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
6498 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
6499 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
6500 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
6501 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
6502 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
6503 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
6504 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
6505 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
6506 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
6507 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
6508 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
6509 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
6510 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
6511 */
6512 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
6513 {
6514 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ));
6515 }
6516
6517 #if defined(RCC_DCKCFGR_PLLSAIDIVR)
6518 /**
6519 * @brief Get SAIPLL division factor for PLLSAIDIVR
6520 * @note used for LTDC domain clock
6521 * @rmtoll DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR
6522 * @retval Returned value can be one of the following values:
6523 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
6524 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
6525 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
6526 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
6527 */
6528 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
6529 {
6530 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR));
6531 }
6532 #endif /* RCC_DCKCFGR_PLLSAIDIVR */
6533
6534 /**
6535 * @}
6536 */
6537 #endif /* RCC_PLLSAI_SUPPORT */
6538
6539 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
6540 * @{
6541 */
6542
6543 /**
6544 * @brief Clear LSI ready interrupt flag
6545 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
6546 * @retval None
6547 */
6548 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
6549 {
6550 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
6551 }
6552
6553 /**
6554 * @brief Clear LSE ready interrupt flag
6555 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
6556 * @retval None
6557 */
6558 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
6559 {
6560 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
6561 }
6562
6563 /**
6564 * @brief Clear HSI ready interrupt flag
6565 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
6566 * @retval None
6567 */
6568 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
6569 {
6570 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
6571 }
6572
6573 /**
6574 * @brief Clear HSE ready interrupt flag
6575 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
6576 * @retval None
6577 */
6578 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
6579 {
6580 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
6581 }
6582
6583 /**
6584 * @brief Clear PLL ready interrupt flag
6585 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
6586 * @retval None
6587 */
6588 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
6589 {
6590 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
6591 }
6592
6593 #if defined(RCC_PLLI2S_SUPPORT)
6594 /**
6595 * @brief Clear PLLI2S ready interrupt flag
6596 * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
6597 * @retval None
6598 */
6599 __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
6600 {
6601 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
6602 }
6603
6604 #endif /* RCC_PLLI2S_SUPPORT */
6605
6606 #if defined(RCC_PLLSAI_SUPPORT)
6607 /**
6608 * @brief Clear PLLSAI ready interrupt flag
6609 * @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY
6610 * @retval None
6611 */
6612 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
6613 {
6614 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
6615 }
6616
6617 #endif /* RCC_PLLSAI_SUPPORT */
6618
6619 /**
6620 * @brief Clear Clock security system interrupt flag
6621 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
6622 * @retval None
6623 */
6624 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
6625 {
6626 SET_BIT(RCC->CIR, RCC_CIR_CSSC);
6627 }
6628
6629 /**
6630 * @brief Check if LSI ready interrupt occurred or not
6631 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
6632 * @retval State of bit (1 or 0).
6633 */
6634 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
6635 {
6636 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
6637 }
6638
6639 /**
6640 * @brief Check if LSE ready interrupt occurred or not
6641 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
6642 * @retval State of bit (1 or 0).
6643 */
6644 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
6645 {
6646 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
6647 }
6648
6649 /**
6650 * @brief Check if HSI ready interrupt occurred or not
6651 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
6652 * @retval State of bit (1 or 0).
6653 */
6654 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
6655 {
6656 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
6657 }
6658
6659 /**
6660 * @brief Check if HSE ready interrupt occurred or not
6661 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
6662 * @retval State of bit (1 or 0).
6663 */
6664 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
6665 {
6666 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
6667 }
6668
6669 /**
6670 * @brief Check if PLL ready interrupt occurred or not
6671 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
6672 * @retval State of bit (1 or 0).
6673 */
6674 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
6675 {
6676 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
6677 }
6678
6679 #if defined(RCC_PLLI2S_SUPPORT)
6680 /**
6681 * @brief Check if PLLI2S ready interrupt occurred or not
6682 * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
6683 * @retval State of bit (1 or 0).
6684 */
6685 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
6686 {
6687 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
6688 }
6689 #endif /* RCC_PLLI2S_SUPPORT */
6690
6691 #if defined(RCC_PLLSAI_SUPPORT)
6692 /**
6693 * @brief Check if PLLSAI ready interrupt occurred or not
6694 * @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY
6695 * @retval State of bit (1 or 0).
6696 */
6697 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
6698 {
6699 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
6700 }
6701 #endif /* RCC_PLLSAI_SUPPORT */
6702
6703 /**
6704 * @brief Check if Clock security system interrupt occurred or not
6705 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
6706 * @retval State of bit (1 or 0).
6707 */
6708 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
6709 {
6710 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
6711 }
6712
6713 /**
6714 * @brief Check if RCC flag Independent Watchdog reset is set or not.
6715 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
6716 * @retval State of bit (1 or 0).
6717 */
6718 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
6719 {
6720 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
6721 }
6722
6723 /**
6724 * @brief Check if RCC flag Low Power reset is set or not.
6725 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
6726 * @retval State of bit (1 or 0).
6727 */
6728 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
6729 {
6730 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
6731 }
6732
6733 /**
6734 * @brief Check if RCC flag Pin reset is set or not.
6735 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
6736 * @retval State of bit (1 or 0).
6737 */
6738 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
6739 {
6740 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
6741 }
6742
6743 /**
6744 * @brief Check if RCC flag POR/PDR reset is set or not.
6745 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
6746 * @retval State of bit (1 or 0).
6747 */
6748 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
6749 {
6750 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
6751 }
6752
6753 /**
6754 * @brief Check if RCC flag Software reset is set or not.
6755 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
6756 * @retval State of bit (1 or 0).
6757 */
6758 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
6759 {
6760 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
6761 }
6762
6763 /**
6764 * @brief Check if RCC flag Window Watchdog reset is set or not.
6765 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
6766 * @retval State of bit (1 or 0).
6767 */
6768 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
6769 {
6770 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
6771 }
6772
6773 #if defined(RCC_CSR_BORRSTF)
6774 /**
6775 * @brief Check if RCC flag BOR reset is set or not.
6776 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
6777 * @retval State of bit (1 or 0).
6778 */
6779 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
6780 {
6781 return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
6782 }
6783 #endif /* RCC_CSR_BORRSTF */
6784
6785 /**
6786 * @brief Set RMVF bit to clear the reset flags.
6787 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
6788 * @retval None
6789 */
6790 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
6791 {
6792 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
6793 }
6794
6795 /**
6796 * @}
6797 */
6798
6799 /** @defgroup RCC_LL_EF_IT_Management IT Management
6800 * @{
6801 */
6802
6803 /**
6804 * @brief Enable LSI ready interrupt
6805 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
6806 * @retval None
6807 */
6808 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
6809 {
6810 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
6811 }
6812
6813 /**
6814 * @brief Enable LSE ready interrupt
6815 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
6816 * @retval None
6817 */
6818 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
6819 {
6820 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
6821 }
6822
6823 /**
6824 * @brief Enable HSI ready interrupt
6825 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
6826 * @retval None
6827 */
6828 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
6829 {
6830 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
6831 }
6832
6833 /**
6834 * @brief Enable HSE ready interrupt
6835 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
6836 * @retval None
6837 */
6838 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
6839 {
6840 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
6841 }
6842
6843 /**
6844 * @brief Enable PLL ready interrupt
6845 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
6846 * @retval None
6847 */
6848 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
6849 {
6850 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
6851 }
6852
6853 #if defined(RCC_PLLI2S_SUPPORT)
6854 /**
6855 * @brief Enable PLLI2S ready interrupt
6856 * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
6857 * @retval None
6858 */
6859 __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
6860 {
6861 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
6862 }
6863 #endif /* RCC_PLLI2S_SUPPORT */
6864
6865 #if defined(RCC_PLLSAI_SUPPORT)
6866 /**
6867 * @brief Enable PLLSAI ready interrupt
6868 * @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY
6869 * @retval None
6870 */
6871 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
6872 {
6873 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
6874 }
6875 #endif /* RCC_PLLSAI_SUPPORT */
6876
6877 /**
6878 * @brief Disable LSI ready interrupt
6879 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
6880 * @retval None
6881 */
6882 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
6883 {
6884 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
6885 }
6886
6887 /**
6888 * @brief Disable LSE ready interrupt
6889 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
6890 * @retval None
6891 */
6892 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
6893 {
6894 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
6895 }
6896
6897 /**
6898 * @brief Disable HSI ready interrupt
6899 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
6900 * @retval None
6901 */
6902 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
6903 {
6904 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
6905 }
6906
6907 /**
6908 * @brief Disable HSE ready interrupt
6909 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
6910 * @retval None
6911 */
6912 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
6913 {
6914 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
6915 }
6916
6917 /**
6918 * @brief Disable PLL ready interrupt
6919 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
6920 * @retval None
6921 */
6922 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
6923 {
6924 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
6925 }
6926
6927 #if defined(RCC_PLLI2S_SUPPORT)
6928 /**
6929 * @brief Disable PLLI2S ready interrupt
6930 * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
6931 * @retval None
6932 */
6933 __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
6934 {
6935 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
6936 }
6937
6938 #endif /* RCC_PLLI2S_SUPPORT */
6939
6940 #if defined(RCC_PLLSAI_SUPPORT)
6941 /**
6942 * @brief Disable PLLSAI ready interrupt
6943 * @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY
6944 * @retval None
6945 */
6946 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
6947 {
6948 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
6949 }
6950 #endif /* RCC_PLLSAI_SUPPORT */
6951
6952 /**
6953 * @brief Checks if LSI ready interrupt source is enabled or disabled.
6954 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
6955 * @retval State of bit (1 or 0).
6956 */
6957 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
6958 {
6959 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
6960 }
6961
6962 /**
6963 * @brief Checks if LSE ready interrupt source is enabled or disabled.
6964 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
6965 * @retval State of bit (1 or 0).
6966 */
6967 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
6968 {
6969 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
6970 }
6971
6972 /**
6973 * @brief Checks if HSI ready interrupt source is enabled or disabled.
6974 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
6975 * @retval State of bit (1 or 0).
6976 */
6977 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
6978 {
6979 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
6980 }
6981
6982 /**
6983 * @brief Checks if HSE ready interrupt source is enabled or disabled.
6984 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
6985 * @retval State of bit (1 or 0).
6986 */
6987 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
6988 {
6989 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
6990 }
6991
6992 /**
6993 * @brief Checks if PLL ready interrupt source is enabled or disabled.
6994 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
6995 * @retval State of bit (1 or 0).
6996 */
6997 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
6998 {
6999 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
7000 }
7001
7002 #if defined(RCC_PLLI2S_SUPPORT)
7003 /**
7004 * @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
7005 * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
7006 * @retval State of bit (1 or 0).
7007 */
7008 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
7009 {
7010 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
7011 }
7012
7013 #endif /* RCC_PLLI2S_SUPPORT */
7014
7015 #if defined(RCC_PLLSAI_SUPPORT)
7016 /**
7017 * @brief Checks if PLLSAI ready interrupt source is enabled or disabled.
7018 * @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY
7019 * @retval State of bit (1 or 0).
7020 */
7021 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
7022 {
7023 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
7024 }
7025 #endif /* RCC_PLLSAI_SUPPORT */
7026
7027 /**
7028 * @}
7029 */
7030
7031 #if defined(USE_FULL_LL_DRIVER)
7032 /** @defgroup RCC_LL_EF_Init De-initialization function
7033 * @{
7034 */
7035 ErrorStatus LL_RCC_DeInit(void);
7036 /**
7037 * @}
7038 */
7039
7040 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
7041 * @{
7042 */
7043 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
7044 #if defined(FMPI2C1)
7045 uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource);
7046 #endif /* FMPI2C1 */
7047 #if defined(LPTIM1)
7048 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
7049 #endif /* LPTIM1 */
7050 #if defined(SAI1)
7051 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
7052 #endif /* SAI1 */
7053 #if defined(SDIO)
7054 uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource);
7055 #endif /* SDIO */
7056 #if defined(RNG)
7057 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
7058 #endif /* RNG */
7059 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
7060 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
7061 #endif /* USB_OTG_FS || USB_OTG_HS */
7062 #if defined(DFSDM1_Channel0)
7063 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
7064 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
7065 #endif /* DFSDM1_Channel0 */
7066 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
7067 #if defined(CEC)
7068 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
7069 #endif /* CEC */
7070 #if defined(LTDC)
7071 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
7072 #endif /* LTDC */
7073 #if defined(SPDIFRX)
7074 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
7075 #endif /* SPDIFRX */
7076 #if defined(DSI)
7077 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
7078 #endif /* DSI */
7079 /**
7080 * @}
7081 */
7082 #endif /* USE_FULL_LL_DRIVER */
7083
7084 /**
7085 * @}
7086 */
7087
7088 /**
7089 * @}
7090 */
7091
7092 #endif /* defined(RCC) */
7093
7094 /**
7095 * @}
7096 */
7097
7098 #ifdef __cplusplus
7099 }
7100 #endif
7101
7102 #endif /* __STM32F4xx_LL_RCC_H */
7103
7104 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/