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Merge pull request #11198 from SteveCEvans/sce_rc2
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_HAL_Driver / Inc / stm32f4xx_ll_spi.h
blob77085e83243126b889dc35d1ec36725d8aa6f594
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_spi.h
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 14-April-2017
7 * @brief Header file of SPI LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_LL_SPI_H
40 #define __STM32F4xx_LL_SPI_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx.h"
48
49 /** @addtogroup STM32F4xx_LL_Driver
50 * @{
51 */
52
53 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6)
54
55 /** @defgroup SPI_LL SPI
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /* Private macros ------------------------------------------------------------*/
62
63 /* Exported types ------------------------------------------------------------*/
64 #if defined(USE_FULL_LL_DRIVER)
65 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
66 * @{
67 */
68
69 /**
70 * @brief SPI Init structures definition
71 */
72 typedef struct
73 {
74 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
75 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
76
77 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
78
79 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
80 This parameter can be a value of @ref SPI_LL_EC_MODE.
81
82 This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
83
84 uint32_t DataWidth; /*!< Specifies the SPI data width.
85 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
86
87 This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
88
89 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
90 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
91
92 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
93
94 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
95 This parameter can be a value of @ref SPI_LL_EC_PHASE.
96
97 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
98
99 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
100 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
101
102 This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
103
104 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
105 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
106 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
107
108 This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
109
110 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
111 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
112
113 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
114
115 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
116 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
117
118 This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
119
120 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
121 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
122
123 This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
124
125 } LL_SPI_InitTypeDef;
126
127 /**
128 * @}
129 */
130 #endif /* USE_FULL_LL_DRIVER */
131
132 /* Exported constants --------------------------------------------------------*/
133 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
134 * @{
135 */
136
137 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
138 * @brief Flags defines which can be used with LL_SPI_ReadReg function
139 * @{
140 */
141 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
142 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
143 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
144 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
145 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
146 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
147 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
148 /**
149 * @}
150 */
151
152 /** @defgroup SPI_LL_EC_IT IT Defines
153 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
154 * @{
155 */
156 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
157 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
158 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
159 /**
160 * @}
161 */
162
163 /** @defgroup SPI_LL_EC_MODE Operation Mode
164 * @{
165 */
166 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
167 #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
168 /**
169 * @}
170 */
171
172 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
173 * @{
174 */
175 #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
176 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
177 /**
178 * @}
179 */
180
181 /** @defgroup SPI_LL_EC_PHASE Clock Phase
182 * @{
183 */
184 #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
185 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
186 /**
187 * @}
188 */
189
190 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
191 * @{
192 */
193 #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
194 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
195 /**
196 * @}
197 */
198
199 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
200 * @{
201 */
202 #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
203 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
204 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
205 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
206 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
207 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
208 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
209 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
210 /**
211 * @}
212 */
213
214 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
215 * @{
216 */
217 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
218 #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
219 /**
220 * @}
221 */
222
223 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
224 * @{
225 */
226 #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
227 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
228 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
229 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
230 /**
231 * @}
232 */
233
234 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
235 * @{
236 */
237 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
238 #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
239 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
240 /**
241 * @}
242 */
243
244 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
245 * @{
246 */
247 #define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
248 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
249 /**
250 * @}
251 */
252 #if defined(USE_FULL_LL_DRIVER)
253
254 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
255 * @{
256 */
257 #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
258 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
259 /**
260 * @}
261 */
262 #endif /* USE_FULL_LL_DRIVER */
263
264 /**
265 * @}
266 */
267
268 /* Exported macro ------------------------------------------------------------*/
269 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
270 * @{
271 */
272
273 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
274 * @{
275 */
276
277 /**
278 * @brief Write a value in SPI register
279 * @param __INSTANCE__ SPI Instance
280 * @param __REG__ Register to be written
281 * @param __VALUE__ Value to be written in the register
282 * @retval None
283 */
284 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
285
286 /**
287 * @brief Read a value in SPI register
288 * @param __INSTANCE__ SPI Instance
289 * @param __REG__ Register to be read
290 * @retval Register value
291 */
292 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
293 /**
294 * @}
295 */
296
297 /**
298 * @}
299 */
300
301 /* Exported functions --------------------------------------------------------*/
302 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
303 * @{
304 */
305
306 /** @defgroup SPI_LL_EF_Configuration Configuration
307 * @{
308 */
309
310 /**
311 * @brief Enable SPI peripheral
312 * @rmtoll CR1 SPE LL_SPI_Enable
313 * @param SPIx SPI Instance
314 * @retval None
315 */
316 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
317 {
318 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
319 }
320
321 /**
322 * @brief Disable SPI peripheral
323 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
324 * @rmtoll CR1 SPE LL_SPI_Disable
325 * @param SPIx SPI Instance
326 * @retval None
327 */
328 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
329 {
330 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
331 }
332
333 /**
334 * @brief Check if SPI peripheral is enabled
335 * @rmtoll CR1 SPE LL_SPI_IsEnabled
336 * @param SPIx SPI Instance
337 * @retval State of bit (1 or 0).
338 */
339 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
340 {
341 return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
342 }
343
344 /**
345 * @brief Set SPI operation mode to Master or Slave
346 * @note This bit should not be changed when communication is ongoing.
347 * @rmtoll CR1 MSTR LL_SPI_SetMode\n
348 * CR1 SSI LL_SPI_SetMode
349 * @param SPIx SPI Instance
350 * @param Mode This parameter can be one of the following values:
351 * @arg @ref LL_SPI_MODE_MASTER
352 * @arg @ref LL_SPI_MODE_SLAVE
353 * @retval None
354 */
355 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
356 {
357 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
358 }
359
360 /**
361 * @brief Get SPI operation mode (Master or Slave)
362 * @rmtoll CR1 MSTR LL_SPI_GetMode\n
363 * CR1 SSI LL_SPI_GetMode
364 * @param SPIx SPI Instance
365 * @retval Returned value can be one of the following values:
366 * @arg @ref LL_SPI_MODE_MASTER
367 * @arg @ref LL_SPI_MODE_SLAVE
368 */
369 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
370 {
371 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
372 }
373
374 /**
375 * @brief Set serial protocol used
376 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
377 * @rmtoll CR2 FRF LL_SPI_SetStandard
378 * @param SPIx SPI Instance
379 * @param Standard This parameter can be one of the following values:
380 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
381 * @arg @ref LL_SPI_PROTOCOL_TI
382 * @retval None
383 */
384 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
385 {
386 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
387 }
388
389 /**
390 * @brief Get serial protocol used
391 * @rmtoll CR2 FRF LL_SPI_GetStandard
392 * @param SPIx SPI Instance
393 * @retval Returned value can be one of the following values:
394 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
395 * @arg @ref LL_SPI_PROTOCOL_TI
396 */
397 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
398 {
399 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
400 }
401
402 /**
403 * @brief Set clock phase
404 * @note This bit should not be changed when communication is ongoing.
405 * This bit is not used in SPI TI mode.
406 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
407 * @param SPIx SPI Instance
408 * @param ClockPhase This parameter can be one of the following values:
409 * @arg @ref LL_SPI_PHASE_1EDGE
410 * @arg @ref LL_SPI_PHASE_2EDGE
411 * @retval None
412 */
413 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
414 {
415 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
416 }
417
418 /**
419 * @brief Get clock phase
420 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
421 * @param SPIx SPI Instance
422 * @retval Returned value can be one of the following values:
423 * @arg @ref LL_SPI_PHASE_1EDGE
424 * @arg @ref LL_SPI_PHASE_2EDGE
425 */
426 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
427 {
428 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
429 }
430
431 /**
432 * @brief Set clock polarity
433 * @note This bit should not be changed when communication is ongoing.
434 * This bit is not used in SPI TI mode.
435 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
436 * @param SPIx SPI Instance
437 * @param ClockPolarity This parameter can be one of the following values:
438 * @arg @ref LL_SPI_POLARITY_LOW
439 * @arg @ref LL_SPI_POLARITY_HIGH
440 * @retval None
441 */
442 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
443 {
444 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
445 }
446
447 /**
448 * @brief Get clock polarity
449 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
450 * @param SPIx SPI Instance
451 * @retval Returned value can be one of the following values:
452 * @arg @ref LL_SPI_POLARITY_LOW
453 * @arg @ref LL_SPI_POLARITY_HIGH
454 */
455 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
456 {
457 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
458 }
459
460 /**
461 * @brief Set baud rate prescaler
462 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
463 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
464 * @param SPIx SPI Instance
465 * @param BaudRate This parameter can be one of the following values:
466 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
467 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
468 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
469 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
470 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
471 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
472 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
473 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
474 * @retval None
475 */
476 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
477 {
478 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
479 }
480
481 /**
482 * @brief Get baud rate prescaler
483 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
484 * @param SPIx SPI Instance
485 * @retval Returned value can be one of the following values:
486 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
487 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
488 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
489 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
490 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
491 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
492 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
493 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
494 */
495 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
496 {
497 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
498 }
499
500 /**
501 * @brief Set transfer bit order
502 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
503 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
504 * @param SPIx SPI Instance
505 * @param BitOrder This parameter can be one of the following values:
506 * @arg @ref LL_SPI_LSB_FIRST
507 * @arg @ref LL_SPI_MSB_FIRST
508 * @retval None
509 */
510 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
511 {
512 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
513 }
514
515 /**
516 * @brief Get transfer bit order
517 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
518 * @param SPIx SPI Instance
519 * @retval Returned value can be one of the following values:
520 * @arg @ref LL_SPI_LSB_FIRST
521 * @arg @ref LL_SPI_MSB_FIRST
522 */
523 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
524 {
525 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
526 }
527
528 /**
529 * @brief Set transfer direction mode
530 * @note For Half-Duplex mode, Rx Direction is set by default.
531 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
532 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
533 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
534 * CR1 BIDIOE LL_SPI_SetTransferDirection
535 * @param SPIx SPI Instance
536 * @param TransferDirection This parameter can be one of the following values:
537 * @arg @ref LL_SPI_FULL_DUPLEX
538 * @arg @ref LL_SPI_SIMPLEX_RX
539 * @arg @ref LL_SPI_HALF_DUPLEX_RX
540 * @arg @ref LL_SPI_HALF_DUPLEX_TX
541 * @retval None
542 */
543 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
544 {
545 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
546 }
547
548 /**
549 * @brief Get transfer direction mode
550 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
551 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
552 * CR1 BIDIOE LL_SPI_GetTransferDirection
553 * @param SPIx SPI Instance
554 * @retval Returned value can be one of the following values:
555 * @arg @ref LL_SPI_FULL_DUPLEX
556 * @arg @ref LL_SPI_SIMPLEX_RX
557 * @arg @ref LL_SPI_HALF_DUPLEX_RX
558 * @arg @ref LL_SPI_HALF_DUPLEX_TX
559 */
560 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
561 {
562 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
563 }
564
565 /**
566 * @brief Set frame data width
567 * @rmtoll CR1 DFF LL_SPI_SetDataWidth
568 * @param SPIx SPI Instance
569 * @param DataWidth This parameter can be one of the following values:
570 * @arg @ref LL_SPI_DATAWIDTH_8BIT
571 * @arg @ref LL_SPI_DATAWIDTH_16BIT
572 * @retval None
573 */
574 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
575 {
576 MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
577 }
578
579 /**
580 * @brief Get frame data width
581 * @rmtoll CR1 DFF LL_SPI_GetDataWidth
582 * @param SPIx SPI Instance
583 * @retval Returned value can be one of the following values:
584 * @arg @ref LL_SPI_DATAWIDTH_8BIT
585 * @arg @ref LL_SPI_DATAWIDTH_16BIT
586 */
587 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
588 {
589 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
590 }
591
592 /**
593 * @}
594 */
595
596 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
597 * @{
598 */
599
600 /**
601 * @brief Enable CRC
602 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
603 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
604 * @param SPIx SPI Instance
605 * @retval None
606 */
607 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
608 {
609 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
610 }
611
612 /**
613 * @brief Disable CRC
614 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
615 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
616 * @param SPIx SPI Instance
617 * @retval None
618 */
619 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
620 {
621 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
622 }
623
624 /**
625 * @brief Check if CRC is enabled
626 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
627 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
628 * @param SPIx SPI Instance
629 * @retval State of bit (1 or 0).
630 */
631 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
632 {
633 return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
634 }
635
636 /**
637 * @brief Set CRCNext to transfer CRC on the line
638 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
639 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
640 * @param SPIx SPI Instance
641 * @retval None
642 */
643 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
644 {
645 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
646 }
647
648 /**
649 * @brief Set polynomial for CRC calculation
650 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
651 * @param SPIx SPI Instance
652 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
653 * @retval None
654 */
655 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
656 {
657 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
658 }
659
660 /**
661 * @brief Get polynomial for CRC calculation
662 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
663 * @param SPIx SPI Instance
664 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
665 */
666 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
667 {
668 return (uint32_t)(READ_REG(SPIx->CRCPR));
669 }
670
671 /**
672 * @brief Get Rx CRC
673 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
674 * @param SPIx SPI Instance
675 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
676 */
677 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
678 {
679 return (uint32_t)(READ_REG(SPIx->RXCRCR));
680 }
681
682 /**
683 * @brief Get Tx CRC
684 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
685 * @param SPIx SPI Instance
686 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
687 */
688 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
689 {
690 return (uint32_t)(READ_REG(SPIx->TXCRCR));
691 }
692
693 /**
694 * @}
695 */
696
697 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
698 * @{
699 */
700
701 /**
702 * @brief Set NSS mode
703 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
704 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
705 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
706 * @param SPIx SPI Instance
707 * @param NSS This parameter can be one of the following values:
708 * @arg @ref LL_SPI_NSS_SOFT
709 * @arg @ref LL_SPI_NSS_HARD_INPUT
710 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
711 * @retval None
712 */
713 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
714 {
715 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
716 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
717 }
718
719 /**
720 * @brief Get NSS mode
721 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
722 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
723 * @param SPIx SPI Instance
724 * @retval Returned value can be one of the following values:
725 * @arg @ref LL_SPI_NSS_SOFT
726 * @arg @ref LL_SPI_NSS_HARD_INPUT
727 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
728 */
729 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
730 {
731 register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
732 register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
733 return (Ssm | Ssoe);
734 }
735
736 /**
737 * @}
738 */
739
740 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
741 * @{
742 */
743
744 /**
745 * @brief Check if Rx buffer is not empty
746 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
747 * @param SPIx SPI Instance
748 * @retval State of bit (1 or 0).
749 */
750 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
751 {
752 return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
753 }
754
755 /**
756 * @brief Check if Tx buffer is empty
757 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
758 * @param SPIx SPI Instance
759 * @retval State of bit (1 or 0).
760 */
761 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
762 {
763 return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
764 }
765
766 /**
767 * @brief Get CRC error flag
768 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
769 * @param SPIx SPI Instance
770 * @retval State of bit (1 or 0).
771 */
772 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
773 {
774 return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
775 }
776
777 /**
778 * @brief Get mode fault error flag
779 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
780 * @param SPIx SPI Instance
781 * @retval State of bit (1 or 0).
782 */
783 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
784 {
785 return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
786 }
787
788 /**
789 * @brief Get overrun error flag
790 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
791 * @param SPIx SPI Instance
792 * @retval State of bit (1 or 0).
793 */
794 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
795 {
796 return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
797 }
798
799 /**
800 * @brief Get busy flag
801 * @note The BSY flag is cleared under any one of the following conditions:
802 * -When the SPI is correctly disabled
803 * -When a fault is detected in Master mode (MODF bit set to 1)
804 * -In Master mode, when it finishes a data transmission and no new data is ready to be
805 * sent
806 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
807 * each data transfer.
808 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
809 * @param SPIx SPI Instance
810 * @retval State of bit (1 or 0).
811 */
812 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
813 {
814 return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
815 }
816
817 /**
818 * @brief Get frame format error flag
819 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
820 * @param SPIx SPI Instance
821 * @retval State of bit (1 or 0).
822 */
823 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
824 {
825 return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
826 }
827
828 /**
829 * @brief Clear CRC error flag
830 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
831 * @param SPIx SPI Instance
832 * @retval None
833 */
834 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
835 {
836 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
837 }
838
839 /**
840 * @brief Clear mode fault error flag
841 * @note Clearing this flag is done by a read access to the SPIx_SR
842 * register followed by a write access to the SPIx_CR1 register
843 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
844 * @param SPIx SPI Instance
845 * @retval None
846 */
847 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
848 {
849 __IO uint32_t tmpreg;
850 tmpreg = SPIx->SR;
851 (void) tmpreg;
852 tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
853 (void) tmpreg;
854 }
855
856 /**
857 * @brief Clear overrun error flag
858 * @note Clearing this flag is done by a read access to the SPIx_DR
859 * register followed by a read access to the SPIx_SR register
860 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
861 * @param SPIx SPI Instance
862 * @retval None
863 */
864 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
865 {
866 __IO uint32_t tmpreg;
867 tmpreg = SPIx->DR;
868 (void) tmpreg;
869 tmpreg = SPIx->SR;
870 (void) tmpreg;
871 }
872
873 /**
874 * @brief Clear frame format error flag
875 * @note Clearing this flag is done by reading SPIx_SR register
876 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
877 * @param SPIx SPI Instance
878 * @retval None
879 */
880 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
881 {
882 __IO uint32_t tmpreg;
883 tmpreg = SPIx->SR;
884 (void) tmpreg;
885 }
886
887 /**
888 * @}
889 */
890
891 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
892 * @{
893 */
894
895 /**
896 * @brief Enable error interrupt
897 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
898 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
899 * @param SPIx SPI Instance
900 * @retval None
901 */
902 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
903 {
904 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
905 }
906
907 /**
908 * @brief Enable Rx buffer not empty interrupt
909 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
910 * @param SPIx SPI Instance
911 * @retval None
912 */
913 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
914 {
915 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
916 }
917
918 /**
919 * @brief Enable Tx buffer empty interrupt
920 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
921 * @param SPIx SPI Instance
922 * @retval None
923 */
924 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
925 {
926 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
927 }
928
929 /**
930 * @brief Disable error interrupt
931 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
932 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
933 * @param SPIx SPI Instance
934 * @retval None
935 */
936 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
937 {
938 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
939 }
940
941 /**
942 * @brief Disable Rx buffer not empty interrupt
943 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
944 * @param SPIx SPI Instance
945 * @retval None
946 */
947 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
948 {
949 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
950 }
951
952 /**
953 * @brief Disable Tx buffer empty interrupt
954 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
955 * @param SPIx SPI Instance
956 * @retval None
957 */
958 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
959 {
960 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
961 }
962
963 /**
964 * @brief Check if error interrupt is enabled
965 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
966 * @param SPIx SPI Instance
967 * @retval State of bit (1 or 0).
968 */
969 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
970 {
971 return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
972 }
973
974 /**
975 * @brief Check if Rx buffer not empty interrupt is enabled
976 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
977 * @param SPIx SPI Instance
978 * @retval State of bit (1 or 0).
979 */
980 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
981 {
982 return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
983 }
984
985 /**
986 * @brief Check if Tx buffer empty interrupt
987 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
988 * @param SPIx SPI Instance
989 * @retval State of bit (1 or 0).
990 */
991 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
992 {
993 return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
994 }
995
996 /**
997 * @}
998 */
999
1000 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
1001 * @{
1002 */
1003
1004 /**
1005 * @brief Enable DMA Rx
1006 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
1007 * @param SPIx SPI Instance
1008 * @retval None
1009 */
1010 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
1011 {
1012 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
1013 }
1014
1015 /**
1016 * @brief Disable DMA Rx
1017 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
1018 * @param SPIx SPI Instance
1019 * @retval None
1020 */
1021 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1022 {
1023 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
1024 }
1025
1026 /**
1027 * @brief Check if DMA Rx is enabled
1028 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
1029 * @param SPIx SPI Instance
1030 * @retval State of bit (1 or 0).
1031 */
1032 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
1033 {
1034 return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
1035 }
1036
1037 /**
1038 * @brief Enable DMA Tx
1039 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
1040 * @param SPIx SPI Instance
1041 * @retval None
1042 */
1043 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1044 {
1045 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1046 }
1047
1048 /**
1049 * @brief Disable DMA Tx
1050 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
1051 * @param SPIx SPI Instance
1052 * @retval None
1053 */
1054 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1055 {
1056 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1057 }
1058
1059 /**
1060 * @brief Check if DMA Tx is enabled
1061 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
1062 * @param SPIx SPI Instance
1063 * @retval State of bit (1 or 0).
1064 */
1065 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
1066 {
1067 return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
1068 }
1069
1070 /**
1071 * @brief Get the data register address used for DMA transfer
1072 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
1073 * @param SPIx SPI Instance
1074 * @retval Address of data register
1075 */
1076 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
1077 {
1078 return (uint32_t) & (SPIx->DR);
1079 }
1080
1081 /**
1082 * @}
1083 */
1084
1085 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
1086 * @{
1087 */
1088
1089 /**
1090 * @brief Read 8-Bits in the data register
1091 * @rmtoll DR DR LL_SPI_ReceiveData8
1092 * @param SPIx SPI Instance
1093 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
1094 */
1095 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
1096 {
1097 return (uint8_t)(READ_REG(SPIx->DR));
1098 }
1099
1100 /**
1101 * @brief Read 16-Bits in the data register
1102 * @rmtoll DR DR LL_SPI_ReceiveData16
1103 * @param SPIx SPI Instance
1104 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1105 */
1106 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
1107 {
1108 return (uint16_t)(READ_REG(SPIx->DR));
1109 }
1110
1111 /**
1112 * @brief Write 8-Bits in the data register
1113 * @rmtoll DR DR LL_SPI_TransmitData8
1114 * @param SPIx SPI Instance
1115 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
1116 * @retval None
1117 */
1118 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
1119 {
1120 SPIx->DR = TxData;
1121 }
1122
1123 /**
1124 * @brief Write 16-Bits in the data register
1125 * @rmtoll DR DR LL_SPI_TransmitData16
1126 * @param SPIx SPI Instance
1127 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1128 * @retval None
1129 */
1130 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1131 {
1132 SPIx->DR = TxData;
1133 }
1134
1135 /**
1136 * @}
1137 */
1138 #if defined(USE_FULL_LL_DRIVER)
1139 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
1140 * @{
1141 */
1142
1143 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
1144 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
1145 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
1146
1147 /**
1148 * @}
1149 */
1150 #endif /* USE_FULL_LL_DRIVER */
1151 /**
1152 * @}
1153 */
1154
1155 /**
1156 * @}
1157 */
1158
1159 /** @defgroup I2S_LL I2S
1160 * @{
1161 */
1162
1163 /* Private variables ---------------------------------------------------------*/
1164 /* Private constants ---------------------------------------------------------*/
1165 /* Private macros ------------------------------------------------------------*/
1166
1167 /* Exported types ------------------------------------------------------------*/
1168 #if defined(USE_FULL_LL_DRIVER)
1169 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
1170 * @{
1171 */
1172
1173 /**
1174 * @brief I2S Init structure definition
1175 */
1176
1177 typedef struct
1178 {
1179 uint32_t Mode; /*!< Specifies the I2S operating mode.
1180 This parameter can be a value of @ref I2S_LL_EC_MODE
1181
1182 This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
1183
1184 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
1185 This parameter can be a value of @ref I2S_LL_EC_STANDARD
1186
1187 This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
1188
1189
1190 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
1191 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
1192
1193 This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
1194
1195
1196 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
1197 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
1198
1199 This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
1200
1201
1202 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
1203 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
1204
1205 Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
1206 and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
1207
1208
1209 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
1210 This parameter can be a value of @ref I2S_LL_EC_POLARITY
1211
1212 This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
1213
1214 } LL_I2S_InitTypeDef;
1215
1216 /**
1217 * @}
1218 */
1219 #endif /*USE_FULL_LL_DRIVER*/
1220
1221 /* Exported constants --------------------------------------------------------*/
1222 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
1223 * @{
1224 */
1225
1226 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
1227 * @brief Flags defines which can be used with LL_I2S_ReadReg function
1228 * @{
1229 */
1230 #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
1231 #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
1232 #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
1233 #define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
1234 #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
1235 #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
1236 /**
1237 * @}
1238 */
1239
1240 /** @defgroup SPI_LL_EC_IT IT Defines
1241 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
1242 * @{
1243 */
1244 #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
1245 #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
1246 #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
1247 /**
1248 * @}
1249 */
1250
1251 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
1252 * @{
1253 */
1254 #define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
1255 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
1256 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
1257 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
1258 /**
1259 * @}
1260 */
1261
1262 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
1263 * @{
1264 */
1265 #define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
1266 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
1267 /**
1268 * @}
1269 */
1270
1271 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
1272 * @{
1273 */
1274 #define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
1275 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
1276 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
1277 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
1278 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
1279 /**
1280 * @}
1281 */
1282
1283 /** @defgroup I2S_LL_EC_MODE Operation Mode
1284 * @{
1285 */
1286 #define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
1287 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
1288 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
1289 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
1290 /**
1291 * @}
1292 */
1293
1294 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
1295 * @{
1296 */
1297 #define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
1298 #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
1299 /**
1300 * @}
1301 */
1302
1303 #if defined(USE_FULL_LL_DRIVER)
1304
1305 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
1306 * @{
1307 */
1308 #define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
1309 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
1310 /**
1311 * @}
1312 */
1313
1314 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
1315 * @{
1316 */
1317
1318 #define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
1319 #define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
1320 #define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
1321 #define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
1322 #define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
1323 #define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
1324 #define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
1325 #define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
1326 #define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
1327 #define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
1328 /**
1329 * @}
1330 */
1331 #endif /* USE_FULL_LL_DRIVER */
1332
1333 /**
1334 * @}
1335 */
1336
1337 /* Exported macro ------------------------------------------------------------*/
1338 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
1339 * @{
1340 */
1341
1342 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
1343 * @{
1344 */
1345
1346 /**
1347 * @brief Write a value in I2S register
1348 * @param __INSTANCE__ I2S Instance
1349 * @param __REG__ Register to be written
1350 * @param __VALUE__ Value to be written in the register
1351 * @retval None
1352 */
1353 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1354
1355 /**
1356 * @brief Read a value in I2S register
1357 * @param __INSTANCE__ I2S Instance
1358 * @param __REG__ Register to be read
1359 * @retval Register value
1360 */
1361 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1362 /**
1363 * @}
1364 */
1365
1366 /**
1367 * @}
1368 */
1369
1370
1371 /* Exported functions --------------------------------------------------------*/
1372
1373 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
1374 * @{
1375 */
1376
1377 /** @defgroup I2S_LL_EF_Configuration Configuration
1378 * @{
1379 */
1380
1381 /**
1382 * @brief Select I2S mode and Enable I2S peripheral
1383 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
1384 * I2SCFGR I2SE LL_I2S_Enable
1385 * @param SPIx SPI Instance
1386 * @retval None
1387 */
1388 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
1389 {
1390 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1391 }
1392
1393 /**
1394 * @brief Disable I2S peripheral
1395 * @rmtoll I2SCFGR I2SE LL_I2S_Disable
1396 * @param SPIx SPI Instance
1397 * @retval None
1398 */
1399 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
1400 {
1401 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1402 }
1403
1404 /**
1405 * @brief Check if I2S peripheral is enabled
1406 * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
1407 * @param SPIx SPI Instance
1408 * @retval State of bit (1 or 0).
1409 */
1410 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
1411 {
1412 return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
1413 }
1414
1415 /**
1416 * @brief Set I2S data frame length
1417 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
1418 * I2SCFGR CHLEN LL_I2S_SetDataFormat
1419 * @param SPIx SPI Instance
1420 * @param DataFormat This parameter can be one of the following values:
1421 * @arg @ref LL_I2S_DATAFORMAT_16B
1422 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1423 * @arg @ref LL_I2S_DATAFORMAT_24B
1424 * @arg @ref LL_I2S_DATAFORMAT_32B
1425 * @retval None
1426 */
1427 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
1428 {
1429 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
1430 }
1431
1432 /**
1433 * @brief Get I2S data frame length
1434 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
1435 * I2SCFGR CHLEN LL_I2S_GetDataFormat
1436 * @param SPIx SPI Instance
1437 * @retval Returned value can be one of the following values:
1438 * @arg @ref LL_I2S_DATAFORMAT_16B
1439 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1440 * @arg @ref LL_I2S_DATAFORMAT_24B
1441 * @arg @ref LL_I2S_DATAFORMAT_32B
1442 */
1443 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
1444 {
1445 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
1446 }
1447
1448 /**
1449 * @brief Set I2S clock polarity
1450 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
1451 * @param SPIx SPI Instance
1452 * @param ClockPolarity This parameter can be one of the following values:
1453 * @arg @ref LL_I2S_POLARITY_LOW
1454 * @arg @ref LL_I2S_POLARITY_HIGH
1455 * @retval None
1456 */
1457 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1458 {
1459 SET_BIT(SPIx->I2SCFGR, ClockPolarity);
1460 }
1461
1462 /**
1463 * @brief Get I2S clock polarity
1464 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
1465 * @param SPIx SPI Instance
1466 * @retval Returned value can be one of the following values:
1467 * @arg @ref LL_I2S_POLARITY_LOW
1468 * @arg @ref LL_I2S_POLARITY_HIGH
1469 */
1470 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
1471 {
1472 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
1473 }
1474
1475 /**
1476 * @brief Set I2S standard protocol
1477 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
1478 * I2SCFGR PCMSYNC LL_I2S_SetStandard
1479 * @param SPIx SPI Instance
1480 * @param Standard This parameter can be one of the following values:
1481 * @arg @ref LL_I2S_STANDARD_PHILIPS
1482 * @arg @ref LL_I2S_STANDARD_MSB
1483 * @arg @ref LL_I2S_STANDARD_LSB
1484 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1485 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1486 * @retval None
1487 */
1488 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1489 {
1490 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
1491 }
1492
1493 /**
1494 * @brief Get I2S standard protocol
1495 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
1496 * I2SCFGR PCMSYNC LL_I2S_GetStandard
1497 * @param SPIx SPI Instance
1498 * @retval Returned value can be one of the following values:
1499 * @arg @ref LL_I2S_STANDARD_PHILIPS
1500 * @arg @ref LL_I2S_STANDARD_MSB
1501 * @arg @ref LL_I2S_STANDARD_LSB
1502 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1503 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1504 */
1505 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
1506 {
1507 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
1508 }
1509
1510 /**
1511 * @brief Set I2S transfer mode
1512 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
1513 * @param SPIx SPI Instance
1514 * @param Mode This parameter can be one of the following values:
1515 * @arg @ref LL_I2S_MODE_SLAVE_TX
1516 * @arg @ref LL_I2S_MODE_SLAVE_RX
1517 * @arg @ref LL_I2S_MODE_MASTER_TX
1518 * @arg @ref LL_I2S_MODE_MASTER_RX
1519 * @retval None
1520 */
1521 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
1522 {
1523 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
1524 }
1525
1526 /**
1527 * @brief Get I2S transfer mode
1528 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
1529 * @param SPIx SPI Instance
1530 * @retval Returned value can be one of the following values:
1531 * @arg @ref LL_I2S_MODE_SLAVE_TX
1532 * @arg @ref LL_I2S_MODE_SLAVE_RX
1533 * @arg @ref LL_I2S_MODE_MASTER_TX
1534 * @arg @ref LL_I2S_MODE_MASTER_RX
1535 */
1536 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
1537 {
1538 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
1539 }
1540
1541 /**
1542 * @brief Set I2S linear prescaler
1543 * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
1544 * @param SPIx SPI Instance
1545 * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1546 * @retval None
1547 */
1548 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
1549 {
1550 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
1551 }
1552
1553 /**
1554 * @brief Get I2S linear prescaler
1555 * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
1556 * @param SPIx SPI Instance
1557 * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1558 */
1559 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
1560 {
1561 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
1562 }
1563
1564 /**
1565 * @brief Set I2S parity prescaler
1566 * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
1567 * @param SPIx SPI Instance
1568 * @param PrescalerParity This parameter can be one of the following values:
1569 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1570 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1571 * @retval None
1572 */
1573 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
1574 {
1575 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
1576 }
1577
1578 /**
1579 * @brief Get I2S parity prescaler
1580 * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
1581 * @param SPIx SPI Instance
1582 * @retval Returned value can be one of the following values:
1583 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1584 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1585 */
1586 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
1587 {
1588 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
1589 }
1590
1591 /**
1592 * @brief Enable the master clock ouput (Pin MCK)
1593 * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
1594 * @param SPIx SPI Instance
1595 * @retval None
1596 */
1597 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
1598 {
1599 SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1600 }
1601
1602 /**
1603 * @brief Disable the master clock ouput (Pin MCK)
1604 * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
1605 * @param SPIx SPI Instance
1606 * @retval None
1607 */
1608 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
1609 {
1610 CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1611 }
1612
1613 /**
1614 * @brief Check if the master clock ouput (Pin MCK) is enabled
1615 * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
1616 * @param SPIx SPI Instance
1617 * @retval State of bit (1 or 0).
1618 */
1619 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
1620 {
1621 return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
1622 }
1623
1624 #if defined(SPI_I2SCFGR_ASTRTEN)
1625 /**
1626 * @brief Enable asynchronous start
1627 * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
1628 * @param SPIx SPI Instance
1629 * @retval None
1630 */
1631 __STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
1632 {
1633 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
1634 }
1635
1636 /**
1637 * @brief Disable asynchronous start
1638 * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
1639 * @param SPIx SPI Instance
1640 * @retval None
1641 */
1642 __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
1643 {
1644 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
1645 }
1646
1647 /**
1648 * @brief Check if asynchronous start is enabled
1649 * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
1650 * @param SPIx SPI Instance
1651 * @retval State of bit (1 or 0).
1652 */
1653 __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
1654 {
1655 return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
1656 }
1657 #endif /* SPI_I2SCFGR_ASTRTEN */
1658
1659 /**
1660 * @}
1661 */
1662
1663 /** @defgroup I2S_LL_EF_FLAG FLAG Management
1664 * @{
1665 */
1666
1667 /**
1668 * @brief Check if Rx buffer is not empty
1669 * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
1670 * @param SPIx SPI Instance
1671 * @retval State of bit (1 or 0).
1672 */
1673 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
1674 {
1675 return LL_SPI_IsActiveFlag_RXNE(SPIx);
1676 }
1677
1678 /**
1679 * @brief Check if Tx buffer is empty
1680 * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
1681 * @param SPIx SPI Instance
1682 * @retval State of bit (1 or 0).
1683 */
1684 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
1685 {
1686 return LL_SPI_IsActiveFlag_TXE(SPIx);
1687 }
1688
1689 /**
1690 * @brief Get busy flag
1691 * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
1692 * @param SPIx SPI Instance
1693 * @retval State of bit (1 or 0).
1694 */
1695 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
1696 {
1697 return LL_SPI_IsActiveFlag_BSY(SPIx);
1698 }
1699
1700 /**
1701 * @brief Get overrun error flag
1702 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
1703 * @param SPIx SPI Instance
1704 * @retval State of bit (1 or 0).
1705 */
1706 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
1707 {
1708 return LL_SPI_IsActiveFlag_OVR(SPIx);
1709 }
1710
1711 /**
1712 * @brief Get underrun error flag
1713 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
1714 * @param SPIx SPI Instance
1715 * @retval State of bit (1 or 0).
1716 */
1717 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
1718 {
1719 return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
1720 }
1721
1722 /**
1723 * @brief Get frame format error flag
1724 * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
1725 * @param SPIx SPI Instance
1726 * @retval State of bit (1 or 0).
1727 */
1728 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
1729 {
1730 return LL_SPI_IsActiveFlag_FRE(SPIx);
1731 }
1732
1733 /**
1734 * @brief Get channel side flag.
1735 * @note 0: Channel Left has to be transmitted or has been received\n
1736 * 1: Channel Right has to be transmitted or has been received\n
1737 * It has no significance in PCM mode.
1738 * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
1739 * @param SPIx SPI Instance
1740 * @retval State of bit (1 or 0).
1741 */
1742 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
1743 {
1744 return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
1745 }
1746
1747 /**
1748 * @brief Clear overrun error flag
1749 * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
1750 * @param SPIx SPI Instance
1751 * @retval None
1752 */
1753 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
1754 {
1755 LL_SPI_ClearFlag_OVR(SPIx);
1756 }
1757
1758 /**
1759 * @brief Clear underrun error flag
1760 * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
1761 * @param SPIx SPI Instance
1762 * @retval None
1763 */
1764 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
1765 {
1766 __IO uint32_t tmpreg;
1767 tmpreg = SPIx->SR;
1768 (void)tmpreg;
1769 }
1770
1771 /**
1772 * @brief Clear frame format error flag
1773 * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
1774 * @param SPIx SPI Instance
1775 * @retval None
1776 */
1777 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
1778 {
1779 LL_SPI_ClearFlag_FRE(SPIx);
1780 }
1781
1782 /**
1783 * @}
1784 */
1785
1786 /** @defgroup I2S_LL_EF_IT Interrupt Management
1787 * @{
1788 */
1789
1790 /**
1791 * @brief Enable error IT
1792 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
1793 * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
1794 * @param SPIx SPI Instance
1795 * @retval None
1796 */
1797 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
1798 {
1799 LL_SPI_EnableIT_ERR(SPIx);
1800 }
1801
1802 /**
1803 * @brief Enable Rx buffer not empty IT
1804 * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
1805 * @param SPIx SPI Instance
1806 * @retval None
1807 */
1808 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
1809 {
1810 LL_SPI_EnableIT_RXNE(SPIx);
1811 }
1812
1813 /**
1814 * @brief Enable Tx buffer empty IT
1815 * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
1816 * @param SPIx SPI Instance
1817 * @retval None
1818 */
1819 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
1820 {
1821 LL_SPI_EnableIT_TXE(SPIx);
1822 }
1823
1824 /**
1825 * @brief Disable error IT
1826 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
1827 * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
1828 * @param SPIx SPI Instance
1829 * @retval None
1830 */
1831 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
1832 {
1833 LL_SPI_DisableIT_ERR(SPIx);
1834 }
1835
1836 /**
1837 * @brief Disable Rx buffer not empty IT
1838 * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
1839 * @param SPIx SPI Instance
1840 * @retval None
1841 */
1842 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
1843 {
1844 LL_SPI_DisableIT_RXNE(SPIx);
1845 }
1846
1847 /**
1848 * @brief Disable Tx buffer empty IT
1849 * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
1850 * @param SPIx SPI Instance
1851 * @retval None
1852 */
1853 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
1854 {
1855 LL_SPI_DisableIT_TXE(SPIx);
1856 }
1857
1858 /**
1859 * @brief Check if ERR IT is enabled
1860 * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
1861 * @param SPIx SPI Instance
1862 * @retval State of bit (1 or 0).
1863 */
1864 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
1865 {
1866 return LL_SPI_IsEnabledIT_ERR(SPIx);
1867 }
1868
1869 /**
1870 * @brief Check if RXNE IT is enabled
1871 * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
1872 * @param SPIx SPI Instance
1873 * @retval State of bit (1 or 0).
1874 */
1875 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
1876 {
1877 return LL_SPI_IsEnabledIT_RXNE(SPIx);
1878 }
1879
1880 /**
1881 * @brief Check if TXE IT is enabled
1882 * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
1883 * @param SPIx SPI Instance
1884 * @retval State of bit (1 or 0).
1885 */
1886 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
1887 {
1888 return LL_SPI_IsEnabledIT_TXE(SPIx);
1889 }
1890
1891 /**
1892 * @}
1893 */
1894
1895 /** @defgroup I2S_LL_EF_DMA DMA Management
1896 * @{
1897 */
1898
1899 /**
1900 * @brief Enable DMA Rx
1901 * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
1902 * @param SPIx SPI Instance
1903 * @retval None
1904 */
1905 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
1906 {
1907 LL_SPI_EnableDMAReq_RX(SPIx);
1908 }
1909
1910 /**
1911 * @brief Disable DMA Rx
1912 * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
1913 * @param SPIx SPI Instance
1914 * @retval None
1915 */
1916 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1917 {
1918 LL_SPI_DisableDMAReq_RX(SPIx);
1919 }
1920
1921 /**
1922 * @brief Check if DMA Rx is enabled
1923 * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
1924 * @param SPIx SPI Instance
1925 * @retval State of bit (1 or 0).
1926 */
1927 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
1928 {
1929 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
1930 }
1931
1932 /**
1933 * @brief Enable DMA Tx
1934 * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
1935 * @param SPIx SPI Instance
1936 * @retval None
1937 */
1938 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1939 {
1940 LL_SPI_EnableDMAReq_TX(SPIx);
1941 }
1942
1943 /**
1944 * @brief Disable DMA Tx
1945 * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
1946 * @param SPIx SPI Instance
1947 * @retval None
1948 */
1949 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1950 {
1951 LL_SPI_DisableDMAReq_TX(SPIx);
1952 }
1953
1954 /**
1955 * @brief Check if DMA Tx is enabled
1956 * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
1957 * @param SPIx SPI Instance
1958 * @retval State of bit (1 or 0).
1959 */
1960 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
1961 {
1962 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
1963 }
1964
1965 /**
1966 * @}
1967 */
1968
1969 /** @defgroup I2S_LL_EF_DATA DATA Management
1970 * @{
1971 */
1972
1973 /**
1974 * @brief Read 16-Bits in data register
1975 * @rmtoll DR DR LL_I2S_ReceiveData16
1976 * @param SPIx SPI Instance
1977 * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
1978 */
1979 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
1980 {
1981 return LL_SPI_ReceiveData16(SPIx);
1982 }
1983
1984 /**
1985 * @brief Write 16-Bits in data register
1986 * @rmtoll DR DR LL_I2S_TransmitData16
1987 * @param SPIx SPI Instance
1988 * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
1989 * @retval None
1990 */
1991 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1992 {
1993 LL_SPI_TransmitData16(SPIx, TxData);
1994 }
1995
1996 /**
1997 * @}
1998 */
1999
2000 #if defined(USE_FULL_LL_DRIVER)
2001 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
2002 * @{
2003 */
2004
2005 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
2006 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
2007 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
2008 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
2009 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
2010 ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct);
2011 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
2012
2013 /**
2014 * @}
2015 */
2016 #endif /* USE_FULL_LL_DRIVER */
2017
2018 /**
2019 * @}
2020 */
2021
2022 /**
2023 * @}
2024 */
2025
2026 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */
2027
2028 /**
2029 * @}
2030 */
2031
2032 #ifdef __cplusplus
2033 }
2034 #endif
2035
2036 #endif /* __STM32F4xx_LL_SPI_H */
2037
2038 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/