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Merge pull request #11198 from SteveCEvans/sce_rc2
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_HAL_Driver / Src / stm32f4xx_hal_dma2d.c
bloba55c463675fe71ed610a9a6641298184d528b785
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_dma2d.c
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 14-April-2017
7 * @brief DMA2D HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the DMA2D peripheral:
10 * + Initialization and de-initialization functions
11 * + IO operation functions
12 * + Peripheral Control functions
13 * + Peripheral State and Errors functions
14 *
15 @verbatim
16 ==============================================================================
17 ##### How to use this driver #####
18 ==============================================================================
19 [..]
20 (#) Program the required configuration through the following parameters:
21 the transfer mode, the output color mode and the output offset using
22 HAL_DMA2D_Init() function.
23
24 (#) Program the required configuration through the following parameters:
25 the input color mode, the input color, the input alpha value, the alpha mode,
26 and the input offset using HAL_DMA2D_ConfigLayer() function for foreground
27 or/and background layer.
28
29 *** Polling mode IO operation ***
30 =================================
31 [..]
32 (#) Configure pdata parameter (explained hereafter), destination and data length
33 and enable the transfer using HAL_DMA2D_Start().
34 (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
35 user can specify the value of timeout according to his end application.
36
37 *** Interrupt mode IO operation ***
38 ===================================
39 [..]
40 (#) Configure pdata parameter, destination and data length and enable
41 the transfer using HAL_DMA2D_Start_IT().
42 (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine
43 (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
44 add his own function by customization of function pointer XferCpltCallback (member
45 of DMA2D handle structure).
46 (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback
47 XferErrorCallback.
48
49 -@- In Register-to-Memory transfer mode, pdata parameter is the register
50 color, in Memory-to-memory or Memory-to-Memory with pixel format
51 conversion pdata is the source address.
52
53 -@- Configure the foreground source address, the background source address,
54 the destination and data length then Enable the transfer using
55 HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
56 in interrupt mode
57
58 -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
59 are used if the memory to memory with blending transfer mode is selected.
60
61 (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
62 mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
63
64 (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()
65
66 (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
67 consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
68 and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
69 HAL_DMA2D_DisableDeadTime().
70
71 (#) The transfer can be suspended, resumed and aborted using the following
72 functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
73
74 (#) The CLUT loading can be suspended, resumed and aborted using the following
75 functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
76 HAL_DMA2D_CLUTLoading_Abort().
77
78 (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
79
80 (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
81
82 *** DMA2D HAL driver macros list ***
83 =============================================
84 [..]
85 Below the list of most used macros in DMA2D HAL driver :
86
87 (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
88 (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
89 (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
90 (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
91 (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
92 (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not
93
94 [..]
95 (@) You can refer to the DMA2D HAL driver header file for more useful macros
96
97 @endverbatim
98 ******************************************************************************
99 * @attention
100 *
101 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
102 *
103 * Redistribution and use in source and binary forms, with or without modification,
104 * are permitted provided that the following conditions are met:
105 * 1. Redistributions of source code must retain the above copyright notice,
106 * this list of conditions and the following disclaimer.
107 * 2. Redistributions in binary form must reproduce the above copyright notice,
108 * this list of conditions and the following disclaimer in the documentation
109 * and/or other materials provided with the distribution.
110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
111 * may be used to endorse or promote products derived from this software
112 * without specific prior written permission.
113 *
114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
124 *
125 ******************************************************************************
126 */
127
128 /* Includes ------------------------------------------------------------------*/
129 #include "stm32f4xx_hal.h"
130
131 /** @addtogroup STM32F4xx_HAL_Driver
132 * @{
133 */
134
135 /** @defgroup DMA2D DMA2D
136 * @brief DMA2D HAL module driver
137 * @{
138 */
139
140 #ifdef HAL_DMA2D_MODULE_ENABLED
141
142 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
143
144 /* Private types -------------------------------------------------------------*/
145 /* Private define ------------------------------------------------------------*/
146 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
147 * @{
148 */
149
150 /** @defgroup DMA2D_TimeOut DMA2D Time Out
151 * @{
152 */
153 #define DMA2D_TIMEOUT_ABORT 1000U /*!< 1s */
154 #define DMA2D_TIMEOUT_SUSPEND 1000U /*!< 1s */
155 /**
156 * @}
157 */
158
159 /** @defgroup DMA2D_Shifts DMA2D Shifts
160 * @{
161 */
162 #define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /*!< Required left shift to set foreground CLUT size */
163 #define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /*!< Required left shift to set background CLUT size */
164
165 #define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /*!< Required left shift to set foreground CLUT color mode */
166 #define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /*!< Required left shift to set background CLUT color mode */
167
168 #define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /*!< Required left shift to set deadtime value */
169
170 #define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /*!< Required left shift to set foreground alpha mode */
171 #define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /*!< Required left shift to set background alpha mode */
172
173 #define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */
174 #define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */
175
176 #define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /*!< Required left shift to set pixels per lines value */
177 /**
178 * @}
179 */
180
181 /**
182 * @}
183 */
184
185 /* Private variables ---------------------------------------------------------*/
186 /* Private constants ---------------------------------------------------------*/
187 /* Private macro -------------------------------------------------------------*/
188 /* Private function prototypes -----------------------------------------------*/
189 /** @addtogroup DMA2D_Private_Functions_Prototypes
190 * @{
191 */
192 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
193 /**
194 * @}
195 */
196
197 /* Private functions ---------------------------------------------------------*/
198 /* Exported functions --------------------------------------------------------*/
199 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
200 * @{
201 */
202
203 /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
204 * @brief Initialization and Configuration functions
205 *
206 @verbatim
207 ===============================================================================
208 ##### Initialization and Configuration functions #####
209 ===============================================================================
210 [..] This section provides functions allowing to:
211 (+) Initialize and configure the DMA2D
212 (+) De-initialize the DMA2D
213
214 @endverbatim
215 * @{
216 */
217
218 /**
219 * @brief Initialize the DMA2D according to the specified
220 * parameters in the DMA2D_InitTypeDef and create the associated handle.
221 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
222 * the configuration information for the DMA2D.
223 * @retval HAL status
224 */
225 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
226 {
227 /* Check the DMA2D peripheral state */
228 if(hdma2d == NULL)
229 {
230 return HAL_ERROR;
231 }
232
233 /* Check the parameters */
234 assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
235 assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
236 assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
237 assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
238
239 if(hdma2d->State == HAL_DMA2D_STATE_RESET)
240 {
241 /* Allocate lock resource and initialize it */
242 hdma2d->Lock = HAL_UNLOCKED;
243 /* Init the low level hardware */
244 HAL_DMA2D_MspInit(hdma2d);
245 }
246
247 /* Change DMA2D peripheral state */
248 hdma2d->State = HAL_DMA2D_STATE_BUSY;
249
250 /* DMA2D CR register configuration -------------------------------------------*/
251 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
252
253 /* DMA2D OPFCCR register configuration ---------------------------------------*/
254 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
255
256 /* DMA2D OOR register configuration ------------------------------------------*/
257 MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
258
259 /* Update error code */
260 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
261
262 /* Initialize the DMA2D state*/
263 hdma2d->State = HAL_DMA2D_STATE_READY;
264
265 return HAL_OK;
266 }
267
268 /**
269 * @brief Deinitializes the DMA2D peripheral registers to their default reset
270 * values.
271 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
272 * the configuration information for the DMA2D.
273 * @retval None
274 */
275
276 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
277 {
278 /* Check the DMA2D peripheral state */
279 if(hdma2d == NULL)
280 {
281 return HAL_ERROR;
282 }
283
284 /* Before aborting any DMA2D transfer or CLUT loading, check
285 first whether or not DMA2D clock is enabled */
286 if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
287 {
288 /* Abort DMA2D transfer if any */
289 if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
290 {
291 if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
292 {
293 /* Issue when aborting DMA2D transfer */
294 return HAL_ERROR;
295 }
296 }
297 else
298 {
299 /* Abort background CLUT loading if any */
300 if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
301 {
302 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
303 {
304 /* Issue when aborting background CLUT loading */
305 return HAL_ERROR;
306 }
307 }
308 else
309 {
310 /* Abort foreground CLUT loading if any */
311 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
312 {
313 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
314 {
315 /* Issue when aborting foreground CLUT loading */
316 return HAL_ERROR;
317 }
318 }
319 }
320 }
321 }
322
323 /* Carry on with de-initialization of low level hardware */
324 HAL_DMA2D_MspDeInit(hdma2d);
325
326 /* Reset DMA2D control registers*/
327 hdma2d->Instance->CR = 0U;
328 hdma2d->Instance->FGOR = 0U;
329 hdma2d->Instance->BGOR = 0U;
330 hdma2d->Instance->FGPFCCR = 0U;
331 hdma2d->Instance->BGPFCCR = 0U;
332 hdma2d->Instance->OPFCCR = 0U;
333
334 /* Update error code */
335 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
336
337 /* Initialize the DMA2D state*/
338 hdma2d->State = HAL_DMA2D_STATE_RESET;
339
340 /* Release Lock */
341 __HAL_UNLOCK(hdma2d);
342
343 return HAL_OK;
344 }
345
346 /**
347 * @brief Initializes the DMA2D MSP.
348 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
349 * the configuration information for the DMA2D.
350 * @retval None
351 */
352 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
353 {
354 /* Prevent unused argument(s) compilation warning */
355 UNUSED(hdma2d);
356
357 /* NOTE : This function should not be modified; when the callback is needed,
358 the HAL_DMA2D_MspInit can be implemented in the user file.
359 */
360 }
361
362 /**
363 * @brief DeInitializes the DMA2D MSP.
364 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
365 * the configuration information for the DMA2D.
366 * @retval None
367 */
368 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
369 {
370 /* Prevent unused argument(s) compilation warning */
371 UNUSED(hdma2d);
372
373 /* NOTE : This function should not be modified; when the callback is needed,
374 the HAL_DMA2D_MspDeInit can be implemented in the user file.
375 */
376 }
377
378 /**
379 * @}
380 */
381
382 /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
383 * @brief IO operation functions
384 *
385 @verbatim
386 ===============================================================================
387 ##### IO operation functions #####
388 ===============================================================================
389 [..] This section provides functions allowing to:
390 (+) Configure the pdata, destination address and data size then
391 start the DMA2D transfer.
392 (+) Configure the source for foreground and background, destination address
393 and data size then start a MultiBuffer DMA2D transfer.
394 (+) Configure the pdata, destination address and data size then
395 start the DMA2D transfer with interrupt.
396 (+) Configure the source for foreground and background, destination address
397 and data size then start a MultiBuffer DMA2D transfer with interrupt.
398 (+) Abort DMA2D transfer.
399 (+) Suspend DMA2D transfer.
400 (+) Resume DMA2D transfer.
401 (+) Enable CLUT transfer.
402 (+) Configure CLUT loading then start transfer in polling mode.
403 (+) Configure CLUT loading then start transfer in interrupt mode.
404 (+) Abort DMA2D CLUT loading.
405 (+) Suspend DMA2D CLUT loading.
406 (+) Resume DMA2D CLUT loading.
407 (+) Poll for transfer complete.
408 (+) handle DMA2D interrupt request.
409 (+) Transfer watermark callback.
410 (+) CLUT Transfer Complete callback.
411
412 @endverbatim
413 * @{
414 */
415
416 /**
417 * @brief Start the DMA2D Transfer.
418 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
419 * the configuration information for the DMA2D.
420 * @param pdata: Configure the source memory Buffer address if
421 * Memory-to-Memory or Memory-to-Memory with pixel format
422 * conversion mode is selected, or configure
423 * the color value if Register-to-Memory mode is selected.
424 * @param DstAddress: The destination memory Buffer address.
425 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
426 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
427 * @retval HAL status
428 */
429 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
430 {
431 /* Check the parameters */
432 assert_param(IS_DMA2D_LINE(Height));
433 assert_param(IS_DMA2D_PIXEL(Width));
434
435 /* Process locked */
436 __HAL_LOCK(hdma2d);
437
438 /* Change DMA2D peripheral state */
439 hdma2d->State = HAL_DMA2D_STATE_BUSY;
440
441 /* Configure the source, destination address and the data size */
442 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
443
444 /* Enable the Peripheral */
445 __HAL_DMA2D_ENABLE(hdma2d);
446
447 return HAL_OK;
448 }
449
450 /**
451 * @brief Start the DMA2D Transfer with interrupt enabled.
452 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
453 * the configuration information for the DMA2D.
454 * @param pdata: Configure the source memory Buffer address if
455 * the Memory-to-Memory or Memory-to-Memory with pixel format
456 * conversion mode is selected, or configure
457 * the color value if Register-to-Memory mode is selected.
458 * @param DstAddress: The destination memory Buffer address.
459 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
460 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
461 * @retval HAL status
462 */
463 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
464 {
465 /* Check the parameters */
466 assert_param(IS_DMA2D_LINE(Height));
467 assert_param(IS_DMA2D_PIXEL(Width));
468
469 /* Process locked */
470 __HAL_LOCK(hdma2d);
471
472 /* Change DMA2D peripheral state */
473 hdma2d->State = HAL_DMA2D_STATE_BUSY;
474
475 /* Configure the source, destination address and the data size */
476 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
477
478 /* Enable the transfer complete, transfer error and configuration error interrupts */
479 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
480
481 /* Enable the Peripheral */
482 __HAL_DMA2D_ENABLE(hdma2d);
483
484 return HAL_OK;
485 }
486
487 /**
488 * @brief Start the multi-source DMA2D Transfer.
489 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
490 * the configuration information for the DMA2D.
491 * @param SrcAddress1: The source memory Buffer address for the foreground layer.
492 * @param SrcAddress2: The source memory Buffer address for the background layer.
493 * @param DstAddress: The destination memory Buffer address.
494 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
495 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
496 * @retval HAL status
497 */
498 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
499 {
500 /* Check the parameters */
501 assert_param(IS_DMA2D_LINE(Height));
502 assert_param(IS_DMA2D_PIXEL(Width));
503
504 /* Process locked */
505 __HAL_LOCK(hdma2d);
506
507 /* Change DMA2D peripheral state */
508 hdma2d->State = HAL_DMA2D_STATE_BUSY;
509
510 /* Configure DMA2D Stream source2 address */
511 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
512
513 /* Configure the source, destination address and the data size */
514 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
515
516 /* Enable the Peripheral */
517 __HAL_DMA2D_ENABLE(hdma2d);
518
519 return HAL_OK;
520 }
521
522 /**
523 * @brief Start the multi-source DMA2D Transfer with interrupt enabled.
524 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
525 * the configuration information for the DMA2D.
526 * @param SrcAddress1: The source memory Buffer address for the foreground layer.
527 * @param SrcAddress2: The source memory Buffer address for the background layer.
528 * @param DstAddress: The destination memory Buffer address.
529 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
530 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
531 * @retval HAL status
532 */
533 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
534 {
535 /* Check the parameters */
536 assert_param(IS_DMA2D_LINE(Height));
537 assert_param(IS_DMA2D_PIXEL(Width));
538
539 /* Process locked */
540 __HAL_LOCK(hdma2d);
541
542 /* Change DMA2D peripheral state */
543 hdma2d->State = HAL_DMA2D_STATE_BUSY;
544
545 /* Configure DMA2D Stream source2 address */
546 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
547
548 /* Configure the source, destination address and the data size */
549 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
550
551 /* Enable the transfer complete, transfer error and configuration error interrupts */
552 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
553
554 /* Enable the Peripheral */
555 __HAL_DMA2D_ENABLE(hdma2d);
556
557 return HAL_OK;
558 }
559
560 /**
561 * @brief Abort the DMA2D Transfer.
562 * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
563 * the configuration information for the DMA2D.
564 * @retval HAL status
565 */
566 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
567 {
568 uint32_t tickstart = 0U;
569
570 /* Abort the DMA2D transfer */
571 /* START bit is reset to make sure not to set it again, in the event the HW clears it
572 between the register read and the register write by the CPU (writing 0 has no
573 effect on START bitvalue) */
574 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
575
576 /* Get tick */
577 tickstart = HAL_GetTick();
578
579 /* Check if the DMA2D is effectively disabled */
580 while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
581 {
582 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
583 {
584 /* Update error code */
585 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
586
587 /* Change the DMA2D state */
588 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
589
590 /* Process Unlocked */
591 __HAL_UNLOCK(hdma2d);
592
593 return HAL_TIMEOUT;
594 }
595 }
596
597 /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
598 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
599
600 /* Change the DMA2D state*/
601 hdma2d->State = HAL_DMA2D_STATE_READY;
602
603 /* Process Unlocked */
604 __HAL_UNLOCK(hdma2d);
605
606 return HAL_OK;
607 }
608
609 /**
610 * @brief Suspend the DMA2D Transfer.
611 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
612 * the configuration information for the DMA2D.
613 * @retval HAL status
614 */
615 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
616 {
617 uint32_t tickstart = 0U;
618
619 /* Suspend the DMA2D transfer */
620 /* START bit is reset to make sure not to set it again, in the event the HW clears it
621 between the register read and the register write by the CPU (writing 0 has no
622 effect on START bitvalue) */
623 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
624
625 /* Get tick */
626 tickstart = HAL_GetTick();
627
628 /* Check if the DMA2D is effectively suspended */
629 while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
630 && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
631 {
632 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
633 {
634 /* Update error code */
635 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
636
637 /* Change the DMA2D state */
638 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
639
640 return HAL_TIMEOUT;
641 }
642 }
643
644 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
645 if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
646 {
647 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
648 }
649 else
650 {
651 /* Make sure SUSP bit is cleared since it is meaningless
652 when no tranfer is on-going */
653 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
654 }
655
656 return HAL_OK;
657 }
658
659 /**
660 * @brief Resume the DMA2D Transfer.
661 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
662 * the configuration information for the DMA2D.
663 * @retval HAL status
664 */
665 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
666 {
667 /* Check the SUSP and START bits */
668 if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
669 {
670 /* Ongoing transfer is suspended: change the DMA2D state before resuming */
671 hdma2d->State = HAL_DMA2D_STATE_BUSY;
672 }
673
674 /* Resume the DMA2D transfer */
675 /* START bit is reset to make sure not to set it again, in the event the HW clears it
676 between the register read and the register write by the CPU (writing 0 has no
677 effect on START bitvalue) */
678 CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
679
680 return HAL_OK;
681 }
682
683 /**
684 * @brief Enable the DMA2D CLUT Transfer.
685 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
686 * the configuration information for the DMA2D.
687 * @param LayerIdx: DMA2D Layer index.
688 * This parameter can be one of the following values:
689 * 0(background) / 1(foreground)
690 * @retval HAL status
691 */
692 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
693 {
694 /* Check the parameters */
695 assert_param(IS_DMA2D_LAYER(LayerIdx));
696
697 /* Process locked */
698 __HAL_LOCK(hdma2d);
699
700 /* Change DMA2D peripheral state */
701 hdma2d->State = HAL_DMA2D_STATE_BUSY;
702
703 if(LayerIdx == 0U)
704 {
705 /* Enable the background CLUT loading */
706 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
707 }
708 else
709 {
710 /* Enable the foreground CLUT loading */
711 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
712 }
713
714 return HAL_OK;
715 }
716
717 /**
718 * @brief Start DMA2D CLUT Loading.
719 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
720 * the configuration information for the DMA2D.
721 * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
722 * the configuration information for the color look up table.
723 * @param LayerIdx: DMA2D Layer index.
724 * This parameter can be one of the following values:
725 * 0(background) / 1(foreground)
726 * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
727 * @retval HAL status
728 */
729 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
730 {
731 /* Check the parameters */
732 assert_param(IS_DMA2D_LAYER(LayerIdx));
733 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
734 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
735
736 /* Process locked */
737 __HAL_LOCK(hdma2d);
738
739 /* Change DMA2D peripheral state */
740 hdma2d->State = HAL_DMA2D_STATE_BUSY;
741
742 /* Configure the CLUT of the background DMA2D layer */
743 if(LayerIdx == 0U)
744 {
745 /* Write background CLUT memory address */
746 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
747
748 /* Write background CLUT size and CLUT color mode */
749 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
750 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
751
752 /* Enable the CLUT loading for the background */
753 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
754 }
755 /* Configure the CLUT of the foreground DMA2D layer */
756 else
757 {
758 /* Write foreground CLUT memory address */
759 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
760
761 /* Write foreground CLUT size and CLUT color mode */
762 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
763 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
764
765 /* Enable the CLUT loading for the foreground */
766 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
767 }
768
769 return HAL_OK;
770 }
771
772 /**
773 * @brief Start DMA2D CLUT Loading with interrupt enabled.
774 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
775 * the configuration information for the DMA2D.
776 * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
777 * the configuration information for the color look up table.
778 * @param LayerIdx: DMA2D Layer index.
779 * This parameter can be one of the following values:
780 * 0(background) / 1(foreground)
781 * @retval HAL status
782 */
783 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
784 {
785 /* Check the parameters */
786 assert_param(IS_DMA2D_LAYER(LayerIdx));
787 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
788 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
789
790 /* Process locked */
791 __HAL_LOCK(hdma2d);
792
793 /* Change DMA2D peripheral state */
794 hdma2d->State = HAL_DMA2D_STATE_BUSY;
795
796 /* Configure the CLUT of the background DMA2D layer */
797 if(LayerIdx == 0U)
798 {
799 /* Write background CLUT memory address */
800 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
801
802 /* Write background CLUT size and CLUT color mode */
803 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
804 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
805
806 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
807 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
808
809 /* Enable the CLUT loading for the background */
810 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
811 }
812 /* Configure the CLUT of the foreground DMA2D layer */
813 else
814 {
815 /* Write foreground CLUT memory address */
816 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
817
818 /* Write foreground CLUT size and CLUT color mode */
819 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
820 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
821
822 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
823 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
824
825 /* Enable the CLUT loading for the foreground */
826 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
827 }
828
829 return HAL_OK;
830 }
831
832 /**
833 * @brief Abort the DMA2D CLUT loading.
834 * @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains
835 * the configuration information for the DMA2D.
836 * @param LayerIdx: DMA2D Layer index.
837 * This parameter can be one of the following values:
838 * 0(background) / 1(foreground)
839 * @retval HAL status
840 */
841 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
842 {
843 uint32_t tickstart = 0U;
844 __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
845
846 /* Abort the CLUT loading */
847 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
848
849 /* If foreground CLUT loading is considered, update local variables */
850 if(LayerIdx == 1)
851 {
852 reg = &(hdma2d->Instance->FGPFCCR);
853 }
854
855 /* Get tick */
856 tickstart = HAL_GetTick();
857
858 /* Check if the CLUT loading is aborted */
859 while((*reg & DMA2D_BGPFCCR_START) != RESET)
860 {
861 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
862 {
863 /* Update error code */
864 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
865
866 /* Change the DMA2D state */
867 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
868
869 /* Process Unlocked */
870 __HAL_UNLOCK(hdma2d);
871
872 return HAL_TIMEOUT;
873 }
874 }
875
876 /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
877 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
878
879 /* Change the DMA2D state*/
880 hdma2d->State = HAL_DMA2D_STATE_READY;
881
882 /* Process Unlocked */
883 __HAL_UNLOCK(hdma2d);
884
885 return HAL_OK;
886 }
887
888 /**
889 * @brief Suspend the DMA2D CLUT loading.
890 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
891 * the configuration information for the DMA2D.
892 * @param LayerIdx: DMA2D Layer index.
893 * This parameter can be one of the following values:
894 * 0(background) / 1(foreground)
895 * @retval HAL status
896 */
897 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
898 {
899 uint32_t tickstart = 0U;
900 __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
901
902 /* Suspend the CLUT loading */
903 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
904
905 /* If foreground CLUT loading is considered, update local variables */
906 if(LayerIdx == 1U)
907 {
908 reg = &(hdma2d->Instance->FGPFCCR);
909 }
910
911 /* Get tick */
912 tickstart = HAL_GetTick();
913
914 /* Check if the CLUT loading is suspended */
915 while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
916 && ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
917 {
918 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
919 {
920 /* Update error code */
921 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
922
923 /* Change the DMA2D state */
924 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
925
926 return HAL_TIMEOUT;
927 }
928 }
929
930 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
931 if ((*reg & DMA2D_BGPFCCR_START) != RESET)
932 {
933 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
934 }
935 else
936 {
937 /* Make sure SUSP bit is cleared since it is meaningless
938 when no tranfer is on-going */
939 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
940 }
941
942 return HAL_OK;
943 }
944
945 /**
946 * @brief Resume the DMA2D CLUT loading.
947 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
948 * the configuration information for the DMA2D.
949 * @param LayerIdx: DMA2D Layer index.
950 * This parameter can be one of the following values:
951 * 0(background) / 1(foreground)
952 * @retval HAL status
953 */
954 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
955 {
956 /* Check the SUSP and START bits for background or foreground CLUT loading */
957 if(LayerIdx == 0U)
958 {
959 /* Background CLUT loading suspension check */
960 if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
961 && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
962 {
963 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
964 hdma2d->State = HAL_DMA2D_STATE_BUSY;
965 }
966 }
967 else
968 {
969 /* Foreground CLUT loading suspension check */
970 if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
971 && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))
972 {
973 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
974 hdma2d->State = HAL_DMA2D_STATE_BUSY;
975 }
976 }
977
978 /* Resume the CLUT loading */
979 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
980
981 return HAL_OK;
982 }
983
984 /**
985 * @brief Polling for transfer complete or CLUT loading.
986 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
987 * the configuration information for the DMA2D.
988 * @param Timeout: Timeout duration
989 * @retval HAL status
990 */
991 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
992 {
993 uint32_t tickstart = 0U;
994 __IO uint32_t isrflags = 0x0U;
995
996 /* Polling for DMA2D transfer */
997 if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
998 {
999 /* Get tick */
1000 tickstart = HAL_GetTick();
1001
1002 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
1003 {
1004 isrflags = READ_REG(hdma2d->Instance->ISR);
1005 if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
1006 {
1007 if ((isrflags & DMA2D_FLAG_CE) != RESET)
1008 {
1009 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1010 }
1011 if ((isrflags & DMA2D_FLAG_TE) != RESET)
1012 {
1013 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1014 }
1015 /* Clear the transfer and configuration error flags */
1016 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1017
1018 /* Change DMA2D state */
1019 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1020
1021 /* Process unlocked */
1022 __HAL_UNLOCK(hdma2d);
1023
1024 return HAL_ERROR;
1025 }
1026 /* Check for the Timeout */
1027 if(Timeout != HAL_MAX_DELAY)
1028 {
1029 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
1030 {
1031 /* Update error code */
1032 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1033
1034 /* Change the DMA2D state */
1035 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1036
1037 /* Process unlocked */
1038 __HAL_UNLOCK(hdma2d);
1039
1040 return HAL_TIMEOUT;
1041 }
1042 }
1043 }
1044 }
1045 /* Polling for CLUT loading (foreground or background) */
1046 if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) ||
1047 ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))
1048 {
1049 /* Get tick */
1050 tickstart = HAL_GetTick();
1051
1052 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
1053 {
1054 isrflags = READ_REG(hdma2d->Instance->ISR);
1055 if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
1056 {
1057 if ((isrflags & DMA2D_FLAG_CAE) != RESET)
1058 {
1059 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1060 }
1061 if ((isrflags & DMA2D_FLAG_CE) != RESET)
1062 {
1063 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1064 }
1065 if ((isrflags & DMA2D_FLAG_TE) != RESET)
1066 {
1067 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1068 }
1069 /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
1070 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1071
1072 /* Change DMA2D state */
1073 hdma2d->State= HAL_DMA2D_STATE_ERROR;
1074
1075 /* Process unlocked */
1076 __HAL_UNLOCK(hdma2d);
1077
1078 return HAL_ERROR;
1079 }
1080 /* Check for the Timeout */
1081 if(Timeout != HAL_MAX_DELAY)
1082 {
1083 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
1084 {
1085 /* Update error code */
1086 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1087
1088 /* Change the DMA2D state */
1089 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
1090
1091 /* Process unlocked */
1092 __HAL_UNLOCK(hdma2d);
1093
1094 return HAL_TIMEOUT;
1095 }
1096 }
1097 }
1098 }
1099
1100 /* Clear the transfer complete and CLUT loading flags */
1101 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
1102
1103 /* Change DMA2D state */
1104 hdma2d->State = HAL_DMA2D_STATE_READY;
1105
1106 /* Process unlocked */
1107 __HAL_UNLOCK(hdma2d);
1108
1109 return HAL_OK;
1110 }
1111 /**
1112 * @brief Handle DMA2D interrupt request.
1113 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
1114 * the configuration information for the DMA2D.
1115 * @retval HAL status
1116 */
1117 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
1118 {
1119 uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
1120 uint32_t crflags = READ_REG(hdma2d->Instance->CR);
1121
1122 /* Transfer Error Interrupt management ***************************************/
1123 if ((isrflags & DMA2D_FLAG_TE) != RESET)
1124 {
1125 if ((crflags & DMA2D_IT_TE) != RESET)
1126 {
1127 /* Disable the transfer Error interrupt */
1128 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
1129
1130 /* Update error code */
1131 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1132
1133 /* Clear the transfer error flag */
1134 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
1135
1136 /* Change DMA2D state */
1137 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1138
1139 /* Process Unlocked */
1140 __HAL_UNLOCK(hdma2d);
1141
1142 if(hdma2d->XferErrorCallback != NULL)
1143 {
1144 /* Transfer error Callback */
1145 hdma2d->XferErrorCallback(hdma2d);
1146 }
1147 }
1148 }
1149 /* Configuration Error Interrupt management **********************************/
1150 if ((isrflags & DMA2D_FLAG_CE) != RESET)
1151 {
1152 if ((crflags & DMA2D_IT_CE) != RESET)
1153 {
1154 /* Disable the Configuration Error interrupt */
1155 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
1156
1157 /* Clear the Configuration error flag */
1158 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
1159
1160 /* Update error code */
1161 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1162
1163 /* Change DMA2D state */
1164 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1165
1166 /* Process Unlocked */
1167 __HAL_UNLOCK(hdma2d);
1168
1169 if(hdma2d->XferErrorCallback != NULL)
1170 {
1171 /* Transfer error Callback */
1172 hdma2d->XferErrorCallback(hdma2d);
1173 }
1174 }
1175 }
1176 /* CLUT access Error Interrupt management ***********************************/
1177 if ((isrflags & DMA2D_FLAG_CAE) != RESET)
1178 {
1179 if ((crflags & DMA2D_IT_CAE) != RESET)
1180 {
1181 /* Disable the CLUT access error interrupt */
1182 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
1183
1184 /* Clear the CLUT access error flag */
1185 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
1186
1187 /* Update error code */
1188 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1189
1190 /* Change DMA2D state */
1191 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1192
1193 /* Process Unlocked */
1194 __HAL_UNLOCK(hdma2d);
1195
1196 if(hdma2d->XferErrorCallback != NULL)
1197 {
1198 /* Transfer error Callback */
1199 hdma2d->XferErrorCallback(hdma2d);
1200 }
1201 }
1202 }
1203 /* Transfer watermark Interrupt management **********************************/
1204 if ((isrflags & DMA2D_FLAG_TW) != RESET)
1205 {
1206 if ((crflags & DMA2D_IT_TW) != RESET)
1207 {
1208 /* Disable the transfer watermark interrupt */
1209 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
1210
1211 /* Clear the transfer watermark flag */
1212 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
1213
1214 /* Transfer watermark Callback */
1215 HAL_DMA2D_LineEventCallback(hdma2d);
1216 }
1217 }
1218 /* Transfer Complete Interrupt management ************************************/
1219 if ((isrflags & DMA2D_FLAG_TC) != RESET)
1220 {
1221 if ((crflags & DMA2D_IT_TC) != RESET)
1222 {
1223 /* Disable the transfer complete interrupt */
1224 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
1225
1226 /* Clear the transfer complete flag */
1227 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
1228
1229 /* Update error code */
1230 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1231
1232 /* Change DMA2D state */
1233 hdma2d->State = HAL_DMA2D_STATE_READY;
1234
1235 /* Process Unlocked */
1236 __HAL_UNLOCK(hdma2d);
1237
1238 if(hdma2d->XferCpltCallback != NULL)
1239 {
1240 /* Transfer complete Callback */
1241 hdma2d->XferCpltCallback(hdma2d);
1242 }
1243 }
1244 }
1245 /* CLUT Transfer Complete Interrupt management ******************************/
1246 if ((isrflags & DMA2D_FLAG_CTC) != RESET)
1247 {
1248 if ((crflags & DMA2D_IT_CTC) != RESET)
1249 {
1250 /* Disable the CLUT transfer complete interrupt */
1251 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
1252
1253 /* Clear the CLUT transfer complete flag */
1254 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
1255
1256 /* Update error code */
1257 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1258
1259 /* Change DMA2D state */
1260 hdma2d->State = HAL_DMA2D_STATE_READY;
1261
1262 /* Process Unlocked */
1263 __HAL_UNLOCK(hdma2d);
1264
1265 /* CLUT Transfer complete Callback */
1266 HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
1267 }
1268 }
1269 }
1270
1271 /**
1272 * @brief Transfer watermark callback.
1273 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
1274 * the configuration information for the DMA2D.
1275 * @retval None
1276 */
1277 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
1278 {
1279 /* Prevent unused argument(s) compilation warning */
1280 UNUSED(hdma2d);
1281
1282 /* NOTE : This function should not be modified; when the callback is needed,
1283 the HAL_DMA2D_LineEventCallback can be implemented in the user file.
1284 */
1285 }
1286
1287 /**
1288 * @brief CLUT Transfer Complete callback.
1289 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
1290 * the configuration information for the DMA2D.
1291 * @retval None
1292 */
1293 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
1294 {
1295 /* Prevent unused argument(s) compilation warning */
1296 UNUSED(hdma2d);
1297
1298 /* NOTE : This function should not be modified; when the callback is needed,
1299 the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
1300 */
1301 }
1302
1303 /**
1304 * @}
1305 */
1306
1307 /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
1308 * @brief Peripheral Control functions
1309 *
1310 @verbatim
1311 ===============================================================================
1312 ##### Peripheral Control functions #####
1313 ===============================================================================
1314 [..] This section provides functions allowing to:
1315 (+) Configure the DMA2D foreground or background layer parameters.
1316 (+) Configure the DMA2D CLUT transfer.
1317 (+) Configure the line watermark
1318 (+) Configure the dead time value.
1319 (+) Enable or disable the dead time value functionality.
1320
1321 @endverbatim
1322 * @{
1323 */
1324
1325 /**
1326 * @brief Configure the DMA2D Layer according to the specified
1327 * parameters in the DMA2D_InitTypeDef and create the associated handle.
1328 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
1329 * the configuration information for the DMA2D.
1330 * @param LayerIdx: DMA2D Layer index.
1331 * This parameter can be one of the following values:
1332 * 0(background) / 1(foreground)
1333 * @retval HAL status
1334 */
1335 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1336 {
1337 DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
1338 uint32_t regValue = 0U;
1339
1340 /* Check the parameters */
1341 assert_param(IS_DMA2D_LAYER(LayerIdx));
1342 assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
1343 if(hdma2d->Init.Mode != DMA2D_R2M)
1344 {
1345 assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
1346 if(hdma2d->Init.Mode != DMA2D_M2M)
1347 {
1348 assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
1349 }
1350 }
1351
1352 /* Process locked */
1353 __HAL_LOCK(hdma2d);
1354
1355 /* Change DMA2D peripheral state */
1356 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1357
1358 /* DMA2D BGPFCR register configuration -----------------------------------*/
1359 /* Prepare the value to be written to the BGPFCCR register */
1360
1361 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1362 {
1363 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
1364 }
1365 else
1366 {
1367 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);
1368 }
1369
1370 /* Configure the background DMA2D layer */
1371 if(LayerIdx == 0)
1372 {
1373 /* Write DMA2D BGPFCCR register */
1374 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA), regValue);
1375
1376 /* DMA2D BGOR register configuration -------------------------------------*/
1377 WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
1378
1379 /* DMA2D BGCOLR register configuration -------------------------------------*/
1380 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1381 {
1382 WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
1383 }
1384 }
1385 /* Configure the foreground DMA2D layer */
1386 else
1387 {
1388 /* Write DMA2D FGPFCCR register */
1389 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA), regValue);
1390
1391 /* DMA2D FGOR register configuration -------------------------------------*/
1392 WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
1393
1394 /* DMA2D FGCOLR register configuration -------------------------------------*/
1395 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1396 {
1397 WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
1398 }
1399 }
1400 /* Initialize the DMA2D state*/
1401 hdma2d->State = HAL_DMA2D_STATE_READY;
1402
1403 /* Process unlocked */
1404 __HAL_UNLOCK(hdma2d);
1405
1406 return HAL_OK;
1407 }
1408
1409 /**
1410 * @brief Configure the DMA2D CLUT Transfer.
1411 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
1412 * the configuration information for the DMA2D.
1413 * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1414 * the configuration information for the color look up table.
1415 * @param LayerIdx: DMA2D Layer index.
1416 * This parameter can be one of the following values:
1417 * 0(background) / 1(foreground)
1418 * @retval HAL status
1419 */
1420 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1421 {
1422 /* Check the parameters */
1423 assert_param(IS_DMA2D_LAYER(LayerIdx));
1424 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1425 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1426
1427 /* Process locked */
1428 __HAL_LOCK(hdma2d);
1429
1430 /* Change DMA2D peripheral state */
1431 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1432
1433 /* Configure the CLUT of the background DMA2D layer */
1434 if(LayerIdx == 0U)
1435 {
1436 /* Write background CLUT memory address */
1437 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1438
1439 /* Write background CLUT size and CLUT color mode */
1440 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1441 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
1442 }
1443 /* Configure the CLUT of the foreground DMA2D layer */
1444 else
1445 {
1446 /* Write foreground CLUT memory address */
1447 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1448
1449 /* Write foreground CLUT size and CLUT color mode */
1450 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1451 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
1452 }
1453
1454 /* Set the DMA2D state to Ready */
1455 hdma2d->State = HAL_DMA2D_STATE_READY;
1456
1457 /* Process unlocked */
1458 __HAL_UNLOCK(hdma2d);
1459
1460 return HAL_OK;
1461 }
1462
1463 /**
1464 * @brief Configure the line watermark.
1465 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
1466 * the configuration information for the DMA2D.
1467 * @param Line: Line Watermark configuration (maximum 16-bit long value expected).
1468 * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
1469 * @note The transfer watermark interrupt is disabled once it has occurred.
1470 * @retval HAL status
1471 */
1472
1473 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
1474 {
1475 /* Check the parameters */
1476 assert_param(IS_DMA2D_LINEWATERMARK(Line));
1477
1478 if (Line > DMA2D_LWR_LW)
1479 {
1480 return HAL_ERROR;
1481 }
1482 else
1483 {
1484 /* Process locked */
1485 __HAL_LOCK(hdma2d);
1486
1487 /* Change DMA2D peripheral state */
1488 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1489
1490 /* Sets the Line watermark configuration */
1491 WRITE_REG(hdma2d->Instance->LWR, Line);
1492
1493 /* Enable the Line interrupt */
1494 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
1495
1496 /* Initialize the DMA2D state */
1497 hdma2d->State = HAL_DMA2D_STATE_READY;
1498
1499 /* Process unlocked */
1500 __HAL_UNLOCK(hdma2d);
1501
1502 return HAL_OK;
1503 }
1504 }
1505
1506 /**
1507 * @brief Enable DMA2D dead time feature.
1508 * @param hdma2d: DMA2D handle.
1509 * @retval HAL status
1510 */
1511 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1512 {
1513 /* Process Locked */
1514 __HAL_LOCK(hdma2d);
1515
1516 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1517
1518 /* Set DMA2D_AMTCR EN bit */
1519 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
1520
1521 hdma2d->State = HAL_DMA2D_STATE_READY;
1522
1523 /* Process Unlocked */
1524 __HAL_UNLOCK(hdma2d);
1525
1526 return HAL_OK;
1527 }
1528
1529 /**
1530 * @brief Disable DMA2D dead time feature.
1531 * @param hdma2d: DMA2D handle.
1532 * @retval HAL status
1533 */
1534 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1535 {
1536 /* Process Locked */
1537 __HAL_LOCK(hdma2d);
1538
1539 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1540
1541 /* Clear DMA2D_AMTCR EN bit */
1542 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
1543
1544 hdma2d->State = HAL_DMA2D_STATE_READY;
1545
1546 /* Process Unlocked */
1547 __HAL_UNLOCK(hdma2d);
1548
1549 return HAL_OK;
1550 }
1551
1552 /**
1553 * @brief Configure dead time.
1554 * @note The dead time value represents the guaranteed minimum number of cycles between
1555 * two consecutive transactions on the AHB bus.
1556 * @param hdma2d: DMA2D handle.
1557 * @param DeadTime: dead time value.
1558 * @retval HAL status
1559 */
1560 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
1561 {
1562 /* Process Locked */
1563 __HAL_LOCK(hdma2d);
1564
1565 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1566
1567 /* Set DMA2D_AMTCR DT field */
1568 MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));
1569
1570 hdma2d->State = HAL_DMA2D_STATE_READY;
1571
1572 /* Process Unlocked */
1573 __HAL_UNLOCK(hdma2d);
1574
1575 return HAL_OK;
1576 }
1577
1578 /**
1579 * @}
1580 */
1581
1582 /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
1583 * @brief Peripheral State functions
1584 *
1585 @verbatim
1586 ===============================================================================
1587 ##### Peripheral State and Errors functions #####
1588 ===============================================================================
1589 [..]
1590 This subsection provides functions allowing to :
1591 (+) Get the DMA2D state
1592 (+) Get the DMA2D error code
1593
1594 @endverbatim
1595 * @{
1596 */
1597
1598 /**
1599 * @brief Return the DMA2D state
1600 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
1601 * the configuration information for the DMA2D.
1602 * @retval HAL state
1603 */
1604 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
1605 {
1606 return hdma2d->State;
1607 }
1608
1609 /**
1610 * @brief Return the DMA2D error code
1611 * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
1612 * the configuration information for DMA2D.
1613 * @retval DMA2D Error Code
1614 */
1615 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
1616 {
1617 return hdma2d->ErrorCode;
1618 }
1619
1620 /**
1621 * @}
1622 */
1623
1624 /**
1625 * @}
1626 */
1627
1628 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
1629 * @{
1630 */
1631
1632 /**
1633 * @brief Set the DMA2D transfer parameters.
1634 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
1635 * the configuration information for the specified DMA2D.
1636 * @param pdata: The source memory Buffer address
1637 * @param DstAddress: The destination memory Buffer address
1638 * @param Width: The width of data to be transferred from source to destination.
1639 * @param Height: The height of data to be transferred from source to destination.
1640 * @retval HAL status
1641 */
1642 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
1643 {
1644 uint32_t tmp = 0U;
1645 uint32_t tmp1 = 0U;
1646 uint32_t tmp2 = 0U;
1647 uint32_t tmp3 = 0U;
1648 uint32_t tmp4 = 0U;
1649
1650 /* Configure DMA2D data size */
1651 MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL)));
1652
1653 /* Configure DMA2D destination address */
1654 WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
1655
1656 /* Register to memory DMA2D mode selected */
1657 if (hdma2d->Init.Mode == DMA2D_R2M)
1658 {
1659 tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
1660 tmp2 = pdata & DMA2D_OCOLR_RED_1;
1661 tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
1662 tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
1663
1664 /* Prepare the value to be written to the OCOLR register according to the color mode */
1665 if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
1666 {
1667 tmp = (tmp3 | tmp2 | tmp1| tmp4);
1668 }
1669 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
1670 {
1671 tmp = (tmp3 | tmp2 | tmp4);
1672 }
1673 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
1674 {
1675 tmp2 = (tmp2 >> 19U);
1676 tmp3 = (tmp3 >> 10U);
1677 tmp4 = (tmp4 >> 3U);
1678 tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
1679 }
1680 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
1681 {
1682 tmp1 = (tmp1 >> 31U);
1683 tmp2 = (tmp2 >> 19U);
1684 tmp3 = (tmp3 >> 11U);
1685 tmp4 = (tmp4 >> 3U);
1686 tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
1687 }
1688 else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
1689 {
1690 tmp1 = (tmp1 >> 28U);
1691 tmp2 = (tmp2 >> 20U);
1692 tmp3 = (tmp3 >> 12U);
1693 tmp4 = (tmp4 >> 4U);
1694 tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
1695 }
1696 /* Write to DMA2D OCOLR register */
1697 WRITE_REG(hdma2d->Instance->OCOLR, tmp);
1698 }
1699 else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
1700 {
1701 /* Configure DMA2D source address */
1702 WRITE_REG(hdma2d->Instance->FGMAR, pdata);
1703 }
1704 }
1705
1706 /**
1707 * @}
1708 */
1709 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
1710 #endif /* HAL_DMA2D_MODULE_ENABLED */
1711 /**
1712 * @}
1713 */
1714
1715 /**
1716 * @}
1717 */
1718
1719 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/