lib/main/STM32F4/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_hal_dsi.c
   4   * @author  MCD Application Team
   5   * @version V1.7.1
   6   * @date    14-April-2017
   7   * @brief   DSI HAL module driver.
   8   *          This file provides firmware functions to manage the following
   9   *          functionalities of the DSI peripheral:
  10   *           + Initialization and de-initialization functions
  11   *           + IO operation functions
  12   *           + Peripheral Control functions
  13   *           + Peripheral State and Errors functions
  14   ******************************************************************************
  15   * @attention
  16   *
  17   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  18   *
  19   * Redistribution and use in source and binary forms, with or without modification,
  20   * are permitted provided that the following conditions are met:
  21   *   1. Redistributions of source code must retain the above copyright notice,
  22   *      this list of conditions and the following disclaimer.
  23   *   2. Redistributions in binary form must reproduce the above copyright notice,
  24   *      this list of conditions and the following disclaimer in the documentation
  25   *      and/or other materials provided with the distribution.
  26   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  27   *      may be used to endorse or promote products derived from this software
  28   *      without specific prior written permission.
  29   *
  30   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  31   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  32   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  34   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  35   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  36   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  37   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  38   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40   *
  41   ******************************************************************************
  42   */
  43
  44 /* Includes ------------------------------------------------------------------*/
  45 #include "stm32f4xx_hal.h"
  46
  47 /** @addtogroup STM32F4xx_HAL_Driver
  48   * @{
  49   */
  50 /** @addtogroup DSI
  51   * @{
  52   */
  53
  54 #ifdef HAL_DSI_MODULE_ENABLED
  55
  56 #if defined(STM32F469xx) || defined(STM32F479xx)
  57
  58 /* Private types -------------------------------------------------------------*/
  59 /* Private defines -----------------------------------------------------------*/
  60 /** @addtogroup DSI_Private_Constants
  61   * @{
  62   */
  63 #define DSI_TIMEOUT_VALUE ((uint32_t)1000U)  /* 1s */
  64
  65 #define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
  66                             DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
  67                             DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \
  68                             DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)
  69 #define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)
  70 #define DSI_ERROR_TX_MASK  DSI_ISR1_TOHSTX
  71 #define DSI_ERROR_RX_MASK  DSI_ISR1_TOLPRX
  72 #define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)
  73 #define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
  74 #define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
  75 #define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
  76 #define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
  77 #define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)
  78 /**
  79   * @}
  80   */
  81
  82 /* Private variables ---------------------------------------------------------*/
  83 /* Private constants ---------------------------------------------------------*/
  84 /* Private macros ------------------------------------------------------------*/
  85 /* Private function prototypes -----------------------------------------------*/
  86 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1);
  87
  88 /* Private functions ---------------------------------------------------------*/
  89 /**
  90   * @brief  Generic DSI packet header configuration
  91   * @param  DSIx: Pointer to DSI register base
  92   * @param  ChannelID: Virtual channel ID of the header packet
  93   * @param  DataType: Packet data type of the header packet
  94   *                   This parameter can be any value of :
  95   *                      @ref DSI_SHORT_WRITE_PKT_Data_Type
  96   *                   or @ref DSI_LONG_WRITE_PKT_Data_Type
  97   *                   or @ref DSI_SHORT_READ_PKT_Data_Type
  98   *                   or DSI_MAX_RETURN_PKT_SIZE
  99   * @param  Data0: Word count LSB
 100   * @param  Data1: Word count MSB
 101   * @retval None
 102   */
 103 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
 104                                    uint32_t ChannelID,
 105                                    uint32_t DataType,
 106                                    uint32_t Data0,
 107                                    uint32_t Data1)
 108 {
 109   /* Update the DSI packet header with new information */
 110   DSIx->GHCR = (DataType | (ChannelID<<6U) | (Data0<<8U) | (Data1<<16U));
 111 }
 112
 113 /* Exported functions --------------------------------------------------------*/
 114 /** @addtogroup DSI_Exported_Functions
 115   * @{
 116   */
 117
 118 /** @defgroup DSI_Group1 Initialization and Configuration functions
 119  *  @brief   Initialization and Configuration functions
 120  *
 121 @verbatim
 122  ===============================================================================
 123                 ##### Initialization and Configuration functions #####
 124  ===============================================================================
 125     [..]  This section provides functions allowing to:
 126       (+) Initialize and configure the DSI
 127       (+) De-initialize the DSI
 128
 129 @endverbatim
 130   * @{
 131   */
 132
 133 /**
 134   * @brief  Initializes the DSI according to the specified
 135   *         parameters in the DSI_InitTypeDef and create the associated handle.
 136   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
 137   *               the configuration information for the DSI.
 138   * @param  PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains
 139   *               the PLL Clock structure definition for the DSI.
 140   * @retval HAL status
 141   */
 142 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
 143 {
 144   uint32_t tickstart = 0U;
 145   uint32_t unitIntervalx4 = 0U;
 146   uint32_t tempIDF = 0U;
 147
 148   /* Check the DSI handle allocation */
 149   if(hdsi == NULL)
 150   {
 151     return HAL_ERROR;
 152   }
 153
 154   /* Check function parameters */
 155   assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
 156   assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
 157   assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
 158   assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
 159   assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
 160
 161   if(hdsi->State == HAL_DSI_STATE_RESET)
 162   {
 163     /* Initialize the low level hardware */
 164     HAL_DSI_MspInit(hdsi);
 165   }
 166
 167   /* Change DSI peripheral state */
 168   hdsi->State = HAL_DSI_STATE_BUSY;
 169
 170   /**************** Turn on the regulator and enable the DSI PLL ****************/
 171
 172     /* Enable the regulator */
 173     __HAL_DSI_REG_ENABLE(hdsi);
 174
 175         /* Get tick */
 176     tickstart = HAL_GetTick();
 177
 178     /* Wait until the regulator is ready */
 179         while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET)
 180     {
 181       /* Check for the Timeout */
 182       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
 183       {
 184         return HAL_TIMEOUT;
 185       }
 186     }
 187
 188     /* Set the PLL division factors */
 189     hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
 190     hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2U) | ((PLLInit->PLLIDF)<<11U) | ((PLLInit->PLLODF)<<16U));
 191
 192     /* Enable the DSI PLL */
 193     __HAL_DSI_PLL_ENABLE(hdsi);
 194
 195         /* Get tick */
 196     tickstart = HAL_GetTick();
 197
 198     /* Wait for the lock of the PLL */
 199     while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
 200     {
 201       /* Check for the Timeout */
 202       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
 203       {
 204         return HAL_TIMEOUT;
 205       }
 206     }
 207
 208   /*************************** Set the PHY parameters ***************************/
 209
 210     /* D-PHY clock and digital enable*/
 211     hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
 212
 213     /* Clock lane configuration */
 214     hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
 215     hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
 216
 217     /* Configure the number of active data lanes */
 218     hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
 219     hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
 220
 221   /************************ Set the DSI clock parameters ************************/
 222
 223     /* Set the TX escape clock division factor */
 224     hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
 225     hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
 226
 227     /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
 228     /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 )          */
 229     /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF)                    */
 230     tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U;
 231     unitIntervalx4 = (4000000U * tempIDF * (1U << PLLInit->PLLODF)) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV);
 232
 233     /* Set the bit period in high-speed mode */
 234     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4;
 235     hdsi->Instance->WPCR[0U] |= unitIntervalx4;
 236
 237   /****************************** Error management *****************************/
 238
 239     /* Disable all error interrupts and reset the Error Mask */
 240     hdsi->Instance->IER[0U] = 0U;
 241     hdsi->Instance->IER[1U] = 0U;
 242     hdsi->ErrorMsk = 0U;
 243
 244     /* Initialise the error code */
 245     hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
 246
 247   /* Initialize the DSI state*/
 248   hdsi->State = HAL_DSI_STATE_READY;
 249
 250   return HAL_OK;
 251 }
 252
 253 /**
 254   * @brief  De-initializes the DSI peripheral registers to their default reset
 255   *         values.
 256   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
 257   *               the configuration information for the DSI.
 258   * @retval HAL status
 259   */
 260 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
 261 {
 262   /* Check the DSI handle allocation */
 263   if(hdsi == NULL)
 264   {
 265     return HAL_ERROR;
 266   }
 267
 268   /* Change DSI peripheral state */
 269   hdsi->State = HAL_DSI_STATE_BUSY;
 270
 271   /* Disable the DSI wrapper */
 272   __HAL_DSI_WRAPPER_DISABLE(hdsi);
 273
 274   /* Disable the DSI host */
 275   __HAL_DSI_DISABLE(hdsi);
 276
 277   /* D-PHY clock and digital disable */
 278   hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);
 279
 280   /* Turn off the DSI PLL */
 281   __HAL_DSI_PLL_DISABLE(hdsi);
 282
 283   /* Disable the regulator */
 284   __HAL_DSI_REG_DISABLE(hdsi);
 285
 286   /* DeInit the low level hardware */
 287   HAL_DSI_MspDeInit(hdsi);
 288
 289   /* Initialise the error code */
 290   hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
 291
 292   /* Initialize the DSI state*/
 293   hdsi->State = HAL_DSI_STATE_RESET;
 294
 295   /* Release Lock */
 296   __HAL_UNLOCK(hdsi);
 297
 298   return HAL_OK;
 299 }
 300
 301 /**
 302   * @brief  Return the DSI error code
 303   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
 304   *               the configuration information for the DSI.
 305   * @retval DSI Error Code
 306   */
 307 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
 308 {
 309   /* Get the error code */
 310   return hdsi->ErrorCode;
 311 }
 312
 313 /**
 314   * @brief  Enable the error monitor flags
 315   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
 316   *               the configuration information for the DSI.
 317   * @param  ActiveErrors: indicates which error interrupts will be enabled.
 318   *                      This parameter can be any combination of @ref DSI_Error_Data_Type.
 319   * @retval HAL status
 320   */
 321 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
 322 {
 323   /* Process locked */
 324   __HAL_LOCK(hdsi);
 325
 326   hdsi->Instance->IER[0U] = 0U;
 327   hdsi->Instance->IER[1U] = 0U;
 328
 329   /* Store active errors to the handle */
 330   hdsi->ErrorMsk = ActiveErrors;
 331
 332   if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET)
 333   {
 334     /* Enable the interrupt generation on selected errors */
 335     hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK;
 336   }
 337
 338   if((ActiveErrors & HAL_DSI_ERROR_PHY) != RESET)
 339   {
 340     /* Enable the interrupt generation on selected errors */
 341     hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK;
 342   }
 343
 344   if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET)
 345   {
 346     /* Enable the interrupt generation on selected errors */
 347     hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK;
 348   }
 349
 350   if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET)
 351   {
 352     /* Enable the interrupt generation on selected errors */
 353     hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK;
 354   }
 355
 356   if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET)
 357   {
 358     /* Enable the interrupt generation on selected errors */
 359     hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK;
 360   }
 361
 362   if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET)
 363   {
 364     /* Enable the interrupt generation on selected errors */
 365     hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK;
 366   }
 367
 368   if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET)
 369   {
 370     /* Enable the interrupt generation on selected errors */
 371     hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK;
 372   }
 373
 374   if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET)
 375   {
 376     /* Enable the interrupt generation on selected errors */
 377     hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK;
 378   }
 379
 380   if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET)
 381   {
 382     /* Enable the interrupt generation on selected errors */
 383     hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK;
 384   }
 385
 386   if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET)
 387   {
 388     /* Enable the interrupt generation on selected errors */
 389     hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK;
 390   }
 391
 392   /* Process Unlocked */
 393   __HAL_UNLOCK(hdsi);
 394
 395   return HAL_OK;
 396 }
 397
 398 /**
 399   * @brief  Initializes the DSI MSP.
 400   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
 401   *               the configuration information for the DSI.
 402   * @retval None
 403   */
 404 __weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)
 405 {
 406   /* Prevent unused argument(s) compilation warning */
 407   UNUSED(hdsi);
 408   /* NOTE : This function Should not be modified, when the callback is needed,
 409             the HAL_DSI_MspInit could be implemented in the user file
 410    */
 411 }
 412
 413 /**
 414   * @brief  De-initializes the DSI MSP.
 415   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
 416   *               the configuration information for the DSI.
 417   * @retval None
 418   */
 419 __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)
 420 {
 421   /* Prevent unused argument(s) compilation warning */
 422   UNUSED(hdsi);
 423   /* NOTE : This function Should not be modified, when the callback is needed,
 424             the HAL_DSI_MspDeInit could be implemented in the user file
 425    */
 426 }
 427
 428 /**
 429   * @}
 430   */
 431
 432 /** @defgroup DSI_Group2 IO operation functions
 433  *  @brief    IO operation functions
 434  *
 435 @verbatim
 436  ===============================================================================
 437                       #####  IO operation functions  #####
 438  ===============================================================================
 439     [..]  This section provides function allowing to:
 440       (+) Handle DSI interrupt request
 441
 442 @endverbatim
 443   * @{
 444   */
 445 /**
 446   * @brief  Handles DSI interrupt request.
 447   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
 448   *               the configuration information for the DSI.
 449   * @retval HAL status
 450   */
 451 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
 452 {
 453   uint32_t ErrorStatus0, ErrorStatus1;
 454
 455   /* Tearing Effect Interrupt management ***************************************/
 456   if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET)
 457   {
 458     if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET)
 459     {
 460       /* Clear the Tearing Effect Interrupt Flag */
 461       __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
 462
 463       /* Tearing Effect Callback */
 464       HAL_DSI_TearingEffectCallback(hdsi);
 465     }
 466   }
 467
 468   /* End of Refresh Interrupt management ***************************************/
 469   if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET)
 470   {
 471     if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET)
 472     {
 473       /* Clear the End of Refresh Interrupt Flag */
 474       __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
 475
 476       /* End of Refresh Callback */
 477       HAL_DSI_EndOfRefreshCallback(hdsi);
 478     }
 479   }
 480
 481   /* Error Interrupts management ***********************************************/
 482   if(hdsi->ErrorMsk != 0U)
 483   {
 484     ErrorStatus0 = hdsi->Instance->ISR[0U];
 485     ErrorStatus0 &= hdsi->Instance->IER[0U];
 486     ErrorStatus1 = hdsi->Instance->ISR[1U];
 487     ErrorStatus1 &= hdsi->Instance->IER[1U];
 488
 489     if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET)
 490     {
 491       hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
 492     }
 493
 494     if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET)
 495     {
 496       hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
 497     }
 498
 499     if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET)
 500     {
 501       hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
 502     }
 503
 504     if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET)
 505     {
 506       hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
 507     }
 508
 509     if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET)
 510     {
 511       hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
 512     }
 513
 514     if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET)
 515     {
 516       hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
 517     }
 518
 519     if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET)
 520     {
 521       hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
 522     }
 523
 524     if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET)
 525     {
 526       hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
 527     }
 528
 529     if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET)
 530     {
 531       hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
 532     }
 533
 534     if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET)
 535     {
 536       hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
 537     }
 538
 539     /* Check only selected errors */
 540     if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
 541     {
 542       /* DSI error interrupt user callback */
 543       HAL_DSI_ErrorCallback(hdsi);
 544     }
 545   }
 546 }
 547
 548 /**
 549   * @brief  Tearing Effect DSI callback.
 550   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
 551   *               the configuration information for the DSI.
 552   * @retval None
 553   */
 554 __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
 555 {
 556   /* Prevent unused argument(s) compilation warning */
 557   UNUSED(hdsi);
 558   /* NOTE : This function Should not be modified, when the callback is needed,
 559             the HAL_DSI_TearingEffectCallback could be implemented in the user file
 560    */
 561 }
 562
 563 /**
 564   * @brief  End of Refresh DSI callback.
 565   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
 566   *               the configuration information for the DSI.
 567   * @retval None
 568   */
 569 __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
 570 {
 571   /* Prevent unused argument(s) compilation warning */
 572   UNUSED(hdsi);
 573   /* NOTE : This function Should not be modified, when the callback is needed,
 574             the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
 575    */
 576 }
 577
 578 /**
 579   * @brief  Operation Error DSI callback.
 580   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
 581   *               the configuration information for the DSI.
 582   * @retval None
 583   */
 584 __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
 585 {
 586   /* Prevent unused argument(s) compilation warning */
 587   UNUSED(hdsi);
 588   /* NOTE : This function Should not be modified, when the callback is needed,
 589             the HAL_DSI_ErrorCallback could be implemented in the user file
 590    */
 591 }
 592
 593 /**
 594   * @}
 595   */
 596
 597 /** @defgroup DSI_Group3 Peripheral Control functions
 598  *  @brief    Peripheral Control functions
 599  *
 600 @verbatim
 601  ===============================================================================
 602                     ##### Peripheral Control functions #####
 603  ===============================================================================
 604
 605 @endverbatim
 606   * @{
 607   */
 608
 609 /**
 610   * @brief  Configure the Generic interface read-back Virtual Channel ID.
 611   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
 612   *               the configuration information for the DSI.
 613   * @param  VirtualChannelID: Virtual channel ID
 614   * @retval HAL status
 615   */
 616 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
 617 {
 618   /* Process locked */
 619   __HAL_LOCK(hdsi);
 620
 621   /* Update the GVCID register */
 622   hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;
 623   hdsi->Instance->GVCIDR |= VirtualChannelID;
 624
 625   /* Process unlocked */
 626   __HAL_UNLOCK(hdsi);
 627
 628   return HAL_OK;
 629 }
 630
 631 /**
 632   * @brief  Select video mode and configure the corresponding parameters
 633   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
 634   *               the configuration information for the DSI.
 635   * @param  VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains
 636   *                 the DSI video mode configuration parameters
 637   * @retval HAL status
 638   */
 639 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
 640 {
 641   /* Process locked */
 642   __HAL_LOCK(hdsi);
 643
 644   /* Check the parameters */
 645   assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
 646   assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
 647   assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
 648   assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
 649   assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
 650   assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
 651   assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
 652   assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
 653   assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
 654   assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
 655   assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
 656   assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
 657   assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
 658   /* Check the LooselyPacked variant only in 18-bit mode */
 659   if(VidCfg->ColorCoding == DSI_RGB666)
 660   {
 661     assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
 662   }
 663
 664   /* Select video mode by resetting CMDM and DSIM bits */
 665   hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
 666   hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
 667
 668   /* Configure the video mode transmission type */
 669   hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
 670   hdsi->Instance->VMCR |= VidCfg->Mode;
 671
 672   /* Configure the video packet size */
 673   hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
 674   hdsi->Instance->VPCR |= VidCfg->PacketSize;
 675
 676   /* Set the chunks number to be transmitted through the DSI link */
 677   hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
 678   hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;
 679
 680   /* Set the size of the null packet */
 681   hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
 682   hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;
 683
 684   /* Select the virtual channel for the LTDC interface traffic */
 685   hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
 686   hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;
 687
 688   /* Configure the polarity of control signals */
 689   hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
 690   hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);
 691
 692   /* Select the color coding for the host */
 693   hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
 694   hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;
 695
 696   /* Select the color coding for the wrapper */
 697   hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
 698   hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1U);
 699
 700   /* Enable/disable the loosely packed variant to 18-bit configuration */
 701   if(VidCfg->ColorCoding == DSI_RGB666)
 702   {
 703     hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
 704     hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
 705   }
 706
 707   /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
 708   hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
 709   hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;
 710
 711   /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
 712   hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
 713   hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;
 714
 715   /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
 716   hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
 717   hdsi->Instance->VLCR |= VidCfg->HorizontalLine;
 718
 719   /* Set the Vertical Synchronization Active (VSA) */
 720   hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
 721   hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;
 722
 723   /* Set the Vertical Back Porch (VBP)*/
 724   hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
 725   hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;
 726
 727   /* Set the Vertical Front Porch (VFP)*/
 728   hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
 729   hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;
 730
 731   /* Set the Vertical Active period*/
 732   hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
 733   hdsi->Instance->VVACR |= VidCfg->VerticalActive;
 734
 735   /* Configure the command transmission mode */
 736   hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
 737   hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;
 738
 739   /* Low power largest packet size */
 740   hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
 741   hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16U);
 742
 743   /* Low power VACT largest packet size */
 744   hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
 745   hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;
 746
 747   /* Enable LP transition in HFP period */
 748   hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
 749   hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;
 750
 751   /* Enable LP transition in HBP period */
 752   hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
 753   hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;
 754
 755   /* Enable LP transition in VACT period */
 756   hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
 757   hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;
 758
 759   /* Enable LP transition in VFP period */
 760   hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
 761   hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;
 762
 763   /* Enable LP transition in VBP period */
 764   hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
 765   hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;
 766
 767   /* Enable LP transition in vertical sync period */
 768   hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
 769   hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;
 770
 771   /* Enable the request for an acknowledge response at the end of a frame */
 772   hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
 773   hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;
 774
 775   /* Process unlocked */
 776   __HAL_UNLOCK(hdsi);
 777
 778   return HAL_OK;
 779 }
 780
 781 /**
 782   * @brief  Select adapted command mode and configure the corresponding parameters
 783   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
 784   *               the configuration information for the DSI.
 785   * @param  CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains
 786   *                 the DSI command mode configuration parameters
 787   * @retval HAL status
 788   */
 789 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)
 790 {
 791   /* Process locked */
 792   __HAL_LOCK(hdsi);
 793
 794   /* Check the parameters */
 795   assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
 796   assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
 797   assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
 798   assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
 799   assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
 800   assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
 801   assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
 802   assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
 803   assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
 804
 805   /* Select command mode by setting CMDM and DSIM bits */
 806   hdsi->Instance->MCR |= DSI_MCR_CMDM;
 807   hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
 808   hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;
 809
 810   /* Select the virtual channel for the LTDC interface traffic */
 811   hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
 812   hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;
 813
 814   /* Configure the polarity of control signals */
 815   hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
 816   hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);
 817
 818   /* Select the color coding for the host */
 819   hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
 820   hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;
 821
 822   /* Select the color coding for the wrapper */
 823   hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
 824   hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1U);
 825
 826   /* Configure the maximum allowed size for write memory command */
 827   hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
 828   hdsi->Instance->LCCR |= CmdCfg->CommandSize;
 829
 830   /* Configure the tearing effect source and polarity and select the refresh mode */
 831   hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
 832   hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol);
 833
 834   /* Configure the tearing effect acknowledge request */
 835   hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
 836   hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;
 837
 838   /* Enable the Tearing Effect interrupt */
 839   __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
 840
 841   /* Enable the End of Refresh interrupt */
 842   __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
 843
 844   /* Process unlocked */
 845   __HAL_UNLOCK(hdsi);
 846
 847   return HAL_OK;
 848 }
 849
 850 /**
 851   * @brief  Configure command transmission mode: High-speed or Low-power
 852   *         and enable/disable acknowledge request after packet transmission
 853   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
 854   *               the configuration information for the DSI.
 855   * @param  LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains
 856   *                the DSI command transmission mode configuration parameters
 857   * @retval HAL status
 858   */
 859 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)
 860 {
 861   /* Process locked */
 862   __HAL_LOCK(hdsi);
 863
 864   assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
 865   assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
 866   assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
 867   assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
 868   assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
 869   assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
 870   assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
 871   assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
 872   assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
 873   assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
 874   assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
 875   assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
 876   assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
 877
 878   /* Select High-speed or Low-power for command transmission */
 879   hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\
 880                             DSI_CMCR_GSW1TX |\
 881                             DSI_CMCR_GSW2TX |\
 882                             DSI_CMCR_GSR0TX |\
 883                             DSI_CMCR_GSR1TX |\
 884                             DSI_CMCR_GSR2TX |\
 885                             DSI_CMCR_GLWTX  |\
 886                             DSI_CMCR_DSW0TX |\
 887                             DSI_CMCR_DSW1TX |\
 888                             DSI_CMCR_DSR0TX |\
 889                             DSI_CMCR_DLWTX  |\
 890                             DSI_CMCR_MRDPS);
 891   hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP  |\
 892                            LPCmd->LPGenShortWriteOneP |\
 893                            LPCmd->LPGenShortWriteTwoP |\
 894                            LPCmd->LPGenShortReadNoP   |\
 895                            LPCmd->LPGenShortReadOneP  |\
 896                            LPCmd->LPGenShortReadTwoP  |\
 897                            LPCmd->LPGenLongWrite      |\
 898                            LPCmd->LPDcsShortWriteNoP  |\
 899                            LPCmd->LPDcsShortWriteOneP |\
 900                            LPCmd->LPDcsShortReadNoP   |\
 901                            LPCmd->LPDcsLongWrite      |\
 902                            LPCmd->LPMaxReadPacket);
 903
 904   /* Configure the acknowledge request after each packet transmission */
 905   hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
 906   hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;
 907
 908   /* Process unlocked */
 909   __HAL_UNLOCK(hdsi);
 910
 911   return HAL_OK;
 912 }
 913
 914 /**
 915   * @brief  Configure the flow control parameters
 916   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
 917   *               the configuration information for the DSI.
 918   * @param  FlowControl: flow control feature(s) to be enabled.
 919   *                      This parameter can be any combination of @ref DSI_FlowControl.
 920   * @retval HAL status
 921   */
 922 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
 923 {
 924   /* Process locked */
 925   __HAL_LOCK(hdsi);
 926
 927   /* Check the parameters */
 928   assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
 929
 930   /* Set the DSI Host Protocol Configuration Register */
 931   hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
 932   hdsi->Instance->PCR |= FlowControl;
 933
 934   /* Process unlocked */
 935   __HAL_UNLOCK(hdsi);
 936
 937   return HAL_OK;
 938 }
 939
 940 /**
 941   * @brief  Configure the DSI PHY timer parameters
 942   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
 943   *               the configuration information for the DSI.
 944   * @param  PhyTimers: DSI_PHY_TimerTypeDef structure that contains
 945   *                    the DSI PHY timing parameters
 946   * @retval HAL status
 947   */
 948 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)
 949 {
 950   uint32_t maxTime;
 951   /* Process locked */
 952   __HAL_LOCK(hdsi);
 953
 954   maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime;
 955
 956   /* Clock lane timer configuration */
 957
 958   /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
 959      High-Speed transmission.
 960      To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
 961      to Low-Power and from Low-Power to High-Speed.
 962      This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
 963      But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
 964
 965      Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
 966   */
 967   hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
 968   hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16U));
 969
 970   /* Data lane timer configuration */
 971   hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
 972   hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16U) | ((PhyTimers->DataLaneHS2LPTime)<<24U));
 973
 974   /* Configure the wait period to request HS transmission after a stop state */
 975   hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
 976   hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8U);
 977
 978   /* Process unlocked */
 979   __HAL_UNLOCK(hdsi);
 980
 981   return HAL_OK;
 982 }
 983
 984 /**
 985   * @brief  Configure the DSI HOST timeout parameters
 986   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
 987   *               the configuration information for the DSI.
 988   * @param  HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains
 989   *                       the DSI host timeout parameters
 990   * @retval HAL status
 991   */
 992 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)
 993 {
 994   /* Process locked */
 995   __HAL_LOCK(hdsi);
 996
 997   /* Set the timeout clock division factor */
 998   hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
 999   hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv)<<8U);
1000
1001   /* High-speed transmission timeout */
1002   hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT;
1003   hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16U);
1004
1005   /* Low-power reception timeout */
1006   hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT;
1007   hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout;
1008
1009   /* High-speed read timeout */
1010   hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT;
1011   hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout;
1012
1013   /* Low-power read timeout */
1014   hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT;
1015   hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout;
1016
1017   /* High-speed write timeout */
1018   hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT;
1019   hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout;
1020
1021   /* High-speed write presp mode */
1022   hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM;
1023   hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode;
1024
1025   /* Low-speed write timeout */
1026   hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT;
1027   hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout;
1028
1029   /* BTA timeout */
1030   hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT;
1031   hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout;
1032
1033   /* Process unlocked */
1034   __HAL_UNLOCK(hdsi);
1035
1036   return HAL_OK;
1037 }
1038
1039 /**
1040   * @brief  Start the DSI module
1041   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1042   *               the configuration information for the DSI.
1043   * @retval HAL status
1044   */
1045 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
1046 {
1047   /* Process locked */
1048   __HAL_LOCK(hdsi);
1049
1050   /* Enable the DSI host */
1051   __HAL_DSI_ENABLE(hdsi);
1052
1053   /* Enable the DSI wrapper */
1054   __HAL_DSI_WRAPPER_ENABLE(hdsi);
1055
1056   /* Process unlocked */
1057   __HAL_UNLOCK(hdsi);
1058
1059   return HAL_OK;
1060 }
1061
1062 /**
1063   * @brief  Stop the DSI module
1064   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1065   *               the configuration information for the DSI.
1066   * @retval HAL status
1067   */
1068 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
1069 {
1070   /* Process locked */
1071   __HAL_LOCK(hdsi);
1072
1073   /* Disable the DSI host */
1074   __HAL_DSI_DISABLE(hdsi);
1075
1076   /* Disable the DSI wrapper */
1077   __HAL_DSI_WRAPPER_DISABLE(hdsi);
1078
1079   /* Process unlocked */
1080   __HAL_UNLOCK(hdsi);
1081
1082   return HAL_OK;
1083 }
1084
1085 /**
1086   * @brief  Refresh the display in command mode
1087   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1088   *               the configuration information for the DSI.
1089   * @retval HAL status
1090   */
1091 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
1092 {
1093   /* Process locked */
1094   __HAL_LOCK(hdsi);
1095
1096   /* Update the display */
1097   hdsi->Instance->WCR |= DSI_WCR_LTDCEN;
1098
1099   /* Process unlocked */
1100   __HAL_UNLOCK(hdsi);
1101
1102   return HAL_OK;
1103 }
1104
1105 /**
1106   * @brief  Controls the display color mode in Video mode
1107   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1108   *               the configuration information for the DSI.
1109   * @param  ColorMode: Color mode (full or 8-colors).
1110   *                    This parameter can be any value of @ref DSI_Color_Mode
1111   * @retval HAL status
1112   */
1113 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
1114 {
1115   /* Process locked */
1116   __HAL_LOCK(hdsi);
1117
1118   /* Check the parameters */
1119   assert_param(IS_DSI_COLOR_MODE(ColorMode));
1120
1121   /* Update the display color mode */
1122   hdsi->Instance->WCR &= ~DSI_WCR_COLM;
1123   hdsi->Instance->WCR |= ColorMode;
1124
1125   /* Process unlocked */
1126   __HAL_UNLOCK(hdsi);
1127
1128   return HAL_OK;
1129 }
1130
1131 /**
1132   * @brief  Control the display shutdown in Video mode
1133   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1134   *               the configuration information for the DSI.
1135   * @param  Shutdown: Shut-down (Display-ON or Display-OFF).
1136   *                   This parameter can be any value of @ref DSI_ShutDown
1137   * @retval HAL status
1138   */
1139 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
1140 {
1141   /* Process locked */
1142   __HAL_LOCK(hdsi);
1143
1144   /* Check the parameters */
1145   assert_param(IS_DSI_SHUT_DOWN(Shutdown));
1146
1147   /* Update the display Shutdown */
1148   hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
1149   hdsi->Instance->WCR |= Shutdown;
1150
1151   /* Process unlocked */
1152   __HAL_UNLOCK(hdsi);
1153
1154   return HAL_OK;
1155 }
1156
1157 /**
1158   * @brief  DCS or Generic short write command
1159   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1160   *               the configuration information for the DSI.
1161   * @param  ChannelID: Virtual channel ID.
1162   * @param  Mode: DSI short packet data type.
1163   *               This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
1164   * @param  Param1: DSC command or first generic parameter.
1165   *                 This parameter can be any value of @ref DSI_DCS_Command or a
1166   *                 generic command code.
1167   * @param  Param2: DSC parameter or second generic parameter.
1168   * @retval HAL status
1169   */
1170 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
1171                                      uint32_t ChannelID,
1172                                      uint32_t Mode,
1173                                      uint32_t Param1,
1174                                      uint32_t Param2)
1175 {
1176   uint32_t tickstart = 0U;
1177
1178   /* Process locked */
1179   __HAL_LOCK(hdsi);
1180
1181   /* Check the parameters */
1182   assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
1183
1184   /* Get tick */
1185   tickstart = HAL_GetTick();
1186
1187   /* Wait for Command FIFO Empty */
1188   while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
1189   {
1190     /* Check for the Timeout */
1191     if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1192     {
1193       /* Process Unlocked */
1194       __HAL_UNLOCK(hdsi);
1195
1196       return HAL_TIMEOUT;
1197     }
1198   }
1199
1200   /* Configure the packet to send a short DCS command with 0 or 1 parameter */
1201   DSI_ConfigPacketHeader(hdsi->Instance,
1202                          ChannelID,
1203                          Mode,
1204                          Param1,
1205                          Param2);
1206
1207   /* Process unlocked */
1208   __HAL_UNLOCK(hdsi);
1209
1210   return HAL_OK;
1211 }
1212
1213 /**
1214   * @brief  DCS or Generic long write command
1215   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1216   *               the configuration information for the DSI.
1217   * @param  ChannelID: Virtual channel ID.
1218   * @param  Mode: DSI long packet data type.
1219   *               This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.
1220   * @param  NbParams: Number of parameters.
1221   * @param  Param1: DSC command or first generic parameter.
1222   *                 This parameter can be any value of @ref DSI_DCS_Command or a
1223   *                 generic command code
1224   * @param  ParametersTable: Pointer to parameter values table.
1225   * @retval HAL status
1226   */
1227 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
1228                                     uint32_t ChannelID,
1229                                     uint32_t Mode,
1230                                     uint32_t NbParams,
1231                                     uint32_t Param1,
1232                                     uint8_t* ParametersTable)
1233 {
1234   uint32_t uicounter = 0U, nbBytes = 0U, count = 0U;
1235   uint32_t tickstart = 0U;
1236   uint32_t fifoword = 0U;
1237
1238   /* Process locked */
1239   __HAL_LOCK(hdsi);
1240
1241   /* Check the parameters */
1242   assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
1243
1244   /* Get tick */
1245   tickstart = HAL_GetTick();
1246
1247   /* Wait for Command FIFO Empty */
1248   while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET)
1249   {
1250     /* Check for the Timeout */
1251     if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1252     {
1253       /* Process Unlocked */
1254       __HAL_UNLOCK(hdsi);
1255
1256       return HAL_TIMEOUT;
1257     }
1258   }
1259
1260   /* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/
1261   fifoword = Param1;
1262   nbBytes = (NbParams < 3U) ? NbParams : 3U;
1263
1264   for(count = 0U; count < nbBytes; count++)
1265   {
1266     fifoword |= (((uint32_t)(*(ParametersTable + count))) << (8U + (8U*count)));
1267   }
1268   hdsi->Instance->GPDR = fifoword;
1269
1270   uicounter = NbParams - nbBytes;
1271   ParametersTable += nbBytes;
1272   /* Set the Next parameters on the write FIFO command*/
1273   while(uicounter != 0U)
1274   {
1275     nbBytes = (uicounter < 4U) ? uicounter : 4U;
1276     fifoword = 0U;
1277     for(count = 0U; count < nbBytes; count++)
1278     {
1279       fifoword |= (((uint32_t)(*(ParametersTable + count))) << (8U*count));
1280     }
1281     hdsi->Instance->GPDR = fifoword;
1282
1283     uicounter -= nbBytes;
1284     ParametersTable += nbBytes;
1285   }
1286
1287   /* Configure the packet to send a long DCS command */
1288   DSI_ConfigPacketHeader(hdsi->Instance,
1289                          ChannelID,
1290                          Mode,
1291                          ((NbParams+1U)&0x00FFU),
1292                          (((NbParams+1U)&0xFF00U)>>8U));
1293
1294   /* Process unlocked */
1295   __HAL_UNLOCK(hdsi);
1296
1297   return HAL_OK;
1298 }
1299
1300 /**
1301   * @brief  Read command (DCS or generic)
1302   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1303   *               the configuration information for the DSI.
1304   * @param  ChannelNbr: Virtual channel ID
1305   * @param  Array: pointer to a buffer to store the payload of a read back operation.
1306   * @param  Size: Data size to be read (in byte).
1307   * @param  Mode: DSI read packet data type.
1308   *               This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.
1309   * @param  DCSCmd: DCS get/read command.
1310   * @param  ParametersTable: Pointer to parameter values table.
1311   * @retval HAL status
1312   */
1313 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
1314                                uint32_t ChannelNbr,
1315                                uint8_t* Array,
1316                                uint32_t Size,
1317                                uint32_t Mode,
1318                                uint32_t DCSCmd,
1319                                uint8_t* ParametersTable)
1320 {
1321   uint32_t tickstart = 0U;
1322
1323   /* Process locked */
1324   __HAL_LOCK(hdsi);
1325
1326   /* Check the parameters */
1327   assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
1328
1329   if(Size > 2U)
1330   {
1331     /* set max return packet size */
1332     HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((Size)&0xFFU), (((Size)>>8U)&0xFFU));
1333   }
1334
1335   /* Configure the packet to read command */
1336   if (Mode == DSI_DCS_SHORT_PKT_READ)
1337   {
1338     DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U);
1339   }
1340   else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
1341   {
1342     DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U);
1343   }
1344   else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
1345   {
1346     DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U);
1347   }
1348   else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
1349   {
1350     DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]);
1351   }
1352   else
1353   {
1354     /* Process Unlocked */
1355     __HAL_UNLOCK(hdsi);
1356
1357     return HAL_ERROR;
1358   }
1359
1360   /* Get tick */
1361   tickstart = HAL_GetTick();
1362
1363   /* Check that the payload read FIFO is not empty */
1364   while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE)
1365   {
1366     /* Check for the Timeout */
1367     if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1368     {
1369       /* Process Unlocked */
1370       __HAL_UNLOCK(hdsi);
1371
1372       return HAL_TIMEOUT;
1373     }
1374   }
1375
1376   /* Get the first byte */
1377   *((uint32_t *)Array) = (hdsi->Instance->GPDR);
1378   if (Size > 4U)
1379   {
1380     Size -= 4U;
1381     Array += 4U;
1382   }
1383   else
1384   {
1385     /* Process unlocked */
1386     __HAL_UNLOCK(hdsi);
1387
1388     return HAL_OK;
1389   }
1390
1391   /* Get tick */
1392   tickstart = HAL_GetTick();
1393
1394   /* Get the remaining bytes if any */
1395   while(((int)(Size)) > 0U)
1396   {
1397     if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U)
1398     {
1399       *((uint32_t *)Array) = (hdsi->Instance->GPDR);
1400       Size -= 4U;
1401       Array += 4U;
1402     }
1403
1404     /* Check for the Timeout */
1405     if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1406     {
1407       /* Process Unlocked */
1408       __HAL_UNLOCK(hdsi);
1409
1410       return HAL_TIMEOUT;
1411     }
1412   }
1413
1414   /* Process unlocked */
1415   __HAL_UNLOCK(hdsi);
1416
1417   return HAL_OK;
1418 }
1419
1420 /**
1421   * @brief  Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
1422   *         (only data lanes are in ULPM)
1423   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1424   *               the configuration information for the DSI.
1425   * @retval HAL status
1426   */
1427 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
1428 {
1429   uint32_t tickstart = 0U;
1430
1431   /* Process locked */
1432   __HAL_LOCK(hdsi);
1433
1434   /* ULPS Request on Data Lanes */
1435   hdsi->Instance->PUCR |= DSI_PUCR_URDL;
1436
1437   /* Get tick */
1438   tickstart = HAL_GetTick();
1439
1440   /* Wait until the D-PHY active lanes enter into ULPM */
1441   if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1442   {
1443         while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET)
1444     {
1445       /* Check for the Timeout */
1446       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1447       {
1448         /* Process Unlocked */
1449         __HAL_UNLOCK(hdsi);
1450
1451         return HAL_TIMEOUT;
1452       }
1453     }
1454   }
1455   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1456   {
1457         while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET)
1458     {
1459       /* Check for the Timeout */
1460       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1461       {
1462         /* Process Unlocked */
1463         __HAL_UNLOCK(hdsi);
1464
1465         return HAL_TIMEOUT;
1466       }
1467     }
1468   }
1469
1470   /* Process unlocked */
1471   __HAL_UNLOCK(hdsi);
1472
1473   return HAL_OK;
1474 }
1475
1476 /**
1477   * @brief  Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
1478   *         (only data lanes are in ULPM)
1479   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1480   *               the configuration information for the DSI.
1481   * @retval HAL status
1482   */
1483 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
1484 {
1485   uint32_t tickstart = 0U;
1486
1487   /* Process locked */
1488   __HAL_LOCK(hdsi);
1489
1490   /* Exit ULPS on Data Lanes */
1491   hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
1492
1493   /* Get tick */
1494   tickstart = HAL_GetTick();
1495
1496   /* Wait until all active lanes exit ULPM */
1497   if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1498   {
1499         while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
1500     {
1501       /* Check for the Timeout */
1502       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1503       {
1504         /* Process Unlocked */
1505         __HAL_UNLOCK(hdsi);
1506
1507         return HAL_TIMEOUT;
1508       }
1509     }
1510   }
1511   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1512   {
1513         while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
1514     {
1515       /* Check for the Timeout */
1516       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1517       {
1518         /* Process Unlocked */
1519         __HAL_UNLOCK(hdsi);
1520
1521         return HAL_TIMEOUT;
1522       }
1523     }
1524   }
1525
1526   /* wait for 1 ms*/
1527   HAL_Delay(1U);
1528
1529   /* De-assert the ULPM requests and the ULPM exit bits */
1530   hdsi->Instance->PUCR = 0U;
1531
1532   /* Process unlocked */
1533   __HAL_UNLOCK(hdsi);
1534
1535   return HAL_OK;
1536 }
1537
1538 /**
1539   * @brief  Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
1540   *         (both data and clock lanes are in ULPM)
1541   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1542   *               the configuration information for the DSI.
1543   * @retval HAL status
1544   */
1545 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
1546 {
1547   uint32_t tickstart = 0U;
1548
1549   /* Process locked */
1550   __HAL_LOCK(hdsi);
1551
1552   /* Clock lane configuration: no more HS request */
1553   hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
1554
1555   /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
1556   __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR);
1557
1558   /* ULPS Request on Clock and Data Lanes */
1559   hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);
1560
1561   /* Get tick */
1562   tickstart = HAL_GetTick();
1563
1564   /* Wait until all active lanes exit ULPM */
1565   if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1566   {
1567         while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET)
1568     {
1569       /* Check for the Timeout */
1570       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1571       {
1572         /* Process Unlocked */
1573         __HAL_UNLOCK(hdsi);
1574
1575         return HAL_TIMEOUT;
1576       }
1577     }
1578   }
1579   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1580   {
1581         while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET)
1582     {
1583       /* Check for the Timeout */
1584       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1585       {
1586         /* Process Unlocked */
1587         __HAL_UNLOCK(hdsi);
1588
1589         return HAL_TIMEOUT;
1590       }
1591     }
1592   }
1593
1594   /* Turn off the DSI PLL */
1595   __HAL_DSI_PLL_DISABLE(hdsi);
1596
1597   /* Process unlocked */
1598   __HAL_UNLOCK(hdsi);
1599
1600   return HAL_OK;
1601 }
1602
1603 /**
1604   * @brief  Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
1605   *         (both data and clock lanes are in ULPM)
1606   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1607   *               the configuration information for the DSI.
1608   * @retval HAL status
1609   */
1610 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
1611 {
1612   uint32_t tickstart = 0U;
1613
1614   /* Process locked */
1615   __HAL_LOCK(hdsi);
1616
1617   /* Turn on the DSI PLL */
1618   __HAL_DSI_PLL_ENABLE(hdsi);
1619
1620   /* Get tick */
1621   tickstart = HAL_GetTick();
1622
1623   /* Wait for the lock of the PLL */
1624   while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
1625   {
1626     /* Check for the Timeout */
1627     if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1628     {
1629       /* Process Unlocked */
1630       __HAL_UNLOCK(hdsi);
1631
1632       return HAL_TIMEOUT;
1633     }
1634   }
1635
1636   /* Exit ULPS on Clock and Data Lanes */
1637   hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
1638
1639   /* Get tick */
1640   tickstart = HAL_GetTick();
1641
1642   /* Wait until all active lanes exit ULPM */
1643   if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1644   {
1645         while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
1646     {
1647       /* Check for the Timeout */
1648       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1649       {
1650         /* Process Unlocked */
1651         __HAL_UNLOCK(hdsi);
1652
1653         return HAL_TIMEOUT;
1654       }
1655     }
1656   }
1657   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1658   {
1659         while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC))
1660     {
1661       /* Check for the Timeout */
1662       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1663       {
1664         /* Process Unlocked */
1665         __HAL_UNLOCK(hdsi);
1666
1667         return HAL_TIMEOUT;
1668       }
1669     }
1670   }
1671
1672   /* wait for 1 ms*/
1673   HAL_Delay(1U);
1674
1675   /* De-assert the ULPM requests and the ULPM exit bits */
1676   hdsi->Instance->PUCR = 0U;
1677
1678   /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
1679   __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
1680
1681   /* Restore clock lane configuration to HS */
1682   hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
1683
1684   /* Process unlocked */
1685   __HAL_UNLOCK(hdsi);
1686
1687   return HAL_OK;
1688 }
1689
1690 /**
1691   * @brief  Start test pattern generation
1692   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1693   *               the configuration information for the DSI.
1694   * @param  Mode: Pattern generator mode
1695   *          This parameter can be one of the following values:
1696   *           0 : Color bars (horizontal or vertical)
1697   *           1 : BER pattern (vertical only)
1698   * @param  Orientation: Pattern generator orientation
1699   *          This parameter can be one of the following values:
1700   *           0 : Vertical color bars
1701   *           1 : Horizontal color bars
1702   * @retval HAL status
1703   */
1704 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
1705 {
1706   /* Process locked */
1707   __HAL_LOCK(hdsi);
1708
1709   /* Configure pattern generator mode and orientation */
1710   hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
1711   hdsi->Instance->VMCR |= ((Mode<<20U) | (Orientation<<24U));
1712
1713   /* Enable pattern generator by setting PGE bit */
1714   hdsi->Instance->VMCR |= DSI_VMCR_PGE;
1715
1716   /* Process unlocked */
1717   __HAL_UNLOCK(hdsi);
1718
1719   return HAL_OK;
1720 }
1721
1722 /**
1723   * @brief  Stop test pattern generation
1724   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1725   *               the configuration information for the DSI.
1726   * @retval HAL status
1727   */
1728 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
1729 {
1730   /* Process locked */
1731   __HAL_LOCK(hdsi);
1732
1733   /* Disable pattern generator by clearing PGE bit */
1734   hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
1735
1736   /* Process unlocked */
1737   __HAL_UNLOCK(hdsi);
1738
1739   return HAL_OK;
1740 }
1741
1742 /**
1743   * @brief  Set Slew-Rate And Delay Tuning
1744   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1745   *               the configuration information for the DSI.
1746   * @param  CommDelay: Communication delay to be adjusted.
1747   *                    This parameter can be any value of @ref DSI_Communication_Delay
1748   * @param  Lane: select between clock or data lanes.
1749   *               This parameter can be any value of @ref DSI_Lane_Group
1750   * @param  Value: Custom value of the slew-rate or delay
1751   * @retval HAL status
1752   */
1753 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)
1754 {
1755   /* Process locked */
1756   __HAL_LOCK(hdsi);
1757
1758   /* Check function parameters */
1759   assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
1760   assert_param(IS_DSI_LANE_GROUP(Lane));
1761
1762   switch(CommDelay)
1763   {
1764   case DSI_SLEW_RATE_HSTX:
1765     if(Lane == DSI_CLOCK_LANE)
1766     {
1767       /* High-Speed Transmission Slew Rate Control on Clock Lane */
1768       hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL;
1769       hdsi->Instance->WPCR[1U] |= Value<<16U;
1770     }
1771     else if(Lane == DSI_DATA_LANES)
1772     {
1773       /* High-Speed Transmission Slew Rate Control on Data Lanes */
1774       hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL;
1775       hdsi->Instance->WPCR[1U] |= Value<<18U;
1776     }
1777     break;
1778   case DSI_SLEW_RATE_LPTX:
1779     if(Lane == DSI_CLOCK_LANE)
1780     {
1781       /* Low-Power transmission Slew Rate Compensation on Clock Lane */
1782       hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL;
1783       hdsi->Instance->WPCR[1U] |= Value<<6U;
1784     }
1785     else if(Lane == DSI_DATA_LANES)
1786     {
1787       /* Low-Power transmission Slew Rate Compensation on Data Lanes */
1788       hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL;
1789       hdsi->Instance->WPCR[1U] |= Value<<8U;
1790     }
1791     break;
1792   case DSI_HS_DELAY:
1793     if(Lane == DSI_CLOCK_LANE)
1794     {
1795       /* High-Speed Transmission Delay on Clock Lane */
1796       hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL;
1797       hdsi->Instance->WPCR[1U] |= Value;
1798     }
1799     else if(Lane == DSI_DATA_LANES)
1800     {
1801       /* High-Speed Transmission Delay on Data Lanes */
1802       hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL;
1803       hdsi->Instance->WPCR[1U] |= Value<<2U;
1804     }
1805     break;
1806   default:
1807     break;
1808   }
1809
1810   /* Process unlocked */
1811   __HAL_UNLOCK(hdsi);
1812
1813   return HAL_OK;
1814 }
1815
1816 /**
1817   * @brief  Low-Power Reception Filter Tuning
1818   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1819   *               the configuration information for the DSI.
1820   * @param  Frequency: cutoff frequency of low-pass filter at the input of LPRX
1821   * @retval HAL status
1822   */
1823 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
1824 {
1825   /* Process locked */
1826   __HAL_LOCK(hdsi);
1827
1828   /* Low-Power RX low-pass Filtering Tuning */
1829   hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT;
1830   hdsi->Instance->WPCR[1U] |= Frequency<<25U;
1831
1832   /* Process unlocked */
1833   __HAL_UNLOCK(hdsi);
1834
1835   return HAL_OK;
1836 }
1837
1838 /**
1839   * @brief  Activate an additional current path on all lanes to meet the SDDTx parameter
1840   *         defined in the MIPI D-PHY specification
1841   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1842   *               the configuration information for the DSI.
1843   * @param  State: ENABLE or DISABLE
1844   * @retval HAL status
1845   */
1846 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
1847 {
1848   /* Process locked */
1849   __HAL_LOCK(hdsi);
1850
1851   /* Check function parameters */
1852   assert_param(IS_FUNCTIONAL_STATE(State));
1853
1854   /* Activate/Disactivate additional current path on all lanes */
1855   hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC;
1856   hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U);
1857
1858   /* Process unlocked */
1859   __HAL_UNLOCK(hdsi);
1860
1861   return HAL_OK;
1862 }
1863
1864 /**
1865   * @brief  Custom lane pins configuration
1866   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1867   *               the configuration information for the DSI.
1868   * @param  CustomLane: Function to be applyed on selected lane.
1869   *                     This parameter can be any value of @ref DSI_CustomLane
1870   * @param  Lane: select between clock or data lane 0 or data lane 1.
1871   *               This parameter can be any value of @ref DSI_Lane_Select
1872   * @param  State: ENABLE or DISABLE
1873   * @retval HAL status
1874   */
1875 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)
1876 {
1877   /* Process locked */
1878   __HAL_LOCK(hdsi);
1879
1880   /* Check function parameters */
1881   assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
1882   assert_param(IS_DSI_LANE(Lane));
1883   assert_param(IS_FUNCTIONAL_STATE(State));
1884
1885   switch(CustomLane)
1886   {
1887   case DSI_SWAP_LANE_PINS:
1888     if(Lane == DSI_CLOCK_LANE)
1889     {
1890       /* Swap pins on clock lane */
1891       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;
1892       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U);
1893     }
1894     else if(Lane == DSI_DATA_LANE0)
1895     {
1896       /* Swap pins on data lane 0 */
1897       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;
1898       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U);
1899     }
1900     else if(Lane == DSI_DATA_LANE1)
1901     {
1902       /* Swap pins on data lane 1 */
1903       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;
1904       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U);
1905     }
1906     break;
1907   case DSI_INVERT_HS_SIGNAL:
1908     if(Lane == DSI_CLOCK_LANE)
1909     {
1910       /* Invert HS signal on clock lane */
1911       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;
1912       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U);
1913     }
1914     else if(Lane == DSI_DATA_LANE0)
1915     {
1916       /* Invert HS signal on data lane 0 */
1917       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0;
1918       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U);
1919     }
1920     else if(Lane == DSI_DATA_LANE1)
1921     {
1922       /* Invert HS signal on data lane 1 */
1923       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;
1924       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U);
1925     }
1926     break;
1927   default:
1928     break;
1929   }
1930
1931   /* Process unlocked */
1932   __HAL_UNLOCK(hdsi);
1933
1934   return HAL_OK;
1935 }
1936
1937 /**
1938   * @brief  Set custom timing for the PHY
1939   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
1940   *               the configuration information for the DSI.
1941   * @param  Timing: PHY timing to be adjusted.
1942   *                 This parameter can be any value of @ref DSI_PHY_Timing
1943   * @param  State: ENABLE or DISABLE
1944   * @param  Value: Custom value of the timing
1945   * @retval HAL status
1946   */
1947 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
1948 {
1949   /* Process locked */
1950   __HAL_LOCK(hdsi);
1951
1952   /* Check function parameters */
1953   assert_param(IS_DSI_PHY_TIMING(Timing));
1954   assert_param(IS_FUNCTIONAL_STATE(State));
1955
1956   switch(Timing)
1957   {
1958   case DSI_TCLK_POST:
1959     /* Enable/Disable custom timing setting */
1960     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;
1961     hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U);
1962
1963     if(State)
1964     {
1965       /* Set custom value */
1966       hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST;
1967       hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST;
1968     }
1969
1970     break;
1971   case DSI_TLPX_CLK:
1972     /* Enable/Disable custom timing setting */
1973     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;
1974     hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U);
1975
1976     if(State)
1977     {
1978       /* Set custom value */
1979       hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC;
1980       hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC;
1981     }
1982
1983     break;
1984   case DSI_THS_EXIT:
1985     /* Enable/Disable custom timing setting */
1986     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;
1987     hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U);
1988
1989     if(State)
1990     {
1991       /* Set custom value */
1992       hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT;
1993       hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT;
1994     }
1995
1996     break;
1997   case DSI_TLPX_DATA:
1998     /* Enable/Disable custom timing setting */
1999     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;
2000     hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U);
2001
2002     if(State)
2003     {
2004       /* Set custom value */
2005       hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD;
2006       hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD;
2007     }
2008
2009     break;
2010   case DSI_THS_ZERO:
2011     /* Enable/Disable custom timing setting */
2012     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;
2013     hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U);
2014
2015     if(State)
2016     {
2017       /* Set custom value */
2018       hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO;
2019       hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO;
2020     }
2021
2022     break;
2023   case DSI_THS_TRAIL:
2024     /* Enable/Disable custom timing setting */
2025     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;
2026     hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U);
2027
2028     if(State)
2029     {
2030       /* Set custom value */
2031       hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL;
2032       hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL;
2033     }
2034
2035     break;
2036   case DSI_THS_PREPARE:
2037     /* Enable/Disable custom timing setting */
2038     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;
2039     hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U);
2040
2041     if(State)
2042     {
2043       /* Set custom value */
2044       hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP;
2045       hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP;
2046     }
2047
2048     break;
2049   case DSI_TCLK_ZERO:
2050     /* Enable/Disable custom timing setting */
2051     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;
2052     hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U);
2053
2054     if(State)
2055     {
2056       /* Set custom value */
2057       hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO;
2058       hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO;
2059     }
2060
2061     break;
2062   case DSI_TCLK_PREPARE:
2063     /* Enable/Disable custom timing setting */
2064     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;
2065     hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U);
2066
2067     if(State)
2068     {
2069       /* Set custom value */
2070       hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP;
2071       hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP;
2072     }
2073
2074     break;
2075   default:
2076     break;
2077   }
2078
2079   /* Process unlocked */
2080   __HAL_UNLOCK(hdsi);
2081
2082   return HAL_OK;
2083 }
2084
2085 /**
2086   * @brief  Force the Clock/Data Lane in TX Stop Mode
2087   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
2088   *               the configuration information for the DSI.
2089   * @param  Lane: select between clock or data lanes.
2090   *               This parameter can be any value of @ref DSI_Lane_Group
2091   * @param  State: ENABLE or DISABLE
2092   * @retval HAL status
2093   */
2094 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
2095 {
2096   /* Process locked */
2097   __HAL_LOCK(hdsi);
2098
2099   /* Check function parameters */
2100   assert_param(IS_DSI_LANE_GROUP(Lane));
2101   assert_param(IS_FUNCTIONAL_STATE(State));
2102
2103   if(Lane == DSI_CLOCK_LANE)
2104   {
2105     /* Force/Unforce the Clock Lane in TX Stop Mode */
2106     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL;
2107     hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U);
2108   }
2109   else if(Lane == DSI_DATA_LANES)
2110   {
2111     /* Force/Unforce the Data Lanes in TX Stop Mode */
2112     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;
2113     hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U);
2114   }
2115
2116   /* Process unlocked */
2117   __HAL_UNLOCK(hdsi);
2118
2119   return HAL_OK;
2120 }
2121
2122 /**
2123   * @brief  Forces LP Receiver in Low-Power Mode
2124   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
2125   *               the configuration information for the DSI.
2126   * @param  State: ENABLE or DISABLE
2127   * @retval HAL status
2128   */
2129 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
2130 {
2131   /* Process locked */
2132   __HAL_LOCK(hdsi);
2133
2134   /* Check function parameters */
2135   assert_param(IS_FUNCTIONAL_STATE(State));
2136
2137   /* Force/Unforce LP Receiver in Low-Power Mode */
2138   hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM;
2139   hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U);
2140
2141   /* Process unlocked */
2142   __HAL_UNLOCK(hdsi);
2143
2144   return HAL_OK;
2145 }
2146
2147 /**
2148   * @brief  Force Data Lanes in RX Mode after a BTA
2149   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
2150   *               the configuration information for the DSI.
2151   * @param  State: ENABLE or DISABLE
2152   * @retval HAL status
2153   */
2154 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
2155 {
2156   /* Process locked */
2157   __HAL_LOCK(hdsi);
2158
2159   /* Check function parameters */
2160   assert_param(IS_FUNCTIONAL_STATE(State));
2161
2162   /* Force Data Lanes in RX Mode */
2163   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL;
2164   hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U);
2165
2166   /* Process unlocked */
2167   __HAL_UNLOCK(hdsi);
2168
2169   return HAL_OK;
2170 }
2171
2172 /**
2173   * @brief  Enable a pull-down on the lanes to prevent from floating states when unused
2174   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
2175   *               the configuration information for the DSI.
2176   * @param  State: ENABLE or DISABLE
2177   * @retval HAL status
2178   */
2179 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
2180 {
2181   /* Process locked */
2182   __HAL_LOCK(hdsi);
2183
2184   /* Check function parameters */
2185   assert_param(IS_FUNCTIONAL_STATE(State));
2186
2187   /* Enable/Disable pull-down on lanes */
2188   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN;
2189   hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U);
2190
2191   /* Process unlocked */
2192   __HAL_UNLOCK(hdsi);
2193
2194   return HAL_OK;
2195 }
2196
2197 /**
2198   * @brief  Switch off the contention detection on data lanes
2199   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
2200   *               the configuration information for the DSI.
2201   * @param  State: ENABLE or DISABLE
2202   * @retval HAL status
2203   */
2204 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
2205 {
2206   /* Process locked */
2207   __HAL_LOCK(hdsi);
2208
2209   /* Check function parameters */
2210   assert_param(IS_FUNCTIONAL_STATE(State));
2211
2212   /* Contention Detection on Data Lanes OFF */
2213   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL;
2214   hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U);
2215
2216   /* Process unlocked */
2217   __HAL_UNLOCK(hdsi);
2218
2219   return HAL_OK;
2220 }
2221
2222 /**
2223   * @}
2224   */
2225
2226 /** @defgroup DSI_Group4 Peripheral State and Errors functions
2227  *  @brief    Peripheral State and Errors functions
2228  *
2229 @verbatim
2230  ===============================================================================
2231                   ##### Peripheral State and Errors functions #####
2232  ===============================================================================
2233     [..]
2234     This subsection provides functions allowing to
2235       (+) Check the DSI state.
2236       (+) Get error code.
2237
2238 @endverbatim
2239   * @{
2240   */
2241
2242 /**
2243   * @brief  Return the DSI state
2244   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
2245   *               the configuration information for the DSI.
2246   * @retval HAL state
2247   */
2248 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
2249 {
2250   return hdsi->State;
2251 }
2252
2253 /**
2254   * @}
2255   */
2256
2257 /**
2258   * @}
2259   */
2260 #endif /* STM32F469xx || STM32F479xx */
2261 #endif /* HAL_DSI_MODULE_ENABLED */
2262 /**
2263   * @}
2264   */
2265
2266 /**
2267   * @}
2268   */
2269
2270 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/