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Merge pull request #11198 from SteveCEvans/sce_rc2
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_HAL_Driver / Src / stm32f4xx_hal_eth.c
blob9ee45bf12304052720afd05b948543cf19aef9d5
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_eth.c
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 14-April-2017
7 * @brief ETH HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Ethernet (ETH) peripheral:
10 * + Initialization and de-initialization functions
11 * + IO operation functions
12 * + Peripheral Control functions
13 * + Peripheral State and Errors functions
14 *
15 @verbatim
16 ==============================================================================
17 ##### How to use this driver #####
18 ==============================================================================
19 [..]
20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
21 ETH_HandleTypeDef heth;
22
23 (#)Fill parameters of Init structure in heth handle
24
25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
26
27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
28 (##) Enable the Ethernet interface clock using
29 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
30 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
31 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
32
33 (##) Initialize the related GPIO clocks
34 (##) Configure Ethernet pin-out
35 (##) Configure Ethernet NVIC interrupt (IT mode)
36
37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
40
41 (#)Enable MAC and DMA transmission and reception:
42 (##) HAL_ETH_Start();
43
44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
45 the frame to MAC TX FIFO:
46 (##) HAL_ETH_TransmitFrame();
47
48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
49 frame parameters
50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
51
52 (#) Get a received frame when an ETH RX interrupt occurs:
53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
54
55 (#) Communicate with external PHY device:
56 (##) Read a specific register from the PHY
57 HAL_ETH_ReadPHYRegister();
58 (##) Write data to a specific RHY register:
59 HAL_ETH_WritePHYRegister();
60
61 (#) Configure the Ethernet MAC after ETH peripheral initialization
62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
63
64 (#) Configure the Ethernet DMA after ETH peripheral initialization
65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
66
67 -@- The PTP protocol and the DMA descriptors ring mode are not supported
68 in this driver
69
70 @endverbatim
71 ******************************************************************************
72 * @attention
73 *
74 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
75 *
76 * Redistribution and use in source and binary forms, with or without modification,
77 * are permitted provided that the following conditions are met:
78 * 1. Redistributions of source code must retain the above copyright notice,
79 * this list of conditions and the following disclaimer.
80 * 2. Redistributions in binary form must reproduce the above copyright notice,
81 * this list of conditions and the following disclaimer in the documentation
82 * and/or other materials provided with the distribution.
83 * 3. Neither the name of STMicroelectronics nor the names of its contributors
84 * may be used to endorse or promote products derived from this software
85 * without specific prior written permission.
86 *
87 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
88 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
89 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
90 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
91 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
92 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
93 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
94 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
95 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
96 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
97 *
98 ******************************************************************************
99 */
100
101 /* Includes ------------------------------------------------------------------*/
102 #include "stm32f4xx_hal.h"
103
104 /** @addtogroup STM32F4xx_HAL_Driver
105 * @{
106 */
107
108 /** @defgroup ETH ETH
109 * @brief ETH HAL module driver
110 * @{
111 */
112
113 #ifdef HAL_ETH_MODULE_ENABLED
114
115 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
116 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
117
118 /* Private typedef -----------------------------------------------------------*/
119 /* Private define ------------------------------------------------------------*/
120 /** @defgroup ETH_Private_Constants ETH Private Constants
121 * @{
122 */
123 #define ETH_TIMEOUT_SWRESET 500U
124 #define ETH_TIMEOUT_LINKED_STATE 5000U
125 #define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U
126
127 /**
128 * @}
129 */
130 /* Private macro -------------------------------------------------------------*/
131 /* Private variables ---------------------------------------------------------*/
132 /* Private function prototypes -----------------------------------------------*/
133 /** @defgroup ETH_Private_Functions ETH Private Functions
134 * @{
135 */
136 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
137 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
138 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
139 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
140 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
141 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
142 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
143 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
144 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
145 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
146 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
147 static void ETH_Delay(uint32_t mdelay);
148
149 /**
150 * @}
151 */
152 /* Private functions ---------------------------------------------------------*/
153
154 /** @defgroup ETH_Exported_Functions ETH Exported Functions
155 * @{
156 */
157
158 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
159 * @brief Initialization and Configuration functions
160 *
161 @verbatim
162 ===============================================================================
163 ##### Initialization and de-initialization functions #####
164 ===============================================================================
165 [..] This section provides functions allowing to:
166 (+) Initialize and configure the Ethernet peripheral
167 (+) De-initialize the Ethernet peripheral
168
169 @endverbatim
170 * @{
171 */
172
173 /**
174 * @brief Initializes the Ethernet MAC and DMA according to default
175 * parameters.
176 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
177 * the configuration information for ETHERNET module
178 * @retval HAL status
179 */
180 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
181 {
182 uint32_t tmpreg1 = 0U, phyreg = 0U;
183 uint32_t hclk = 60000000U;
184 uint32_t tickstart = 0U;
185 uint32_t err = ETH_SUCCESS;
186
187 /* Check the ETH peripheral state */
188 if(heth == NULL)
189 {
190 return HAL_ERROR;
191 }
192
193 /* Check parameters */
194 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
195 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
196 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
197 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
198
199 if(heth->State == HAL_ETH_STATE_RESET)
200 {
201 /* Allocate lock resource and initialize it */
202 heth->Lock = HAL_UNLOCKED;
203 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
204 HAL_ETH_MspInit(heth);
205 }
206
207 /* Enable SYSCFG Clock */
208 __HAL_RCC_SYSCFG_CLK_ENABLE();
209
210 /* Select MII or RMII Mode*/
211 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
212 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
213
214 /* Ethernet Software reset */
215 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
216 /* After reset all the registers holds their respective reset values */
217 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
218
219 /* Get tick */
220 tickstart = HAL_GetTick();
221
222 /* Wait for software reset */
223 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
224 {
225 /* Check for the Timeout */
226 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
227 {
228 heth->State= HAL_ETH_STATE_TIMEOUT;
229
230 /* Process Unlocked */
231 __HAL_UNLOCK(heth);
232
233 /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
234 not available, please check your external PHY or the IO configuration */
235 return HAL_TIMEOUT;
236 }
237 }
238
239 /*-------------------------------- MAC Initialization ----------------------*/
240 /* Get the ETHERNET MACMIIAR value */
241 tmpreg1 = (heth->Instance)->MACMIIAR;
242 /* Clear CSR Clock Range CR[2:0] bits */
243 tmpreg1 &= ETH_MACMIIAR_CR_MASK;
244
245 /* Get hclk frequency value */
246 hclk = HAL_RCC_GetHCLKFreq();
247
248 /* Set CR bits depending on hclk value */
249 if((hclk >= 20000000U)&&(hclk < 35000000U))
250 {
251 /* CSR Clock Range between 20-35 MHz */
252 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16;
253 }
254 else if((hclk >= 35000000U)&&(hclk < 60000000U))
255 {
256 /* CSR Clock Range between 35-60 MHz */
257 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26;
258 }
259 else if((hclk >= 60000000U)&&(hclk < 100000000U))
260 {
261 /* CSR Clock Range between 60-100 MHz */
262 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42;
263 }
264 else if((hclk >= 100000000U)&&(hclk < 150000000U))
265 {
266 /* CSR Clock Range between 100-150 MHz */
267 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
268 }
269 else /* ((hclk >= 150000000)&&(hclk <= 183000000)) */
270 {
271 /* CSR Clock Range between 150-183 MHz */
272 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102;
273 }
274
275 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
276 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
277
278 /*-------------------- PHY initialization and configuration ----------------*/
279 /* Put the PHY in reset mode */
280 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
281 {
282 /* In case of write timeout */
283 err = ETH_ERROR;
284
285 /* Config MAC and DMA */
286 ETH_MACDMAConfig(heth, err);
287
288 /* Set the ETH peripheral state to READY */
289 heth->State = HAL_ETH_STATE_READY;
290
291 /* Return HAL_ERROR */
292 return HAL_ERROR;
293 }
294
295 /* Delay to assure PHY reset */
296 HAL_Delay(PHY_RESET_DELAY);
297
298 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
299 {
300 /* Get tick */
301 tickstart = HAL_GetTick();
302
303 /* We wait for linked status */
304 do
305 {
306 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
307
308 /* Check for the Timeout */
309 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
310 {
311 /* In case of write timeout */
312 err = ETH_ERROR;
313
314 /* Config MAC and DMA */
315 ETH_MACDMAConfig(heth, err);
316
317 heth->State= HAL_ETH_STATE_READY;
318
319 /* Process Unlocked */
320 __HAL_UNLOCK(heth);
321
322 return HAL_TIMEOUT;
323 }
324 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
325
326
327 /* Enable Auto-Negotiation */
328 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
329 {
330 /* In case of write timeout */
331 err = ETH_ERROR;
332
333 /* Config MAC and DMA */
334 ETH_MACDMAConfig(heth, err);
335
336 /* Set the ETH peripheral state to READY */
337 heth->State = HAL_ETH_STATE_READY;
338
339 /* Return HAL_ERROR */
340 return HAL_ERROR;
341 }
342
343 /* Get tick */
344 tickstart = HAL_GetTick();
345
346 /* Wait until the auto-negotiation will be completed */
347 do
348 {
349 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
350
351 /* Check for the Timeout */
352 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
353 {
354 /* In case of write timeout */
355 err = ETH_ERROR;
356
357 /* Config MAC and DMA */
358 ETH_MACDMAConfig(heth, err);
359
360 heth->State= HAL_ETH_STATE_READY;
361
362 /* Process Unlocked */
363 __HAL_UNLOCK(heth);
364
365 return HAL_TIMEOUT;
366 }
367
368 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
369
370 /* Read the result of the auto-negotiation */
371 if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
372 {
373 /* In case of write timeout */
374 err = ETH_ERROR;
375
376 /* Config MAC and DMA */
377 ETH_MACDMAConfig(heth, err);
378
379 /* Set the ETH peripheral state to READY */
380 heth->State = HAL_ETH_STATE_READY;
381
382 /* Return HAL_ERROR */
383 return HAL_ERROR;
384 }
385
386 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
387 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
388 {
389 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
390 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
391 }
392 else
393 {
394 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
395 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
396 }
397 /* Configure the MAC with the speed fixed by the auto-negotiation process */
398 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
399 {
400 /* Set Ethernet speed to 10M following the auto-negotiation */
401 (heth->Init).Speed = ETH_SPEED_10M;
402 }
403 else
404 {
405 /* Set Ethernet speed to 100M following the auto-negotiation */
406 (heth->Init).Speed = ETH_SPEED_100M;
407 }
408 }
409 else /* AutoNegotiation Disable */
410 {
411 /* Check parameters */
412 assert_param(IS_ETH_SPEED(heth->Init.Speed));
413 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
414
415 /* Set MAC Speed and Duplex Mode */
416 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) |
417 (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK)
418 {
419 /* In case of write timeout */
420 err = ETH_ERROR;
421
422 /* Config MAC and DMA */
423 ETH_MACDMAConfig(heth, err);
424
425 /* Set the ETH peripheral state to READY */
426 heth->State = HAL_ETH_STATE_READY;
427
428 /* Return HAL_ERROR */
429 return HAL_ERROR;
430 }
431
432 /* Delay to assure PHY configuration */
433 HAL_Delay(PHY_CONFIG_DELAY);
434 }
435
436 /* Config MAC and DMA */
437 ETH_MACDMAConfig(heth, err);
438
439 /* Set ETH HAL State to Ready */
440 heth->State= HAL_ETH_STATE_READY;
441
442 /* Return function status */
443 return HAL_OK;
444 }
445
446 /**
447 * @brief De-Initializes the ETH peripheral.
448 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
449 * the configuration information for ETHERNET module
450 * @retval HAL status
451 */
452 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
453 {
454 /* Set the ETH peripheral state to BUSY */
455 heth->State = HAL_ETH_STATE_BUSY;
456
457 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
458 HAL_ETH_MspDeInit(heth);
459
460 /* Set ETH HAL state to Disabled */
461 heth->State= HAL_ETH_STATE_RESET;
462
463 /* Release Lock */
464 __HAL_UNLOCK(heth);
465
466 /* Return function status */
467 return HAL_OK;
468 }
469
470 /**
471 * @brief Initializes the DMA Tx descriptors in chain mode.
472 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
473 * the configuration information for ETHERNET module
474 * @param DMATxDescTab: Pointer to the first Tx desc list
475 * @param TxBuff: Pointer to the first TxBuffer list
476 * @param TxBuffCount: Number of the used Tx desc in the list
477 * @retval HAL status
478 */
479 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
480 {
481 uint32_t i = 0U;
482 ETH_DMADescTypeDef *dmatxdesc;
483
484 /* Process Locked */
485 __HAL_LOCK(heth);
486
487 /* Set the ETH peripheral state to BUSY */
488 heth->State = HAL_ETH_STATE_BUSY;
489
490 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
491 heth->TxDesc = DMATxDescTab;
492
493 /* Fill each DMATxDesc descriptor with the right values */
494 for(i=0U; i < TxBuffCount; i++)
495 {
496 /* Get the pointer on the ith member of the Tx Desc list */
497 dmatxdesc = DMATxDescTab + i;
498
499 /* Set Second Address Chained bit */
500 dmatxdesc->Status = ETH_DMATXDESC_TCH;
501
502 /* Set Buffer1 address pointer */
503 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
504
505 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
506 {
507 /* Set the DMA Tx descriptors checksum insertion */
508 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
509 }
510
511 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
512 if(i < (TxBuffCount-1U))
513 {
514 /* Set next descriptor address register with next descriptor base address */
515 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U);
516 }
517 else
518 {
519 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
520 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
521 }
522 }
523
524 /* Set Transmit Descriptor List Address Register */
525 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
526
527 /* Set ETH HAL State to Ready */
528 heth->State= HAL_ETH_STATE_READY;
529
530 /* Process Unlocked */
531 __HAL_UNLOCK(heth);
532
533 /* Return function status */
534 return HAL_OK;
535 }
536
537 /**
538 * @brief Initializes the DMA Rx descriptors in chain mode.
539 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
540 * the configuration information for ETHERNET module
541 * @param DMARxDescTab: Pointer to the first Rx desc list
542 * @param RxBuff: Pointer to the first RxBuffer list
543 * @param RxBuffCount: Number of the used Rx desc in the list
544 * @retval HAL status
545 */
546 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
547 {
548 uint32_t i = 0U;
549 ETH_DMADescTypeDef *DMARxDesc;
550
551 /* Process Locked */
552 __HAL_LOCK(heth);
553
554 /* Set the ETH peripheral state to BUSY */
555 heth->State = HAL_ETH_STATE_BUSY;
556
557 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
558 heth->RxDesc = DMARxDescTab;
559
560 /* Fill each DMARxDesc descriptor with the right values */
561 for(i=0U; i < RxBuffCount; i++)
562 {
563 /* Get the pointer on the ith member of the Rx Desc list */
564 DMARxDesc = DMARxDescTab+i;
565
566 /* Set Own bit of the Rx descriptor Status */
567 DMARxDesc->Status = ETH_DMARXDESC_OWN;
568
569 /* Set Buffer1 size and Second Address Chained bit */
570 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
571
572 /* Set Buffer1 address pointer */
573 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
574
575 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
576 {
577 /* Enable Ethernet DMA Rx Descriptor interrupt */
578 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
579 }
580
581 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
582 if(i < (RxBuffCount-1U))
583 {
584 /* Set next descriptor address register with next descriptor base address */
585 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U);
586 }
587 else
588 {
589 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
590 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
591 }
592 }
593
594 /* Set Receive Descriptor List Address Register */
595 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
596
597 /* Set ETH HAL State to Ready */
598 heth->State= HAL_ETH_STATE_READY;
599
600 /* Process Unlocked */
601 __HAL_UNLOCK(heth);
602
603 /* Return function status */
604 return HAL_OK;
605 }
606
607 /**
608 * @brief Initializes the ETH MSP.
609 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
610 * the configuration information for ETHERNET module
611 * @retval None
612 */
613 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
614 {
615 /* Prevent unused argument(s) compilation warning */
616 UNUSED(heth);
617 /* NOTE : This function Should not be modified, when the callback is needed,
618 the HAL_ETH_MspInit could be implemented in the user file
619 */
620 }
621
622 /**
623 * @brief DeInitializes ETH MSP.
624 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
625 * the configuration information for ETHERNET module
626 * @retval None
627 */
628 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
629 {
630 /* Prevent unused argument(s) compilation warning */
631 UNUSED(heth);
632 /* NOTE : This function Should not be modified, when the callback is needed,
633 the HAL_ETH_MspDeInit could be implemented in the user file
634 */
635 }
636
637 /**
638 * @}
639 */
640
641 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
642 * @brief Data transfers functions
643 *
644 @verbatim
645 ==============================================================================
646 ##### IO operation functions #####
647 ==============================================================================
648 [..] This section provides functions allowing to:
649 (+) Transmit a frame
650 HAL_ETH_TransmitFrame();
651 (+) Receive a frame
652 HAL_ETH_GetReceivedFrame();
653 HAL_ETH_GetReceivedFrame_IT();
654 (+) Read from an External PHY register
655 HAL_ETH_ReadPHYRegister();
656 (+) Write to an External PHY register
657 HAL_ETH_WritePHYRegister();
658
659 @endverbatim
660
661 * @{
662 */
663
664 /**
665 * @brief Sends an Ethernet frame.
666 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
667 * the configuration information for ETHERNET module
668 * @param FrameLength: Amount of data to be sent
669 * @retval HAL status
670 */
671 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
672 {
673 uint32_t bufcount = 0U, size = 0U, i = 0U;
674
675 /* Process Locked */
676 __HAL_LOCK(heth);
677
678 /* Set the ETH peripheral state to BUSY */
679 heth->State = HAL_ETH_STATE_BUSY;
680
681 if (FrameLength == 0U)
682 {
683 /* Set ETH HAL state to READY */
684 heth->State = HAL_ETH_STATE_READY;
685
686 /* Process Unlocked */
687 __HAL_UNLOCK(heth);
688
689 return HAL_ERROR;
690 }
691
692 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
693 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
694 {
695 /* OWN bit set */
696 heth->State = HAL_ETH_STATE_BUSY_TX;
697
698 /* Process Unlocked */
699 __HAL_UNLOCK(heth);
700
701 return HAL_ERROR;
702 }
703
704 /* Get the number of needed Tx buffers for the current frame */
705 if (FrameLength > ETH_TX_BUF_SIZE)
706 {
707 bufcount = FrameLength/ETH_TX_BUF_SIZE;
708 if (FrameLength % ETH_TX_BUF_SIZE)
709 {
710 bufcount++;
711 }
712 }
713 else
714 {
715 bufcount = 1U;
716 }
717 if (bufcount == 1U)
718 {
719 /* Set LAST and FIRST segment */
720 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
721 /* Set frame size */
722 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
723 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
724 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
725 /* Point to next descriptor */
726 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
727 }
728 else
729 {
730 for (i=0U; i< bufcount; i++)
731 {
732 /* Clear FIRST and LAST segment bits */
733 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
734
735 if (i == 0U)
736 {
737 /* Setting the first segment bit */
738 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
739 }
740
741 /* Program size */
742 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
743
744 if (i == (bufcount-1U))
745 {
746 /* Setting the last segment bit */
747 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
748 size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE;
749 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
750 }
751
752 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
753 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
754 /* point to next descriptor */
755 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
756 }
757 }
758
759 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
760 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
761 {
762 /* Clear TBUS ETHERNET DMA flag */
763 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
764 /* Resume DMA transmission*/
765 (heth->Instance)->DMATPDR = 0U;
766 }
767
768 /* Set ETH HAL State to Ready */
769 heth->State = HAL_ETH_STATE_READY;
770
771 /* Process Unlocked */
772 __HAL_UNLOCK(heth);
773
774 /* Return function status */
775 return HAL_OK;
776 }
777
778 /**
779 * @brief Checks for received frames.
780 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
781 * the configuration information for ETHERNET module
782 * @retval HAL status
783 */
784 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
785 {
786 uint32_t framelength = 0U;
787
788 /* Process Locked */
789 __HAL_LOCK(heth);
790
791 /* Check the ETH state to BUSY */
792 heth->State = HAL_ETH_STATE_BUSY;
793
794 /* Check if segment is not owned by DMA */
795 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
796 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
797 {
798 /* Check if last segment */
799 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
800 {
801 /* increment segment count */
802 (heth->RxFrameInfos).SegCount++;
803
804 /* Check if last segment is first segment: one segment contains the frame */
805 if ((heth->RxFrameInfos).SegCount == 1U)
806 {
807 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
808 }
809
810 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
811
812 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
813 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
814 heth->RxFrameInfos.length = framelength;
815
816 /* Get the address of the buffer start address */
817 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
818 /* point to next descriptor */
819 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
820
821 /* Set HAL State to Ready */
822 heth->State = HAL_ETH_STATE_READY;
823
824 /* Process Unlocked */
825 __HAL_UNLOCK(heth);
826
827 /* Return function status */
828 return HAL_OK;
829 }
830 /* Check if first segment */
831 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
832 {
833 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
834 (heth->RxFrameInfos).LSRxDesc = NULL;
835 (heth->RxFrameInfos).SegCount = 1U;
836 /* Point to next descriptor */
837 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
838 }
839 /* Check if intermediate segment */
840 else
841 {
842 (heth->RxFrameInfos).SegCount++;
843 /* Point to next descriptor */
844 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
845 }
846 }
847
848 /* Set ETH HAL State to Ready */
849 heth->State = HAL_ETH_STATE_READY;
850
851 /* Process Unlocked */
852 __HAL_UNLOCK(heth);
853
854 /* Return function status */
855 return HAL_ERROR;
856 }
857
858 /**
859 * @brief Gets the Received frame in interrupt mode.
860 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
861 * the configuration information for ETHERNET module
862 * @retval HAL status
863 */
864 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
865 {
866 uint32_t descriptorscancounter = 0U;
867
868 /* Process Locked */
869 __HAL_LOCK(heth);
870
871 /* Set ETH HAL State to BUSY */
872 heth->State = HAL_ETH_STATE_BUSY;
873
874 /* Scan descriptors owned by CPU */
875 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
876 {
877 /* Just for security */
878 descriptorscancounter++;
879
880 /* Check if first segment in frame */
881 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
882 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
883 {
884 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
885 heth->RxFrameInfos.SegCount = 1U;
886 /* Point to next descriptor */
887 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
888 }
889 /* Check if intermediate segment */
890 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
891 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
892 {
893 /* Increment segment count */
894 (heth->RxFrameInfos.SegCount)++;
895 /* Point to next descriptor */
896 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
897 }
898 /* Should be last segment */
899 else
900 {
901 /* Last segment */
902 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
903
904 /* Increment segment count */
905 (heth->RxFrameInfos.SegCount)++;
906
907 /* Check if last segment is first segment: one segment contains the frame */
908 if ((heth->RxFrameInfos.SegCount) == 1U)
909 {
910 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
911 }
912
913 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
914 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
915
916 /* Get the address of the buffer start address */
917 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
918
919 /* Point to next descriptor */
920 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
921
922 /* Set HAL State to Ready */
923 heth->State = HAL_ETH_STATE_READY;
924
925 /* Process Unlocked */
926 __HAL_UNLOCK(heth);
927
928 /* Return function status */
929 return HAL_OK;
930 }
931 }
932
933 /* Set HAL State to Ready */
934 heth->State = HAL_ETH_STATE_READY;
935
936 /* Process Unlocked */
937 __HAL_UNLOCK(heth);
938
939 /* Return function status */
940 return HAL_ERROR;
941 }
942
943 /**
944 * @brief This function handles ETH interrupt request.
945 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
946 * the configuration information for ETHERNET module
947 * @retval HAL status
948 */
949 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
950 {
951 /* Frame received */
952 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
953 {
954 /* Receive complete callback */
955 HAL_ETH_RxCpltCallback(heth);
956
957 /* Clear the Eth DMA Rx IT pending bits */
958 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
959
960 /* Set HAL State to Ready */
961 heth->State = HAL_ETH_STATE_READY;
962
963 /* Process Unlocked */
964 __HAL_UNLOCK(heth);
965
966 }
967 /* Frame transmitted */
968 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
969 {
970 /* Transfer complete callback */
971 HAL_ETH_TxCpltCallback(heth);
972
973 /* Clear the Eth DMA Tx IT pending bits */
974 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
975
976 /* Set HAL State to Ready */
977 heth->State = HAL_ETH_STATE_READY;
978
979 /* Process Unlocked */
980 __HAL_UNLOCK(heth);
981 }
982
983 /* Clear the interrupt flags */
984 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
985
986 /* ETH DMA Error */
987 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
988 {
989 /* Ethernet Error callback */
990 HAL_ETH_ErrorCallback(heth);
991
992 /* Clear the interrupt flags */
993 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
994
995 /* Set HAL State to Ready */
996 heth->State = HAL_ETH_STATE_READY;
997
998 /* Process Unlocked */
999 __HAL_UNLOCK(heth);
1000 }
1001 }
1002
1003 /**
1004 * @brief Tx Transfer completed callbacks.
1005 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1006 * the configuration information for ETHERNET module
1007 * @retval None
1008 */
1009 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
1010 {
1011 /* Prevent unused argument(s) compilation warning */
1012 UNUSED(heth);
1013 /* NOTE : This function Should not be modified, when the callback is needed,
1014 the HAL_ETH_TxCpltCallback could be implemented in the user file
1015 */
1016 }
1017
1018 /**
1019 * @brief Rx Transfer completed callbacks.
1020 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1021 * the configuration information for ETHERNET module
1022 * @retval None
1023 */
1024 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
1025 {
1026 /* Prevent unused argument(s) compilation warning */
1027 UNUSED(heth);
1028 /* NOTE : This function Should not be modified, when the callback is needed,
1029 the HAL_ETH_TxCpltCallback could be implemented in the user file
1030 */
1031 }
1032
1033 /**
1034 * @brief Ethernet transfer error callbacks
1035 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1036 * the configuration information for ETHERNET module
1037 * @retval None
1038 */
1039 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
1040 {
1041 /* Prevent unused argument(s) compilation warning */
1042 UNUSED(heth);
1043 /* NOTE : This function Should not be modified, when the callback is needed,
1044 the HAL_ETH_TxCpltCallback could be implemented in the user file
1045 */
1046 }
1047
1048 /**
1049 * @brief Reads a PHY register
1050 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1051 * the configuration information for ETHERNET module
1052 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
1053 * This parameter can be one of the following values:
1054 * PHY_BCR: Transceiver Basic Control Register,
1055 * PHY_BSR: Transceiver Basic Status Register.
1056 * More PHY register could be read depending on the used PHY
1057 * @param RegValue: PHY register value
1058 * @retval HAL status
1059 */
1060 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
1061 {
1062 uint32_t tmpreg1 = 0U;
1063 uint32_t tickstart = 0U;
1064
1065 /* Check parameters */
1066 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
1067
1068 /* Check the ETH peripheral state */
1069 if(heth->State == HAL_ETH_STATE_BUSY_RD)
1070 {
1071 return HAL_BUSY;
1072 }
1073 /* Set ETH HAL State to BUSY_RD */
1074 heth->State = HAL_ETH_STATE_BUSY_RD;
1075
1076 /* Get the ETHERNET MACMIIAR value */
1077 tmpreg1 = heth->Instance->MACMIIAR;
1078
1079 /* Keep only the CSR Clock Range CR[2:0] bits value */
1080 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
1081
1082 /* Prepare the MII address register value */
1083 tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
1084 tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
1085 tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
1086 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
1087
1088 /* Write the result value into the MII Address register */
1089 heth->Instance->MACMIIAR = tmpreg1;
1090
1091 /* Get tick */
1092 tickstart = HAL_GetTick();
1093
1094 /* Check for the Busy flag */
1095 while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
1096 {
1097 /* Check for the Timeout */
1098 if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
1099 {
1100 heth->State= HAL_ETH_STATE_READY;
1101
1102 /* Process Unlocked */
1103 __HAL_UNLOCK(heth);
1104
1105 return HAL_TIMEOUT;
1106 }
1107
1108 tmpreg1 = heth->Instance->MACMIIAR;
1109 }
1110
1111 /* Get MACMIIDR value */
1112 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
1113
1114 /* Set ETH HAL State to READY */
1115 heth->State = HAL_ETH_STATE_READY;
1116
1117 /* Return function status */
1118 return HAL_OK;
1119 }
1120
1121 /**
1122 * @brief Writes to a PHY register.
1123 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1124 * the configuration information for ETHERNET module
1125 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
1126 * This parameter can be one of the following values:
1127 * PHY_BCR: Transceiver Control Register.
1128 * More PHY register could be written depending on the used PHY
1129 * @param RegValue: the value to write
1130 * @retval HAL status
1131 */
1132 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
1133 {
1134 uint32_t tmpreg1 = 0U;
1135 uint32_t tickstart = 0U;
1136
1137 /* Check parameters */
1138 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
1139
1140 /* Check the ETH peripheral state */
1141 if(heth->State == HAL_ETH_STATE_BUSY_WR)
1142 {
1143 return HAL_BUSY;
1144 }
1145 /* Set ETH HAL State to BUSY_WR */
1146 heth->State = HAL_ETH_STATE_BUSY_WR;
1147
1148 /* Get the ETHERNET MACMIIAR value */
1149 tmpreg1 = heth->Instance->MACMIIAR;
1150
1151 /* Keep only the CSR Clock Range CR[2:0] bits value */
1152 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
1153
1154 /* Prepare the MII register address value */
1155 tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
1156 tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
1157 tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
1158 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
1159
1160 /* Give the value to the MII data register */
1161 heth->Instance->MACMIIDR = (uint16_t)RegValue;
1162
1163 /* Write the result value into the MII Address register */
1164 heth->Instance->MACMIIAR = tmpreg1;
1165
1166 /* Get tick */
1167 tickstart = HAL_GetTick();
1168
1169 /* Check for the Busy flag */
1170 while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
1171 {
1172 /* Check for the Timeout */
1173 if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
1174 {
1175 heth->State= HAL_ETH_STATE_READY;
1176
1177 /* Process Unlocked */
1178 __HAL_UNLOCK(heth);
1179
1180 return HAL_TIMEOUT;
1181 }
1182
1183 tmpreg1 = heth->Instance->MACMIIAR;
1184 }
1185
1186 /* Set ETH HAL State to READY */
1187 heth->State = HAL_ETH_STATE_READY;
1188
1189 /* Return function status */
1190 return HAL_OK;
1191 }
1192
1193 /**
1194 * @}
1195 */
1196
1197 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
1198 * @brief Peripheral Control functions
1199 *
1200 @verbatim
1201 ===============================================================================
1202 ##### Peripheral Control functions #####
1203 ===============================================================================
1204 [..] This section provides functions allowing to:
1205 (+) Enable MAC and DMA transmission and reception.
1206 HAL_ETH_Start();
1207 (+) Disable MAC and DMA transmission and reception.
1208 HAL_ETH_Stop();
1209 (+) Set the MAC configuration in runtime mode
1210 HAL_ETH_ConfigMAC();
1211 (+) Set the DMA configuration in runtime mode
1212 HAL_ETH_ConfigDMA();
1213
1214 @endverbatim
1215 * @{
1216 */
1217
1218 /**
1219 * @brief Enables Ethernet MAC and DMA reception/transmission
1220 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1221 * the configuration information for ETHERNET module
1222 * @retval HAL status
1223 */
1224 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
1225 {
1226 /* Process Locked */
1227 __HAL_LOCK(heth);
1228
1229 /* Set the ETH peripheral state to BUSY */
1230 heth->State = HAL_ETH_STATE_BUSY;
1231
1232 /* Enable transmit state machine of the MAC for transmission on the MII */
1233 ETH_MACTransmissionEnable(heth);
1234
1235 /* Enable receive state machine of the MAC for reception from the MII */
1236 ETH_MACReceptionEnable(heth);
1237
1238 /* Flush Transmit FIFO */
1239 ETH_FlushTransmitFIFO(heth);
1240
1241 /* Start DMA transmission */
1242 ETH_DMATransmissionEnable(heth);
1243
1244 /* Start DMA reception */
1245 ETH_DMAReceptionEnable(heth);
1246
1247 /* Set the ETH state to READY*/
1248 heth->State= HAL_ETH_STATE_READY;
1249
1250 /* Process Unlocked */
1251 __HAL_UNLOCK(heth);
1252
1253 /* Return function status */
1254 return HAL_OK;
1255 }
1256
1257 /**
1258 * @brief Stop Ethernet MAC and DMA reception/transmission
1259 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1260 * the configuration information for ETHERNET module
1261 * @retval HAL status
1262 */
1263 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
1264 {
1265 /* Process Locked */
1266 __HAL_LOCK(heth);
1267
1268 /* Set the ETH peripheral state to BUSY */
1269 heth->State = HAL_ETH_STATE_BUSY;
1270
1271 /* Stop DMA transmission */
1272 ETH_DMATransmissionDisable(heth);
1273
1274 /* Stop DMA reception */
1275 ETH_DMAReceptionDisable(heth);
1276
1277 /* Disable receive state machine of the MAC for reception from the MII */
1278 ETH_MACReceptionDisable(heth);
1279
1280 /* Flush Transmit FIFO */
1281 ETH_FlushTransmitFIFO(heth);
1282
1283 /* Disable transmit state machine of the MAC for transmission on the MII */
1284 ETH_MACTransmissionDisable(heth);
1285
1286 /* Set the ETH state*/
1287 heth->State = HAL_ETH_STATE_READY;
1288
1289 /* Process Unlocked */
1290 __HAL_UNLOCK(heth);
1291
1292 /* Return function status */
1293 return HAL_OK;
1294 }
1295
1296 /**
1297 * @brief Set ETH MAC Configuration.
1298 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1299 * the configuration information for ETHERNET module
1300 * @param macconf: MAC Configuration structure
1301 * @retval HAL status
1302 */
1303 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
1304 {
1305 uint32_t tmpreg1 = 0U;
1306
1307 /* Process Locked */
1308 __HAL_LOCK(heth);
1309
1310 /* Set the ETH peripheral state to BUSY */
1311 heth->State= HAL_ETH_STATE_BUSY;
1312
1313 assert_param(IS_ETH_SPEED(heth->Init.Speed));
1314 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
1315
1316 if (macconf != NULL)
1317 {
1318 /* Check the parameters */
1319 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
1320 assert_param(IS_ETH_JABBER(macconf->Jabber));
1321 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
1322 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
1323 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
1324 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
1325 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
1326 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
1327 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
1328 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
1329 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
1330 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
1331 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
1332 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
1333 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
1334 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
1335 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
1336 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
1337 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
1338 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
1339 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
1340 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
1341 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
1342 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
1343 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
1344 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
1345 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
1346
1347 /*------------------------ ETHERNET MACCR Configuration --------------------*/
1348 /* Get the ETHERNET MACCR value */
1349 tmpreg1 = (heth->Instance)->MACCR;
1350 /* Clear WD, PCE, PS, TE and RE bits */
1351 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
1352
1353 tmpreg1 |= (uint32_t)(macconf->Watchdog |
1354 macconf->Jabber |
1355 macconf->InterFrameGap |
1356 macconf->CarrierSense |
1357 (heth->Init).Speed |
1358 macconf->ReceiveOwn |
1359 macconf->LoopbackMode |
1360 (heth->Init).DuplexMode |
1361 macconf->ChecksumOffload |
1362 macconf->RetryTransmission |
1363 macconf->AutomaticPadCRCStrip |
1364 macconf->BackOffLimit |
1365 macconf->DeferralCheck);
1366
1367 /* Write to ETHERNET MACCR */
1368 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
1369
1370 /* Wait until the write operation will be taken into account :
1371 at least four TX_CLK/RX_CLK clock cycles */
1372 tmpreg1 = (heth->Instance)->MACCR;
1373 HAL_Delay(ETH_REG_WRITE_DELAY);
1374 (heth->Instance)->MACCR = tmpreg1;
1375
1376 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
1377 /* Write to ETHERNET MACFFR */
1378 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
1379 macconf->SourceAddrFilter |
1380 macconf->PassControlFrames |
1381 macconf->BroadcastFramesReception |
1382 macconf->DestinationAddrFilter |
1383 macconf->PromiscuousMode |
1384 macconf->MulticastFramesFilter |
1385 macconf->UnicastFramesFilter);
1386
1387 /* Wait until the write operation will be taken into account :
1388 at least four TX_CLK/RX_CLK clock cycles */
1389 tmpreg1 = (heth->Instance)->MACFFR;
1390 HAL_Delay(ETH_REG_WRITE_DELAY);
1391 (heth->Instance)->MACFFR = tmpreg1;
1392
1393 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
1394 /* Write to ETHERNET MACHTHR */
1395 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
1396
1397 /* Write to ETHERNET MACHTLR */
1398 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
1399 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
1400
1401 /* Get the ETHERNET MACFCR value */
1402 tmpreg1 = (heth->Instance)->MACFCR;
1403 /* Clear xx bits */
1404 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
1405
1406 tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
1407 macconf->ZeroQuantaPause |
1408 macconf->PauseLowThreshold |
1409 macconf->UnicastPauseFrameDetect |
1410 macconf->ReceiveFlowControl |
1411 macconf->TransmitFlowControl);
1412
1413 /* Write to ETHERNET MACFCR */
1414 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
1415
1416 /* Wait until the write operation will be taken into account :
1417 at least four TX_CLK/RX_CLK clock cycles */
1418 tmpreg1 = (heth->Instance)->MACFCR;
1419 HAL_Delay(ETH_REG_WRITE_DELAY);
1420 (heth->Instance)->MACFCR = tmpreg1;
1421
1422 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
1423 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
1424 macconf->VLANTagIdentifier);
1425
1426 /* Wait until the write operation will be taken into account :
1427 at least four TX_CLK/RX_CLK clock cycles */
1428 tmpreg1 = (heth->Instance)->MACVLANTR;
1429 HAL_Delay(ETH_REG_WRITE_DELAY);
1430 (heth->Instance)->MACVLANTR = tmpreg1;
1431 }
1432 else /* macconf == NULL : here we just configure Speed and Duplex mode */
1433 {
1434 /*------------------------ ETHERNET MACCR Configuration --------------------*/
1435 /* Get the ETHERNET MACCR value */
1436 tmpreg1 = (heth->Instance)->MACCR;
1437
1438 /* Clear FES and DM bits */
1439 tmpreg1 &= ~(0x00004800U);
1440
1441 tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
1442
1443 /* Write to ETHERNET MACCR */
1444 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
1445
1446 /* Wait until the write operation will be taken into account:
1447 at least four TX_CLK/RX_CLK clock cycles */
1448 tmpreg1 = (heth->Instance)->MACCR;
1449 HAL_Delay(ETH_REG_WRITE_DELAY);
1450 (heth->Instance)->MACCR = tmpreg1;
1451 }
1452
1453 /* Set the ETH state to Ready */
1454 heth->State= HAL_ETH_STATE_READY;
1455
1456 /* Process Unlocked */
1457 __HAL_UNLOCK(heth);
1458
1459 /* Return function status */
1460 return HAL_OK;
1461 }
1462
1463 /**
1464 * @brief Sets ETH DMA Configuration.
1465 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1466 * the configuration information for ETHERNET module
1467 * @param dmaconf: DMA Configuration structure
1468 * @retval HAL status
1469 */
1470 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
1471 {
1472 uint32_t tmpreg1 = 0U;
1473
1474 /* Process Locked */
1475 __HAL_LOCK(heth);
1476
1477 /* Set the ETH peripheral state to BUSY */
1478 heth->State= HAL_ETH_STATE_BUSY;
1479
1480 /* Check parameters */
1481 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
1482 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
1483 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
1484 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
1485 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
1486 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
1487 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
1488 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
1489 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
1490 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
1491 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
1492 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
1493 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
1494 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
1495 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
1496 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
1497
1498 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
1499 /* Get the ETHERNET DMAOMR value */
1500 tmpreg1 = (heth->Instance)->DMAOMR;
1501 /* Clear xx bits */
1502 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
1503
1504 tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
1505 dmaconf->ReceiveStoreForward |
1506 dmaconf->FlushReceivedFrame |
1507 dmaconf->TransmitStoreForward |
1508 dmaconf->TransmitThresholdControl |
1509 dmaconf->ForwardErrorFrames |
1510 dmaconf->ForwardUndersizedGoodFrames |
1511 dmaconf->ReceiveThresholdControl |
1512 dmaconf->SecondFrameOperate);
1513
1514 /* Write to ETHERNET DMAOMR */
1515 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
1516
1517 /* Wait until the write operation will be taken into account:
1518 at least four TX_CLK/RX_CLK clock cycles */
1519 tmpreg1 = (heth->Instance)->DMAOMR;
1520 HAL_Delay(ETH_REG_WRITE_DELAY);
1521 (heth->Instance)->DMAOMR = tmpreg1;
1522
1523 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
1524 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
1525 dmaconf->FixedBurst |
1526 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
1527 dmaconf->TxDMABurstLength |
1528 dmaconf->EnhancedDescriptorFormat |
1529 (dmaconf->DescriptorSkipLength << 2U) |
1530 dmaconf->DMAArbitration |
1531 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
1532
1533 /* Wait until the write operation will be taken into account:
1534 at least four TX_CLK/RX_CLK clock cycles */
1535 tmpreg1 = (heth->Instance)->DMABMR;
1536 HAL_Delay(ETH_REG_WRITE_DELAY);
1537 (heth->Instance)->DMABMR = tmpreg1;
1538
1539 /* Set the ETH state to Ready */
1540 heth->State= HAL_ETH_STATE_READY;
1541
1542 /* Process Unlocked */
1543 __HAL_UNLOCK(heth);
1544
1545 /* Return function status */
1546 return HAL_OK;
1547 }
1548
1549 /**
1550 * @}
1551 */
1552
1553 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
1554 * @brief Peripheral State functions
1555 *
1556 @verbatim
1557 ===============================================================================
1558 ##### Peripheral State functions #####
1559 ===============================================================================
1560 [..]
1561 This subsection permits to get in run-time the status of the peripheral
1562 and the data flow.
1563 (+) Get the ETH handle state:
1564 HAL_ETH_GetState();
1565
1566
1567 @endverbatim
1568 * @{
1569 */
1570
1571 /**
1572 * @brief Return the ETH HAL state
1573 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1574 * the configuration information for ETHERNET module
1575 * @retval HAL state
1576 */
1577 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
1578 {
1579 /* Return ETH state */
1580 return heth->State;
1581 }
1582
1583 /**
1584 * @}
1585 */
1586
1587 /**
1588 * @}
1589 */
1590
1591 /** @addtogroup ETH_Private_Functions
1592 * @{
1593 */
1594
1595 /**
1596 * @brief Configures Ethernet MAC and DMA with default parameters.
1597 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1598 * the configuration information for ETHERNET module
1599 * @param err: Ethernet Init error
1600 * @retval HAL status
1601 */
1602 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
1603 {
1604 ETH_MACInitTypeDef macinit;
1605 ETH_DMAInitTypeDef dmainit;
1606 uint32_t tmpreg1 = 0U;
1607
1608 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
1609 {
1610 /* Set Ethernet duplex mode to Full-duplex */
1611 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
1612
1613 /* Set Ethernet speed to 100M */
1614 (heth->Init).Speed = ETH_SPEED_100M;
1615 }
1616
1617 /* Ethernet MAC default initialization **************************************/
1618 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
1619 macinit.Jabber = ETH_JABBER_ENABLE;
1620 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
1621 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
1622 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
1623 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
1624 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
1625 {
1626 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
1627 }
1628 else
1629 {
1630 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
1631 }
1632 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
1633 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
1634 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
1635 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
1636 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
1637 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
1638 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
1639 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
1640 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
1641 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
1642 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
1643 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
1644 macinit.HashTableHigh = 0x0U;
1645 macinit.HashTableLow = 0x0U;
1646 macinit.PauseTime = 0x0U;
1647 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
1648 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
1649 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
1650 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
1651 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
1652 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
1653 macinit.VLANTagIdentifier = 0x0U;
1654
1655 /*------------------------ ETHERNET MACCR Configuration --------------------*/
1656 /* Get the ETHERNET MACCR value */
1657 tmpreg1 = (heth->Instance)->MACCR;
1658 /* Clear WD, PCE, PS, TE and RE bits */
1659 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
1660 /* Set the WD bit according to ETH Watchdog value */
1661 /* Set the JD: bit according to ETH Jabber value */
1662 /* Set the IFG bit according to ETH InterFrameGap value */
1663 /* Set the DCRS bit according to ETH CarrierSense value */
1664 /* Set the FES bit according to ETH Speed value */
1665 /* Set the DO bit according to ETH ReceiveOwn value */
1666 /* Set the LM bit according to ETH LoopbackMode value */
1667 /* Set the DM bit according to ETH Mode value */
1668 /* Set the IPCO bit according to ETH ChecksumOffload value */
1669 /* Set the DR bit according to ETH RetryTransmission value */
1670 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
1671 /* Set the BL bit according to ETH BackOffLimit value */
1672 /* Set the DC bit according to ETH DeferralCheck value */
1673 tmpreg1 |= (uint32_t)(macinit.Watchdog |
1674 macinit.Jabber |
1675 macinit.InterFrameGap |
1676 macinit.CarrierSense |
1677 (heth->Init).Speed |
1678 macinit.ReceiveOwn |
1679 macinit.LoopbackMode |
1680 (heth->Init).DuplexMode |
1681 macinit.ChecksumOffload |
1682 macinit.RetryTransmission |
1683 macinit.AutomaticPadCRCStrip |
1684 macinit.BackOffLimit |
1685 macinit.DeferralCheck);
1686
1687 /* Write to ETHERNET MACCR */
1688 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
1689
1690 /* Wait until the write operation will be taken into account:
1691 at least four TX_CLK/RX_CLK clock cycles */
1692 tmpreg1 = (heth->Instance)->MACCR;
1693 HAL_Delay(ETH_REG_WRITE_DELAY);
1694 (heth->Instance)->MACCR = tmpreg1;
1695
1696 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
1697 /* Set the RA bit according to ETH ReceiveAll value */
1698 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
1699 /* Set the PCF bit according to ETH PassControlFrames value */
1700 /* Set the DBF bit according to ETH BroadcastFramesReception value */
1701 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
1702 /* Set the PR bit according to ETH PromiscuousMode value */
1703 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
1704 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
1705 /* Write to ETHERNET MACFFR */
1706 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
1707 macinit.SourceAddrFilter |
1708 macinit.PassControlFrames |
1709 macinit.BroadcastFramesReception |
1710 macinit.DestinationAddrFilter |
1711 macinit.PromiscuousMode |
1712 macinit.MulticastFramesFilter |
1713 macinit.UnicastFramesFilter);
1714
1715 /* Wait until the write operation will be taken into account:
1716 at least four TX_CLK/RX_CLK clock cycles */
1717 tmpreg1 = (heth->Instance)->MACFFR;
1718 HAL_Delay(ETH_REG_WRITE_DELAY);
1719 (heth->Instance)->MACFFR = tmpreg1;
1720
1721 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
1722 /* Write to ETHERNET MACHTHR */
1723 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
1724
1725 /* Write to ETHERNET MACHTLR */
1726 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
1727 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
1728
1729 /* Get the ETHERNET MACFCR value */
1730 tmpreg1 = (heth->Instance)->MACFCR;
1731 /* Clear xx bits */
1732 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
1733
1734 /* Set the PT bit according to ETH PauseTime value */
1735 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
1736 /* Set the PLT bit according to ETH PauseLowThreshold value */
1737 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
1738 /* Set the RFE bit according to ETH ReceiveFlowControl value */
1739 /* Set the TFE bit according to ETH TransmitFlowControl value */
1740 tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) |
1741 macinit.ZeroQuantaPause |
1742 macinit.PauseLowThreshold |
1743 macinit.UnicastPauseFrameDetect |
1744 macinit.ReceiveFlowControl |
1745 macinit.TransmitFlowControl);
1746
1747 /* Write to ETHERNET MACFCR */
1748 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
1749
1750 /* Wait until the write operation will be taken into account:
1751 at least four TX_CLK/RX_CLK clock cycles */
1752 tmpreg1 = (heth->Instance)->MACFCR;
1753 HAL_Delay(ETH_REG_WRITE_DELAY);
1754 (heth->Instance)->MACFCR = tmpreg1;
1755
1756 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
1757 /* Set the ETV bit according to ETH VLANTagComparison value */
1758 /* Set the VL bit according to ETH VLANTagIdentifier value */
1759 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
1760 macinit.VLANTagIdentifier);
1761
1762 /* Wait until the write operation will be taken into account:
1763 at least four TX_CLK/RX_CLK clock cycles */
1764 tmpreg1 = (heth->Instance)->MACVLANTR;
1765 HAL_Delay(ETH_REG_WRITE_DELAY);
1766 (heth->Instance)->MACVLANTR = tmpreg1;
1767
1768 /* Ethernet DMA default initialization ************************************/
1769 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
1770 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
1771 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
1772 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
1773 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
1774 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
1775 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
1776 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
1777 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
1778 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
1779 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
1780 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
1781 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
1782 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
1783 dmainit.DescriptorSkipLength = 0x0U;
1784 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
1785
1786 /* Get the ETHERNET DMAOMR value */
1787 tmpreg1 = (heth->Instance)->DMAOMR;
1788 /* Clear xx bits */
1789 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
1790
1791 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
1792 /* Set the RSF bit according to ETH ReceiveStoreForward value */
1793 /* Set the DFF bit according to ETH FlushReceivedFrame value */
1794 /* Set the TSF bit according to ETH TransmitStoreForward value */
1795 /* Set the TTC bit according to ETH TransmitThresholdControl value */
1796 /* Set the FEF bit according to ETH ForwardErrorFrames value */
1797 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
1798 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
1799 /* Set the OSF bit according to ETH SecondFrameOperate value */
1800 tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
1801 dmainit.ReceiveStoreForward |
1802 dmainit.FlushReceivedFrame |
1803 dmainit.TransmitStoreForward |
1804 dmainit.TransmitThresholdControl |
1805 dmainit.ForwardErrorFrames |
1806 dmainit.ForwardUndersizedGoodFrames |
1807 dmainit.ReceiveThresholdControl |
1808 dmainit.SecondFrameOperate);
1809
1810 /* Write to ETHERNET DMAOMR */
1811 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
1812
1813 /* Wait until the write operation will be taken into account:
1814 at least four TX_CLK/RX_CLK clock cycles */
1815 tmpreg1 = (heth->Instance)->DMAOMR;
1816 HAL_Delay(ETH_REG_WRITE_DELAY);
1817 (heth->Instance)->DMAOMR = tmpreg1;
1818
1819 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
1820 /* Set the AAL bit according to ETH AddressAlignedBeats value */
1821 /* Set the FB bit according to ETH FixedBurst value */
1822 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
1823 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
1824 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
1825 /* Set the DSL bit according to ETH DesciptorSkipLength value */
1826 /* Set the PR and DA bits according to ETH DMAArbitration value */
1827 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
1828 dmainit.FixedBurst |
1829 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
1830 dmainit.TxDMABurstLength |
1831 dmainit.EnhancedDescriptorFormat |
1832 (dmainit.DescriptorSkipLength << 2U) |
1833 dmainit.DMAArbitration |
1834 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
1835
1836 /* Wait until the write operation will be taken into account:
1837 at least four TX_CLK/RX_CLK clock cycles */
1838 tmpreg1 = (heth->Instance)->DMABMR;
1839 HAL_Delay(ETH_REG_WRITE_DELAY);
1840 (heth->Instance)->DMABMR = tmpreg1;
1841
1842 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
1843 {
1844 /* Enable the Ethernet Rx Interrupt */
1845 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
1846 }
1847
1848 /* Initialize MAC address in ethernet MAC */
1849 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
1850 }
1851
1852 /**
1853 * @brief Configures the selected MAC address.
1854 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1855 * the configuration information for ETHERNET module
1856 * @param MacAddr: The MAC address to configure
1857 * This parameter can be one of the following values:
1858 * @arg ETH_MAC_Address0: MAC Address0
1859 * @arg ETH_MAC_Address1: MAC Address1
1860 * @arg ETH_MAC_Address2: MAC Address2
1861 * @arg ETH_MAC_Address3: MAC Address3
1862 * @param Addr: Pointer to MAC address buffer data (6 bytes)
1863 * @retval HAL status
1864 */
1865 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
1866 {
1867 uint32_t tmpreg1;
1868
1869 /* Prevent unused argument(s) compilation warning */
1870 UNUSED(heth);
1871
1872 /* Check the parameters */
1873 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
1874
1875 /* Calculate the selected MAC address high register */
1876 tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U];
1877 /* Load the selected MAC address high register */
1878 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
1879 /* Calculate the selected MAC address low register */
1880 tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U];
1881
1882 /* Load the selected MAC address low register */
1883 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
1884 }
1885
1886 /**
1887 * @brief Enables the MAC transmission.
1888 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1889 * the configuration information for ETHERNET module
1890 * @retval None
1891 */
1892 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
1893 {
1894 __IO uint32_t tmpreg1 = 0U;
1895
1896 /* Enable the MAC transmission */
1897 (heth->Instance)->MACCR |= ETH_MACCR_TE;
1898
1899 /* Wait until the write operation will be taken into account:
1900 at least four TX_CLK/RX_CLK clock cycles */
1901 tmpreg1 = (heth->Instance)->MACCR;
1902 ETH_Delay(ETH_REG_WRITE_DELAY);
1903 (heth->Instance)->MACCR = tmpreg1;
1904 }
1905
1906 /**
1907 * @brief Disables the MAC transmission.
1908 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1909 * the configuration information for ETHERNET module
1910 * @retval None
1911 */
1912 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
1913 {
1914 __IO uint32_t tmpreg1 = 0U;
1915
1916 /* Disable the MAC transmission */
1917 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
1918
1919 /* Wait until the write operation will be taken into account:
1920 at least four TX_CLK/RX_CLK clock cycles */
1921 tmpreg1 = (heth->Instance)->MACCR;
1922 ETH_Delay(ETH_REG_WRITE_DELAY);
1923 (heth->Instance)->MACCR = tmpreg1;
1924 }
1925
1926 /**
1927 * @brief Enables the MAC reception.
1928 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1929 * the configuration information for ETHERNET module
1930 * @retval None
1931 */
1932 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
1933 {
1934 __IO uint32_t tmpreg1 = 0U;
1935
1936 /* Enable the MAC reception */
1937 (heth->Instance)->MACCR |= ETH_MACCR_RE;
1938
1939 /* Wait until the write operation will be taken into account:
1940 at least four TX_CLK/RX_CLK clock cycles */
1941 tmpreg1 = (heth->Instance)->MACCR;
1942 ETH_Delay(ETH_REG_WRITE_DELAY);
1943 (heth->Instance)->MACCR = tmpreg1;
1944 }
1945
1946 /**
1947 * @brief Disables the MAC reception.
1948 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1949 * the configuration information for ETHERNET module
1950 * @retval None
1951 */
1952 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
1953 {
1954 __IO uint32_t tmpreg1 = 0U;
1955
1956 /* Disable the MAC reception */
1957 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
1958
1959 /* Wait until the write operation will be taken into account:
1960 at least four TX_CLK/RX_CLK clock cycles */
1961 tmpreg1 = (heth->Instance)->MACCR;
1962 ETH_Delay(ETH_REG_WRITE_DELAY);
1963 (heth->Instance)->MACCR = tmpreg1;
1964 }
1965
1966 /**
1967 * @brief Enables the DMA transmission.
1968 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1969 * the configuration information for ETHERNET module
1970 * @retval None
1971 */
1972 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
1973 {
1974 /* Enable the DMA transmission */
1975 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
1976 }
1977
1978 /**
1979 * @brief Disables the DMA transmission.
1980 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1981 * the configuration information for ETHERNET module
1982 * @retval None
1983 */
1984 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
1985 {
1986 /* Disable the DMA transmission */
1987 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
1988 }
1989
1990 /**
1991 * @brief Enables the DMA reception.
1992 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1993 * the configuration information for ETHERNET module
1994 * @retval None
1995 */
1996 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
1997 {
1998 /* Enable the DMA reception */
1999 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
2000 }
2001
2002 /**
2003 * @brief Disables the DMA reception.
2004 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2005 * the configuration information for ETHERNET module
2006 * @retval None
2007 */
2008 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
2009 {
2010 /* Disable the DMA reception */
2011 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
2012 }
2013
2014 /**
2015 * @brief Clears the ETHERNET transmit FIFO.
2016 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2017 * the configuration information for ETHERNET module
2018 * @retval None
2019 */
2020 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
2021 {
2022 __IO uint32_t tmpreg1 = 0U;
2023
2024 /* Set the Flush Transmit FIFO bit */
2025 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
2026
2027 /* Wait until the write operation will be taken into account:
2028 at least four TX_CLK/RX_CLK clock cycles */
2029 tmpreg1 = (heth->Instance)->DMAOMR;
2030 ETH_Delay(ETH_REG_WRITE_DELAY);
2031 (heth->Instance)->DMAOMR = tmpreg1;
2032 }
2033
2034 /**
2035 * @brief This function provides delay (in milliseconds) based on CPU cycles method.
2036 * @param mdelay: specifies the delay time length, in milliseconds.
2037 * @retval None
2038 */
2039 static void ETH_Delay(uint32_t mdelay)
2040 {
2041 __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
2042 do
2043 {
2044 __NOP();
2045 }
2046 while (Delay --);
2047 }
2048
2049 /**
2050 * @}
2051 */
2052
2053 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
2054 STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
2055 #endif /* HAL_ETH_MODULE_ENABLED */
2056 /**
2057 * @}
2058 */
2059
2060 /**
2061 * @}
2062 */
2063
2064 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/