lib/main/STM32F4/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_hal_sdram.c
   4   * @author  MCD Application Team
   5   * @version V1.7.1
   6   * @date    14-April-2017
   7   * @brief   SDRAM HAL module driver.
   8   *          This file provides a generic firmware to drive SDRAM memories mounted
   9   *          as external device.
  10   *
  11   @verbatim
  12   ==============================================================================
  13                        ##### How to use this driver #####
  14   ==============================================================================
  15   [..]
  16     This driver is a generic layered driver which contains a set of APIs used to
  17     control SDRAM memories. It uses the FMC layer functions to interface
  18     with SDRAM devices.
  19     The following sequence should be followed to configure the FMC to interface
  20     with SDRAM memories:
  21
  22    (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
  23           SDRAM_HandleTypeDef  hdsram
  24
  25        (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
  26             values of the structure member.
  27
  28        (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
  29             base register instance for NOR or SDRAM device
  30
  31    (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
  32           FMC_SDRAM_TimingTypeDef  Timing;
  33       and fill its fields with the allowed values of the structure member.
  34
  35    (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
  36        performs the following sequence:
  37
  38        (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
  39        (##) Control register configuration using the FMC SDRAM interface function
  40             FMC_SDRAM_Init()
  41        (##) Timing register configuration using the FMC SDRAM interface function
  42             FMC_SDRAM_Timing_Init()
  43        (##) Program the SDRAM external device by applying its initialization sequence
  44             according to the device plugged in your hardware. This step is mandatory
  45             for accessing the SDRAM device.
  46
  47    (#) At this stage you can perform read/write accesses from/to the memory connected
  48        to the SDRAM Bank. You can perform either polling or DMA transfer using the
  49        following APIs:
  50        (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
  51        (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
  52
  53    (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
  54        HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
  55        the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
  56        device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
  57        structure.
  58
  59    (#) You can continuously monitor the SDRAM device HAL state by calling the function
  60        HAL_SDRAM_GetState()
  61
  62   @endverbatim
  63   ******************************************************************************
  64   * @attention
  65   *
  66   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  67   *
  68   * Redistribution and use in source and binary forms, with or without modification,
  69   * are permitted provided that the following conditions are met:
  70   *   1. Redistributions of source code must retain the above copyright notice,
  71   *      this list of conditions and the following disclaimer.
  72   *   2. Redistributions in binary form must reproduce the above copyright notice,
  73   *      this list of conditions and the following disclaimer in the documentation
  74   *      and/or other materials provided with the distribution.
  75   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  76   *      may be used to endorse or promote products derived from this software
  77   *      without specific prior written permission.
  78   *
  79   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  80   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  81   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  82   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  83   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  84   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  85   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  86   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  87   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  88   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  89   *
  90   ******************************************************************************
  91   */
  92
  93 /* Includes ------------------------------------------------------------------*/
  94 #include "stm32f4xx_hal.h"
  95
  96 /** @addtogroup STM32F4xx_HAL_Driver
  97   * @{
  98   */
  99
 100 /** @defgroup SDRAM SDRAM
 101   * @brief SDRAM driver modules
 102   * @{
 103   */
 104 #ifdef HAL_SDRAM_MODULE_ENABLED
 105 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
 106     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 107
 108 /* Private typedef -----------------------------------------------------------*/
 109 /* Private define ------------------------------------------------------------*/
 110 /* Private macro -------------------------------------------------------------*/
 111 /* Private variables ---------------------------------------------------------*/
 112 /* Private functions ---------------------------------------------------------*/
 113 /* Exported functions --------------------------------------------------------*/
 114 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
 115   * @{
 116   */
 117
 118 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
 119   * @brief    Initialization and Configuration functions
 120   *
 121   @verbatim
 122   ==============================================================================
 123            ##### SDRAM Initialization and de_initialization functions #####
 124   ==============================================================================
 125   [..]
 126     This section provides functions allowing to initialize/de-initialize
 127     the SDRAM memory
 128
 129 @endverbatim
 130   * @{
 131   */
 132
 133 /**
 134   * @brief  Performs the SDRAM device initialization sequence.
 135   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 136   *                the configuration information for SDRAM module.
 137   * @param  Timing: Pointer to SDRAM control timing structure
 138   * @retval HAL status
 139   */
 140 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
 141 {
 142   /* Check the SDRAM handle parameter */
 143   if(hsdram == NULL)
 144   {
 145     return HAL_ERROR;
 146   }
 147
 148   if(hsdram->State == HAL_SDRAM_STATE_RESET)
 149   {
 150     /* Allocate lock resource and initialize it */
 151     hsdram->Lock = HAL_UNLOCKED;
 152     /* Initialize the low level hardware (MSP) */
 153     HAL_SDRAM_MspInit(hsdram);
 154   }
 155
 156   /* Initialize the SDRAM controller state */
 157   hsdram->State = HAL_SDRAM_STATE_BUSY;
 158
 159   /* Initialize SDRAM control Interface */
 160   FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
 161
 162   /* Initialize SDRAM timing Interface */
 163   FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
 164
 165   /* Update the SDRAM controller state */
 166   hsdram->State = HAL_SDRAM_STATE_READY;
 167
 168   return HAL_OK;
 169 }
 170
 171 /**
 172   * @brief  Perform the SDRAM device initialization sequence.
 173   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 174   *                the configuration information for SDRAM module.
 175   * @retval HAL status
 176   */
 177 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
 178 {
 179   /* Initialize the low level hardware (MSP) */
 180   HAL_SDRAM_MspDeInit(hsdram);
 181
 182   /* Configure the SDRAM registers with their reset values */
 183   FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
 184
 185   /* Reset the SDRAM controller state */
 186   hsdram->State = HAL_SDRAM_STATE_RESET;
 187
 188   /* Release Lock */
 189   __HAL_UNLOCK(hsdram);
 190
 191   return HAL_OK;
 192 }
 193
 194 /**
 195   * @brief  SDRAM MSP Init.
 196   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 197   *                the configuration information for SDRAM module.
 198   * @retval None
 199   */
 200 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
 201 {
 202   /* Prevent unused argument(s) compilation warning */
 203   UNUSED(hsdram);
 204   /* NOTE: This function Should not be modified, when the callback is needed,
 205             the HAL_SDRAM_MspInit could be implemented in the user file
 206    */
 207 }
 208
 209 /**
 210   * @brief  SDRAM MSP DeInit.
 211   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 212   *                the configuration information for SDRAM module.
 213   * @retval None
 214   */
 215 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
 216 {
 217   /* Prevent unused argument(s) compilation warning */
 218   UNUSED(hsdram);
 219   /* NOTE: This function Should not be modified, when the callback is needed,
 220             the HAL_SDRAM_MspDeInit could be implemented in the user file
 221    */
 222 }
 223
 224 /**
 225   * @brief  This function handles SDRAM refresh error interrupt request.
 226   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 227   *                the configuration information for SDRAM module.
 228   * @retval HAL status
 229 */
 230 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
 231 {
 232   /* Check SDRAM interrupt Rising edge flag */
 233   if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
 234   {
 235     /* SDRAM refresh error interrupt callback */
 236     HAL_SDRAM_RefreshErrorCallback(hsdram);
 237
 238     /* Clear SDRAM refresh error interrupt pending bit */
 239     __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
 240   }
 241 }
 242
 243 /**
 244   * @brief  SDRAM Refresh error callback.
 245   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 246   *                the configuration information for SDRAM module.
 247   * @retval None
 248   */
 249 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
 250 {
 251   /* Prevent unused argument(s) compilation warning */
 252   UNUSED(hsdram);
 253   /* NOTE: This function Should not be modified, when the callback is needed,
 254             the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
 255    */
 256 }
 257
 258 /**
 259   * @brief  DMA transfer complete callback.
 260   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
 261   *                the configuration information for the specified DMA module.
 262   * @retval None
 263   */
 264 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
 265 {
 266   /* Prevent unused argument(s) compilation warning */
 267   UNUSED(hdma);
 268   /* NOTE: This function Should not be modified, when the callback is needed,
 269             the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
 270    */
 271 }
 272
 273 /**
 274   * @brief  DMA transfer complete error callback.
 275   * @param  hdma: DMA handle
 276   * @retval None
 277   */
 278 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
 279 {
 280   /* Prevent unused argument(s) compilation warning */
 281   UNUSED(hdma);
 282   /* NOTE: This function Should not be modified, when the callback is needed,
 283             the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
 284    */
 285 }
 286 /**
 287   * @}
 288   */
 289
 290 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
 291   * @brief    Input Output and memory control functions
 292   *
 293   @verbatim
 294   ==============================================================================
 295                     ##### SDRAM Input and Output functions #####
 296   ==============================================================================
 297   [..]
 298     This section provides functions allowing to use and control the SDRAM memory
 299
 300 @endverbatim
 301   * @{
 302   */
 303
 304 /**
 305   * @brief  Reads 8-bit data buffer from the SDRAM memory.
 306   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 307   *                the configuration information for SDRAM module.
 308   * @param  pAddress: Pointer to read start address
 309   * @param  pDstBuffer: Pointer to destination buffer
 310   * @param  BufferSize: Size of the buffer to read from memory
 311   * @retval HAL status
 312   */
 313 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
 314 {
 315   __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
 316
 317   /* Process Locked */
 318   __HAL_LOCK(hsdram);
 319
 320   /* Check the SDRAM controller state */
 321   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
 322   {
 323     return HAL_BUSY;
 324   }
 325   else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
 326   {
 327     return  HAL_ERROR;
 328   }
 329
 330   /* Read data from source */
 331   for(; BufferSize != 0U; BufferSize--)
 332   {
 333     *pDstBuffer = *(__IO uint8_t *)pSdramAddress;
 334     pDstBuffer++;
 335     pSdramAddress++;
 336   }
 337
 338   /* Process Unlocked */
 339   __HAL_UNLOCK(hsdram);
 340
 341   return HAL_OK;
 342 }
 343
 344 /**
 345   * @brief  Writes 8-bit data buffer to SDRAM memory.
 346   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 347   *                the configuration information for SDRAM module.
 348   * @param  pAddress: Pointer to write start address
 349   * @param  pSrcBuffer: Pointer to source buffer to write
 350   * @param  BufferSize: Size of the buffer to write to memory
 351   * @retval HAL status
 352   */
 353 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
 354 {
 355   __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
 356   uint32_t tmp = 0U;
 357
 358   /* Process Locked */
 359   __HAL_LOCK(hsdram);
 360
 361   /* Check the SDRAM controller state */
 362   tmp = hsdram->State;
 363
 364   if(tmp == HAL_SDRAM_STATE_BUSY)
 365   {
 366     return HAL_BUSY;
 367   }
 368   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
 369   {
 370     return  HAL_ERROR;
 371   }
 372
 373   /* Write data to memory */
 374   for(; BufferSize != 0U; BufferSize--)
 375   {
 376     *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
 377     pSrcBuffer++;
 378     pSdramAddress++;
 379   }
 380
 381   /* Process Unlocked */
 382   __HAL_UNLOCK(hsdram);
 383
 384   return HAL_OK;
 385 }
 386
 387 /**
 388   * @brief  Reads 16-bit data buffer from the SDRAM memory.
 389   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 390   *                the configuration information for SDRAM module.
 391   * @param  pAddress: Pointer to read start address
 392   * @param  pDstBuffer: Pointer to destination buffer
 393   * @param  BufferSize: Size of the buffer to read from memory
 394   * @retval HAL status
 395   */
 396 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
 397 {
 398   __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
 399
 400   /* Process Locked */
 401   __HAL_LOCK(hsdram);
 402
 403   /* Check the SDRAM controller state */
 404   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
 405   {
 406     return HAL_BUSY;
 407   }
 408   else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
 409   {
 410     return  HAL_ERROR;
 411   }
 412
 413   /* Read data from source */
 414   for(; BufferSize != 0U; BufferSize--)
 415   {
 416     *pDstBuffer = *(__IO uint16_t *)pSdramAddress;
 417     pDstBuffer++;
 418     pSdramAddress++;
 419   }
 420
 421   /* Process Unlocked */
 422   __HAL_UNLOCK(hsdram);
 423
 424   return HAL_OK;
 425 }
 426
 427 /**
 428   * @brief  Writes 16-bit data buffer to SDRAM memory.
 429   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 430   *                the configuration information for SDRAM module.
 431   * @param  pAddress: Pointer to write start address
 432   * @param  pSrcBuffer: Pointer to source buffer to write
 433   * @param  BufferSize: Size of the buffer to write to memory
 434   * @retval HAL status
 435   */
 436 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
 437 {
 438   __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
 439   uint32_t tmp = 0U;
 440
 441   /* Process Locked */
 442   __HAL_LOCK(hsdram);
 443
 444   /* Check the SDRAM controller state */
 445   tmp = hsdram->State;
 446
 447   if(tmp == HAL_SDRAM_STATE_BUSY)
 448   {
 449     return HAL_BUSY;
 450   }
 451   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
 452   {
 453     return  HAL_ERROR;
 454   }
 455
 456   /* Write data to memory */
 457   for(; BufferSize != 0U; BufferSize--)
 458   {
 459     *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
 460     pSrcBuffer++;
 461     pSdramAddress++;
 462   }
 463
 464   /* Process Unlocked */
 465   __HAL_UNLOCK(hsdram);
 466
 467   return HAL_OK;
 468 }
 469
 470 /**
 471   * @brief  Reads 32-bit data buffer from the SDRAM memory.
 472   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 473   *                the configuration information for SDRAM module.
 474   * @param  pAddress: Pointer to read start address
 475   * @param  pDstBuffer: Pointer to destination buffer
 476   * @param  BufferSize: Size of the buffer to read from memory
 477   * @retval HAL status
 478   */
 479 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
 480 {
 481   __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
 482
 483   /* Process Locked */
 484   __HAL_LOCK(hsdram);
 485
 486   /* Check the SDRAM controller state */
 487   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
 488   {
 489     return HAL_BUSY;
 490   }
 491   else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
 492   {
 493     return  HAL_ERROR;
 494   }
 495
 496   /* Read data from source */
 497   for(; BufferSize != 0U; BufferSize--)
 498   {
 499     *pDstBuffer = *(__IO uint32_t *)pSdramAddress;
 500     pDstBuffer++;
 501     pSdramAddress++;
 502   }
 503
 504   /* Process Unlocked */
 505   __HAL_UNLOCK(hsdram);
 506
 507   return HAL_OK;
 508 }
 509
 510 /**
 511   * @brief  Writes 32-bit data buffer to SDRAM memory.
 512   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 513   *                the configuration information for SDRAM module.
 514   * @param  pAddress: Pointer to write start address
 515   * @param  pSrcBuffer: Pointer to source buffer to write
 516   * @param  BufferSize: Size of the buffer to write to memory
 517   * @retval HAL status
 518   */
 519 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
 520 {
 521   __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
 522   uint32_t tmp = 0U;
 523
 524   /* Process Locked */
 525   __HAL_LOCK(hsdram);
 526
 527   /* Check the SDRAM controller state */
 528   tmp = hsdram->State;
 529
 530   if(tmp == HAL_SDRAM_STATE_BUSY)
 531   {
 532     return HAL_BUSY;
 533   }
 534   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
 535   {
 536     return  HAL_ERROR;
 537   }
 538
 539   /* Write data to memory */
 540   for(; BufferSize != 0U; BufferSize--)
 541   {
 542     *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
 543     pSrcBuffer++;
 544     pSdramAddress++;
 545   }
 546
 547   /* Process Unlocked */
 548   __HAL_UNLOCK(hsdram);
 549
 550   return HAL_OK;
 551 }
 552
 553 /**
 554   * @brief  Reads a Words data from the SDRAM memory using DMA transfer.
 555   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 556   *                the configuration information for SDRAM module.
 557   * @param  pAddress: Pointer to read start address
 558   * @param  pDstBuffer: Pointer to destination buffer
 559   * @param  BufferSize: Size of the buffer to read from memory
 560   * @retval HAL status
 561   */
 562 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
 563 {
 564   uint32_t tmp = 0U;
 565
 566   /* Process Locked */
 567   __HAL_LOCK(hsdram);
 568
 569   /* Check the SDRAM controller state */
 570   tmp = hsdram->State;
 571
 572   if(tmp == HAL_SDRAM_STATE_BUSY)
 573   {
 574     return HAL_BUSY;
 575   }
 576   else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
 577   {
 578     return  HAL_ERROR;
 579   }
 580
 581   /* Configure DMA user callbacks */
 582   hsdram->hdma->XferCpltCallback  = HAL_SDRAM_DMA_XferCpltCallback;
 583   hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
 584
 585   /* Enable the DMA Stream */
 586   HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
 587
 588   /* Process Unlocked */
 589   __HAL_UNLOCK(hsdram);
 590
 591   return HAL_OK;
 592 }
 593
 594 /**
 595   * @brief  Writes a Words data buffer to SDRAM memory using DMA transfer.
 596   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 597   *                the configuration information for SDRAM module.
 598   * @param  pAddress: Pointer to write start address
 599   * @param  pSrcBuffer: Pointer to source buffer to write
 600   * @param  BufferSize: Size of the buffer to write to memory
 601   * @retval HAL status
 602   */
 603 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
 604 {
 605   uint32_t tmp = 0U;
 606
 607   /* Process Locked */
 608   __HAL_LOCK(hsdram);
 609
 610   /* Check the SDRAM controller state */
 611   tmp = hsdram->State;
 612
 613   if(tmp == HAL_SDRAM_STATE_BUSY)
 614   {
 615     return HAL_BUSY;
 616   }
 617   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
 618   {
 619     return  HAL_ERROR;
 620   }
 621
 622   /* Configure DMA user callbacks */
 623   hsdram->hdma->XferCpltCallback  = HAL_SDRAM_DMA_XferCpltCallback;
 624   hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
 625
 626   /* Enable the DMA Stream */
 627   HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
 628
 629   /* Process Unlocked */
 630   __HAL_UNLOCK(hsdram);
 631
 632   return HAL_OK;
 633 }
 634 /**
 635   * @}
 636   */
 637
 638 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
 639  *  @brief   management functions
 640  *
 641 @verbatim
 642   ==============================================================================
 643                          ##### SDRAM Control functions #####
 644   ==============================================================================
 645   [..]
 646     This subsection provides a set of functions allowing to control dynamically
 647     the SDRAM interface.
 648
 649 @endverbatim
 650   * @{
 651   */
 652
 653 /**
 654   * @brief  Enables dynamically SDRAM write protection.
 655   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 656   *                the configuration information for SDRAM module.
 657   * @retval HAL status
 658   */
 659 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
 660 {
 661   /* Check the SDRAM controller state */
 662   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
 663   {
 664     return HAL_BUSY;
 665   }
 666
 667   /* Update the SDRAM state */
 668   hsdram->State = HAL_SDRAM_STATE_BUSY;
 669
 670   /* Enable write protection */
 671   FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
 672
 673   /* Update the SDRAM state */
 674   hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
 675
 676   return HAL_OK;
 677 }
 678
 679 /**
 680   * @brief  Disables dynamically SDRAM write protection.
 681   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 682   *                the configuration information for SDRAM module.
 683   * @retval HAL status
 684   */
 685 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
 686 {
 687   /* Check the SDRAM controller state */
 688   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
 689   {
 690     return HAL_BUSY;
 691   }
 692
 693   /* Update the SDRAM state */
 694   hsdram->State = HAL_SDRAM_STATE_BUSY;
 695
 696   /* Disable write protection */
 697   FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
 698
 699   /* Update the SDRAM state */
 700   hsdram->State = HAL_SDRAM_STATE_READY;
 701
 702   return HAL_OK;
 703 }
 704
 705 /**
 706   * @brief  Sends Command to the SDRAM bank.
 707   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 708   *                the configuration information for SDRAM module.
 709   * @param  Command: SDRAM command structure
 710   * @param  Timeout: Timeout duration
 711   * @retval HAL status
 712   */
 713 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
 714 {
 715   /* Check the SDRAM controller state */
 716   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
 717   {
 718     return HAL_BUSY;
 719   }
 720
 721   /* Update the SDRAM state */
 722   hsdram->State = HAL_SDRAM_STATE_BUSY;
 723
 724   /* Send SDRAM command */
 725   FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
 726
 727   /* Update the SDRAM controller state */
 728   if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
 729   {
 730     hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
 731   }
 732   else
 733   {
 734     hsdram->State = HAL_SDRAM_STATE_READY;
 735   }
 736
 737   return HAL_OK;
 738 }
 739
 740 /**
 741   * @brief  Programs the SDRAM Memory Refresh rate.
 742   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 743   *                the configuration information for SDRAM module.
 744   * @param  RefreshRate: The SDRAM refresh rate value
 745   * @retval HAL status
 746   */
 747 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
 748 {
 749   /* Check the SDRAM controller state */
 750   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
 751   {
 752     return HAL_BUSY;
 753   }
 754
 755   /* Update the SDRAM state */
 756   hsdram->State = HAL_SDRAM_STATE_BUSY;
 757
 758   /* Program the refresh rate */
 759   FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
 760
 761   /* Update the SDRAM state */
 762   hsdram->State = HAL_SDRAM_STATE_READY;
 763
 764   return HAL_OK;
 765 }
 766
 767 /**
 768   * @brief  Sets the Number of consecutive SDRAM Memory auto Refresh commands.
 769   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 770   *                the configuration information for SDRAM module.
 771   * @param  AutoRefreshNumber: The SDRAM auto Refresh number
 772   * @retval HAL status
 773   */
 774 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
 775 {
 776   /* Check the SDRAM controller state */
 777   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
 778   {
 779     return HAL_BUSY;
 780   }
 781
 782   /* Update the SDRAM state */
 783   hsdram->State = HAL_SDRAM_STATE_BUSY;
 784
 785   /* Set the Auto-Refresh number */
 786   FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
 787
 788   /* Update the SDRAM state */
 789   hsdram->State = HAL_SDRAM_STATE_READY;
 790
 791   return HAL_OK;
 792 }
 793
 794 /**
 795   * @brief  Returns the SDRAM memory current mode.
 796   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 797   *                the configuration information for SDRAM module.
 798   * @retval The SDRAM memory mode.
 799   */
 800 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
 801 {
 802   /* Return the SDRAM memory current mode */
 803   return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
 804 }
 805
 806 /**
 807   * @}
 808   */
 809
 810 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
 811  *  @brief   Peripheral State functions
 812  *
 813 @verbatim
 814   ==============================================================================
 815                       ##### SDRAM State functions #####
 816   ==============================================================================
 817   [..]
 818     This subsection permits to get in run-time the status of the SDRAM controller
 819     and the data flow.
 820
 821 @endverbatim
 822   * @{
 823   */
 824
 825 /**
 826   * @brief  Returns the SDRAM state.
 827   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 828   *                the configuration information for SDRAM module.
 829   * @retval HAL state
 830   */
 831 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
 832 {
 833   return hsdram->State;
 834 }
 835
 836 /**
 837   * @}
 838   */
 839
 840 /**
 841   * @}
 842   */
 843 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
 844 #endif /* HAL_SDRAM_MODULE_ENABLED */
 845 /**
 846   * @}
 847   */
 848
 849 /**
 850   * @}
 851   */
 852
 853 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/