lib/main/STM32F4/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_ll_fsmc.c
   4   * @author  MCD Application Team
   5   * @version V1.7.1
   6   * @date    14-April-2017
   7   * @brief   FSMC Low Layer HAL module driver.
   8   *
   9   *          This file provides firmware functions to manage the following
  10   *          functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
  11   *           + Initialization/de-initialization functions
  12   *           + Peripheral Control functions
  13   *           + Peripheral State functions
  14   *
  15   @verbatim
  16   ==============================================================================
  17                         ##### FSMC peripheral features #####
  18   ==============================================================================
  19     [..] The Flexible static memory controller (FSMC) includes two memory controllers:
  20          (+) The NOR/PSRAM memory controller
  21          (+) The NAND/PC Card memory controller
  22
  23     [..] The FSMC functional block makes the interface with synchronous and asynchronous static
  24          memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
  25          (+) to translate AHB transactions into the appropriate external device protocol.
  26          (+) to meet the access time requirements of the external memory devices.
  27
  28     [..] All external memories share the addresses, data and control signals with the controller.
  29          Each external device is accessed by means of a unique Chip Select. The FSMC performs
  30          only one access at a time to an external device.
  31          The main features of the FSMC controller are the following:
  32           (+) Interface with static-memory mapped devices including:
  33              (++) Static random access memory (SRAM).
  34              (++) Read-only memory (ROM).
  35              (++) NOR Flash memory/OneNAND Flash memory.
  36              (++) PSRAM (4 memory banks).
  37              (++) 16-bit PC Card compatible devices.
  38              (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
  39                   data.
  40           (+) Independent Chip Select control for each memory bank.
  41           (+) Independent configuration for each memory bank.
  42
  43   @endverbatim
  44   ******************************************************************************
  45   * @attention
  46   *
  47   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  48   *
  49   * Redistribution and use in source and binary forms, with or without modification,
  50   * are permitted provided that the following conditions are met:
  51   *   1. Redistributions of source code must retain the above copyright notice,
  52   *      this list of conditions and the following disclaimer.
  53   *   2. Redistributions in binary form must reproduce the above copyright notice,
  54   *      this list of conditions and the following disclaimer in the documentation
  55   *      and/or other materials provided with the distribution.
  56   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  57   *      may be used to endorse or promote products derived from this software
  58   *      without specific prior written permission.
  59   *
  60   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  61   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  62   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  63   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  64   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  65   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  66   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  67   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  68   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  69   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  70   *
  71   ******************************************************************************
  72   */
  73
  74 /* Includes ------------------------------------------------------------------*/
  75 #include "stm32f4xx_hal.h"
  76
  77 /** @addtogroup STM32F4xx_HAL_Driver
  78   * @{
  79   */
  80
  81 /** @defgroup FSMC_LL  FSMC Low Layer
  82   * @brief FSMC driver modules
  83   * @{
  84   */
  85
  86 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
  87 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
  88     defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
  89 /* Private typedef -----------------------------------------------------------*/
  90 /* Private define ------------------------------------------------------------*/
  91 /* Private macro -------------------------------------------------------------*/
  92 /* Private variables ---------------------------------------------------------*/
  93 /* Private function prototypes -----------------------------------------------*/
  94 /* Private functions ---------------------------------------------------------*/
  95 /** @addtogroup FSMC_LL_Private_Functions
  96   * @{
  97   */
  98
  99 /** @addtogroup FSMC_LL_NORSRAM
 100   * @brief    NORSRAM Controller functions
 101   *
 102   @verbatim
 103   ==============================================================================
 104                    ##### How to use NORSRAM device driver #####
 105   ==============================================================================
 106
 107   [..]
 108     This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
 109     to run the NORSRAM external devices.
 110
 111     (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
 112     (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
 113     (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
 114     (+) FSMC NORSRAM bank extended timing configuration using the function
 115         FSMC_NORSRAM_Extended_Timing_Init()
 116     (+) FSMC NORSRAM bank enable/disable write operation using the functions
 117         FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
 118
 119 @endverbatim
 120   * @{
 121   */
 122
 123 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
 124   * @brief    Initialization and Configuration functions
 125   *
 126   @verbatim
 127   ==============================================================================
 128               ##### Initialization and de_initialization functions #####
 129   ==============================================================================
 130   [..]
 131     This section provides functions allowing to:
 132     (+) Initialize and configure the FSMC NORSRAM interface
 133     (+) De-initialize the FSMC NORSRAM interface
 134     (+) Configure the FSMC clock and associated GPIOs
 135
 136 @endverbatim
 137   * @{
 138   */
 139
 140 /**
 141   * @brief  Initialize the FSMC_NORSRAM device according to the specified
 142   *         control parameters in the FSMC_NORSRAM_InitTypeDef
 143   * @param  Device: Pointer to NORSRAM device instance
 144   * @param  Init: Pointer to NORSRAM Initialization structure
 145   * @retval HAL status
 146   */
 147 HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
 148 {
 149   uint32_t tmpr = 0U;
 150
 151   /* Check the parameters */
 152   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
 153   assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
 154   assert_param(IS_FSMC_MUX(Init->DataAddressMux));
 155   assert_param(IS_FSMC_MEMORY(Init->MemoryType));
 156   assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
 157   assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
 158   assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
 159 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
 160   assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
 161 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
 162   assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
 163   assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
 164   assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
 165   assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
 166   assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
 167   assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
 168   assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
 169 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
 170   assert_param(IS_FSMC_WRITE_FIFO(Init->WriteFifo));
 171   assert_param(IS_FSMC_CONTINOUS_CLOCK(Init->ContinuousClock));
 172 #endif /* STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */
 173
 174   /* Get the BTCR register value */
 175   tmpr = Device->BTCR[Init->NSBank];
 176
 177 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
 178   /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
 179            WAITEN, EXTMOD, ASYNCWAIT, CPSIZE and CBURSTRW bits */
 180   tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN     | FSMC_BCR1_MUXEN    | FSMC_BCR1_MTYP     | \
 181                        FSMC_BCR1_MWID      | FSMC_BCR1_FACCEN   | FSMC_BCR1_BURSTEN  | \
 182                        FSMC_BCR1_WAITPOL   | FSMC_BCR1_WRAPMOD  | FSMC_BCR1_WAITCFG  | \
 183                        FSMC_BCR1_WREN      | FSMC_BCR1_WAITEN   | FSMC_BCR1_EXTMOD   | \
 184                        FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CPSIZE   | FSMC_BCR1_CBURSTRW));
 185   /* Set NORSRAM device control parameters */
 186   tmpr |= (uint32_t)(Init->DataAddressMux       |\
 187                      Init->MemoryType           |\
 188                      Init->MemoryDataWidth      |\
 189                      Init->BurstAccessMode      |\
 190                      Init->WaitSignalPolarity   |\
 191                      Init->WrapMode             |\
 192                      Init->WaitSignalActive     |\
 193                      Init->WriteOperation       |\
 194                      Init->WaitSignal           |\
 195                      Init->ExtendedMode         |\
 196                      Init->AsynchronousWait     |\
 197                      Init->PageSize             |\
 198                      Init->WriteBurst
 199                      );
 200 #else /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
 201   /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,
 202            WAITEN, EXTMOD, ASYNCWAIT,CPSIZE,  CBURSTRW, CCLKEN and WFDIS bits */
 203   tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN     | FSMC_BCR1_MUXEN    | FSMC_BCR1_MTYP      | \
 204                        FSMC_BCR1_MWID      | FSMC_BCR1_FACCEN   | FSMC_BCR1_BURSTEN   | \
 205                        FSMC_BCR1_WAITPOL   | FSMC_BCR1_WAITCFG  | FSMC_BCR1_WREN      | \
 206                        FSMC_BCR1_WAITEN    | FSMC_BCR1_EXTMOD   | FSMC_BCR1_ASYNCWAIT | \
 207                        FSMC_BCR1_CPSIZE    | FSMC_BCR1_CBURSTRW | FSMC_BCR1_CCLKEN    | \
 208                        FSMC_BCR1_WFDIS));
 209   /* Set NORSRAM device control parameters */
 210   tmpr |= (uint32_t)(Init->DataAddressMux       |\
 211                      Init->MemoryType           |\
 212                      Init->MemoryDataWidth      |\
 213                      Init->BurstAccessMode      |\
 214                      Init->WaitSignalPolarity   |\
 215                      Init->WaitSignalActive     |\
 216                      Init->WriteOperation       |\
 217                      Init->WaitSignal           |\
 218                      Init->ExtendedMode         |\
 219                      Init->AsynchronousWait     |\
 220                      Init->WriteBurst           |\
 221                      Init->ContinuousClock      |\
 222                      Init->PageSize             |\
 223                      Init->WriteFifo);
 224 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
 225
 226   if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
 227   {
 228     tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
 229   }
 230
 231   Device->BTCR[Init->NSBank] = tmpr;
 232
 233 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
 234   /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
 235   if((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1))
 236   {
 237     Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock);
 238   }
 239
 240   if(Init->NSBank != FSMC_NORSRAM_BANK1)
 241   {
 242     Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
 243   }
 244 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
 245
 246   return HAL_OK;
 247 }
 248
 249 /**
 250   * @brief  DeInitialize the FSMC_NORSRAM peripheral
 251   * @param  Device: Pointer to NORSRAM device instance
 252   * @param  ExDevice: Pointer to NORSRAM extended mode device instance
 253   * @param  Bank: NORSRAM bank number
 254   * @retval HAL status
 255   */
 256 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
 257 {
 258   /* Check the parameters */
 259   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
 260   assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
 261   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
 262
 263   /* Disable the FSMC_NORSRAM device */
 264   __FSMC_NORSRAM_DISABLE(Device, Bank);
 265
 266   /* De-initialize the FSMC_NORSRAM device */
 267   /* FSMC_NORSRAM_BANK1 */
 268   if(Bank == FSMC_NORSRAM_BANK1)
 269   {
 270     Device->BTCR[Bank] = 0x000030DBU;
 271   }
 272   /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
 273   else
 274   {
 275     Device->BTCR[Bank] = 0x000030D2U;
 276   }
 277
 278   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
 279   ExDevice->BWTR[Bank]    = 0x0FFFFFFFU;
 280
 281   return HAL_OK;
 282 }
 283
 284
 285 /**
 286   * @brief  Initialize the FSMC_NORSRAM Timing according to the specified
 287   *         parameters in the FSMC_NORSRAM_TimingTypeDef
 288   * @param  Device: Pointer to NORSRAM device instance
 289   * @param  Timing: Pointer to NORSRAM Timing structure
 290   * @param  Bank: NORSRAM bank number
 291   * @retval HAL status
 292   */
 293 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
 294 {
 295   uint32_t tmpr = 0U;
 296
 297   /* Check the parameters */
 298   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
 299   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
 300   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
 301   assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
 302   assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
 303   assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
 304   assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
 305   assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
 306   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
 307
 308   /* Get the BTCR register value */
 309   tmpr = Device->BTCR[Bank + 1U];
 310
 311   /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
 312   tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET  | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \
 313                        FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \
 314                        FSMC_BTR1_ACCMOD));
 315
 316   /* Set FSMC_NORSRAM device timing parameters */
 317   tmpr |= (uint32_t)(Timing->AddressSetupTime                  |\
 318                     ((Timing->AddressHoldTime) << 4U)          |\
 319                     ((Timing->DataSetupTime) << 8U)            |\
 320                     ((Timing->BusTurnAroundDuration) << 16U)   |\
 321                     (((Timing->CLKDivision)-1U) << 20U)        |\
 322                     (((Timing->DataLatency)-2U) << 24U)        |\
 323                     (Timing->AccessMode));
 324
 325   Device->BTCR[Bank + 1] = tmpr;
 326
 327 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
 328   /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
 329   if(HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN))
 330   {
 331     tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~(0x0FU << 20U));
 332     tmpr |= (uint32_t)(((Timing->CLKDivision)-1U) << 20U);
 333     Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] = tmpr;
 334   }
 335 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
 336
 337   return HAL_OK;
 338 }
 339
 340 /**
 341   * @brief  Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
 342   *         parameters in the FSMC_NORSRAM_TimingTypeDef
 343   * @param  Device: Pointer to NORSRAM device instance
 344   * @param  Timing: Pointer to NORSRAM Timing structure
 345   * @param  Bank: NORSRAM bank number
 346   * @retval HAL status
 347   */
 348 HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
 349 {
 350   uint32_t tmpr = 0U;
 351
 352   /* Check the parameters */
 353   assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
 354
 355   /* Set NORSRAM device timing register for write configuration, if extended mode is used */
 356   if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
 357   {
 358     /* Check the parameters */
 359     assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
 360     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
 361     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
 362     assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
 363     assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
 364     assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
 365     assert_param(IS_FSMC_NORSRAM_BANK(Bank));
 366
 367     /* Get the BWTR register value */
 368     tmpr = Device->BWTR[Bank];
 369
 370     /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
 371     tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET  | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \
 372                          FSMC_BWTR1_BUSTURN | FSMC_BWTR1_ACCMOD));
 373
 374     tmpr |= (uint32_t)(Timing->AddressSetupTime                  |\
 375                       ((Timing->AddressHoldTime) << 4U)          |\
 376                       ((Timing->DataSetupTime) << 8U)            |\
 377                       ((Timing->BusTurnAroundDuration) << 16U)   |\
 378                       (Timing->AccessMode));
 379
 380     Device->BWTR[Bank] = tmpr;
 381   }
 382   else
 383   {
 384     Device->BWTR[Bank] = 0x0FFFFFFFU;
 385   }
 386
 387   return HAL_OK;
 388 }
 389 /**
 390   * @}
 391   */
 392
 393 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
 394   *  @brief   management functions
 395   *
 396 @verbatim
 397   ==============================================================================
 398                       ##### FSMC_NORSRAM Control functions #####
 399   ==============================================================================
 400   [..]
 401     This subsection provides a set of functions allowing to control dynamically
 402     the FSMC NORSRAM interface.
 403
 404 @endverbatim
 405   * @{
 406   */
 407
 408 /**
 409   * @brief  Enables dynamically FSMC_NORSRAM write operation.
 410   * @param  Device: Pointer to NORSRAM device instance
 411   * @param  Bank: NORSRAM bank number
 412   * @retval HAL status
 413   */
 414 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
 415 {
 416   /* Check the parameters */
 417   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
 418   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
 419
 420   /* Enable write operation */
 421   Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE;
 422
 423   return HAL_OK;
 424 }
 425
 426 /**
 427   * @brief  Disables dynamically FSMC_NORSRAM write operation.
 428   * @param  Device: Pointer to NORSRAM device instance
 429   * @param  Bank: NORSRAM bank number
 430   * @retval HAL status
 431   */
 432 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
 433 {
 434   /* Check the parameters */
 435   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
 436   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
 437
 438   /* Disable write operation */
 439   Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE;
 440
 441   return HAL_OK;
 442 }
 443 /**
 444   * @}
 445   */
 446
 447 /**
 448   * @}
 449   */
 450
 451 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
 452 /** @addtogroup FSMC_LL_NAND
 453   * @brief    NAND Controller functions
 454   *
 455   @verbatim
 456   ==============================================================================
 457                     ##### How to use NAND device driver #####
 458   ==============================================================================
 459   [..]
 460     This driver contains a set of APIs to interface with the FSMC NAND banks in order
 461     to run the NAND external devices.
 462
 463     (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
 464     (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
 465     (+) FSMC NAND bank common space timing configuration using the function
 466         FSMC_NAND_CommonSpace_Timing_Init()
 467     (+) FSMC NAND bank attribute space timing configuration using the function
 468         FSMC_NAND_AttributeSpace_Timing_Init()
 469     (+) FSMC NAND bank enable/disable ECC correction feature using the functions
 470         FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
 471     (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
 472
 473 @endverbatim
 474   * @{
 475   */
 476
 477 /** @addtogroup FSMC_LL_NAND_Private_Functions_Group1
 478   *  @brief    Initialization and Configuration functions
 479   *
 480 @verbatim
 481   ==============================================================================
 482               ##### Initialization and de_initialization functions #####
 483   ==============================================================================
 484   [..]
 485     This section provides functions allowing to:
 486     (+) Initialize and configure the FSMC NAND interface
 487     (+) De-initialize the FSMC NAND interface
 488     (+) Configure the FSMC clock and associated GPIOs
 489
 490 @endverbatim
 491   * @{
 492   */
 493
 494 /**
 495   * @brief  Initializes the FSMC_NAND device according to the specified
 496   *         control parameters in the FSMC_NAND_HandleTypeDef
 497   * @param  Device: Pointer to NAND device instance
 498   * @param  Init: Pointer to NAND Initialization structure
 499   * @retval HAL status
 500   */
 501 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
 502 {
 503   uint32_t tmpr  = 0U;
 504
 505   /* Check the parameters */
 506   assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
 507   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
 508   assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
 509   assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
 510   assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
 511   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
 512   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
 513
 514     if(Init->NandBank == FSMC_NAND_BANK2)
 515   {
 516     /* Get the NAND bank 2 register value */
 517     tmpr = Device->PCR2;
 518   }
 519   else
 520   {
 521     /* Get the NAND bank 3 register value */
 522     tmpr = Device->PCR3;
 523   }
 524
 525   /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
 526   tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN  | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \
 527                        FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
 528                        FSMC_PCR2_TAR | FSMC_PCR2_ECCPS));
 529
 530   /* Set NAND device control parameters */
 531   tmpr |= (uint32_t)(Init->Waitfeature                |\
 532                      FSMC_PCR_MEMORY_TYPE_NAND        |\
 533                      Init->MemoryDataWidth            |\
 534                      Init->EccComputation             |\
 535                      Init->ECCPageSize                |\
 536                      ((Init->TCLRSetupTime) << 9U)    |\
 537                      ((Init->TARSetupTime) << 13U));
 538
 539   if(Init->NandBank == FSMC_NAND_BANK2)
 540   {
 541     /* NAND bank 2 registers configuration */
 542     Device->PCR2  = tmpr;
 543   }
 544   else
 545   {
 546     /* NAND bank 3 registers configuration */
 547     Device->PCR3  = tmpr;
 548   }
 549
 550   return HAL_OK;
 551 }
 552
 553 /**
 554   * @brief  Initializes the FSMC_NAND Common space Timing according to the specified
 555   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 556   * @param  Device: Pointer to NAND device instance
 557   * @param  Timing: Pointer to NAND timing structure
 558   * @param  Bank: NAND bank number
 559   * @retval HAL status
 560   */
 561 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
 562 {
 563   uint32_t tmpr = 0U;
 564
 565   /* Check the parameters */
 566   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 567   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 568   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 569   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 570
 571   if(Bank == FSMC_NAND_BANK2)
 572   {
 573     /* Get the NAND bank 2 register value */
 574     tmpr = Device->PMEM2;
 575   }
 576   else
 577   {
 578     /* Get the NAND bank 3 register value */
 579     tmpr = Device->PMEM3;
 580   }
 581
 582   /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
 583   tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2  | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
 584                        FSMC_PMEM2_MEMHIZ2));
 585
 586   /* Set FSMC_NAND device timing parameters */
 587   tmpr |= (uint32_t)(Timing->SetupTime                     |\
 588                        ((Timing->WaitSetupTime) << 8U)     |\
 589                        ((Timing->HoldSetupTime) << 16U)    |\
 590                        ((Timing->HiZSetupTime) << 24U)
 591                        );
 592
 593   if(Bank == FSMC_NAND_BANK2)
 594   {
 595     /* NAND bank 2 registers configuration */
 596     Device->PMEM2 = tmpr;
 597   }
 598   else
 599   {
 600     /* NAND bank 3 registers configuration */
 601     Device->PMEM3 = tmpr;
 602   }
 603
 604   return HAL_OK;
 605 }
 606
 607 /**
 608   * @brief  Initializes the FSMC_NAND Attribute space Timing according to the specified
 609   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 610   * @param  Device: Pointer to NAND device instance
 611   * @param  Timing: Pointer to NAND timing structure
 612   * @param  Bank: NAND bank number
 613   * @retval HAL status
 614   */
 615 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
 616 {
 617   uint32_t tmpr = 0U;
 618
 619   /* Check the parameters */
 620   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 621   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 622   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 623   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 624
 625   if(Bank == FSMC_NAND_BANK2)
 626   {
 627     /* Get the NAND bank 2 register value */
 628     tmpr = Device->PATT2;
 629   }
 630   else
 631   {
 632     /* Get the NAND bank 3 register value */
 633     tmpr = Device->PATT3;
 634   }
 635
 636   /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
 637   tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2  | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
 638                        FSMC_PATT2_ATTHIZ2));
 639
 640   /* Set FSMC_NAND device timing parameters */
 641   tmpr |= (uint32_t)(Timing->SetupTime                     |\
 642                        ((Timing->WaitSetupTime) << 8U)     |\
 643                        ((Timing->HoldSetupTime) << 16U)    |\
 644                        ((Timing->HiZSetupTime) << 24U)
 645                        );
 646
 647   if(Bank == FSMC_NAND_BANK2)
 648   {
 649     /* NAND bank 2 registers configuration */
 650     Device->PATT2 = tmpr;
 651   }
 652   else
 653   {
 654     /* NAND bank 3 registers configuration */
 655     Device->PATT3 = tmpr;
 656   }
 657
 658   return HAL_OK;
 659 }
 660
 661 /**
 662   * @brief  DeInitializes the FSMC_NAND device
 663   * @param  Device: Pointer to NAND device instance
 664   * @param  Bank: NAND bank number
 665   * @retval HAL status
 666   */
 667 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
 668 {
 669   /* Disable the NAND Bank */
 670   __FSMC_NAND_DISABLE(Device, Bank);
 671
 672   /* De-initialize the NAND Bank */
 673   if(Bank == FSMC_NAND_BANK2)
 674   {
 675     /* Set the FSMC_NAND_BANK2 registers to their reset values */
 676     Device->PCR2  = 0x00000018U;
 677     Device->SR2   = 0x00000040U;
 678     Device->PMEM2 = 0xFCFCFCFCU;
 679     Device->PATT2 = 0xFCFCFCFCU;
 680   }
 681   /* FSMC_Bank3_NAND */
 682   else
 683   {
 684     /* Set the FSMC_NAND_BANK3 registers to their reset values */
 685     Device->PCR3  = 0x00000018U;
 686     Device->SR3   = 0x00000040U;
 687     Device->PMEM3 = 0xFCFCFCFCU;
 688     Device->PATT3 = 0xFCFCFCFCU;
 689   }
 690
 691   return HAL_OK;
 692 }
 693 /**
 694   * @}
 695   */
 696
 697 /** @addtogroup FSMC_LL_NAND_Private_Functions_Group2
 698   *  @brief   management functions
 699   *
 700 @verbatim
 701   ==============================================================================
 702                        ##### FSMC_NAND Control functions #####
 703   ==============================================================================
 704   [..]
 705     This subsection provides a set of functions allowing to control dynamically
 706     the FSMC NAND interface.
 707
 708 @endverbatim
 709   * @{
 710   */
 711
 712 /**
 713   * @brief  Enables dynamically FSMC_NAND ECC feature.
 714   * @param  Device: Pointer to NAND device instance
 715   * @param  Bank: NAND bank number
 716   * @retval HAL status
 717   */
 718 HAL_StatusTypeDef  FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
 719 {
 720   /* Enable ECC feature */
 721   if(Bank == FSMC_NAND_BANK2)
 722   {
 723     Device->PCR2 |= FSMC_PCR2_ECCEN;
 724   }
 725   else
 726   {
 727     Device->PCR3 |= FSMC_PCR3_ECCEN;
 728   }
 729
 730   return HAL_OK;
 731 }
 732
 733 /**
 734   * @brief  Disables dynamically FSMC_NAND ECC feature.
 735   * @param  Device: Pointer to NAND device instance
 736   * @param  Bank: NAND bank number
 737   * @retval HAL status
 738   */
 739 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
 740 {
 741   /* Disable ECC feature */
 742   if(Bank == FSMC_NAND_BANK2)
 743   {
 744     Device->PCR2 &= ~FSMC_PCR2_ECCEN;
 745   }
 746   else
 747   {
 748     Device->PCR3 &= ~FSMC_PCR3_ECCEN;
 749   }
 750
 751   return HAL_OK;
 752 }
 753
 754 /**
 755   * @brief  Disables dynamically FSMC_NAND ECC feature.
 756   * @param  Device: Pointer to NAND device instance
 757   * @param  ECCval: Pointer to ECC value
 758   * @param  Bank: NAND bank number
 759   * @param  Timeout: Timeout wait value
 760   * @retval HAL status
 761   */
 762 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
 763 {
 764   uint32_t tickstart = 0U;
 765
 766   /* Check the parameters */
 767   assert_param(IS_FSMC_NAND_DEVICE(Device));
 768   assert_param(IS_FSMC_NAND_BANK(Bank));
 769
 770   /* Get tick */
 771   tickstart = HAL_GetTick();
 772
 773   /* Wait until FIFO is empty */
 774   while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
 775   {
 776     /* Check for the Timeout */
 777     if(Timeout != HAL_MAX_DELAY)
 778     {
 779       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
 780       {
 781         return HAL_TIMEOUT;
 782       }
 783     }
 784   }
 785
 786   if(Bank == FSMC_NAND_BANK2)
 787   {
 788     /* Get the ECCR2 register value */
 789     *ECCval = (uint32_t)Device->ECCR2;
 790   }
 791   else
 792   {
 793     /* Get the ECCR3 register value */
 794     *ECCval = (uint32_t)Device->ECCR3;
 795   }
 796
 797   return HAL_OK;
 798 }
 799
 800 /**
 801   * @}
 802   */
 803
 804 /**
 805   * @}
 806   */
 807
 808 /** @addtogroup FSMC_LL_PCCARD
 809   * @brief    PCCARD Controller functions
 810   *
 811   @verbatim
 812   ==============================================================================
 813                     ##### How to use PCCARD device driver #####
 814   ==============================================================================
 815   [..]
 816     This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
 817     to run the PCCARD/compact flash external devices.
 818
 819     (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
 820     (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
 821     (+) FSMC PCCARD bank common space timing configuration using the function
 822         FSMC_PCCARD_CommonSpace_Timing_Init()
 823     (+) FSMC PCCARD bank attribute space timing configuration using the function
 824         FSMC_PCCARD_AttributeSpace_Timing_Init()
 825     (+) FSMC PCCARD bank IO space timing configuration using the function
 826         FSMC_PCCARD_IOSpace_Timing_Init()
 827
 828 @endverbatim
 829   * @{
 830   */
 831
 832 /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
 833   *  @brief   Initialization and Configuration functions
 834   *
 835 @verbatim
 836   ==============================================================================
 837               ##### Initialization and de_initialization functions #####
 838   ==============================================================================
 839   [..]
 840     This section provides functions allowing to:
 841     (+) Initialize and configure the FSMC PCCARD interface
 842     (+) De-initialize the FSMC PCCARD interface
 843     (+) Configure the FSMC clock and associated GPIOs
 844
 845 @endverbatim
 846   * @{
 847   */
 848
 849 /**
 850   * @brief  Initializes the FSMC_PCCARD device according to the specified
 851   *         control parameters in the FSMC_PCCARD_HandleTypeDef
 852   * @param  Device: Pointer to PCCARD device instance
 853   * @param  Init: Pointer to PCCARD Initialization structure
 854   * @retval HAL status
 855   */
 856 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
 857 {
 858   uint32_t tmpr = 0U;
 859
 860   /* Check the parameters */
 861   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
 862   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
 863   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
 864
 865   /* Get PCCARD control register value */
 866   tmpr = Device->PCR4;
 867
 868   /* Clear TAR, TCLR, PWAITEN and PWID bits */
 869   tmpr &= ((uint32_t)~(FSMC_PCR4_TAR  | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
 870                        FSMC_PCR4_PWID));
 871
 872   /* Set FSMC_PCCARD device control parameters */
 873   tmpr |= (uint32_t)(Init->Waitfeature               |\
 874                      FSMC_NAND_PCC_MEM_BUS_WIDTH_16  |\
 875                      (Init->TCLRSetupTime << 9U)     |\
 876                      (Init->TARSetupTime << 13U));
 877
 878   Device->PCR4 = tmpr;
 879
 880   return HAL_OK;
 881 }
 882
 883 /**
 884   * @brief  Initializes the FSMC_PCCARD Common space Timing according to the specified
 885   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 886   * @param  Device: Pointer to PCCARD device instance
 887   * @param  Timing: Pointer to PCCARD timing structure
 888   * @retval HAL status
 889   */
 890 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
 891 {
 892   uint32_t tmpr = 0U;
 893
 894   /* Check the parameters */
 895   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 896   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 897   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 898   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 899
 900   /* Get PCCARD common space timing register value */
 901   tmpr = Device->PMEM4;
 902
 903   /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
 904   tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4  | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
 905                        FSMC_PMEM4_MEMHIZ4));
 906   /* Set PCCARD timing parameters */
 907   tmpr |= (uint32_t)((Timing->SetupTime                 |\
 908                     ((Timing->WaitSetupTime) << 8U)     |\
 909                     (Timing->HoldSetupTime) << 16U)     |\
 910                     ((Timing->HiZSetupTime) << 24U));
 911
 912   Device->PMEM4 = tmpr;
 913
 914   return HAL_OK;
 915 }
 916
 917 /**
 918   * @brief  Initializes the FSMC_PCCARD Attribute space Timing according to the specified
 919   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 920   * @param  Device: Pointer to PCCARD device instance
 921   * @param  Timing: Pointer to PCCARD timing structure
 922   * @retval HAL status
 923   */
 924 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
 925 {
 926   uint32_t tmpr = 0U;
 927
 928   /* Check the parameters */
 929   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 930   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 931   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 932   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 933
 934   /* Get PCCARD timing parameters */
 935   tmpr = Device->PATT4;
 936
 937   /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
 938   tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4  | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
 939                        FSMC_PATT4_ATTHIZ4));
 940
 941   /* Set PCCARD timing parameters */
 942   tmpr |= (uint32_t)(Timing->SetupTime                 |\
 943                    ((Timing->WaitSetupTime) << 8U)     |\
 944                    ((Timing->HoldSetupTime) << 16U)    |\
 945                    ((Timing->HiZSetupTime) << 24U));
 946   Device->PATT4 = tmpr;
 947
 948   return HAL_OK;
 949 }
 950
 951 /**
 952   * @brief  Initializes the FSMC_PCCARD IO space Timing according to the specified
 953   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 954   * @param  Device: Pointer to PCCARD device instance
 955   * @param  Timing: Pointer to PCCARD timing structure
 956   * @retval HAL status
 957   */
 958 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
 959 {
 960   uint32_t tmpr = 0U;
 961
 962   /* Check the parameters */
 963   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 964   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 965   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 966   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 967
 968   /* Get FSMC_PCCARD device timing parameters */
 969   tmpr = Device->PIO4;
 970
 971   /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
 972   tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4  | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
 973                        FSMC_PIO4_IOHIZ4));
 974
 975   /* Set FSMC_PCCARD device timing parameters */
 976   tmpr |= (uint32_t)(Timing->SetupTime                   |\
 977                      ((Timing->WaitSetupTime) << 8U)     |\
 978                      ((Timing->HoldSetupTime) << 16U)    |\
 979                      ((Timing->HiZSetupTime) << 24U));
 980
 981   Device->PIO4 = tmpr;
 982
 983   return HAL_OK;
 984 }
 985
 986 /**
 987   * @brief  DeInitializes the FSMC_PCCARD device
 988   * @param  Device: Pointer to PCCARD device instance
 989   * @retval HAL status
 990   */
 991 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
 992 {
 993   /* Disable the FSMC_PCCARD device */
 994   __FSMC_PCCARD_DISABLE(Device);
 995
 996   /* De-initialize the FSMC_PCCARD device */
 997   Device->PCR4    = 0x00000018U;
 998   Device->SR4     = 0x00000000U;
 999   Device->PMEM4   = 0xFCFCFCFCU;
1000   Device->PATT4   = 0xFCFCFCFCU;
1001   Device->PIO4    = 0xFCFCFCFCU;
1002
1003   return HAL_OK;
1004 }
1005 /**
1006   * @}
1007   */
1008
1009 /**
1010   * @}
1011   */
1012 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
1013
1014 /**
1015   * @}
1016   */
1017 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */
1018 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
1019
1020 /**
1021   * @}
1022   */
1023
1024 /**
1025   * @}
1026   */
1027 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/