?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge pull request #11198 from SteveCEvans/sce_rc2
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_HAL_Driver / Src / stm32f4xx_ll_rcc.c
blob80c1368a54274edd6e16a40fc86cadbe8b88e2ad
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_rcc.c
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 14-April-2017
7 * @brief RCC LL module driver.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37 #if defined(USE_FULL_LL_DRIVER)
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32f4xx_ll_rcc.h"
41 #ifdef USE_FULL_ASSERT
42 #include "stm32_assert.h"
43 #else
44 #define assert_param(expr) ((void)0U)
45 #endif
46 /** @addtogroup STM32F4xx_LL_Driver
47 * @{
48 */
49
50 #if defined(RCC)
51
52 /** @addtogroup RCC_LL
53 * @{
54 */
55
56 /* Private types -------------------------------------------------------------*/
57 /* Private variables ---------------------------------------------------------*/
58 /* Private constants ---------------------------------------------------------*/
59 /* Private macros ------------------------------------------------------------*/
60 /** @addtogroup RCC_LL_Private_Macros
61 * @{
62 */
63 #if defined(FMPI2C1)
64 #define IS_LL_RCC_FMPI2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_FMPI2C1_CLKSOURCE)
65 #endif /* FMPI2C1 */
66
67 #if defined(LPTIM1)
68 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
69 #endif /* LPTIM1 */
70
71 #if defined(SAI1)
72 #if defined(RCC_DCKCFGR_SAI1SRC)
73 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
74 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
75 #elif defined(RCC_DCKCFGR_SAI1ASRC)
76 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_A_CLKSOURCE) \
77 || ((__VALUE__) == LL_RCC_SAI1_B_CLKSOURCE))
78 #endif /* RCC_DCKCFGR_SAI1SRC */
79 #endif /* SAI1 */
80
81 #if defined(SDIO)
82 #define IS_LL_RCC_SDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDIO_CLKSOURCE))
83 #endif /* SDIO */
84
85 #if defined(RNG)
86 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
87 #endif /* RNG */
88
89 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
90 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
91 #endif /* USB_OTG_FS || USB_OTG_HS */
92
93 #if defined(DFSDM2_Channel0)
94 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
95
96 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE) \
97 || ((__VALUE__) == LL_RCC_DFSDM2_AUDIO_CLKSOURCE))
98 #elif defined(DFSDM1_Channel0)
99 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
100
101 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
102 #endif /* DFSDM2_Channel0 */
103
104 #if defined(RCC_DCKCFGR_I2S2SRC)
105 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE) \
106 || ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE))
107 #else
108 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
109 #endif /* RCC_DCKCFGR_I2S2SRC */
110
111 #if defined(CEC)
112 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
113 #endif /* CEC */
114
115 #if defined(DSI)
116 #define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
117 #endif /* DSI */
118
119 #if defined(LTDC)
120 #define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
121 #endif /* LTDC */
122
123 #if defined(SPDIFRX)
124 #define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE))
125 #endif /* SPDIFRX */
126 /**
127 * @}
128 */
129
130 /* Private function prototypes -----------------------------------------------*/
131 /** @defgroup RCC_LL_Private_Functions RCC Private functions
132 * @{
133 */
134 uint32_t RCC_GetSystemClockFreq(void);
135 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
136 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
137 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
138 uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source);
139 uint32_t RCC_PLL_GetFreqDomain_48M(void);
140 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
141 uint32_t RCC_PLL_GetFreqDomain_I2S(void);
142 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
143 #if defined(SPDIFRX)
144 uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void);
145 #endif /* SPDIFRX */
146 #if defined(RCC_PLLCFGR_PLLR)
147 #if defined(SAI1)
148 uint32_t RCC_PLL_GetFreqDomain_SAI(void);
149 #endif /* SAI1 */
150 #endif /* RCC_PLLCFGR_PLLR */
151 #if defined(DSI)
152 uint32_t RCC_PLL_GetFreqDomain_DSI(void);
153 #endif /* DSI */
154 #if defined(RCC_PLLSAI_SUPPORT)
155 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void);
156 #if defined(RCC_PLLSAICFGR_PLLSAIP)
157 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void);
158 #endif /* RCC_PLLSAICFGR_PLLSAIP */
159 #if defined(LTDC)
160 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void);
161 #endif /* LTDC */
162 #endif /* RCC_PLLSAI_SUPPORT */
163 #if defined(RCC_PLLI2S_SUPPORT)
164 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
165 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
166 uint32_t RCC_PLLI2S_GetFreqDomain_48M(void);
167 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
168 #if defined(SAI1)
169 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void);
170 #endif /* SAI1 */
171 #if defined(SPDIFRX)
172 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);
173 #endif /* SPDIFRX */
174 #endif /* RCC_PLLI2S_SUPPORT */
175 /**
176 * @}
177 */
178
179
180 /* Exported functions --------------------------------------------------------*/
181 /** @addtogroup RCC_LL_Exported_Functions
182 * @{
183 */
184
185 /** @addtogroup RCC_LL_EF_Init
186 * @{
187 */
188
189 /**
190 * @brief Reset the RCC clock configuration to the default reset state.
191 * @note The default reset state of the clock configuration is given below:
192 * - HSI ON and used as system clock source
193 * - HSE and PLL OFF
194 * - AHB, APB1 and APB2 prescaler set to 1.
195 * - CSS, MCO OFF
196 * - All interrupts disabled
197 * @note This function doesn't modify the configuration of the
198 * - Peripheral clocks
199 * - LSI, LSE and RTC clocks
200 * @retval An ErrorStatus enumeration value:
201 * - SUCCESS: RCC registers are de-initialized
202 * - ERROR: not applicable
203 */
204 ErrorStatus LL_RCC_DeInit(void)
205 {
206 uint32_t vl_mask = 0U;
207
208 /* Set HSION bit */
209 LL_RCC_HSI_Enable();
210
211 /* Reset CFGR register */
212 LL_RCC_WriteReg(CFGR, 0x00000000U);
213
214 vl_mask = 0xFFFFFFFFU;
215
216 /* Reset HSEON, PLLSYSON bits */
217 CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON));
218
219 #if defined(RCC_PLLSAI_SUPPORT)
220 /* Reset PLLSAION bit */
221 CLEAR_BIT(vl_mask, RCC_CR_PLLSAION);
222 #endif /* RCC_PLLSAI_SUPPORT */
223
224 #if defined(RCC_PLLI2S_SUPPORT)
225 /* Reset PLLI2SON bit */
226 CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON);
227 #endif /* RCC_PLLI2S_SUPPORT */
228
229 /* Write new mask in CR register */
230 LL_RCC_WriteReg(CR, vl_mask);
231
232 /* Set HSITRIM bits to the reset value*/
233 LL_RCC_HSI_SetCalibTrimming(0x10U);
234
235 /* Reset PLLCFGR register */
236 LL_RCC_WriteReg(PLLCFGR, RCC_PLLCFGR_RST_VALUE);
237
238 #if defined(RCC_PLLI2S_SUPPORT)
239 /* Reset PLLI2SCFGR register */
240 LL_RCC_WriteReg(PLLI2SCFGR, RCC_PLLI2SCFGR_RST_VALUE);
241 #endif /* RCC_PLLI2S_SUPPORT */
242
243 #if defined(RCC_PLLSAI_SUPPORT)
244 /* Reset PLLSAICFGR register */
245 LL_RCC_WriteReg(PLLSAICFGR, RCC_PLLSAICFGR_RST_VALUE);
246 #endif /* RCC_PLLSAI_SUPPORT */
247
248 /* Reset HSEBYP bit */
249 LL_RCC_HSE_DisableBypass();
250
251 /* Disable all interrupts */
252 LL_RCC_WriteReg(CIR, 0x00000000U);
253
254 return SUCCESS;
255 }
256
257 /**
258 * @}
259 */
260
261 /** @addtogroup RCC_LL_EF_Get_Freq
262 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
263 * and different peripheral clocks available on the device.
264 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
265 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
266 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
267 * or HSI_VALUE(**) multiplied/divided by the PLL factors.
268 * @note (**) HSI_VALUE is a constant defined in this file (default value
269 * 16 MHz) but the real value may vary depending on the variations
270 * in voltage and temperature.
271 * @note (***) HSE_VALUE is a constant defined in this file (default value
272 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
273 * frequency of the crystal used. Otherwise, this function may
274 * have wrong result.
275 * @note The result of this function could be incorrect when using fractional
276 * value for HSE crystal.
277 * @note This function can be used by the user application to compute the
278 * baud-rate for the communication peripherals or configure other parameters.
279 * @{
280 */
281
282 /**
283 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
284 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
285 * must be called to update structure fields. Otherwise, any
286 * configuration based on this function will be incorrect.
287 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
288 * @retval None
289 */
290 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
291 {
292 /* Get SYSCLK frequency */
293 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
294
295 /* HCLK clock frequency */
296 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
297
298 /* PCLK1 clock frequency */
299 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
300
301 /* PCLK2 clock frequency */
302 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
303 }
304
305 #if defined(FMPI2C1)
306 /**
307 * @brief Return FMPI2Cx clock frequency
308 * @param FMPI2CxSource This parameter can be one of the following values:
309 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
310 * @retval FMPI2C clock frequency (in Hz)
311 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
312 */
313 uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource)
314 {
315 uint32_t FMPI2C_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
316
317 /* Check parameter */
318 assert_param(IS_LL_RCC_FMPI2C_CLKSOURCE(FMPI2CxSource));
319
320 if (FMPI2CxSource == LL_RCC_FMPI2C1_CLKSOURCE)
321 {
322 /* FMPI2C1 CLK clock frequency */
323 switch (LL_RCC_GetFMPI2CClockSource(FMPI2CxSource))
324 {
325 case LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK: /* FMPI2C1 Clock is System Clock */
326 FMPI2C_frequency = RCC_GetSystemClockFreq();
327 break;
328
329 case LL_RCC_FMPI2C1_CLKSOURCE_HSI: /* FMPI2C1 Clock is HSI Osc. */
330 if (LL_RCC_HSI_IsReady())
331 {
332 FMPI2C_frequency = HSI_VALUE;
333 }
334 break;
335
336 case LL_RCC_FMPI2C1_CLKSOURCE_PCLK1: /* FMPI2C1 Clock is PCLK1 */
337 default:
338 FMPI2C_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
339 break;
340 }
341 }
342
343 return FMPI2C_frequency;
344 }
345 #endif /* FMPI2C1 */
346
347 /**
348 * @brief Return I2Sx clock frequency
349 * @param I2SxSource This parameter can be one of the following values:
350 * @arg @ref LL_RCC_I2S1_CLKSOURCE
351 * @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
352 *
353 * (*) value not defined in all devices.
354 * @retval I2S clock frequency (in Hz)
355 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
356 */
357 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
358 {
359 uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
360
361 /* Check parameter */
362 assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
363
364 if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
365 {
366 /* I2S1 CLK clock frequency */
367 switch (LL_RCC_GetI2SClockSource(I2SxSource))
368 {
369 #if defined(RCC_PLLI2S_SUPPORT)
370 case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */
371 if (LL_RCC_PLLI2S_IsReady())
372 {
373 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
374 }
375 break;
376 #endif /* RCC_PLLI2S_SUPPORT */
377
378 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
379 case LL_RCC_I2S1_CLKSOURCE_PLL: /* I2S1 Clock is PLL */
380 if (LL_RCC_PLL_IsReady())
381 {
382 i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
383 }
384 break;
385
386 case LL_RCC_I2S1_CLKSOURCE_PLLSRC: /* I2S1 Clock is PLL Main source */
387 switch (LL_RCC_PLL_GetMainSource())
388 {
389 case LL_RCC_PLLSOURCE_HSE: /* I2S1 Clock is HSE Osc. */
390 if (LL_RCC_HSE_IsReady())
391 {
392 i2s_frequency = HSE_VALUE;
393 }
394 break;
395
396 case LL_RCC_PLLSOURCE_HSI: /* I2S1 Clock is HSI Osc. */
397 default:
398 if (LL_RCC_HSI_IsReady())
399 {
400 i2s_frequency = HSI_VALUE;
401 }
402 break;
403 }
404 break;
405 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
406
407 case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */
408 default:
409 i2s_frequency = EXTERNAL_CLOCK_VALUE;
410 break;
411 }
412 }
413 #if defined(RCC_DCKCFGR_I2S2SRC)
414 else
415 {
416 /* I2S2 CLK clock frequency */
417 switch (LL_RCC_GetI2SClockSource(I2SxSource))
418 {
419 case LL_RCC_I2S2_CLKSOURCE_PLLI2S: /* I2S2 Clock is PLLI2S */
420 if (LL_RCC_PLLI2S_IsReady())
421 {
422 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
423 }
424 break;
425
426 case LL_RCC_I2S2_CLKSOURCE_PLL: /* I2S2 Clock is PLL */
427 if (LL_RCC_PLL_IsReady())
428 {
429 i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
430 }
431 break;
432
433 case LL_RCC_I2S2_CLKSOURCE_PLLSRC: /* I2S2 Clock is PLL Main source */
434 switch (LL_RCC_PLL_GetMainSource())
435 {
436 case LL_RCC_PLLSOURCE_HSE: /* I2S2 Clock is HSE Osc. */
437 if (LL_RCC_HSE_IsReady())
438 {
439 i2s_frequency = HSE_VALUE;
440 }
441 break;
442
443 case LL_RCC_PLLSOURCE_HSI: /* I2S2 Clock is HSI Osc. */
444 default:
445 if (LL_RCC_HSI_IsReady())
446 {
447 i2s_frequency = HSI_VALUE;
448 }
449 break;
450 }
451 break;
452
453 case LL_RCC_I2S2_CLKSOURCE_PIN: /* I2S2 Clock is External clock */
454 default:
455 i2s_frequency = EXTERNAL_CLOCK_VALUE;
456 break;
457 }
458 }
459 #endif /* RCC_DCKCFGR_I2S2SRC */
460
461 return i2s_frequency;
462 }
463
464 #if defined(LPTIM1)
465 /**
466 * @brief Return LPTIMx clock frequency
467 * @param LPTIMxSource This parameter can be one of the following values:
468 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
469 * @retval LPTIM clock frequency (in Hz)
470 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
471 */
472 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
473 {
474 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
475
476 /* Check parameter */
477 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
478
479 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
480 {
481 /* LPTIM1CLK clock frequency */
482 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
483 {
484 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
485 if (LL_RCC_LSI_IsReady())
486 {
487 lptim_frequency = LSI_VALUE;
488 }
489 break;
490
491 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
492 if (LL_RCC_HSI_IsReady())
493 {
494 lptim_frequency = HSI_VALUE;
495 }
496 break;
497
498 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
499 if (LL_RCC_LSE_IsReady())
500 {
501 lptim_frequency = LSE_VALUE;
502 }
503 break;
504
505 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
506 default:
507 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
508 break;
509 }
510 }
511
512 return lptim_frequency;
513 }
514 #endif /* LPTIM1 */
515
516 #if defined(SAI1)
517 /**
518 * @brief Return SAIx clock frequency
519 * @param SAIxSource This parameter can be one of the following values:
520 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
521 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
522 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
523 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
524 *
525 * (*) value not defined in all devices.
526 * @retval SAI clock frequency (in Hz)
527 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
528 */
529 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
530 {
531 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
532
533 /* Check parameter */
534 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
535
536 #if defined(RCC_DCKCFGR_SAI1SRC)
537 if ((SAIxSource == LL_RCC_SAI1_CLKSOURCE) || (SAIxSource == LL_RCC_SAI2_CLKSOURCE))
538 {
539 /* SAI1CLK clock frequency */
540 switch (LL_RCC_GetSAIClockSource(SAIxSource))
541 {
542 case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */
543 case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */
544 if (LL_RCC_PLLSAI_IsReady())
545 {
546 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
547 }
548 break;
549
550 case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */
551 case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */
552 if (LL_RCC_PLLI2S_IsReady())
553 {
554 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
555 }
556 break;
557
558 case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
559 case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */
560 if (LL_RCC_PLL_IsReady())
561 {
562 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
563 }
564 break;
565
566 case LL_RCC_SAI2_CLKSOURCE_PLLSRC:
567 switch (LL_RCC_PLL_GetMainSource())
568 {
569 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */
570 if (LL_RCC_HSE_IsReady())
571 {
572 sai_frequency = HSE_VALUE;
573 }
574 break;
575
576 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */
577 default:
578 if (LL_RCC_HSI_IsReady())
579 {
580 sai_frequency = HSI_VALUE;
581 }
582 break;
583 }
584 break;
585
586 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
587 default:
588 sai_frequency = EXTERNAL_CLOCK_VALUE;
589 break;
590 }
591 }
592 #endif /* RCC_DCKCFGR_SAI1SRC */
593 #if defined(RCC_DCKCFGR_SAI1ASRC)
594 if ((SAIxSource == LL_RCC_SAI1_A_CLKSOURCE) || (SAIxSource == LL_RCC_SAI1_B_CLKSOURCE))
595 {
596 /* SAI1CLK clock frequency */
597 switch (LL_RCC_GetSAIClockSource(SAIxSource))
598 {
599 #if defined(RCC_PLLSAI_SUPPORT)
600 case LL_RCC_SAI1_A_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block A clock source */
601 case LL_RCC_SAI1_B_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block B clock source */
602 if (LL_RCC_PLLSAI_IsReady())
603 {
604 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
605 }
606 break;
607 #endif /* RCC_PLLSAI_SUPPORT */
608
609 case LL_RCC_SAI1_A_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block A clock source */
610 case LL_RCC_SAI1_B_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block B clock source */
611 if (LL_RCC_PLLI2S_IsReady())
612 {
613 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
614 }
615 break;
616
617 #if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
618 case LL_RCC_SAI1_A_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block A clock source */
619 case LL_RCC_SAI1_B_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block B clock source */
620 if (LL_RCC_PLL_IsReady())
621 {
622 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
623 }
624 break;
625
626 case LL_RCC_SAI1_A_CLKSOURCE_PLLSRC:
627 case LL_RCC_SAI1_B_CLKSOURCE_PLLSRC:
628 switch (LL_RCC_PLL_GetMainSource())
629 {
630 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 Block A or B clock source */
631 if (LL_RCC_HSE_IsReady())
632 {
633 sai_frequency = HSE_VALUE;
634 }
635 break;
636
637 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 Block A or B clock source */
638 default:
639 if (LL_RCC_HSI_IsReady())
640 {
641 sai_frequency = HSI_VALUE;
642 }
643 break;
644 }
645 break;
646 #endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
647
648 case LL_RCC_SAI1_A_CLKSOURCE_PIN: /* External input clock used as SAI1 Block A clock source */
649 case LL_RCC_SAI1_B_CLKSOURCE_PIN: /* External input clock used as SAI1 Block B clock source */
650 default:
651 sai_frequency = EXTERNAL_CLOCK_VALUE;
652 break;
653 }
654 }
655 #endif /* RCC_DCKCFGR_SAI1ASRC */
656
657 return sai_frequency;
658 }
659 #endif /* SAI1 */
660
661 #if defined(SDIO)
662 /**
663 * @brief Return SDIOx clock frequency
664 * @param SDIOxSource This parameter can be one of the following values:
665 * @arg @ref LL_RCC_SDIO_CLKSOURCE
666 * @retval SDIO clock frequency (in Hz)
667 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
668 */
669 uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource)
670 {
671 uint32_t SDIO_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
672
673 /* Check parameter */
674 assert_param(IS_LL_RCC_SDIO_CLKSOURCE(SDIOxSource));
675
676 if (SDIOxSource == LL_RCC_SDIO_CLKSOURCE)
677 {
678 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
679 /* SDIOCLK clock frequency */
680 switch (LL_RCC_GetSDIOClockSource(SDIOxSource))
681 {
682 case LL_RCC_SDIO_CLKSOURCE_PLL48CLK: /* PLL48M clock used as SDIO clock source */
683 switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
684 {
685 case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
686 if (LL_RCC_PLL_IsReady())
687 {
688 SDIO_frequency = RCC_PLL_GetFreqDomain_48M();
689 }
690 break;
691
692 #if defined(RCC_PLLSAI_SUPPORT)
693 case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
694 default:
695 if (LL_RCC_PLLSAI_IsReady())
696 {
697 SDIO_frequency = RCC_PLLSAI_GetFreqDomain_48M();
698 }
699 break;
700 #endif /* RCC_PLLSAI_SUPPORT */
701
702 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
703 case LL_RCC_CK48M_CLKSOURCE_PLLI2S: /* PLLI2S clock used as 48Mhz domain clock */
704 default:
705 if (LL_RCC_PLLI2S_IsReady())
706 {
707 SDIO_frequency = RCC_PLLI2S_GetFreqDomain_48M();
708 }
709 break;
710 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
711 }
712 break;
713
714 case LL_RCC_SDIO_CLKSOURCE_SYSCLK: /* PLL clock used as SDIO clock source */
715 default:
716 SDIO_frequency = RCC_GetSystemClockFreq();
717 break;
718 }
719 #else
720 /* PLL clock used as 48Mhz domain clock */
721 if (LL_RCC_PLL_IsReady())
722 {
723 SDIO_frequency = RCC_PLL_GetFreqDomain_48M();
724 }
725 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
726 }
727
728 return SDIO_frequency;
729 }
730 #endif /* SDIO */
731
732 #if defined(RNG)
733 /**
734 * @brief Return RNGx clock frequency
735 * @param RNGxSource This parameter can be one of the following values:
736 * @arg @ref LL_RCC_RNG_CLKSOURCE
737 * @retval RNG clock frequency (in Hz)
738 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
739 */
740 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
741 {
742 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
743
744 /* Check parameter */
745 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
746
747 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
748 /* RNGCLK clock frequency */
749 switch (LL_RCC_GetRNGClockSource(RNGxSource))
750 {
751 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
752 case LL_RCC_RNG_CLKSOURCE_PLLI2S: /* PLLI2S clock used as RNG clock source */
753 if (LL_RCC_PLLI2S_IsReady())
754 {
755 rng_frequency = RCC_PLLI2S_GetFreqDomain_48M();
756 }
757 break;
758 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
759
760 #if defined(RCC_PLLSAI_SUPPORT)
761 case LL_RCC_RNG_CLKSOURCE_PLLSAI: /* PLLSAI clock used as RNG clock source */
762 if (LL_RCC_PLLSAI_IsReady())
763 {
764 rng_frequency = RCC_PLLSAI_GetFreqDomain_48M();
765 }
766 break;
767 #endif /* RCC_PLLSAI_SUPPORT */
768
769 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
770 default:
771 if (LL_RCC_PLL_IsReady())
772 {
773 rng_frequency = RCC_PLL_GetFreqDomain_48M();
774 }
775 break;
776 }
777 #else
778 /* PLL clock used as RNG clock source */
779 if (LL_RCC_PLL_IsReady())
780 {
781 rng_frequency = RCC_PLL_GetFreqDomain_48M();
782 }
783 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
784
785 return rng_frequency;
786 }
787 #endif /* RNG */
788
789 #if defined(CEC)
790 /**
791 * @brief Return CEC clock frequency
792 * @param CECxSource This parameter can be one of the following values:
793 * @arg @ref LL_RCC_CEC_CLKSOURCE
794 * @retval CEC clock frequency (in Hz)
795 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
796 */
797 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
798 {
799 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
800
801 /* Check parameter */
802 assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
803
804 /* CECCLK clock frequency */
805 switch (LL_RCC_GetCECClockSource(CECxSource))
806 {
807 case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */
808 if (LL_RCC_LSE_IsReady())
809 {
810 cec_frequency = LSE_VALUE;
811 }
812 break;
813
814 case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */
815 default:
816 if (LL_RCC_HSI_IsReady())
817 {
818 cec_frequency = HSI_VALUE/488U;
819 }
820 break;
821 }
822
823 return cec_frequency;
824 }
825 #endif /* CEC */
826
827 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
828 /**
829 * @brief Return USBx clock frequency
830 * @param USBxSource This parameter can be one of the following values:
831 * @arg @ref LL_RCC_USB_CLKSOURCE
832 * @retval USB clock frequency (in Hz)
833 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
834 */
835 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
836 {
837 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
838
839 /* Check parameter */
840 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
841
842 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
843 /* USBCLK clock frequency */
844 switch (LL_RCC_GetUSBClockSource(USBxSource))
845 {
846 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
847 case LL_RCC_USB_CLKSOURCE_PLLI2S: /* PLLI2S clock used as USB clock source */
848 if (LL_RCC_PLLI2S_IsReady())
849 {
850 usb_frequency = RCC_PLLI2S_GetFreqDomain_48M();
851 }
852 break;
853
854 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
855
856 #if defined(RCC_PLLSAI_SUPPORT)
857 case LL_RCC_USB_CLKSOURCE_PLLSAI: /* PLLSAI clock used as USB clock source */
858 if (LL_RCC_PLLSAI_IsReady())
859 {
860 usb_frequency = RCC_PLLSAI_GetFreqDomain_48M();
861 }
862 break;
863 #endif /* RCC_PLLSAI_SUPPORT */
864
865 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
866 default:
867 if (LL_RCC_PLL_IsReady())
868 {
869 usb_frequency = RCC_PLL_GetFreqDomain_48M();
870 }
871 break;
872 }
873 #else
874 /* PLL clock used as USB clock source */
875 if (LL_RCC_PLL_IsReady())
876 {
877 usb_frequency = RCC_PLL_GetFreqDomain_48M();
878 }
879 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
880
881 return usb_frequency;
882 }
883 #endif /* USB_OTG_FS || USB_OTG_HS */
884
885 #if defined(DFSDM1_Channel0)
886 /**
887 * @brief Return DFSDMx clock frequency
888 * @param DFSDMxSource This parameter can be one of the following values:
889 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
890 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
891 *
892 * (*) value not defined in all devices.
893 * @retval DFSDM clock frequency (in Hz)
894 */
895 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
896 {
897 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
898
899 /* Check parameter */
900 assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
901
902 if (DFSDMxSource == LL_RCC_DFSDM1_CLKSOURCE)
903 {
904 /* DFSDM1CLK clock frequency */
905 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
906 {
907 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
908 dfsdm_frequency = RCC_GetSystemClockFreq();
909 break;
910
911 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
912 default:
913 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
914 break;
915 }
916 }
917 #if defined(DFSDM2_Channel0)
918 else
919 {
920 /* DFSDM2CLK clock frequency */
921 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
922 {
923 case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK: /* DFSDM2 Clock is SYSCLK */
924 dfsdm_frequency = RCC_GetSystemClockFreq();
925 break;
926
927 case LL_RCC_DFSDM2_CLKSOURCE_PCLK2: /* DFSDM2 Clock is PCLK2 */
928 default:
929 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
930 break;
931 }
932 }
933 #endif /* DFSDM2_Channel0 */
934
935 return dfsdm_frequency;
936 }
937
938 /**
939 * @brief Return DFSDMx Audio clock frequency
940 * @param DFSDMxSource This parameter can be one of the following values:
941 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
942 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
943 *
944 * (*) value not defined in all devices.
945 * @retval DFSDM clock frequency (in Hz)
946 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
947 */
948 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
949 {
950 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
951
952 /* Check parameter */
953 assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
954
955 if (DFSDMxSource == LL_RCC_DFSDM1_AUDIO_CLKSOURCE)
956 {
957 /* DFSDM1CLK clock frequency */
958 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
959 {
960 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM1 clock */
961 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
962 break;
963
964 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM1 clock */
965 default:
966 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
967 break;
968 }
969 }
970 #if defined(DFSDM2_Channel0)
971 else
972 {
973 /* DFSDM2CLK clock frequency */
974 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
975 {
976 case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM2 clock */
977 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
978 break;
979
980 case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM2 clock */
981 default:
982 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
983 break;
984 }
985 }
986 #endif /* DFSDM2_Channel0 */
987
988 return dfsdm_frequency;
989 }
990 #endif /* DFSDM1_Channel0 */
991
992 #if defined(DSI)
993 /**
994 * @brief Return DSI clock frequency
995 * @param DSIxSource This parameter can be one of the following values:
996 * @arg @ref LL_RCC_DSI_CLKSOURCE
997 * @retval DSI clock frequency (in Hz)
998 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
999 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
1000 */
1001 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
1002 {
1003 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1004
1005 /* Check parameter */
1006 assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
1007
1008 /* DSICLK clock frequency */
1009 switch (LL_RCC_GetDSIClockSource(DSIxSource))
1010 {
1011 case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLL Osc. */
1012 if (LL_RCC_PLL_IsReady())
1013 {
1014 dsi_frequency = RCC_PLL_GetFreqDomain_DSI();
1015 }
1016 break;
1017
1018 case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */
1019 default:
1020 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1021 break;
1022 }
1023
1024 return dsi_frequency;
1025 }
1026 #endif /* DSI */
1027
1028 #if defined(LTDC)
1029 /**
1030 * @brief Return LTDC clock frequency
1031 * @param LTDCxSource This parameter can be one of the following values:
1032 * @arg @ref LL_RCC_LTDC_CLKSOURCE
1033 * @retval LTDC clock frequency (in Hz)
1034 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
1035 */
1036 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
1037 {
1038 uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1039
1040 /* Check parameter */
1041 assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
1042
1043 if (LL_RCC_PLLSAI_IsReady())
1044 {
1045 ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC();
1046 }
1047
1048 return ltdc_frequency;
1049 }
1050 #endif /* LTDC */
1051
1052 #if defined(SPDIFRX)
1053 /**
1054 * @brief Return SPDIFRX clock frequency
1055 * @param SPDIFRXxSource This parameter can be one of the following values:
1056 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
1057 * @retval SPDIFRX clock frequency (in Hz)
1058 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1059 */
1060 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
1061 {
1062 uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1063
1064 /* Check parameter */
1065 assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
1066
1067 /* SPDIFRX1CLK clock frequency */
1068 switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource))
1069 {
1070 case LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S: /* SPDIFRX Clock is PLLI2S Osc. */
1071 if (LL_RCC_PLLI2S_IsReady())
1072 {
1073 spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX();
1074 }
1075 break;
1076
1077 case LL_RCC_SPDIFRX1_CLKSOURCE_PLL: /* SPDIFRX Clock is PLL Osc. */
1078 default:
1079 if (LL_RCC_PLL_IsReady())
1080 {
1081 spdifrx_frequency = RCC_PLL_GetFreqDomain_SPDIFRX();
1082 }
1083 break;
1084 }
1085
1086 return spdifrx_frequency;
1087 }
1088 #endif /* SPDIFRX */
1089
1090 /**
1091 * @}
1092 */
1093
1094 /**
1095 * @}
1096 */
1097
1098 /** @addtogroup RCC_LL_Private_Functions
1099 * @{
1100 */
1101
1102 /**
1103 * @brief Return SYSTEM clock frequency
1104 * @retval SYSTEM clock frequency (in Hz)
1105 */
1106 uint32_t RCC_GetSystemClockFreq(void)
1107 {
1108 uint32_t frequency = 0U;
1109
1110 /* Get SYSCLK source -------------------------------------------------------*/
1111 switch (LL_RCC_GetSysClkSource())
1112 {
1113 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1114 frequency = HSI_VALUE;
1115 break;
1116
1117 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
1118 frequency = HSE_VALUE;
1119 break;
1120
1121 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
1122 frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLL);
1123 break;
1124
1125 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
1126 case LL_RCC_SYS_CLKSOURCE_STATUS_PLLR: /* PLLR used as system clock source */
1127 frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLLR);
1128 break;
1129 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
1130
1131 default:
1132 frequency = HSI_VALUE;
1133 break;
1134 }
1135
1136 return frequency;
1137 }
1138
1139 /**
1140 * @brief Return HCLK clock frequency
1141 * @param SYSCLK_Frequency SYSCLK clock frequency
1142 * @retval HCLK clock frequency (in Hz)
1143 */
1144 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1145 {
1146 /* HCLK clock frequency */
1147 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1148 }
1149
1150 /**
1151 * @brief Return PCLK1 clock frequency
1152 * @param HCLK_Frequency HCLK clock frequency
1153 * @retval PCLK1 clock frequency (in Hz)
1154 */
1155 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1156 {
1157 /* PCLK1 clock frequency */
1158 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1159 }
1160
1161 /**
1162 * @brief Return PCLK2 clock frequency
1163 * @param HCLK_Frequency HCLK clock frequency
1164 * @retval PCLK2 clock frequency (in Hz)
1165 */
1166 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1167 {
1168 /* PCLK2 clock frequency */
1169 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1170 }
1171
1172 /**
1173 * @brief Return PLL clock frequency used for system domain
1174 * @param SYSCLK_Source System clock source
1175 * @retval PLL clock frequency (in Hz)
1176 */
1177 uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source)
1178 {
1179 uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;
1180
1181 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1182 SYSCLK = PLL_VCO / (PLLP or PLLR)
1183 */
1184 pllsource = LL_RCC_PLL_GetMainSource();
1185
1186 switch (pllsource)
1187 {
1188 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1189 pllinputfreq = HSI_VALUE;
1190 break;
1191
1192 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1193 pllinputfreq = HSE_VALUE;
1194 break;
1195
1196 default:
1197 pllinputfreq = HSI_VALUE;
1198 break;
1199 }
1200
1201 if (SYSCLK_Source == LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
1202 {
1203 plloutputfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1204 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
1205 }
1206 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
1207 else
1208 {
1209 plloutputfreq = __LL_RCC_CALC_PLLRCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1210 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1211 }
1212 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
1213
1214 return plloutputfreq;
1215 }
1216
1217 /**
1218 * @brief Return PLL clock frequency used for 48 MHz domain
1219 * @retval PLL clock frequency (in Hz)
1220 */
1221 uint32_t RCC_PLL_GetFreqDomain_48M(void)
1222 {
1223 uint32_t pllinputfreq = 0U, pllsource = 0U;
1224
1225 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
1226 48M Domain clock = PLL_VCO / PLLQ
1227 */
1228 pllsource = LL_RCC_PLL_GetMainSource();
1229
1230 switch (pllsource)
1231 {
1232 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1233 pllinputfreq = HSI_VALUE;
1234 break;
1235
1236 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1237 pllinputfreq = HSE_VALUE;
1238 break;
1239
1240 default:
1241 pllinputfreq = HSI_VALUE;
1242 break;
1243 }
1244 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1245 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
1246 }
1247
1248 #if defined(DSI)
1249 /**
1250 * @brief Return PLL clock frequency used for DSI clock
1251 * @retval PLL clock frequency (in Hz)
1252 */
1253 uint32_t RCC_PLL_GetFreqDomain_DSI(void)
1254 {
1255 uint32_t pllinputfreq = 0U, pllsource = 0U;
1256
1257 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1258 DSICLK = PLL_VCO / PLLR
1259 */
1260 pllsource = LL_RCC_PLL_GetMainSource();
1261
1262 switch (pllsource)
1263 {
1264 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1265 pllinputfreq = HSE_VALUE;
1266 break;
1267
1268 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1269 default:
1270 pllinputfreq = HSI_VALUE;
1271 break;
1272 }
1273 return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1274 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1275 }
1276 #endif /* DSI */
1277
1278 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
1279 /**
1280 * @brief Return PLL clock frequency used for I2S clock
1281 * @retval PLL clock frequency (in Hz)
1282 */
1283 uint32_t RCC_PLL_GetFreqDomain_I2S(void)
1284 {
1285 uint32_t pllinputfreq = 0U, pllsource = 0U;
1286
1287 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1288 I2SCLK = PLL_VCO / PLLR
1289 */
1290 pllsource = LL_RCC_PLL_GetMainSource();
1291
1292 switch (pllsource)
1293 {
1294 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1295 pllinputfreq = HSE_VALUE;
1296 break;
1297
1298 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1299 default:
1300 pllinputfreq = HSI_VALUE;
1301 break;
1302 }
1303 return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1304 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1305 }
1306 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
1307
1308 #if defined(SPDIFRX)
1309 /**
1310 * @brief Return PLL clock frequency used for SPDIFRX clock
1311 * @retval PLL clock frequency (in Hz)
1312 */
1313 uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void)
1314 {
1315 uint32_t pllinputfreq = 0U, pllsource = 0U;
1316
1317 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1318 SPDIFRXCLK = PLL_VCO / PLLR
1319 */
1320 pllsource = LL_RCC_PLL_GetMainSource();
1321
1322 switch (pllsource)
1323 {
1324 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1325 pllinputfreq = HSE_VALUE;
1326 break;
1327
1328 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1329 default:
1330 pllinputfreq = HSI_VALUE;
1331 break;
1332 }
1333 return __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1334 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1335 }
1336 #endif /* SPDIFRX */
1337
1338 #if defined(RCC_PLLCFGR_PLLR)
1339 #if defined(SAI1)
1340 /**
1341 * @brief Return PLL clock frequency used for SAI clock
1342 * @retval PLL clock frequency (in Hz)
1343 */
1344 uint32_t RCC_PLL_GetFreqDomain_SAI(void)
1345 {
1346 uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;
1347
1348 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1349 SAICLK = (PLL_VCO / PLLR) / PLLDIVR
1350 or
1351 SAICLK = PLL_VCO / PLLR
1352 */
1353 pllsource = LL_RCC_PLL_GetMainSource();
1354
1355 switch (pllsource)
1356 {
1357 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1358 pllinputfreq = HSE_VALUE;
1359 break;
1360
1361 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1362 default:
1363 pllinputfreq = HSI_VALUE;
1364 break;
1365 }
1366
1367 #if defined(RCC_DCKCFGR_PLLDIVR)
1368 plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1369 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR(), LL_RCC_PLL_GetDIVR());
1370 #else
1371 plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1372 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1373 #endif /* RCC_DCKCFGR_PLLDIVR */
1374
1375 return plloutputfreq;
1376 }
1377 #endif /* SAI1 */
1378 #endif /* RCC_PLLCFGR_PLLR */
1379
1380 #if defined(RCC_PLLSAI_SUPPORT)
1381 /**
1382 * @brief Return PLLSAI clock frequency used for SAI domain
1383 * @retval PLLSAI clock frequency (in Hz)
1384 */
1385 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void)
1386 {
1387 uint32_t pllinputfreq = 0U, pllsource = 0U;
1388
1389 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
1390 SAI domain clock = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ
1391 */
1392 pllsource = LL_RCC_PLL_GetMainSource();
1393
1394 switch (pllsource)
1395 {
1396 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1397 pllinputfreq = HSI_VALUE;
1398 break;
1399
1400 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1401 pllinputfreq = HSE_VALUE;
1402 break;
1403
1404 default:
1405 pllinputfreq = HSI_VALUE;
1406 break;
1407 }
1408 return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
1409 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ());
1410 }
1411
1412 #if defined(RCC_PLLSAICFGR_PLLSAIP)
1413 /**
1414 * @brief Return PLLSAI clock frequency used for 48Mhz domain
1415 * @retval PLLSAI clock frequency (in Hz)
1416 */
1417 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void)
1418 {
1419 uint32_t pllinputfreq = 0U, pllsource = 0U;
1420
1421 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
1422 48M Domain clock = PLLSAI_VCO / PLLSAIP
1423 */
1424 pllsource = LL_RCC_PLL_GetMainSource();
1425
1426 switch (pllsource)
1427 {
1428 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1429 pllinputfreq = HSI_VALUE;
1430 break;
1431
1432 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1433 pllinputfreq = HSE_VALUE;
1434 break;
1435
1436 default:
1437 pllinputfreq = HSI_VALUE;
1438 break;
1439 }
1440 return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
1441 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP());
1442 }
1443 #endif /* RCC_PLLSAICFGR_PLLSAIP */
1444
1445 #if defined(LTDC)
1446 /**
1447 * @brief Return PLLSAI clock frequency used for LTDC domain
1448 * @retval PLLSAI clock frequency (in Hz)
1449 */
1450 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)
1451 {
1452 uint32_t pllinputfreq = 0U, pllsource = 0U;
1453
1454 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
1455 LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR
1456 */
1457 pllsource = LL_RCC_PLL_GetMainSource();
1458
1459 switch (pllsource)
1460 {
1461 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1462 pllinputfreq = HSI_VALUE;
1463 break;
1464
1465 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1466 pllinputfreq = HSE_VALUE;
1467 break;
1468
1469 default:
1470 pllinputfreq = HSI_VALUE;
1471 break;
1472 }
1473 return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
1474 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());
1475 }
1476 #endif /* LTDC */
1477 #endif /* RCC_PLLSAI_SUPPORT */
1478
1479 #if defined(RCC_PLLI2S_SUPPORT)
1480 #if defined(SAI1)
1481 /**
1482 * @brief Return PLLI2S clock frequency used for SAI domains
1483 * @retval PLLI2S clock frequency (in Hz)
1484 */
1485 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)
1486 {
1487 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
1488
1489 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1490 SAI domain clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ
1491 or
1492 SAI domain clock = (PLLI2S_VCO / PLLI2SR) / PLLI2SDIVR
1493 */
1494 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
1495
1496 switch (plli2ssource)
1497 {
1498 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1499 plli2sinputfreq = HSE_VALUE;
1500 break;
1501
1502 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
1503 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
1504 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
1505 break;
1506 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
1507
1508 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1509 default:
1510 plli2sinputfreq = HSI_VALUE;
1511 break;
1512 }
1513
1514 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
1515 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1516 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());
1517 #else
1518 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1519 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR(), LL_RCC_PLLI2S_GetDIVR());
1520 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
1521
1522 return plli2soutputfreq;
1523 }
1524 #endif /* SAI1 */
1525
1526 #if defined(SPDIFRX)
1527 /**
1528 * @brief Return PLLI2S clock frequency used for SPDIFRX domain
1529 * @retval PLLI2S clock frequency (in Hz)
1530 */
1531 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)
1532 {
1533 uint32_t pllinputfreq = 0U, pllsource = 0U;
1534
1535 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1536 SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP
1537 */
1538 pllsource = LL_RCC_PLLI2S_GetMainSource();
1539
1540 switch (pllsource)
1541 {
1542 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1543 pllinputfreq = HSE_VALUE;
1544 break;
1545
1546 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1547 default:
1548 pllinputfreq = HSI_VALUE;
1549 break;
1550 }
1551
1552 return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLLI2S_GetDivider(),
1553 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());
1554 }
1555 #endif /* SPDIFRX */
1556
1557 /**
1558 * @brief Return PLLI2S clock frequency used for I2S domain
1559 * @retval PLLI2S clock frequency (in Hz)
1560 */
1561 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
1562 {
1563 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
1564
1565 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1566 I2S Domain clock = PLLI2S_VCO / PLLI2SR
1567 */
1568 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
1569
1570 switch (plli2ssource)
1571 {
1572 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1573 plli2sinputfreq = HSE_VALUE;
1574 break;
1575
1576 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
1577 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
1578 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
1579 break;
1580 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
1581
1582 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1583 default:
1584 plli2sinputfreq = HSI_VALUE;
1585 break;
1586 }
1587
1588 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_I2S_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1589 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR());
1590
1591 return plli2soutputfreq;
1592 }
1593
1594 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
1595 /**
1596 * @brief Return PLLI2S clock frequency used for 48Mhz domain
1597 * @retval PLLI2S clock frequency (in Hz)
1598 */
1599 uint32_t RCC_PLLI2S_GetFreqDomain_48M(void)
1600 {
1601 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
1602
1603 /* PLL48M_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1604 48M Domain clock = PLLI2S_VCO / PLLI2SQ
1605 */
1606 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
1607
1608 switch (plli2ssource)
1609 {
1610 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1611 plli2sinputfreq = HSE_VALUE;
1612 break;
1613
1614 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
1615 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
1616 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
1617 break;
1618 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
1619
1620 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1621 default:
1622 plli2sinputfreq = HSI_VALUE;
1623 break;
1624 }
1625
1626 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_48M_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1627 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ());
1628
1629 return plli2soutputfreq;
1630 }
1631 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
1632 #endif /* RCC_PLLI2S_SUPPORT */
1633 /**
1634 * @}
1635 */
1636
1637 /**
1638 * @}
1639 */
1640
1641 #endif /* defined(RCC) */
1642
1643 /**
1644 * @}
1645 */
1646
1647 #endif /* USE_FULL_LL_DRIVER */
1648
1649 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/