lib/main/STM32F4/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_spi.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_ll_spi.c
   4   * @author  MCD Application Team
   5   * @version V1.7.1
   6   * @date    14-April-2017
   7   * @brief   SPI LL module driver.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37 #if defined(USE_FULL_LL_DRIVER)
  38
  39 /* Includes ------------------------------------------------------------------*/
  40 #include "stm32f4xx_ll_spi.h"
  41 #include "stm32f4xx_ll_bus.h"
  42 #include "stm32f4xx_ll_rcc.h"
  43
  44 #ifdef  USE_FULL_ASSERT
  45 #include "stm32_assert.h"
  46 #else
  47 #define assert_param(expr) ((void)0U)
  48 #endif
  49
  50 /** @addtogroup STM32F4xx_LL_Driver
  51   * @{
  52   */
  53
  54 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6)
  55
  56 /** @addtogroup SPI_LL
  57   * @{
  58   */
  59
  60 /* Private types -------------------------------------------------------------*/
  61 /* Private variables ---------------------------------------------------------*/
  62
  63 /* Private constants ---------------------------------------------------------*/
  64 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
  65   * @{
  66   */
  67 /* SPI registers Masks */
  68 #define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
  69                                             SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
  70                                             SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_DFF    | \
  71                                             SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
  72                                             SPI_CR1_BIDIMODE)
  73 /**
  74   * @}
  75   */
  76
  77 /* Private macros ------------------------------------------------------------*/
  78 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
  79   * @{
  80   */
  81 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)    \
  82                                               || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
  83                                               || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
  84                                               || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
  85
  86 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
  87                                 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
  88
  89 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
  90                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
  91
  92 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
  93                                     || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
  94
  95 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
  96                                  || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
  97
  98 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
  99                                || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
 100                                || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
 101
 102 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)   \
 103                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
 104                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
 105                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
 106                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
 107                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
 108                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
 109                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
 110
 111 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
 112                                     || ((__VALUE__) == LL_SPI_MSB_FIRST))
 113
 114 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
 115                                           || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
 116
 117 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
 118
 119 /**
 120   * @}
 121   */
 122
 123 /* Private function prototypes -----------------------------------------------*/
 124
 125 /* Exported functions --------------------------------------------------------*/
 126 /** @addtogroup SPI_LL_Exported_Functions
 127   * @{
 128   */
 129
 130 /** @addtogroup SPI_LL_EF_Init
 131   * @{
 132   */
 133
 134 /**
 135   * @brief  De-initialize the SPI registers to their default reset values.
 136   * @param  SPIx SPI Instance
 137   * @retval An ErrorStatus enumeration value:
 138   *          - SUCCESS: SPI registers are de-initialized
 139   *          - ERROR: SPI registers are not de-initialized
 140   */
 141 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
 142 {
 143   ErrorStatus status = ERROR;
 144
 145   /* Check the parameters */
 146   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
 147
 148 #if defined(SPI1)
 149   if (SPIx == SPI1)
 150   {
 151     /* Force reset of SPI clock */
 152     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
 153
 154     /* Release reset of SPI clock */
 155     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
 156
 157     status = SUCCESS;
 158   }
 159 #endif /* SPI1 */
 160 #if defined(SPI2)
 161   if (SPIx == SPI2)
 162   {
 163     /* Force reset of SPI clock */
 164     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
 165
 166     /* Release reset of SPI clock */
 167     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
 168
 169     status = SUCCESS;
 170   }
 171 #endif /* SPI2 */
 172 #if defined(SPI3)
 173   if (SPIx == SPI3)
 174   {
 175     /* Force reset of SPI clock */
 176     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
 177
 178     /* Release reset of SPI clock */
 179     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
 180
 181     status = SUCCESS;
 182   }
 183 #endif /* SPI3 */
 184 #if defined(SPI4)
 185   if (SPIx == SPI4)
 186   {
 187     /* Force reset of SPI clock */
 188     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
 189
 190     /* Release reset of SPI clock */
 191     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
 192
 193     status = SUCCESS;
 194   }
 195 #endif /* SPI4 */
 196 #if defined(SPI5)
 197   if (SPIx == SPI5)
 198   {
 199     /* Force reset of SPI clock */
 200     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
 201
 202     /* Release reset of SPI clock */
 203     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
 204
 205     status = SUCCESS;
 206   }
 207 #endif /* SPI5 */
 208 #if defined(SPI6)
 209   if (SPIx == SPI6)
 210   {
 211     /* Force reset of SPI clock */
 212     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6);
 213
 214     /* Release reset of SPI clock */
 215     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6);
 216
 217     status = SUCCESS;
 218   }
 219 #endif /* SPI6 */
 220
 221   return status;
 222 }
 223
 224 /**
 225   * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
 226   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
 227   *         SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
 228   * @param  SPIx SPI Instance
 229   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
 230   * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
 231   */
 232 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
 233 {
 234   ErrorStatus status = ERROR;
 235
 236   /* Check the SPI Instance SPIx*/
 237   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
 238
 239   /* Check the SPI parameters from SPI_InitStruct*/
 240   assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
 241   assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
 242   assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
 243   assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
 244   assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
 245   assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
 246   assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
 247   assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
 248   assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
 249
 250   if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
 251   {
 252     /*---------------------------- SPIx CR1 Configuration ------------------------
 253      * Configure SPIx CR1 with parameters:
 254      * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
 255      * - Master/Slave Mode:  SPI_CR1_MSTR bit
 256      * - DataWidth:          SPI_CR1_DFF bit
 257      * - ClockPolarity:      SPI_CR1_CPOL bit
 258      * - ClockPhase:         SPI_CR1_CPHA bit
 259      * - NSS management:     SPI_CR1_SSM bit
 260      * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
 261      * - BitOrder:           SPI_CR1_LSBFIRST bit
 262      * - CRCCalculation:     SPI_CR1_CRCEN bit
 263      */
 264     MODIFY_REG(SPIx->CR1,
 265                SPI_CR1_CLEAR_MASK,
 266                SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
 267                SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
 268                SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
 269                SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
 270
 271     /*---------------------------- SPIx CR2 Configuration ------------------------
 272      * Configure SPIx CR2 with parameters:
 273      * - NSS management:     SSOE bit
 274      */
 275     MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
 276
 277     /*---------------------------- SPIx CRCPR Configuration ----------------------
 278      * Configure SPIx CRCPR with parameters:
 279      * - CRCPoly:            CRCPOLY[15:0] bits
 280      */
 281     if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
 282     {
 283       assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
 284       LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
 285     }
 286     status = SUCCESS;
 287   }
 288
 289   /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
 290   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
 291   return status;
 292 }
 293
 294 /**
 295   * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
 296   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
 297   * whose fields will be set to default values.
 298   * @retval None
 299   */
 300 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
 301 {
 302   /* Set SPI_InitStruct fields to default values */
 303   SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
 304   SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
 305   SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
 306   SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
 307   SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
 308   SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
 309   SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
 310   SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
 311   SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
 312   SPI_InitStruct->CRCPoly           = 7U;
 313 }
 314
 315 /**
 316   * @}
 317   */
 318
 319 /**
 320   * @}
 321   */
 322
 323 /**
 324   * @}
 325   */
 326
 327 /** @addtogroup I2S_LL
 328   * @{
 329   */
 330
 331 /* Private types -------------------------------------------------------------*/
 332 /* Private variables ---------------------------------------------------------*/
 333 /* Private constants ---------------------------------------------------------*/
 334 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
 335   * @{
 336   */
 337 /* I2S registers Masks */
 338 #define I2S_I2SCFGR_CLEAR_MASK             (SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
 339                                             SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
 340                                             SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )
 341
 342 #define I2S_I2SPR_CLEAR_MASK               0x0002U
 343 /**
 344   * @}
 345   */
 346 /* Private macros ------------------------------------------------------------*/
 347 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
 348   * @{
 349   */
 350
 351 #define IS_LL_I2S_DATAFORMAT(__VALUE__)  (((__VALUE__) == LL_I2S_DATAFORMAT_16B)          \
 352                                        || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
 353                                        || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
 354                                        || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
 355
 356 #define IS_LL_I2S_CPOL(__VALUE__)        (((__VALUE__) == LL_I2S_POLARITY_LOW)  \
 357                                        || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
 358
 359 #define IS_LL_I2S_STANDARD(__VALUE__)    (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)   \
 360                                        || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
 361                                        || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
 362                                        || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
 363                                        || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
 364
 365 #define IS_LL_I2S_MODE(__VALUE__)        (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)  \
 366                                        || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
 367                                        || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
 368                                        || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
 369
 370 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
 371                                        || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
 372
 373 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)    \
 374                                        && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
 375                                        || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
 376
 377 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__)  ((__VALUE__) >= 0x2U)
 378
 379 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
 380                                            || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
 381 /**
 382   * @}
 383   */
 384
 385 /* Private function prototypes -----------------------------------------------*/
 386
 387 /* Exported functions --------------------------------------------------------*/
 388 /** @addtogroup I2S_LL_Exported_Functions
 389   * @{
 390   */
 391
 392 /** @addtogroup I2S_LL_EF_Init
 393   * @{
 394   */
 395
 396 /**
 397   * @brief  De-initialize the SPI/I2S registers to their default reset values.
 398   * @param  SPIx SPI Instance
 399   * @retval An ErrorStatus enumeration value:
 400   *          - SUCCESS: SPI registers are de-initialized
 401   *          - ERROR: SPI registers are not de-initialized
 402   */
 403 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
 404 {
 405   return LL_SPI_DeInit(SPIx);
 406 }
 407
 408 /**
 409   * @brief  Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
 410   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
 411   *         SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
 412   * @param  SPIx SPI Instance
 413   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
 414   * @retval An ErrorStatus enumeration value:
 415   *          - SUCCESS: SPI registers are Initialized
 416   *          - ERROR: SPI registers are not Initialized
 417   */
 418 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
 419 {
 420   uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
 421   uint32_t tmp = 0U;
 422   uint32_t sourceclock = 0U;
 423   ErrorStatus status = ERROR;
 424
 425   /* Check the I2S parameters */
 426   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
 427   assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
 428   assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
 429   assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
 430   assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
 431   assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
 432   assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
 433
 434   if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
 435   {
 436     /*---------------------------- SPIx I2SCFGR Configuration --------------------
 437      * Configure SPIx I2SCFGR with parameters:
 438      * - Mode:          SPI_I2SCFGR_I2SCFG[1:0] bit
 439      * - Standard:      SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
 440      * - DataFormat:    SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
 441      * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
 442      */
 443
 444     /* Write to SPIx I2SCFGR */
 445     MODIFY_REG(SPIx->I2SCFGR,
 446                I2S_I2SCFGR_CLEAR_MASK,
 447                I2S_InitStruct->Mode | I2S_InitStruct->Standard |
 448                I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
 449                SPI_I2SCFGR_I2SMOD);
 450
 451     /*---------------------------- SPIx I2SPR Configuration ----------------------
 452      * Configure SPIx I2SPR with parameters:
 453      * - MCLKOutput:    SPI_I2SPR_MCKOE bit
 454      * - AudioFreq:     SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
 455      */
 456
 457     /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
 458      * else, default values are used:  i2sodd = 0U, i2sdiv = 2U.
 459      */
 460     if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
 461     {
 462       /* Check the frame length (For the Prescaler computing)
 463        * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
 464        */
 465       if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
 466       {
 467         /* Packet length is 32 bits */
 468         packetlength = 2U;
 469       }
 470
 471       /* If an external I2S clock has to be used, the specific define should be set
 472       in the project configuration or in the stm32f4xx_ll_rcc.h file */
 473       /* Get the I2S source clock value */
 474       sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
 475
 476       /* Compute the Real divider depending on the MCLK output state with a floating point */
 477       if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
 478       {
 479         /* MCLK output is enabled */
 480         tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
 481       }
 482       else
 483       {
 484         /* MCLK output is disabled */
 485         tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
 486       }
 487
 488       /* Remove the floating point */
 489       tmp = tmp / 10U;
 490
 491       /* Check the parity of the divider */
 492       i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
 493
 494       /* Compute the i2sdiv prescaler */
 495       i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
 496
 497       /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
 498       i2sodd = (uint16_t)(i2sodd << 8U);
 499     }
 500
 501     /* Test if the divider is 1 or 0 or greater than 0xFF */
 502     if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
 503     {
 504       /* Set the default values */
 505       i2sdiv = 2U;
 506       i2sodd = 0U;
 507     }
 508
 509     /* Write to SPIx I2SPR register the computed value */
 510     WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
 511
 512     status = SUCCESS;
 513   }
 514   return status;
 515 }
 516
 517 /**
 518   * @brief  Set each @ref LL_I2S_InitTypeDef field to default value.
 519   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
 520   *         whose fields will be set to default values.
 521   * @retval None
 522   */
 523 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
 524 {
 525   /*--------------- Reset I2S init structure parameters values -----------------*/
 526   I2S_InitStruct->Mode              = LL_I2S_MODE_SLAVE_TX;
 527   I2S_InitStruct->Standard          = LL_I2S_STANDARD_PHILIPS;
 528   I2S_InitStruct->DataFormat        = LL_I2S_DATAFORMAT_16B;
 529   I2S_InitStruct->MCLKOutput        = LL_I2S_MCLK_OUTPUT_DISABLE;
 530   I2S_InitStruct->AudioFreq         = LL_I2S_AUDIOFREQ_DEFAULT;
 531   I2S_InitStruct->ClockPolarity     = LL_I2S_POLARITY_LOW;
 532 }
 533
 534 /**
 535   * @brief  Set linear and parity prescaler.
 536   * @note   To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
 537   *         Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
 538   * @param  SPIx SPI Instance
 539   * @param  PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
 540   * @param  PrescalerParity This parameter can be one of the following values:
 541   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
 542   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
 543   * @retval None
 544   */
 545 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
 546 {
 547   /* Check the I2S parameters */
 548   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
 549   assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
 550   assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
 551
 552   /* Write to SPIx I2SPR */
 553   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
 554 }
 555
 556 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
 557 /**
 558   * @brief  Configures the full duplex mode for the I2Sx peripheral using its extension
 559   *         I2Sxext according to the specified parameters in the I2S_InitStruct.
 560   * @note   The structure pointed by I2S_InitStruct parameter should be the same
 561   *         used for the master I2S peripheral. In this case, if the master is
 562   *         configured as transmitter, the slave will be receiver and vice versa.
 563   *         Or you can force a different mode by modifying the field I2S_Mode to the
 564   *         value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration.
 565   * @param  I2Sxext SPI Instance
 566   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
 567   * @retval An ErrorStatus enumeration value:
 568   *          - SUCCESS: I2Sxext registers are Initialized
 569   *          - ERROR: I2Sxext registers are not Initialized
 570   */
 571 ErrorStatus  LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct)
 572 {
 573   uint16_t mode = 0U;
 574   ErrorStatus status = ERROR;
 575
 576   /* Check the I2S parameters */
 577   assert_param(IS_I2S_EXT_ALL_INSTANCE(I2Sxext));
 578   assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
 579   assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
 580   assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
 581   assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
 582
 583   if (LL_I2S_IsEnabled(I2Sxext) == 0x00000000U)
 584   {
 585     /*---------------------------- SPIx I2SCFGR Configuration --------------------
 586      * Configure SPIx I2SCFGR with parameters:
 587      * - Mode:          SPI_I2SCFGR_I2SCFG[1:0] bit
 588      * - Standard:      SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
 589      * - DataFormat:    SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
 590      * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
 591      */
 592
 593     /* Reset I2SPR registers */
 594     WRITE_REG(I2Sxext->I2SPR, I2S_I2SPR_CLEAR_MASK);
 595
 596     /* Get the mode to be configured for the extended I2S */
 597     if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_TX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_TX))
 598     {
 599       mode = LL_I2S_MODE_SLAVE_RX;
 600     }
 601     else
 602     {
 603       if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_RX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_RX))
 604       {
 605         mode = LL_I2S_MODE_SLAVE_TX;
 606       }
 607     }
 608
 609     /* Write to SPIx I2SCFGR */
 610     MODIFY_REG(I2Sxext->I2SCFGR,
 611                I2S_I2SCFGR_CLEAR_MASK,
 612                I2S_InitStruct->Standard |
 613                I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
 614                SPI_I2SCFGR_I2SMOD | mode);
 615
 616     status = SUCCESS;
 617   }
 618   return status;
 619 }
 620 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
 621
 622 /**
 623   * @}
 624   */
 625
 626 /**
 627   * @}
 628   */
 629
 630 /**
 631   * @}
 632   */
 633
 634 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */
 635
 636 /**
 637   * @}
 638   */
 639
 640 #endif /* USE_FULL_LL_DRIVER */
 641
 642 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/