lib/main/STM32F4/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_tim.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_ll_tim.c
   4   * @author  MCD Application Team
   5   * @version V1.7.1
   6   * @date    14-April-2017
   7   * @brief   TIM LL module driver.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37 #if defined(USE_FULL_LL_DRIVER)
  38
  39 /* Includes ------------------------------------------------------------------*/
  40 #include "stm32f4xx_ll_tim.h"
  41 #include "stm32f4xx_ll_bus.h"
  42
  43 #ifdef  USE_FULL_ASSERT
  44 #include "stm32_assert.h"
  45 #else
  46 #define assert_param(expr) ((void)0U)
  47 #endif
  48
  49 /** @addtogroup STM32F4xx_LL_Driver
  50   * @{
  51   */
  52
  53 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14)
  54
  55 /** @addtogroup TIM_LL
  56   * @{
  57   */
  58
  59 /* Private types -------------------------------------------------------------*/
  60 /* Private variables ---------------------------------------------------------*/
  61 /* Private constants ---------------------------------------------------------*/
  62 /* Private macros ------------------------------------------------------------*/
  63 /** @addtogroup TIM_LL_Private_Macros
  64   * @{
  65   */
  66 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
  67                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
  68                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
  69                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
  70                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
  71
  72 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
  73                                          || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
  74                                          || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
  75
  76 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
  77                                   || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
  78                                   || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
  79                                   || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
  80                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
  81                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
  82                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
  83                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
  84
  85 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
  86                                    || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
  87
  88 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
  89                                       || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
  90
  91 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
  92                                        || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
  93
  94 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
  95                                        || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
  96                                        || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
  97
  98 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
  99                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
 100                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
 101                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
 102
 103 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
 104                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
 105                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
 106                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
 107                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
 108                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
 109                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
 110                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
 111                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
 112                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
 113                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
 114                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
 115                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
 116                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
 117                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
 118                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
 119
 120 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
 121                                        || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
 122                                        || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
 123
 124 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
 125                                        || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
 126                                        || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
 127
 128 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
 129                                                || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
 130
 131 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
 132                                      || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
 133
 134 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
 135                                       || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
 136
 137 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
 138                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
 139                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
 140                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
 141
 142 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
 143                                        || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
 144
 145 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
 146                                           || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
 147
 148 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
 149                                                   || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
 150 /**
 151   * @}
 152   */
 153
 154
 155 /* Private function prototypes -----------------------------------------------*/
 156 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
 157   * @{
 158   */
 159 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 160 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 161 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 162 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 163 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 164 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 165 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 166 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 167 /**
 168   * @}
 169   */
 170
 171 /* Exported functions --------------------------------------------------------*/
 172 /** @addtogroup TIM_LL_Exported_Functions
 173   * @{
 174   */
 175
 176 /** @addtogroup TIM_LL_EF_Init
 177   * @{
 178   */
 179
 180 /**
 181   * @brief  Set TIMx registers to their reset values.
 182   * @param  TIMx Timer instance
 183   * @retval An ErrorStatus enumeration value:
 184   *          - SUCCESS: TIMx registers are de-initialized
 185   *          - ERROR: invalid TIMx instance
 186   */
 187 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
 188 {
 189   ErrorStatus result = SUCCESS;
 190
 191   /* Check the parameters */
 192   assert_param(IS_TIM_INSTANCE(TIMx));
 193
 194   if (TIMx == TIM1)
 195   {
 196     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
 197     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
 198   }
 199 #if defined(TIM2)
 200   else if (TIMx == TIM2)
 201   {
 202     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
 203     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
 204   }
 205 #endif
 206 #if defined(TIM3)
 207   else if (TIMx == TIM3)
 208   {
 209     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
 210     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
 211   }
 212 #endif
 213 #if defined(TIM4)
 214   else if (TIMx == TIM4)
 215   {
 216     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
 217     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
 218   }
 219 #endif
 220 #if defined(TIM5)
 221   else if (TIMx == TIM5)
 222   {
 223     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
 224     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
 225   }
 226 #endif
 227 #if defined(TIM6)
 228   else if (TIMx == TIM6)
 229   {
 230     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
 231     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
 232   }
 233 #endif
 234 #if defined (TIM7)
 235   else if (TIMx == TIM7)
 236   {
 237     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
 238     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
 239   }
 240 #endif
 241 #if defined(TIM8)
 242   else if (TIMx == TIM8)
 243   {
 244     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
 245     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
 246   }
 247 #endif
 248 #if defined(TIM9)
 249   else if (TIMx == TIM9)
 250   {
 251     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
 252     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
 253   }
 254 #endif
 255 #if defined(TIM10)
 256   else if (TIMx == TIM10)
 257   {
 258     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
 259     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
 260   }
 261 #endif
 262 #if defined(TIM11)
 263   else if (TIMx == TIM11)
 264   {
 265     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
 266     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
 267   }
 268 #endif
 269 #if defined(TIM12)
 270   else if (TIMx == TIM12)
 271   {
 272     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
 273     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
 274   }
 275 #endif
 276 #if defined(TIM13)
 277   else if (TIMx == TIM13)
 278   {
 279     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
 280     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
 281   }
 282 #endif
 283 #if defined(TIM14)
 284   else if (TIMx == TIM14)
 285   {
 286     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
 287     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
 288   }
 289 #endif
 290   else
 291   {
 292     result = ERROR;
 293   }
 294
 295   return result;
 296 }
 297
 298 /**
 299   * @brief  Set the fields of the time base unit configuration data structure
 300   *         to their default values.
 301   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
 302   * @retval None
 303   */
 304 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
 305 {
 306   /* Set the default configuration */
 307   TIM_InitStruct->Prescaler         = (uint16_t)0x0000U;
 308   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
 309   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
 310   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
 311   TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
 312 }
 313
 314 /**
 315   * @brief  Configure the TIMx time base unit.
 316   * @param  TIMx Timer Instance
 317   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
 318   * @retval An ErrorStatus enumeration value:
 319   *          - SUCCESS: TIMx registers are de-initialized
 320   *          - ERROR: not applicable
 321   */
 322 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
 323 {
 324   uint32_t tmpcr1 = 0U;
 325
 326   /* Check the parameters */
 327   assert_param(IS_TIM_INSTANCE(TIMx));
 328   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
 329   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
 330
 331   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
 332
 333   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 334   {
 335     /* Select the Counter Mode */
 336     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
 337   }
 338
 339   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 340   {
 341     /* Set the clock division */
 342     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
 343   }
 344
 345   /* Write to TIMx CR1 */
 346   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
 347
 348   /* Set the Autoreload value */
 349   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
 350
 351   /* Set the Prescaler value */
 352   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
 353
 354   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 355   {
 356     /* Set the Repetition Counter value */
 357     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
 358   }
 359
 360   /* Generate an update event to reload the Prescaler
 361      and the repetition counter value (if applicable) immediately */
 362   LL_TIM_GenerateEvent_UPDATE(TIMx);
 363
 364   return SUCCESS;
 365 }
 366
 367 /**
 368   * @brief  Set the fields of the TIMx output channel configuration data
 369   *         structure to their default values.
 370   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
 371   * @retval None
 372   */
 373 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
 374 {
 375   /* Set the default configuration */
 376   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
 377   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
 378   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
 379   TIM_OC_InitStruct->CompareValue = 0x00000000U;
 380   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
 381   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
 382   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
 383   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
 384 }
 385
 386 /**
 387   * @brief  Configure the TIMx output channel.
 388   * @param  TIMx Timer Instance
 389   * @param  Channel This parameter can be one of the following values:
 390   *         @arg @ref LL_TIM_CHANNEL_CH1
 391   *         @arg @ref LL_TIM_CHANNEL_CH2
 392   *         @arg @ref LL_TIM_CHANNEL_CH3
 393   *         @arg @ref LL_TIM_CHANNEL_CH4
 394   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
 395   * @retval An ErrorStatus enumeration value:
 396   *          - SUCCESS: TIMx output channel is initialized
 397   *          - ERROR: TIMx output channel is not initialized
 398   */
 399 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
 400 {
 401   ErrorStatus result = ERROR;
 402
 403   switch (Channel)
 404   {
 405     case LL_TIM_CHANNEL_CH1:
 406       result = OC1Config(TIMx, TIM_OC_InitStruct);
 407       break;
 408     case LL_TIM_CHANNEL_CH2:
 409       result = OC2Config(TIMx, TIM_OC_InitStruct);
 410       break;
 411     case LL_TIM_CHANNEL_CH3:
 412       result = OC3Config(TIMx, TIM_OC_InitStruct);
 413       break;
 414     case LL_TIM_CHANNEL_CH4:
 415       result = OC4Config(TIMx, TIM_OC_InitStruct);
 416       break;
 417     default:
 418       break;
 419   }
 420
 421   return result;
 422 }
 423
 424 /**
 425   * @brief  Set the fields of the TIMx input channel configuration data
 426   *         structure to their default values.
 427   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
 428   * @retval None
 429   */
 430 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
 431 {
 432   /* Set the default configuration */
 433   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
 434   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 435   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
 436   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
 437 }
 438
 439 /**
 440   * @brief  Configure the TIMx input channel.
 441   * @param  TIMx Timer Instance
 442   * @param  Channel This parameter can be one of the following values:
 443   *         @arg @ref LL_TIM_CHANNEL_CH1
 444   *         @arg @ref LL_TIM_CHANNEL_CH2
 445   *         @arg @ref LL_TIM_CHANNEL_CH3
 446   *         @arg @ref LL_TIM_CHANNEL_CH4
 447   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
 448   * @retval An ErrorStatus enumeration value:
 449   *          - SUCCESS: TIMx output channel is initialized
 450   *          - ERROR: TIMx output channel is not initialized
 451   */
 452 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
 453 {
 454   ErrorStatus result = ERROR;
 455
 456   switch (Channel)
 457   {
 458     case LL_TIM_CHANNEL_CH1:
 459       result = IC1Config(TIMx, TIM_IC_InitStruct);
 460       break;
 461     case LL_TIM_CHANNEL_CH2:
 462       result = IC2Config(TIMx, TIM_IC_InitStruct);
 463       break;
 464     case LL_TIM_CHANNEL_CH3:
 465       result = IC3Config(TIMx, TIM_IC_InitStruct);
 466       break;
 467     case LL_TIM_CHANNEL_CH4:
 468       result = IC4Config(TIMx, TIM_IC_InitStruct);
 469       break;
 470     default:
 471       break;
 472   }
 473
 474   return result;
 475 }
 476
 477 /**
 478   * @brief  Fills each TIM_EncoderInitStruct field with its default value
 479   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
 480   * @retval None
 481   */
 482 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
 483 {
 484   /* Set the default configuration */
 485   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
 486   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
 487   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 488   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
 489   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
 490   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
 491   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 492   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
 493   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
 494 }
 495
 496 /**
 497   * @brief  Configure the encoder interface of the timer instance.
 498   * @param  TIMx Timer Instance
 499   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
 500   * @retval An ErrorStatus enumeration value:
 501   *          - SUCCESS: TIMx registers are de-initialized
 502   *          - ERROR: not applicable
 503   */
 504 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
 505 {
 506   uint32_t tmpccmr1 = 0U;
 507   uint32_t tmpccer = 0U;
 508
 509   /* Check the parameters */
 510   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
 511   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
 512   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
 513   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
 514   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
 515   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
 516   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
 517   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
 518   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
 519   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
 520
 521   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
 522   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
 523
 524   /* Get the TIMx CCMR1 register value */
 525   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 526
 527   /* Get the TIMx CCER register value */
 528   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 529
 530   /* Configure TI1 */
 531   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
 532   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
 533   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
 534   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
 535
 536   /* Configure TI2 */
 537   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
 538   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
 539   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
 540   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
 541
 542   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
 543   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
 544   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
 545   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
 546   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
 547
 548   /* Set encoder mode */
 549   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
 550
 551   /* Write to TIMx CCMR1 */
 552   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 553
 554   /* Write to TIMx CCER */
 555   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 556
 557   return SUCCESS;
 558 }
 559
 560 /**
 561   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
 562   *         structure to their default values.
 563   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
 564   * @retval None
 565   */
 566 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
 567 {
 568   /* Set the default configuration */
 569   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
 570   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
 571   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
 572   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
 573 }
 574
 575 /**
 576   * @brief  Configure the Hall sensor interface of the timer instance.
 577   * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
 578   *       to the TI1 input channel
 579   * @note TIMx slave mode controller is configured in reset mode.
 580           Selected internal trigger is TI1F_ED.
 581   * @note Channel 1 is configured as input, IC1 is mapped on TRC.
 582   * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
 583   *       between 2 changes on the inputs. It gives information about motor speed.
 584   * @note Channel 2 is configured in output PWM 2 mode.
 585   * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
 586   * @note OC2REF is selected as trigger output on TRGO.
 587   * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
 588   *       when TIMx operates in Hall sensor interface mode.
 589   * @param  TIMx Timer Instance
 590   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
 591   * @retval An ErrorStatus enumeration value:
 592   *          - SUCCESS: TIMx registers are de-initialized
 593   *          - ERROR: not applicable
 594   */
 595 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
 596 {
 597   uint32_t tmpcr2 = 0U;
 598   uint32_t tmpccmr1 = 0U;
 599   uint32_t tmpccer = 0U;
 600   uint32_t tmpsmcr = 0U;
 601
 602   /* Check the parameters */
 603   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
 604   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
 605   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
 606   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
 607
 608   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
 609   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
 610
 611   /* Get the TIMx CR2 register value */
 612   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 613
 614   /* Get the TIMx CCMR1 register value */
 615   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 616
 617   /* Get the TIMx CCER register value */
 618   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 619
 620   /* Get the TIMx SMCR register value */
 621   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
 622
 623   /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
 624   tmpcr2 |= TIM_CR2_TI1S;
 625
 626   /* OC2REF signal is used as trigger output (TRGO) */
 627   tmpcr2 |= LL_TIM_TRGO_OC2REF;
 628
 629   /* Configure the slave mode controller */
 630   tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
 631   tmpsmcr |= LL_TIM_TS_TI1F_ED;
 632   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
 633
 634   /* Configure input channel 1 */
 635   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
 636   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
 637   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
 638   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
 639
 640   /* Configure input channel 2 */
 641   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
 642   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
 643
 644   /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
 645   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
 646   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
 647   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
 648
 649   /* Write to TIMx CR2 */
 650   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 651
 652   /* Write to TIMx SMCR */
 653   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
 654
 655   /* Write to TIMx CCMR1 */
 656   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 657
 658   /* Write to TIMx CCER */
 659   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 660
 661   /* Write to TIMx CCR2 */
 662   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
 663
 664   return SUCCESS;
 665 }
 666
 667 /**
 668   * @brief  Set the fields of the Break and Dead Time configuration data structure
 669   *         to their default values.
 670   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
 671   * @retval None
 672   */
 673 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
 674 {
 675   /* Set the default configuration */
 676   TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
 677   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
 678   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
 679   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00U;
 680   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
 681   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
 682   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
 683 }
 684
 685 /**
 686   * @brief  Configure the Break and Dead Time feature of the timer instance.
 687   * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
 688   *  depending on the LOCK configuration, it can be necessary to configure all of
 689   *  them during the first write access to the TIMx_BDTR register.
 690   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
 691   *       a timer instance provides a break input.
 692   * @param  TIMx Timer Instance
 693   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
 694   * @retval An ErrorStatus enumeration value:
 695   *          - SUCCESS: Break and Dead Time is initialized
 696   *          - ERROR: not applicable
 697   */
 698 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
 699 {
 700   uint32_t tmpbdtr = 0;
 701
 702   /* Check the parameters */
 703   assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
 704   assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
 705   assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
 706   assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
 707   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
 708   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
 709   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
 710
 711   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
 712   the OSSI State, the dead time value and the Automatic Output Enable Bit */
 713
 714   /* Set the BDTR bits */
 715   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
 716   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
 717   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
 718   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
 719   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
 720   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
 721   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
 722   MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
 723
 724   /* Set TIMx_BDTR */
 725   LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
 726
 727   return SUCCESS;
 728 }
 729 /**
 730   * @}
 731   */
 732
 733 /**
 734   * @}
 735   */
 736
 737 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
 738  *  @brief   Private functions
 739   * @{
 740   */
 741 /**
 742   * @brief  Configure the TIMx output channel 1.
 743   * @param  TIMx Timer Instance
 744   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
 745   * @retval An ErrorStatus enumeration value:
 746   *          - SUCCESS: TIMx registers are de-initialized
 747   *          - ERROR: not applicable
 748   */
 749 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 750 {
 751   uint32_t tmpccmr1 = 0U;
 752   uint32_t tmpccer = 0U;
 753   uint32_t tmpcr2 = 0U;
 754
 755   /* Check the parameters */
 756   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
 757   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 758   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 759   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 760   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 761   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 762
 763   /* Disable the Channel 1: Reset the CC1E Bit */
 764   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
 765
 766   /* Get the TIMx CCER register value */
 767   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 768
 769   /* Get the TIMx CR2 register value */
 770   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 771
 772   /* Get the TIMx CCMR1 register value */
 773   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 774
 775   /* Reset Capture/Compare selection Bits */
 776   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
 777
 778   /* Set the Output Compare Mode */
 779   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
 780
 781   /* Set the Output Compare Polarity */
 782   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
 783
 784   /* Set the Output State */
 785   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
 786
 787   if (IS_TIM_BREAK_INSTANCE(TIMx))
 788   {
 789     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 790     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
 791
 792     /* Set the complementary output Polarity */
 793     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
 794
 795     /* Set the complementary output State */
 796     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
 797
 798     /* Set the Output Idle state */
 799     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
 800
 801     /* Set the complementary output Idle state */
 802     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
 803   }
 804
 805   /* Write to TIMx CR2 */
 806   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 807
 808   /* Write to TIMx CCMR1 */
 809   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 810
 811   /* Set the Capture Compare Register value */
 812   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
 813
 814   /* Write to TIMx CCER */
 815   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 816
 817   return SUCCESS;
 818 }
 819
 820 /**
 821   * @brief  Configure the TIMx output channel 2.
 822   * @param  TIMx Timer Instance
 823   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
 824   * @retval An ErrorStatus enumeration value:
 825   *          - SUCCESS: TIMx registers are de-initialized
 826   *          - ERROR: not applicable
 827   */
 828 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 829 {
 830   uint32_t tmpccmr1 = 0U;
 831   uint32_t tmpccer = 0U;
 832   uint32_t tmpcr2 = 0U;
 833
 834   /* Check the parameters */
 835   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
 836   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 837   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 838   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 839   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 840   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 841
 842   /* Disable the Channel 2: Reset the CC2E Bit */
 843   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
 844
 845   /* Get the TIMx CCER register value */
 846   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
 847
 848   /* Get the TIMx CR2 register value */
 849   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 850
 851   /* Get the TIMx CCMR1 register value */
 852   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 853
 854   /* Reset Capture/Compare selection Bits */
 855   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
 856
 857   /* Select the Output Compare Mode */
 858   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
 859
 860   /* Set the Output Compare Polarity */
 861   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
 862
 863   /* Set the Output State */
 864   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
 865
 866   if (IS_TIM_BREAK_INSTANCE(TIMx))
 867   {
 868     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 869     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
 870
 871     /* Set the complementary output Polarity */
 872     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
 873
 874     /* Set the complementary output State */
 875     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
 876
 877     /* Set the Output Idle state */
 878     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
 879
 880     /* Set the complementary output Idle state */
 881     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
 882   }
 883
 884   /* Write to TIMx CR2 */
 885   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 886
 887   /* Write to TIMx CCMR1 */
 888   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 889
 890   /* Set the Capture Compare Register value */
 891   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
 892
 893   /* Write to TIMx CCER */
 894   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 895
 896   return SUCCESS;
 897 }
 898
 899 /**
 900   * @brief  Configure the TIMx output channel 3.
 901   * @param  TIMx Timer Instance
 902   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
 903   * @retval An ErrorStatus enumeration value:
 904   *          - SUCCESS: TIMx registers are de-initialized
 905   *          - ERROR: not applicable
 906   */
 907 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 908 {
 909   uint32_t tmpccmr2 = 0U;
 910   uint32_t tmpccer = 0U;
 911   uint32_t tmpcr2 = 0U;
 912
 913   /* Check the parameters */
 914   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
 915   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 916   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 917   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 918   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 919   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 920
 921   /* Disable the Channel 3: Reset the CC3E Bit */
 922   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
 923
 924   /* Get the TIMx CCER register value */
 925   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
 926
 927   /* Get the TIMx CR2 register value */
 928   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 929
 930   /* Get the TIMx CCMR2 register value */
 931   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
 932
 933   /* Reset Capture/Compare selection Bits */
 934   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
 935
 936   /* Select the Output Compare Mode */
 937   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
 938
 939   /* Set the Output Compare Polarity */
 940   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
 941
 942   /* Set the Output State */
 943   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
 944
 945   if (IS_TIM_BREAK_INSTANCE(TIMx))
 946   {
 947     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 948     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
 949
 950     /* Set the complementary output Polarity */
 951     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
 952
 953     /* Set the complementary output State */
 954     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
 955
 956     /* Set the Output Idle state */
 957     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
 958
 959     /* Set the complementary output Idle state */
 960     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
 961   }
 962
 963   /* Write to TIMx CR2 */
 964   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 965
 966   /* Write to TIMx CCMR2 */
 967   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
 968
 969   /* Set the Capture Compare Register value */
 970   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
 971
 972   /* Write to TIMx CCER */
 973   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 974
 975   return SUCCESS;
 976 }
 977
 978 /**
 979   * @brief  Configure the TIMx output channel 4.
 980   * @param  TIMx Timer Instance
 981   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
 982   * @retval An ErrorStatus enumeration value:
 983   *          - SUCCESS: TIMx registers are de-initialized
 984   *          - ERROR: not applicable
 985   */
 986 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 987 {
 988   uint32_t tmpccmr2 = 0U;
 989   uint32_t tmpccer = 0U;
 990   uint32_t tmpcr2 = 0U;
 991
 992   /* Check the parameters */
 993   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
 994   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 995   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 996   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 997   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 998   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 999
1000   /* Disable the Channel 4: Reset the CC4E Bit */
1001   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1002
1003   /* Get the TIMx CCER register value */
1004   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1005
1006   /* Get the TIMx CR2 register value */
1007   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
1008
1009   /* Get the TIMx CCMR2 register value */
1010   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1011
1012   /* Reset Capture/Compare selection Bits */
1013   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1014
1015   /* Select the Output Compare Mode */
1016   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1017
1018   /* Set the Output Compare Polarity */
1019   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1020
1021   /* Set the Output State */
1022   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1023
1024   if (IS_TIM_BREAK_INSTANCE(TIMx))
1025   {
1026     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1027     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1028
1029     /* Set the Output Idle state */
1030     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1031   }
1032
1033   /* Write to TIMx CR2 */
1034   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1035
1036   /* Write to TIMx CCMR2 */
1037   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1038
1039   /* Set the Capture Compare Register value */
1040   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1041
1042   /* Write to TIMx CCER */
1043   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1044
1045   return SUCCESS;
1046 }
1047
1048
1049 /**
1050   * @brief  Configure the TIMx input channel 1.
1051   * @param  TIMx Timer Instance
1052   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1053   * @retval An ErrorStatus enumeration value:
1054   *          - SUCCESS: TIMx registers are de-initialized
1055   *          - ERROR: not applicable
1056   */
1057 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1058 {
1059   /* Check the parameters */
1060   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1061   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1062   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1063   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1064   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1065
1066   /* Disable the Channel 1: Reset the CC1E Bit */
1067   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1068
1069   /* Select the Input and set the filter and the prescaler value */
1070   MODIFY_REG(TIMx->CCMR1,
1071              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1072              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1073
1074   /* Select the Polarity and set the CC1E Bit */
1075   MODIFY_REG(TIMx->CCER,
1076              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1077              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1078
1079   return SUCCESS;
1080 }
1081
1082 /**
1083   * @brief  Configure the TIMx input channel 2.
1084   * @param  TIMx Timer Instance
1085   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1086   * @retval An ErrorStatus enumeration value:
1087   *          - SUCCESS: TIMx registers are de-initialized
1088   *          - ERROR: not applicable
1089   */
1090 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1091 {
1092   /* Check the parameters */
1093   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1094   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1095   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1096   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1097   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1098
1099   /* Disable the Channel 2: Reset the CC2E Bit */
1100   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1101
1102   /* Select the Input and set the filter and the prescaler value */
1103   MODIFY_REG(TIMx->CCMR1,
1104              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1105              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1106
1107   /* Select the Polarity and set the CC2E Bit */
1108   MODIFY_REG(TIMx->CCER,
1109              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1110              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1111
1112   return SUCCESS;
1113 }
1114
1115 /**
1116   * @brief  Configure the TIMx input channel 3.
1117   * @param  TIMx Timer Instance
1118   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1119   * @retval An ErrorStatus enumeration value:
1120   *          - SUCCESS: TIMx registers are de-initialized
1121   *          - ERROR: not applicable
1122   */
1123 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1124 {
1125   /* Check the parameters */
1126   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1127   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1128   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1129   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1130   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1131
1132   /* Disable the Channel 3: Reset the CC3E Bit */
1133   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1134
1135   /* Select the Input and set the filter and the prescaler value */
1136   MODIFY_REG(TIMx->CCMR2,
1137              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1138              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1139
1140   /* Select the Polarity and set the CC3E Bit */
1141   MODIFY_REG(TIMx->CCER,
1142              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1143              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1144
1145   return SUCCESS;
1146 }
1147
1148 /**
1149   * @brief  Configure the TIMx input channel 4.
1150   * @param  TIMx Timer Instance
1151   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1152   * @retval An ErrorStatus enumeration value:
1153   *          - SUCCESS: TIMx registers are de-initialized
1154   *          - ERROR: not applicable
1155   */
1156 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1157 {
1158   /* Check the parameters */
1159   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1160   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1161   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1162   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1163   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1164
1165   /* Disable the Channel 4: Reset the CC4E Bit */
1166   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1167
1168   /* Select the Input and set the filter and the prescaler value */
1169   MODIFY_REG(TIMx->CCMR2,
1170              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1171              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1172
1173   /* Select the Polarity and set the CC2E Bit */
1174   MODIFY_REG(TIMx->CCER,
1175              (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1176              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1177
1178   return SUCCESS;
1179 }
1180
1181
1182 /**
1183   * @}
1184   */
1185
1186 /**
1187   * @}
1188   */
1189
1190 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */
1191
1192 /**
1193   * @}
1194   */
1195
1196 #endif /* USE_FULL_LL_DRIVER */
1197
1198 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/