src/main/drivers/memprot_stm32h7xx.c

   1 /*
   2  * This file is part of Cleanflight and Betaflight.
   3  *
   4  * Cleanflight and Betaflight are free software. You can redistribute
   5  * this software and/or modify this software under the terms of the
   6  * GNU General Public License as published by the Free Software
   7  * Foundation, either version 3 of the License, or (at your option)
   8  * any later version.
   9  *
  10  * Cleanflight and Betaflight are distributed in the hope that they
  11  * will be useful, but WITHOUT ANY WARRANTY; without even the implied
  12  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  13  * See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this software.
  17  *
  18  * If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "platform.h"
  22
  23 #include "memprot.h"
  24
  25 // Defined in linker script
  26 extern uint8_t dmaram_start;
  27 extern uint8_t dmaram_end;
  28
  29 extern uint8_t dmarwaxi_start;
  30 extern uint8_t dmarwaxi_end;
  31
  32 mpuRegion_t mpuRegions[] = {
  33 #ifdef USE_ITCM_RAM
  34     {
  35         //  Mark ITCM-RAM as read-only
  36         // "For Cortex®-M7, TCMs memories always behave as Non-cacheable, Non-shared normal memories, irrespective of the memory type attributes defined in the MPU for a memory region containing addresses held in the TCM"
  37         // See AN4838
  38         .start      = 0x00000000,
  39         .end        = 0, // Size defined by "size"
  40         .size       = MPU_REGION_SIZE_64KB,
  41         .perm       = MPU_REGION_PRIV_RO_URO,
  42         .exec       = MPU_INSTRUCTION_ACCESS_ENABLE,
  43         .shareable  = MPU_ACCESS_NOT_SHAREABLE,
  44         .cacheable  = MPU_ACCESS_NOT_CACHEABLE,
  45         .bufferable = MPU_ACCESS_BUFFERABLE,
  46     },
  47 #endif
  48 #ifdef USE_DMA_RAM
  49     {
  50         // DMA transmit buffer in D2 SRAM1
  51         // Reading needs cache coherence operation
  52         .start      = (uint32_t)&dmaram_start,
  53         .end        = (uint32_t)&dmaram_end,
  54         .size       = 0,  // Size determined by ".end"
  55         .perm       = MPU_REGION_FULL_ACCESS,
  56         .exec       = MPU_INSTRUCTION_ACCESS_ENABLE,
  57         .shareable  = MPU_ACCESS_SHAREABLE,
  58         .cacheable  = MPU_ACCESS_CACHEABLE,
  59         .bufferable = MPU_ACCESS_NOT_BUFFERABLE,
  60     },
  61     {
  62         // A region in AXI RAM accessible from SDIO internal DMA
  63         .start      = (uint32_t)&dmarwaxi_start,
  64         .end        = (uint32_t)&dmarwaxi_end,
  65         .size       = 0,  // Size determined by ".end"
  66         .perm       = MPU_REGION_FULL_ACCESS,
  67         .exec       = MPU_INSTRUCTION_ACCESS_ENABLE,
  68         .shareable  = MPU_ACCESS_NOT_SHAREABLE,
  69         .cacheable  = MPU_ACCESS_CACHEABLE,
  70         .bufferable = MPU_ACCESS_NOT_BUFFERABLE,
  71     },
  72 #endif
  73 };
  74
  75 unsigned mpuRegionCount = ARRAYLEN(mpuRegions);
  76
  77 STATIC_ASSERT(ARRAYLEN(mpuRegions) <= MAX_MPU_REGIONS, MPU_region_count_exceeds_limit);