lib/main/STM32F1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nand.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f1xx_hal_nand.c
   4   * @author  MCD Application Team
   5   * @version V1.1.1
   6   * @date    12-May-2017
   7   * @brief   NAND HAL module driver.
   8   *          This file provides a generic firmware to drive NAND memories mounted
   9   *          as external device.
  10   *
  11   @verbatim
  12   ==============================================================================
  13                          ##### How to use this driver #####
  14   ==============================================================================
  15     [..]
  16       This driver is a generic layered driver which contains a set of APIs used to
  17       control NAND flash memories. It uses the FSMC layer functions to interface
  18       with NAND devices. This driver is used as follows:
  19
  20       (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
  21           with control and timing parameters for both common and attribute spaces.
  22
  23       (+) Read NAND flash memory maker and device IDs using the function
  24           HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
  25           structure declared by the function caller.
  26
  27       (+) Access NAND flash memory by read/write operations using the functions
  28           HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
  29           HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
  30           HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
  31           HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
  32           to read/write page(s)/spare area(s). These functions use specific device
  33           information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
  34           structure. The read/write address information is contained by the Nand_Address_Typedef
  35           structure passed as parameter.
  36
  37       (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
  38
  39       (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
  40           The erase block address information is contained in the Nand_Address_Typedef
  41           structure passed as parameter.
  42
  43       (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
  44
  45       (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
  46           HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
  47           feature or the function HAL_NAND_GetECC() to get the ECC correction code.
  48
  49       (+) You can monitor the NAND device HAL state by calling the function
  50           HAL_NAND_GetState()
  51
  52     [..]
  53       (@) This driver is a set of generic APIs which handle standard NAND flash operations.
  54           If a NAND flash device contains different operations and/or implementations,
  55           it should be implemented separately.
  56
  57   @endverbatim
  58   ******************************************************************************
  59   * @attention
  60   *
  61   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  62   *
  63   * Redistribution and use in source and binary forms, with or without modification,
  64   * are permitted provided that the following conditions are met:
  65   *   1. Redistributions of source code must retain the above copyright notice,
  66   *      this list of conditions and the following disclaimer.
  67   *   2. Redistributions in binary form must reproduce the above copyright notice,
  68   *      this list of conditions and the following disclaimer in the documentation
  69   *      and/or other materials provided with the distribution.
  70   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  71   *      may be used to endorse or promote products derived from this software
  72   *      without specific prior written permission.
  73   *
  74   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  75   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  76   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  77   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  78   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  79   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  80   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  81   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  82   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  83   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  84   *
  85   ******************************************************************************
  86   */
  87
  88 /* Includes ------------------------------------------------------------------*/
  89 #include "stm32f1xx_hal.h"
  90
  91 /** @addtogroup STM32F1xx_HAL_Driver
  92   * @{
  93   */
  94
  95 #ifdef HAL_NAND_MODULE_ENABLED
  96
  97 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
  98
  99 /** @defgroup NAND NAND
 100   * @brief NAND HAL module driver
 101   * @{
 102   */
 103
 104 /* Private typedef -----------------------------------------------------------*/
 105 /* Private define ------------------------------------------------------------*/
 106 /** @defgroup NAND_Private_Constants NAND Private Constants
 107   * @{
 108   */
 109
 110 /**
 111   * @}
 112   */
 113
 114 /* Private macro -------------------------------------------------------------*/
 115 /** @defgroup NAND_Private_Macros NAND Private Macros
 116   * @{
 117   */
 118
 119 /**
 120   * @}
 121   */
 122
 123 /* Private variables ---------------------------------------------------------*/
 124 /* Private function prototypes -----------------------------------------------*/
 125 /* Exported functions --------------------------------------------------------*/
 126 /** @defgroup NAND_Exported_Functions NAND Exported Functions
 127   * @{
 128   */
 129
 130 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
 131   * @brief    Initialization and Configuration functions
 132   *
 133   @verbatim
 134   ==============================================================================
 135             ##### NAND Initialization and de-initialization functions #####
 136   ==============================================================================
 137   [..]
 138     This section provides functions allowing to initialize/de-initialize
 139     the NAND memory
 140
 141 @endverbatim
 142   * @{
 143   */
 144
 145 /**
 146   * @brief  Perform NAND memory Initialization sequence
 147   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 148   *                the configuration information for NAND module.
 149   * @param  ComSpace_Timing: pointer to Common space timing structure
 150   * @param  AttSpace_Timing: pointer to Attribute space timing structure
 151   * @retval HAL status
 152   */
 153 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
 154 {
 155   /* Check the NAND handle state */
 156   if(hnand == NULL)
 157   {
 158      return HAL_ERROR;
 159   }
 160
 161   if(hnand->State == HAL_NAND_STATE_RESET)
 162   {
 163     /* Allocate lock resource and initialize it */
 164     hnand->Lock = HAL_UNLOCKED;
 165     /* Initialize the low level hardware (MSP) */
 166     HAL_NAND_MspInit(hnand);
 167   }
 168
 169   /* Initialize NAND control Interface */
 170   FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
 171
 172   /* Initialize NAND common space timing Interface */
 173   FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
 174
 175   /* Initialize NAND attribute space timing Interface */
 176   FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
 177
 178   /* Enable the NAND device */
 179   __FSMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
 180
 181   /* Update the NAND controller state */
 182   hnand->State = HAL_NAND_STATE_READY;
 183
 184   return HAL_OK;
 185 }
 186
 187 /**
 188   * @brief  Perform NAND memory De-Initialization sequence
 189   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 190   *                the configuration information for NAND module.
 191   * @retval HAL status
 192   */
 193 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
 194 {
 195   /* Initialize the low level hardware (MSP) */
 196   HAL_NAND_MspDeInit(hnand);
 197
 198   /* Configure the NAND registers with their reset values */
 199   FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
 200
 201   /* Reset the NAND controller state */
 202   hnand->State = HAL_NAND_STATE_RESET;
 203
 204   /* Release Lock */
 205   __HAL_UNLOCK(hnand);
 206
 207   return HAL_OK;
 208 }
 209
 210 /**
 211   * @brief  NAND MSP Init
 212   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 213   *                the configuration information for NAND module.
 214   * @retval None
 215   */
 216 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
 217 {
 218   /* Prevent unused argument(s) compilation warning */
 219   UNUSED(hnand);
 220   /* NOTE : This function Should not be modified, when the callback is needed,
 221             the HAL_NAND_MspInit could be implemented in the user file
 222    */
 223 }
 224
 225 /**
 226   * @brief  NAND MSP DeInit
 227   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 228   *                the configuration information for NAND module.
 229   * @retval None
 230   */
 231 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
 232 {
 233   /* Prevent unused argument(s) compilation warning */
 234   UNUSED(hnand);
 235   /* NOTE : This function Should not be modified, when the callback is needed,
 236             the HAL_NAND_MspDeInit could be implemented in the user file
 237    */
 238 }
 239
 240
 241 /**
 242   * @brief  This function handles NAND device interrupt request.
 243   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 244   *                the configuration information for NAND module.
 245   * @retval HAL status
 246 */
 247 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
 248 {
 249   /* Check NAND interrupt Rising edge flag */
 250   if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
 251   {
 252     /* NAND interrupt callback*/
 253     HAL_NAND_ITCallback(hnand);
 254
 255     /* Clear NAND interrupt Rising edge pending bit */
 256     __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE);
 257   }
 258
 259   /* Check NAND interrupt Level flag */
 260   if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
 261   {
 262     /* NAND interrupt callback*/
 263     HAL_NAND_ITCallback(hnand);
 264
 265     /* Clear NAND interrupt Level pending bit */
 266     __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL);
 267   }
 268
 269   /* Check NAND interrupt Falling edge flag */
 270   if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
 271   {
 272     /* NAND interrupt callback*/
 273     HAL_NAND_ITCallback(hnand);
 274
 275     /* Clear NAND interrupt Falling edge pending bit */
 276     __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE);
 277   }
 278
 279   /* Check NAND interrupt FIFO empty flag */
 280   if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
 281   {
 282     /* NAND interrupt callback*/
 283     HAL_NAND_ITCallback(hnand);
 284
 285     /* Clear NAND interrupt FIFO empty pending bit */
 286     __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
 287   }
 288 }
 289
 290 /**
 291   * @brief  NAND interrupt feature callback
 292   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 293   *                the configuration information for NAND module.
 294   * @retval None
 295   */
 296 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
 297 {
 298   /* Prevent unused argument(s) compilation warning */
 299   UNUSED(hnand);
 300   /* NOTE : This function Should not be modified, when the callback is needed,
 301             the HAL_NAND_ITCallback could be implemented in the user file
 302    */
 303 }
 304
 305 /**
 306   * @}
 307   */
 308
 309 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
 310   * @brief    Input Output and memory control functions
 311   *
 312   @verbatim
 313   ==============================================================================
 314                     ##### NAND Input and Output functions #####
 315   ==============================================================================
 316   [..]
 317     This section provides functions allowing to use and control the NAND
 318     memory
 319
 320 @endverbatim
 321   * @{
 322   */
 323
 324 /**
 325   * @brief  Read the NAND memory electronic signature
 326   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 327   *                the configuration information for NAND module.
 328   * @param  pNAND_ID: NAND ID structure
 329   * @retval HAL status
 330   */
 331 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
 332 {
 333   __IO uint32_t data = 0U;
 334   __IO uint32_t data1 = 0U;
 335   uint32_t deviceaddress = 0U;
 336
 337   /* Process Locked */
 338   __HAL_LOCK(hnand);
 339
 340   /* Check the NAND controller state */
 341   if(hnand->State == HAL_NAND_STATE_BUSY)
 342   {
 343      return HAL_BUSY;
 344   }
 345
 346   /* Identify the device address */
 347   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 348   {
 349     deviceaddress = NAND_DEVICE1;
 350   }
 351   else
 352   {
 353     deviceaddress = NAND_DEVICE2;
 354   }
 355
 356   /* Update the NAND controller state */
 357   hnand->State = HAL_NAND_STATE_BUSY;
 358
 359   /* Send Read ID command sequence */
 360   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_READID;
 361   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 362
 363   /* Read the electronic signature from NAND flash */
 364   if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
 365   {
 366     data = *(__IO uint32_t *)deviceaddress;
 367
 368     /* Return the data read */
 369     pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
 370     pNAND_ID->Device_Id  = ADDR_2ND_CYCLE(data);
 371     pNAND_ID->Third_Id   = ADDR_3RD_CYCLE(data);
 372     pNAND_ID->Fourth_Id  = ADDR_4TH_CYCLE(data);
 373   }
 374   else
 375   {
 376     data = *(__IO uint32_t *)deviceaddress;
 377     data1 = *((__IO uint32_t *)deviceaddress + 4U);
 378
 379     /* Return the data read */
 380     pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
 381     pNAND_ID->Device_Id  = ADDR_3RD_CYCLE(data);
 382     pNAND_ID->Third_Id   = ADDR_1ST_CYCLE(data1);
 383     pNAND_ID->Fourth_Id  = ADDR_3RD_CYCLE(data1);
 384   }
 385
 386   /* Update the NAND controller state */
 387   hnand->State = HAL_NAND_STATE_READY;
 388
 389   /* Process unlocked */
 390   __HAL_UNLOCK(hnand);
 391
 392   return HAL_OK;
 393 }
 394
 395 /**
 396   * @brief  NAND memory reset
 397   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 398   *                the configuration information for NAND module.
 399   * @retval HAL status
 400   */
 401 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
 402 {
 403   uint32_t deviceaddress = 0U;
 404
 405   /* Process Locked */
 406   __HAL_LOCK(hnand);
 407
 408   /* Check the NAND controller state */
 409   if(hnand->State == HAL_NAND_STATE_BUSY)
 410   {
 411      return HAL_BUSY;
 412   }
 413
 414   /* Identify the device address */
 415   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 416   {
 417     deviceaddress = NAND_DEVICE1;
 418   }
 419   else
 420   {
 421     deviceaddress = NAND_DEVICE2;
 422   }
 423
 424   /* Update the NAND controller state */
 425   hnand->State = HAL_NAND_STATE_BUSY;
 426
 427   /* Send NAND reset command */
 428   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
 429
 430
 431   /* Update the NAND controller state */
 432   hnand->State = HAL_NAND_STATE_READY;
 433
 434   /* Process unlocked */
 435   __HAL_UNLOCK(hnand);
 436
 437   return HAL_OK;
 438
 439 }
 440
 441 /**
 442   * @brief  Configure the device: Enter the physical parameters of the device
 443   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 444   *                the configuration information for NAND module.
 445   * @param  pDeviceConfig : pointer to NAND_DeviceConfigTypeDef structure
 446   * @retval HAL status
 447   */
 448 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
 449 {
 450   hnand->Config.PageSize           = pDeviceConfig->PageSize;
 451   hnand->Config.SpareAreaSize      = pDeviceConfig->SpareAreaSize;
 452   hnand->Config.BlockSize          = pDeviceConfig->BlockSize;
 453   hnand->Config.BlockNbr           = pDeviceConfig->BlockNbr;
 454   hnand->Config.PlaneSize          = pDeviceConfig->PlaneSize;
 455   hnand->Config.PlaneNbr           = pDeviceConfig->PlaneNbr;
 456   hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
 457
 458   return HAL_OK;
 459 }
 460
 461 /**
 462   * @brief  Read Page(s) from NAND memory block (8-bits addressing)
 463   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 464   *                the configuration information for NAND module.
 465   * @param  pAddress : pointer to NAND address structure
 466   * @param  pBuffer : pointer to destination read buffer
 467   * @param  NumPageToRead : number of pages to read from block
 468   * @retval HAL status
 469   */
 470 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
 471 {
 472   __IO uint32_t index  = 0U;
 473   uint32_t tickstart = 0U;
 474   uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
 475
 476   /* Process Locked */
 477   __HAL_LOCK(hnand);
 478
 479   /* Check the NAND controller state */
 480   if(hnand->State == HAL_NAND_STATE_BUSY)
 481   {
 482      return HAL_BUSY;
 483   }
 484
 485   /* Identify the device address */
 486   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 487   {
 488     deviceaddress = NAND_DEVICE1;
 489   }
 490   else
 491   {
 492     deviceaddress = NAND_DEVICE2;
 493   }
 494
 495   /* Update the NAND controller state */
 496   hnand->State = HAL_NAND_STATE_BUSY;
 497
 498   /* NAND raw address calculation */
 499   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
 500
 501   /* Page(s) read loop */
 502   while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
 503   {
 504     /* update the buffer size */
 505     size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
 506
 507     /* Send read page command sequence */
 508     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
 509
 510     /* Cards with page size <= 512 bytes */
 511     if((hnand->Config.PageSize) <= 512U)
 512     {
 513       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 514       {
 515         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 516         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 517         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 518       }
 519       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 520       {
 521         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 522         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 523         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 524         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 525       }
 526     }
 527     else /* (hnand->Config.PageSize) > 512 */
 528     {
 529       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 530       {
 531         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 532         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 533         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 534         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 535       }
 536       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 537       {
 538         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 539         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 540         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 541         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 542         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 543       }
 544     }
 545
 546     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
 547
 548     /* Check if an extra command is needed for reading pages  */
 549     if(hnand->Config.ExtraCommandEnable == ENABLE)
 550     {
 551       /* Get tick */
 552       tickstart = HAL_GetTick();
 553
 554       /* Read status until NAND is ready */
 555       while(HAL_NAND_Read_Status(hnand) != NAND_READY)
 556       {
 557         if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
 558         {
 559           return HAL_TIMEOUT;
 560         }
 561       }
 562
 563       /* Go back to read mode */
 564       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
 565     }
 566
 567     /* Get Data into Buffer */
 568     for(; index < size; index++)
 569     {
 570       *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
 571     }
 572
 573     /* Increment read pages number */
 574     numPagesRead++;
 575
 576     /* Decrement pages to read */
 577     NumPageToRead--;
 578
 579     /* Increment the NAND address */
 580     nandaddress = (uint32_t)(nandaddress + 1U);
 581   }
 582
 583   /* Update the NAND controller state */
 584   hnand->State = HAL_NAND_STATE_READY;
 585
 586   /* Process unlocked */
 587   __HAL_UNLOCK(hnand);
 588
 589   return HAL_OK;
 590 }
 591
 592 /**
 593   * @brief  Read Page(s) from NAND memory block (16-bits addressing)
 594   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 595   *                the configuration information for NAND module.
 596   * @param  pAddress : pointer to NAND address structure
 597   * @param  pBuffer : pointer to destination read buffer. pBuffer should be 16bits aligned
 598   * @param  NumPageToRead : number of pages to read from block
 599   * @retval HAL status
 600   */
 601 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
 602 {
 603   __IO uint32_t index  = 0U;
 604   uint32_t tickstart = 0U;
 605   uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
 606
 607   /* Process Locked */
 608   __HAL_LOCK(hnand);
 609
 610   /* Check the NAND controller state */
 611   if(hnand->State == HAL_NAND_STATE_BUSY)
 612   {
 613      return HAL_BUSY;
 614   }
 615
 616   /* Identify the device address */
 617   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 618   {
 619     deviceaddress = NAND_DEVICE1;
 620   }
 621   else
 622   {
 623     deviceaddress = NAND_DEVICE2;
 624   }
 625
 626   /* Update the NAND controller state */
 627   hnand->State = HAL_NAND_STATE_BUSY;
 628
 629   /* NAND raw address calculation */
 630   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
 631
 632   /* Page(s) read loop */
 633   while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
 634   {
 635     /* update the buffer size */
 636     size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
 637
 638     /* Send read page command sequence */
 639     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
 640
 641     /* Cards with page size <= 512 bytes */
 642     if((hnand->Config.PageSize) <= 512U)
 643     {
 644       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 645       {
 646         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 647         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 648         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 649       }
 650       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 651       {
 652         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 653         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 654         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 655         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 656       }
 657     }
 658     else /* (hnand->Config.PageSize) > 512 */
 659     {
 660       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 661       {
 662         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 663         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 664         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 665         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 666       }
 667       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 668       {
 669         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 670         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 671         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 672         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 673         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 674       }
 675     }
 676
 677     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
 678
 679     if(hnand->Config.ExtraCommandEnable == ENABLE)
 680     {
 681       /* Get tick */
 682       tickstart = HAL_GetTick();
 683
 684       /* Read status until NAND is ready */
 685       while(HAL_NAND_Read_Status(hnand) != NAND_READY)
 686       {
 687         if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
 688         {
 689           return HAL_TIMEOUT;
 690         }
 691       }
 692
 693       /* Go back to read mode */
 694       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
 695     }
 696
 697     /* Get Data into Buffer */
 698     for(; index < size; index++)
 699     {
 700       *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
 701     }
 702
 703     /* Increment read pages number */
 704     numPagesRead++;
 705
 706     /* Decrement pages to read */
 707     NumPageToRead--;
 708
 709     /* Increment the NAND address */
 710     nandaddress = (uint32_t)(nandaddress + 1U);
 711   }
 712
 713   /* Update the NAND controller state */
 714   hnand->State = HAL_NAND_STATE_READY;
 715
 716   /* Process unlocked */
 717   __HAL_UNLOCK(hnand);
 718
 719   return HAL_OK;
 720 }
 721
 722 /**
 723   * @brief  Write Page(s) to NAND memory block (8-bits addressing)
 724   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 725   *                the configuration information for NAND module.
 726   * @param  pAddress : pointer to NAND address structure
 727   * @param  pBuffer : pointer to source buffer to write
 728   * @param  NumPageToWrite  : number of pages to write to block
 729   * @retval HAL status
 730   */
 731 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
 732 {
 733   __IO uint32_t index = 0U;
 734   uint32_t tickstart = 0U;
 735   uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
 736
 737   /* Process Locked */
 738   __HAL_LOCK(hnand);
 739
 740   /* Check the NAND controller state */
 741   if(hnand->State == HAL_NAND_STATE_BUSY)
 742   {
 743      return HAL_BUSY;
 744   }
 745
 746   /* Identify the device address */
 747   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 748   {
 749     deviceaddress = NAND_DEVICE1;
 750   }
 751   else
 752   {
 753     deviceaddress = NAND_DEVICE2;
 754   }
 755
 756   /* Update the NAND controller state */
 757   hnand->State = HAL_NAND_STATE_BUSY;
 758
 759   /* NAND raw address calculation */
 760   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
 761
 762   /* Page(s) write loop */
 763   while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
 764   {
 765     /* update the buffer size */
 766     size = hnand->Config.PageSize + ((hnand->Config.PageSize) * numPagesWritten);
 767
 768     /* Send write page command sequence */
 769     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
 770     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
 771
 772     /* Cards with page size <= 512 bytes */
 773     if((hnand->Config.PageSize) <= 512U)
 774     {
 775       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 776       {
 777         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 778         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 779         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 780       }
 781       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 782       {
 783         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 784         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 785         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 786         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 787       }
 788     }
 789     else /* (hnand->Config.PageSize) > 512 */
 790     {
 791       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 792       {
 793         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 794         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 795         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 796         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 797       }
 798       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 799       {
 800         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 801         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 802         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 803         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 804         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 805       }
 806     }
 807
 808
 809     /* Write data to memory */
 810     for(; index < size; index++)
 811     {
 812       *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
 813     }
 814
 815     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
 816
 817     /* Read status until NAND is ready */
 818     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
 819     {
 820       /* Get tick */
 821       tickstart = HAL_GetTick();
 822
 823       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
 824       {
 825         return HAL_TIMEOUT;
 826       }
 827     }
 828
 829     /* Increment written pages number */
 830     numPagesWritten++;
 831
 832     /* Decrement pages to write */
 833     NumPageToWrite--;
 834
 835     /* Increment the NAND address */
 836     nandaddress = (uint32_t)(nandaddress + 1U);
 837   }
 838
 839   /* Update the NAND controller state */
 840   hnand->State = HAL_NAND_STATE_READY;
 841
 842   /* Process unlocked */
 843   __HAL_UNLOCK(hnand);
 844
 845   return HAL_OK;
 846 }
 847
 848 /**
 849   * @brief  Write Page(s) to NAND memory block (16-bits addressing)
 850   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 851   *                the configuration information for NAND module.
 852   * @param  pAddress : pointer to NAND address structure
 853   * @param  pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned
 854   * @param  NumPageToWrite  : number of pages to write to block
 855   * @retval HAL status
 856   */
 857 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
 858 {
 859   __IO uint32_t index = 0U;
 860   uint32_t tickstart = 0U;
 861   uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
 862
 863   /* Process Locked */
 864   __HAL_LOCK(hnand);
 865
 866   /* Check the NAND controller state */
 867   if(hnand->State == HAL_NAND_STATE_BUSY)
 868   {
 869      return HAL_BUSY;
 870   }
 871
 872   /* Identify the device address */
 873   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 874   {
 875     deviceaddress = NAND_DEVICE1;
 876   }
 877   else
 878   {
 879     deviceaddress = NAND_DEVICE2;
 880   }
 881
 882   /* Update the NAND controller state */
 883   hnand->State = HAL_NAND_STATE_BUSY;
 884
 885   /* NAND raw address calculation */
 886   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
 887
 888   /* Page(s) write loop */
 889   while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
 890   {
 891     /* update the buffer size */
 892     size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
 893
 894     /* Send write page command sequence */
 895     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
 896     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
 897
 898     /* Cards with page size <= 512 bytes */
 899     if((hnand->Config.PageSize) <= 512U)
 900     {
 901       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 902       {
 903         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 904         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 905         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 906       }
 907       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 908       {
 909         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 910         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 911         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 912         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 913       }
 914     }
 915     else /* (hnand->Config.PageSize) > 512 */
 916     {
 917       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 918       {
 919         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 920         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 921         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 922         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 923       }
 924       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 925       {
 926         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 927         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 928         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 929         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 930         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 931       }
 932     }
 933
 934     /* Write data to memory */
 935     for(; index < size; index++)
 936     {
 937       *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
 938     }
 939
 940     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
 941
 942     /* Read status until NAND is ready */
 943     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
 944     {
 945       /* Get tick */
 946       tickstart = HAL_GetTick();
 947
 948       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
 949       {
 950         return HAL_TIMEOUT;
 951       }
 952     }
 953
 954     /* Increment written pages number */
 955     numPagesWritten++;
 956
 957     /* Decrement pages to write */
 958     NumPageToWrite--;
 959
 960     /* Increment the NAND address */
 961     nandaddress = (uint32_t)(nandaddress + 1U);
 962   }
 963
 964   /* Update the NAND controller state */
 965   hnand->State = HAL_NAND_STATE_READY;
 966
 967   /* Process unlocked */
 968   __HAL_UNLOCK(hnand);
 969
 970   return HAL_OK;
 971 }
 972
 973 /**
 974   * @brief  Read Spare area(s) from NAND memory (8-bits addressing)
 975   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 976   *                the configuration information for NAND module.
 977   * @param  pAddress : pointer to NAND address structure
 978   * @param  pBuffer: pointer to source buffer to write
 979   * @param  NumSpareAreaToRead: Number of spare area to read
 980   * @retval HAL status
 981 */
 982 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
 983 {
 984   __IO uint32_t index = 0U;
 985   uint32_t tickstart = 0U;
 986   uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
 987
 988   /* Process Locked */
 989   __HAL_LOCK(hnand);
 990
 991   /* Check the NAND controller state */
 992   if(hnand->State == HAL_NAND_STATE_BUSY)
 993   {
 994      return HAL_BUSY;
 995   }
 996
 997   /* Identify the device address */
 998   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 999   {
1000     deviceaddress = NAND_DEVICE1;
1001   }
1002   else
1003   {
1004     deviceaddress = NAND_DEVICE2;
1005   }
1006
1007   /* Update the NAND controller state */
1008   hnand->State = HAL_NAND_STATE_BUSY;
1009
1010   /* NAND raw address calculation */
1011   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
1012
1013   /* Column in page address */
1014   columnaddress = COLUMN_ADDRESS(hnand);
1015
1016   /* Spare area(s) read loop */
1017   while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1018   {
1019     /* update the buffer size */
1020     size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
1021
1022     /* Cards with page size <= 512 bytes */
1023     if((hnand->Config.PageSize) <= 512U)
1024     {
1025       /* Send read spare area command sequence */
1026       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
1027
1028       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
1029       {
1030         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
1031         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1032         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1033       }
1034       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1035       {
1036         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
1037         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1038         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1039         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
1040       }
1041     }
1042     else /* (hnand->Config.PageSize) > 512 */
1043     {
1044       /* Send read spare area command sequence */
1045       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
1046
1047       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
1048       {
1049         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
1050         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
1051         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1052         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1053       }
1054       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1055       {
1056         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
1057         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
1058         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1059         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1060         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
1061       }
1062     }
1063
1064     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
1065
1066     if(hnand->Config.ExtraCommandEnable == ENABLE)
1067     {
1068       /* Get tick */
1069       tickstart = HAL_GetTick();
1070
1071       /* Read status until NAND is ready */
1072       while(HAL_NAND_Read_Status(hnand) != NAND_READY)
1073       {
1074         if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
1075         {
1076           return HAL_TIMEOUT;
1077         }
1078       }
1079
1080       /* Go back to read mode */
1081       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
1082     }
1083
1084     /* Get Data into Buffer */
1085     for(; index < size; index++)
1086     {
1087       *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
1088     }
1089
1090     /* Increment read spare areas number */
1091     numSpareAreaRead++;
1092
1093     /* Decrement spare areas to read */
1094     NumSpareAreaToRead--;
1095
1096     /* Increment the NAND address */
1097     nandaddress = (uint32_t)(nandaddress + 1U);
1098   }
1099
1100   /* Update the NAND controller state */
1101   hnand->State = HAL_NAND_STATE_READY;
1102
1103   /* Process unlocked */
1104   __HAL_UNLOCK(hnand);
1105
1106   return HAL_OK;
1107 }
1108
1109 /**
1110   * @brief  Read Spare area(s) from NAND memory (16-bits addressing)
1111   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
1112   *                the configuration information for NAND module.
1113   * @param  pAddress : pointer to NAND address structure
1114   * @param  pBuffer: pointer to source buffer to write. pBuffer should be 16bits aligned.
1115   * @param  NumSpareAreaToRead: Number of spare area to read
1116   * @retval HAL status
1117 */
1118 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
1119 {
1120   __IO uint32_t index = 0U;
1121   uint32_t tickstart = 0U;
1122   uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
1123
1124   /* Process Locked */
1125   __HAL_LOCK(hnand);
1126
1127   /* Check the NAND controller state */
1128   if(hnand->State == HAL_NAND_STATE_BUSY)
1129   {
1130      return HAL_BUSY;
1131   }
1132
1133   /* Identify the device address */
1134   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
1135   {
1136     deviceaddress = NAND_DEVICE1;
1137   }
1138   else
1139   {
1140     deviceaddress = NAND_DEVICE2;
1141   }
1142
1143   /* Update the NAND controller state */
1144   hnand->State = HAL_NAND_STATE_BUSY;
1145
1146   /* NAND raw address calculation */
1147   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
1148
1149   /* Column in page address */
1150   columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
1151
1152   /* Spare area(s) read loop */
1153   while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1154   {
1155     /* update the buffer size */
1156     size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
1157
1158     /* Cards with page size <= 512 bytes */
1159     if((hnand->Config.PageSize) <= 512U)
1160     {
1161       /* Send read spare area command sequence */
1162       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
1163
1164       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
1165       {
1166         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
1167         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1168         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1169       }
1170       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1171       {
1172         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
1173         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1174         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1175         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
1176       }
1177     }
1178     else /* (hnand->Config.PageSize) > 512 */
1179     {
1180       /* Send read spare area command sequence */
1181       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
1182
1183       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
1184       {
1185         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
1186         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
1187         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1188         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1189       }
1190       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1191       {
1192         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
1193         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
1194         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1195         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1196         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
1197       }
1198     }
1199
1200     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
1201
1202     if(hnand->Config.ExtraCommandEnable == ENABLE)
1203     {
1204       /* Get tick */
1205       tickstart = HAL_GetTick();
1206
1207       /* Read status until NAND is ready */
1208       while(HAL_NAND_Read_Status(hnand) != NAND_READY)
1209       {
1210         if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
1211         {
1212           return HAL_TIMEOUT;
1213         }
1214       }
1215
1216       /* Go back to read mode */
1217       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
1218     }
1219
1220     /* Get Data into Buffer */
1221     for(; index < size; index++)
1222     {
1223       *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
1224     }
1225
1226     /* Increment read spare areas number */
1227     numSpareAreaRead++;
1228
1229     /* Decrement spare areas to read */
1230     NumSpareAreaToRead--;
1231
1232     /* Increment the NAND address */
1233     nandaddress = (uint32_t)(nandaddress + 1U);
1234   }
1235
1236   /* Update the NAND controller state */
1237   hnand->State = HAL_NAND_STATE_READY;
1238
1239   /* Process unlocked */
1240   __HAL_UNLOCK(hnand);
1241
1242   return HAL_OK;
1243 }
1244
1245 /**
1246   * @brief  Write Spare area(s) to NAND memory (8-bits addressing)
1247   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
1248   *                the configuration information for NAND module.
1249   * @param  pAddress : pointer to NAND address structure
1250   * @param  pBuffer : pointer to source buffer to write
1251   * @param  NumSpareAreaTowrite  : number of spare areas to write to block
1252   * @retval HAL status
1253   */
1254 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
1255 {
1256   __IO uint32_t index = 0U;
1257   uint32_t tickstart = 0U;
1258   uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
1259
1260   /* Process Locked */
1261   __HAL_LOCK(hnand);
1262
1263   /* Check the NAND controller state */
1264   if(hnand->State == HAL_NAND_STATE_BUSY)
1265   {
1266      return HAL_BUSY;
1267   }
1268
1269   /* Identify the device address */
1270   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
1271   {
1272     deviceaddress = NAND_DEVICE1;
1273   }
1274   else
1275   {
1276     deviceaddress = NAND_DEVICE2;
1277   }
1278
1279   /* Update the FSMC_NAND controller state */
1280   hnand->State = HAL_NAND_STATE_BUSY;
1281
1282   /* Page address calculation */
1283   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
1284
1285   /* Column in page address */
1286   columnaddress = COLUMN_ADDRESS(hnand);
1287
1288   /* Spare area(s) write loop */
1289   while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1290   {
1291     /* update the buffer size */
1292     size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
1293
1294     /* Cards with page size <= 512 bytes */
1295     if((hnand->Config.PageSize) <= 512U)
1296     {
1297       /* Send write Spare area command sequence */
1298       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
1299       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
1300
1301       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
1302       {
1303         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
1304         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1305         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1306       }
1307       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1308       {
1309         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
1310         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1311         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1312         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
1313       }
1314     }
1315     else /* (hnand->Config.PageSize) > 512 */
1316     {
1317       /* Send write Spare area command sequence */
1318       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
1319       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
1320
1321       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
1322       {
1323         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
1324         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
1325         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1326         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1327       }
1328       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1329       {
1330         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
1331         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
1332         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1333         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1334         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
1335       }
1336     }
1337
1338     /* Write data to memory */
1339     for(; index < size; index++)
1340     {
1341       *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
1342     }
1343
1344     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
1345
1346     /* Get tick */
1347     tickstart = HAL_GetTick();
1348
1349     /* Read status until NAND is ready */
1350     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
1351     {
1352       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
1353       {
1354         return HAL_TIMEOUT;
1355       }
1356     }
1357
1358     /* Increment written spare areas number */
1359     numSpareAreaWritten++;
1360
1361     /* Decrement spare areas to write */
1362     NumSpareAreaTowrite--;
1363
1364     /* Increment the NAND address */
1365     nandaddress = (uint32_t)(nandaddress + 1U);
1366   }
1367
1368   /* Update the NAND controller state */
1369   hnand->State = HAL_NAND_STATE_READY;
1370
1371   /* Process unlocked */
1372   __HAL_UNLOCK(hnand);
1373
1374   return HAL_OK;
1375 }
1376
1377 /**
1378   * @brief  Write Spare area(s) to NAND memory (16-bits addressing)
1379   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
1380   *                the configuration information for NAND module.
1381   * @param  pAddress : pointer to NAND address structure
1382   * @param  pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned.
1383   * @param  NumSpareAreaTowrite  : number of spare areas to write to block
1384   * @retval HAL status
1385   */
1386 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
1387 {
1388   __IO uint32_t index = 0U;
1389   uint32_t tickstart = 0U;
1390   uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
1391
1392   /* Process Locked */
1393   __HAL_LOCK(hnand);
1394
1395   /* Check the NAND controller state */
1396   if(hnand->State == HAL_NAND_STATE_BUSY)
1397   {
1398      return HAL_BUSY;
1399   }
1400
1401   /* Identify the device address */
1402   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
1403   {
1404     deviceaddress = NAND_DEVICE1;
1405   }
1406   else
1407   {
1408     deviceaddress = NAND_DEVICE2;
1409   }
1410
1411   /* Update the FSMC_NAND controller state */
1412   hnand->State = HAL_NAND_STATE_BUSY;
1413
1414   /* NAND raw address calculation */
1415   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
1416
1417   /* Column in page address */
1418   columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
1419
1420   /* Spare area(s) write loop */
1421   while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1422   {
1423     /* update the buffer size */
1424     size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
1425
1426     /* Cards with page size <= 512 bytes */
1427     if((hnand->Config.PageSize) <= 512U)
1428     {
1429       /* Send write Spare area command sequence */
1430       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
1431       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
1432
1433       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
1434       {
1435         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
1436         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1437         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1438       }
1439       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1440       {
1441         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
1442         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1443         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1444         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
1445       }
1446     }
1447     else /* (hnand->Config.PageSize) > 512 */
1448     {
1449       /* Send write Spare area command sequence */
1450       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
1451       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
1452
1453       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
1454       {
1455         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
1456         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
1457         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1458         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1459       }
1460       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1461       {
1462         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
1463         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
1464         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1465         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1466         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
1467       }
1468     }
1469
1470     /* Write data to memory */
1471     for(; index < size; index++)
1472     {
1473       *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
1474     }
1475
1476     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
1477
1478     /* Read status until NAND is ready */
1479     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
1480     {
1481       /* Get tick */
1482       tickstart = HAL_GetTick();
1483
1484       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
1485       {
1486         return HAL_TIMEOUT;
1487       }
1488     }
1489
1490     /* Increment written spare areas number */
1491     numSpareAreaWritten++;
1492
1493     /* Decrement spare areas to write */
1494     NumSpareAreaTowrite--;
1495
1496     /* Increment the NAND address */
1497     nandaddress = (uint32_t)(nandaddress + 1U);
1498   }
1499
1500   /* Update the NAND controller state */
1501   hnand->State = HAL_NAND_STATE_READY;
1502
1503   /* Process unlocked */
1504   __HAL_UNLOCK(hnand);
1505
1506   return HAL_OK;
1507 }
1508
1509 /**
1510   * @brief  NAND memory Block erase
1511   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
1512   *                the configuration information for NAND module.
1513   * @param  pAddress : pointer to NAND address structure
1514   * @retval HAL status
1515   */
1516 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
1517 {
1518   uint32_t deviceaddress = 0U;
1519   uint32_t tickstart = 0U;
1520
1521   /* Process Locked */
1522   __HAL_LOCK(hnand);
1523
1524   /* Check the NAND controller state */
1525   if(hnand->State == HAL_NAND_STATE_BUSY)
1526   {
1527      return HAL_BUSY;
1528   }
1529
1530   /* Identify the device address */
1531   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
1532   {
1533     deviceaddress = NAND_DEVICE1;
1534   }
1535   else
1536   {
1537     deviceaddress = NAND_DEVICE2;
1538   }
1539
1540   /* Update the NAND controller state */
1541   hnand->State = HAL_NAND_STATE_BUSY;
1542
1543   /* Send Erase block command sequence */
1544   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
1545
1546   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
1547   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
1548   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
1549
1550   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
1551
1552   /* Update the NAND controller state */
1553   hnand->State = HAL_NAND_STATE_READY;
1554
1555   /* Get tick */
1556   tickstart = HAL_GetTick();
1557
1558   /* Read status until NAND is ready */
1559   while(HAL_NAND_Read_Status(hnand) != NAND_READY)
1560   {
1561     if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
1562     {
1563       /* Process unlocked */
1564       __HAL_UNLOCK(hnand);
1565
1566       return HAL_TIMEOUT;
1567     }
1568   }
1569
1570   /* Process unlocked */
1571   __HAL_UNLOCK(hnand);
1572
1573   return HAL_OK;
1574 }
1575
1576 /**
1577   * @brief  NAND memory read status
1578   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
1579   *                the configuration information for NAND module.
1580   * @retval NAND status
1581   */
1582 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
1583 {
1584   uint32_t data = 0U;
1585   uint32_t deviceaddress = 0U;
1586
1587   /* Identify the device address */
1588   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
1589   {
1590     deviceaddress = NAND_DEVICE1;
1591   }
1592   else
1593   {
1594     deviceaddress = NAND_DEVICE2;
1595   }
1596
1597   /* Send Read status operation command */
1598   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
1599
1600   /* Read status register data */
1601   data = *(__IO uint8_t *)deviceaddress;
1602
1603   /* Return the status */
1604   if((data & NAND_ERROR) == NAND_ERROR)
1605   {
1606     return NAND_ERROR;
1607   }
1608   else if((data & NAND_READY) == NAND_READY)
1609   {
1610     return NAND_READY;
1611   }
1612
1613   return NAND_BUSY;
1614 }
1615
1616 /**
1617   * @brief  Increment the NAND memory address
1618   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
1619   *                the configuration information for NAND module.
1620   * @param pAddress: pointer to NAND address structure
1621   * @retval The new status of the increment address operation. It can be:
1622   *           - NAND_VALID_ADDRESS: When the new address is valid address
1623   *           - NAND_INVALID_ADDRESS: When the new address is invalid address
1624   */
1625 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
1626 {
1627   uint32_t status = NAND_VALID_ADDRESS;
1628
1629   /* Increment page address */
1630   pAddress->Page++;
1631
1632   /* Check NAND address is valid */
1633   if(pAddress->Page == hnand->Config.BlockSize)
1634   {
1635     pAddress->Page = 0U;
1636     pAddress->Block++;
1637
1638     if(pAddress->Block == hnand->Config.PlaneSize)
1639     {
1640       pAddress->Block = 0U;
1641       pAddress->Plane++;
1642
1643       if(pAddress->Plane == (hnand->Config.PlaneNbr))
1644       {
1645         status = NAND_INVALID_ADDRESS;
1646       }
1647     }
1648   }
1649
1650   return (status);
1651 }
1652 /**
1653   * @}
1654   */
1655
1656 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
1657  *  @brief   management functions
1658  *
1659 @verbatim
1660   ==============================================================================
1661                          ##### NAND Control functions #####
1662   ==============================================================================
1663   [..]
1664     This subsection provides a set of functions allowing to control dynamically
1665     the NAND interface.
1666
1667 @endverbatim
1668   * @{
1669   */
1670
1671
1672 /**
1673   * @brief  Enables dynamically NAND ECC feature.
1674   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
1675   *                the configuration information for NAND module.
1676   * @retval HAL status
1677   */
1678 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
1679 {
1680   /* Check the NAND controller state */
1681   if(hnand->State == HAL_NAND_STATE_BUSY)
1682   {
1683      return HAL_BUSY;
1684   }
1685
1686   /* Update the NAND state */
1687   hnand->State = HAL_NAND_STATE_BUSY;
1688
1689   /* Enable ECC feature */
1690   FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
1691
1692   /* Update the NAND state */
1693   hnand->State = HAL_NAND_STATE_READY;
1694
1695   return HAL_OK;
1696 }
1697
1698 /**
1699   * @brief  Disables dynamically FSMC_NAND ECC feature.
1700   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
1701   *                the configuration information for NAND module.
1702   * @retval HAL status
1703   */
1704 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
1705 {
1706   /* Check the NAND controller state */
1707   if(hnand->State == HAL_NAND_STATE_BUSY)
1708   {
1709      return HAL_BUSY;
1710   }
1711
1712   /* Update the NAND state */
1713   hnand->State = HAL_NAND_STATE_BUSY;
1714
1715   /* Disable ECC feature */
1716   FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
1717
1718   /* Update the NAND state */
1719   hnand->State = HAL_NAND_STATE_READY;
1720
1721   return HAL_OK;
1722 }
1723
1724 /**
1725   * @brief  Disables dynamically NAND ECC feature.
1726   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
1727   *                the configuration information for NAND module.
1728   * @param  ECCval: pointer to ECC value
1729   * @param  Timeout: maximum timeout to wait
1730   * @retval HAL status
1731   */
1732 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
1733 {
1734   HAL_StatusTypeDef status = HAL_OK;
1735
1736   /* Check the NAND controller state */
1737   if(hnand->State == HAL_NAND_STATE_BUSY)
1738   {
1739      return HAL_BUSY;
1740   }
1741
1742   /* Update the NAND state */
1743   hnand->State = HAL_NAND_STATE_BUSY;
1744
1745   /* Get NAND ECC value */
1746   status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
1747
1748   /* Update the NAND state */
1749   hnand->State = HAL_NAND_STATE_READY;
1750
1751   return status;
1752 }
1753
1754 /**
1755   * @}
1756   */
1757
1758
1759 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
1760  *  @brief   Peripheral State functions
1761  *
1762 @verbatim
1763   ==============================================================================
1764                          ##### NAND State functions #####
1765   ==============================================================================
1766   [..]
1767     This subsection permits to get in run-time the status of the NAND controller
1768     and the data flow.
1769
1770 @endverbatim
1771   * @{
1772   */
1773
1774 /**
1775   * @brief  return the NAND state
1776   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
1777   *                the configuration information for NAND module.
1778   * @retval HAL state
1779   */
1780 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
1781 {
1782   return hnand->State;
1783 }
1784
1785 /**
1786   * @}
1787   */
1788
1789 /**
1790   * @}
1791   */
1792
1793 /**
1794   * @}
1795   */
1796
1797 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
1798 #endif /* HAL_NAND_MODULE_ENABLED  */
1799
1800 /**
1801   * @}
1802   */
1803
1804 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/