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[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_HAL_Driver / Inc / stm32f4xx_hal_dsi.h
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1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_dsi.h
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 14-April-2017
7 * @brief Header file of DSI HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_DSI_H
40 #define __STM32F4xx_HAL_DSI_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 #if defined(STM32F469xx) || defined(STM32F479xx)
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32f4xx_hal_def.h"
49
50 /** @addtogroup STM32F4xx_HAL_Driver
51 * @{
52 */
53
54 /** @defgroup DSI DSI
55 * @brief DSI HAL module driver
56 * @{
57 */
58
59 /* Exported types ------------------------------------------------------------*/
60 /**
61 * @brief DSI Init Structure definition
62 */
63 typedef struct
64 {
65 uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control
66 This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
67
68 uint32_t TXEscapeCkdiv; /*!< TX Escape clock division
69 The values 0 and 1 stop the TX_ESC clock generation */
70
71 uint32_t NumberOfLanes; /*!< Number of lanes
72 This parameter can be any value of @ref DSI_Number_Of_Lanes */
73
74 }DSI_InitTypeDef;
75
76 /**
77 * @brief DSI PLL Clock structure definition
78 */
79 typedef struct
80 {
81 uint32_t PLLNDIV; /*!< PLL Loop Division Factor
82 This parameter must be a value between 10 and 125 */
83
84 uint32_t PLLIDF; /*!< PLL Input Division Factor
85 This parameter can be any value of @ref DSI_PLL_IDF */
86
87 uint32_t PLLODF; /*!< PLL Output Division Factor
88 This parameter can be any value of @ref DSI_PLL_ODF */
89
90 }DSI_PLLInitTypeDef;
91
92 /**
93 * @brief DSI Video mode configuration
94 */
95 typedef struct
96 {
97 uint32_t VirtualChannelID; /*!< Virtual channel ID */
98
99 uint32_t ColorCoding; /*!< Color coding for LTDC interface
100 This parameter can be any value of @ref DSI_Color_Coding */
101
102 uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using
103 18-bit configuration).
104 This parameter can be any value of @ref DSI_LooselyPacked */
105
106 uint32_t Mode; /*!< Video mode type
107 This parameter can be any value of @ref DSI_Video_Mode_Type */
108
109 uint32_t PacketSize; /*!< Video packet size */
110
111 uint32_t NumberOfChunks; /*!< Number of chunks */
112
113 uint32_t NullPacketSize; /*!< Null packet size */
114
115 uint32_t HSPolarity; /*!< HSYNC pin polarity
116 This parameter can be any value of @ref DSI_HSYNC_Polarity */
117
118 uint32_t VSPolarity; /*!< VSYNC pin polarity
119 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
120
121 uint32_t DEPolarity; /*!< Data Enable pin polarity
122 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
123
124 uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */
125
126 uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */
127
128 uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */
129
130 uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */
131
132 uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */
133
134 uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */
135
136 uint32_t VerticalActive; /*!< Vertical active duration */
137
138 uint32_t LPCommandEnable; /*!< Low-power command enable
139 This parameter can be any value of @ref DSI_LP_Command */
140
141 uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
142 can fit in a line during VSA, VBP and VFP regions */
143
144 uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
145 can fit in a line during VACT region */
146
147 uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable
148 This parameter can be any value of @ref DSI_LP_HFP */
149
150 uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable
151 This parameter can be any value of @ref DSI_LP_HBP */
152
153 uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable
154 This parameter can be any value of @ref DSI_LP_VACT */
155
156 uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable
157 This parameter can be any value of @ref DSI_LP_VFP */
158
159 uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable
160 This parameter can be any value of @ref DSI_LP_VBP */
161
162 uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable
163 This parameter can be any value of @ref DSI_LP_VSYNC */
164
165 uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable
166 This parameter can be any value of @ref DSI_FBTA_acknowledge */
167
168 }DSI_VidCfgTypeDef;
169
170 /**
171 * @brief DSI Adapted command mode configuration
172 */
173 typedef struct
174 {
175 uint32_t VirtualChannelID; /*!< Virtual channel ID */
176
177 uint32_t ColorCoding; /*!< Color coding for LTDC interface
178 This parameter can be any value of @ref DSI_Color_Coding */
179
180 uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
181 pixels. This parameter can be any value between 0x00 and 0xFFFFU */
182
183 uint32_t TearingEffectSource; /*!< Tearing effect source
184 This parameter can be any value of @ref DSI_TearingEffectSource */
185
186 uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity
187 This parameter can be any value of @ref DSI_TearingEffectPolarity */
188
189 uint32_t HSPolarity; /*!< HSYNC pin polarity
190 This parameter can be any value of @ref DSI_HSYNC_Polarity */
191
192 uint32_t VSPolarity; /*!< VSYNC pin polarity
193 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
194
195 uint32_t DEPolarity; /*!< Data Enable pin polarity
196 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
197
198 uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted
199 This parameter can be any value of @ref DSI_Vsync_Polarity */
200
201 uint32_t AutomaticRefresh; /*!< Automatic refresh mode
202 This parameter can be any value of @ref DSI_AutomaticRefresh */
203
204 uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable
205 This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
206
207 }DSI_CmdCfgTypeDef;
208
209 /**
210 * @brief DSI command transmission mode configuration
211 */
212 typedef struct
213 {
214 uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission
215 This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */
216
217 uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission
218 This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
219
220 uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission
221 This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
222
223 uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission
224 This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */
225
226 uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission
227 This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */
228
229 uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission
230 This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */
231
232 uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission
233 This parameter can be any value of @ref DSI_LP_LPGenLongWrite */
234
235 uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission
236 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */
237
238 uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission
239 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
240
241 uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission
242 This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */
243
244 uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission
245 This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */
246
247 uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission
248 This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */
249
250 uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable
251 This parameter can be any value of @ref DSI_AcknowledgeRequest */
252
253 }DSI_LPCmdTypeDef;
254
255 /**
256 * @brief DSI PHY Timings definition
257 */
258 typedef struct
259 {
260 uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
261 to low-power transmission */
262
263 uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power
264 to high-speed transmission */
265
266 uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
267 to low-power transmission */
268
269 uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power
270 to high-speed transmission */
271
272 uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */
273
274 uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the
275 Stop state */
276
277 }DSI_PHY_TimerTypeDef;
278
279 /**
280 * @brief DSI HOST Timeouts definition
281 */
282 typedef struct
283 {
284 uint32_t TimeoutCkdiv; /*!< Time-out clock division */
285
286 uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */
287
288 uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */
289
290 uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */
291
292 uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */
293
294 uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */
295
296 uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode
297 This parameter can be any value of @ref DSI_HS_PrespMode */
298
299 uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */
300
301 uint32_t BTATimeout; /*!< BTA time-out */
302
303 }DSI_HOST_TimeoutTypeDef;
304
305 /**
306 * @brief DSI States Structure definition
307 */
308 typedef enum
309 {
310 HAL_DSI_STATE_RESET = 0x00U,
311 HAL_DSI_STATE_READY = 0x01U,
312 HAL_DSI_STATE_ERROR = 0x02U,
313 HAL_DSI_STATE_BUSY = 0x03U,
314 HAL_DSI_STATE_TIMEOUT = 0x04U
315 }HAL_DSI_StateTypeDef;
316
317 /**
318 * @brief DSI Handle Structure definition
319 */
320 typedef struct
321 {
322 DSI_TypeDef *Instance; /*!< Register base address */
323 DSI_InitTypeDef Init; /*!< DSI required parameters */
324 HAL_LockTypeDef Lock; /*!< DSI peripheral status */
325 __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */
326 __IO uint32_t ErrorCode; /*!< DSI Error code */
327 uint32_t ErrorMsk; /*!< DSI Error monitoring mask */
328 }DSI_HandleTypeDef;
329
330 /* Exported constants --------------------------------------------------------*/
331 /** @defgroup DSI_DCS_Command DSI DCS Command
332 * @{
333 */
334 #define DSI_ENTER_IDLE_MODE 0x39U
335 #define DSI_ENTER_INVERT_MODE 0x21U
336 #define DSI_ENTER_NORMAL_MODE 0x13U
337 #define DSI_ENTER_PARTIAL_MODE 0x12U
338 #define DSI_ENTER_SLEEP_MODE 0x10U
339 #define DSI_EXIT_IDLE_MODE 0x38U
340 #define DSI_EXIT_INVERT_MODE 0x20U
341 #define DSI_EXIT_SLEEP_MODE 0x11U
342 #define DSI_GET_3D_CONTROL 0x3FU
343 #define DSI_GET_ADDRESS_MODE 0x0BU
344 #define DSI_GET_BLUE_CHANNEL 0x08U
345 #define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
346 #define DSI_GET_DISPLAY_MODE 0x0DU
347 #define DSI_GET_GREEN_CHANNEL 0x07U
348 #define DSI_GET_PIXEL_FORMAT 0x0CU
349 #define DSI_GET_POWER_MODE 0x0AU
350 #define DSI_GET_RED_CHANNEL 0x06U
351 #define DSI_GET_SCANLINE 0x45U
352 #define DSI_GET_SIGNAL_MODE 0x0EU
353 #define DSI_NOP 0x00U
354 #define DSI_READ_DDB_CONTINUE 0xA8U
355 #define DSI_READ_DDB_START 0xA1U
356 #define DSI_READ_MEMORY_CONTINUE 0x3EU
357 #define DSI_READ_MEMORY_START 0x2EU
358 #define DSI_SET_3D_CONTROL 0x3DU
359 #define DSI_SET_ADDRESS_MODE 0x36U
360 #define DSI_SET_COLUMN_ADDRESS 0x2AU
361 #define DSI_SET_DISPLAY_OFF 0x28U
362 #define DSI_SET_DISPLAY_ON 0x29U
363 #define DSI_SET_GAMMA_CURVE 0x26U
364 #define DSI_SET_PAGE_ADDRESS 0x2BU
365 #define DSI_SET_PARTIAL_COLUMNS 0x31U
366 #define DSI_SET_PARTIAL_ROWS 0x30U
367 #define DSI_SET_PIXEL_FORMAT 0x3AU
368 #define DSI_SET_SCROLL_AREA 0x33U
369 #define DSI_SET_SCROLL_START 0x37U
370 #define DSI_SET_TEAR_OFF 0x34U
371 #define DSI_SET_TEAR_ON 0x35U
372 #define DSI_SET_TEAR_SCANLINE 0x44U
373 #define DSI_SET_VSYNC_TIMING 0x40U
374 #define DSI_SOFT_RESET 0x01U
375 #define DSI_WRITE_LUT 0x2DU
376 #define DSI_WRITE_MEMORY_CONTINUE 0x3CU
377 #define DSI_WRITE_MEMORY_START 0x2CU
378 /**
379 * @}
380 */
381
382 /** @defgroup DSI_Video_Mode_Type DSI Video Mode Type
383 * @{
384 */
385 #define DSI_VID_MODE_NB_PULSES 0U
386 #define DSI_VID_MODE_NB_EVENTS 1U
387 #define DSI_VID_MODE_BURST 2U
388 /**
389 * @}
390 */
391
392 /** @defgroup DSI_Color_Mode DSI Color Mode
393 * @{
394 */
395 #define DSI_COLOR_MODE_FULL 0x00000000U
396 #define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
397 /**
398 * @}
399 */
400
401 /** @defgroup DSI_ShutDown DSI ShutDown
402 * @{
403 */
404 #define DSI_DISPLAY_ON 0x00000000U
405 #define DSI_DISPLAY_OFF DSI_WCR_SHTDN
406 /**
407 * @}
408 */
409
410 /** @defgroup DSI_LP_Command DSI LP Command
411 * @{
412 */
413 #define DSI_LP_COMMAND_DISABLE 0x00000000U
414 #define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
415 /**
416 * @}
417 */
418
419 /** @defgroup DSI_LP_HFP DSI LP HFP
420 * @{
421 */
422 #define DSI_LP_HFP_DISABLE 0x00000000U
423 #define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
424 /**
425 * @}
426 */
427
428 /** @defgroup DSI_LP_HBP DSI LP HBP
429 * @{
430 */
431 #define DSI_LP_HBP_DISABLE 0x00000000U
432 #define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
433 /**
434 * @}
435 */
436
437 /** @defgroup DSI_LP_VACT DSI LP VACT
438 * @{
439 */
440 #define DSI_LP_VACT_DISABLE 0x00000000U
441 #define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
442 /**
443 * @}
444 */
445
446 /** @defgroup DSI_LP_VFP DSI LP VFP
447 * @{
448 */
449 #define DSI_LP_VFP_DISABLE 0x00000000U
450 #define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
451 /**
452 * @}
453 */
454
455 /** @defgroup DSI_LP_VBP DSI LP VBP
456 * @{
457 */
458 #define DSI_LP_VBP_DISABLE 0x00000000U
459 #define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
460 /**
461 * @}
462 */
463
464 /** @defgroup DSI_LP_VSYNC DSI LP VSYNC
465 * @{
466 */
467 #define DSI_LP_VSYNC_DISABLE 0x00000000U
468 #define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
469 /**
470 * @}
471 */
472
473 /** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge
474 * @{
475 */
476 #define DSI_FBTAA_DISABLE 0x00000000U
477 #define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
478 /**
479 * @}
480 */
481
482 /** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source
483 * @{
484 */
485 #define DSI_TE_DSILINK 0x00000000U
486 #define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
487 /**
488 * @}
489 */
490
491 /** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity
492 * @{
493 */
494 #define DSI_TE_RISING_EDGE 0x00000000U
495 #define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
496 /**
497 * @}
498 */
499
500 /** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity
501 * @{
502 */
503 #define DSI_VSYNC_FALLING 0x00000000U
504 #define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
505 /**
506 * @}
507 */
508
509 /** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh
510 * @{
511 */
512 #define DSI_AR_DISABLE 0x00000000U
513 #define DSI_AR_ENABLE DSI_WCFGR_AR
514 /**
515 * @}
516 */
517
518 /** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request
519 * @{
520 */
521 #define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U
522 #define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
523 /**
524 * @}
525 */
526
527 /** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request
528 * @{
529 */
530 #define DSI_ACKNOWLEDGE_DISABLE 0x00000000U
531 #define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
532 /**
533 * @}
534 */
535
536 /** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP
537 * @{
538 */
539 #define DSI_LP_GSW0P_DISABLE 0x00000000U
540 #define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
541 /**
542 * @}
543 */
544
545 /** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP
546 * @{
547 */
548 #define DSI_LP_GSW1P_DISABLE 0x00000000U
549 #define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
550 /**
551 * @}
552 */
553
554 /** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP
555 * @{
556 */
557 #define DSI_LP_GSW2P_DISABLE 0x00000000U
558 #define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
559 /**
560 * @}
561 */
562
563 /** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP
564 * @{
565 */
566 #define DSI_LP_GSR0P_DISABLE 0x00000000U
567 #define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
568 /**
569 * @}
570 */
571
572 /** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP
573 * @{
574 */
575 #define DSI_LP_GSR1P_DISABLE 0x00000000U
576 #define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
577 /**
578 * @}
579 */
580
581 /** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP
582 * @{
583 */
584 #define DSI_LP_GSR2P_DISABLE 0x00000000U
585 #define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
586 /**
587 * @}
588 */
589
590 /** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite
591 * @{
592 */
593 #define DSI_LP_GLW_DISABLE 0x00000000U
594 #define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
595 /**
596 * @}
597 */
598
599 /** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP
600 * @{
601 */
602 #define DSI_LP_DSW0P_DISABLE 0x00000000U
603 #define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
604 /**
605 * @}
606 */
607
608 /** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP
609 * @{
610 */
611 #define DSI_LP_DSW1P_DISABLE 0x00000000U
612 #define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
613 /**
614 * @}
615 */
616
617 /** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP
618 * @{
619 */
620 #define DSI_LP_DSR0P_DISABLE 0x00000000U
621 #define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
622 /**
623 * @}
624 */
625
626 /** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write
627 * @{
628 */
629 #define DSI_LP_DLW_DISABLE 0x00000000U
630 #define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
631 /**
632 * @}
633 */
634
635 /** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet
636 * @{
637 */
638 #define DSI_LP_MRDP_DISABLE 0x00000000U
639 #define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
640 /**
641 * @}
642 */
643
644 /** @defgroup DSI_HS_PrespMode DSI HS Presp Mode
645 * @{
646 */
647 #define DSI_HS_PM_DISABLE 0x00000000U
648 #define DSI_HS_PM_ENABLE DSI_TCCR3_PM
649 /**
650 * @}
651 */
652
653
654 /** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control
655 * @{
656 */
657 #define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U
658 #define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
659 /**
660 * @}
661 */
662
663 /** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes
664 * @{
665 */
666 #define DSI_ONE_DATA_LANE 0U
667 #define DSI_TWO_DATA_LANES 1U
668 /**
669 * @}
670 */
671
672 /** @defgroup DSI_FlowControl DSI Flow Control
673 * @{
674 */
675 #define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
676 #define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
677 #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
678 #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
679 #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
680 #define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
681 DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
682 DSI_FLOW_CONTROL_EOTP_TX)
683 /**
684 * @}
685 */
686
687 /** @defgroup DSI_Color_Coding DSI Color Coding
688 * @{
689 */
690 #define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */
691 #define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */
692 #define DSI_RGB888 0x00000005U
693 /**
694 * @}
695 */
696
697 /** @defgroup DSI_LooselyPacked DSI Loosely Packed
698 * @{
699 */
700 #define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
701 #define DSI_LOOSELY_PACKED_DISABLE 0x00000000U
702 /**
703 * @}
704 */
705
706 /** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity
707 * @{
708 */
709 #define DSI_HSYNC_ACTIVE_HIGH 0x00000000U
710 #define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
711 /**
712 * @}
713 */
714
715 /** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity
716 * @{
717 */
718 #define DSI_VSYNC_ACTIVE_HIGH 0x00000000U
719 #define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
720 /**
721 * @}
722 */
723
724 /** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity
725 * @{
726 */
727 #define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U
728 #define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
729 /**
730 * @}
731 */
732
733 /** @defgroup DSI_PLL_IDF DSI PLL IDF
734 * @{
735 */
736 #define DSI_PLL_IN_DIV1 0x00000001U
737 #define DSI_PLL_IN_DIV2 0x00000002U
738 #define DSI_PLL_IN_DIV3 0x00000003U
739 #define DSI_PLL_IN_DIV4 0x00000004U
740 #define DSI_PLL_IN_DIV5 0x00000005U
741 #define DSI_PLL_IN_DIV6 0x00000006U
742 #define DSI_PLL_IN_DIV7 0x00000007U
743 /**
744 * @}
745 */
746
747 /** @defgroup DSI_PLL_ODF DSI PLL ODF
748 * @{
749 */
750 #define DSI_PLL_OUT_DIV1 0x00000000U
751 #define DSI_PLL_OUT_DIV2 0x00000001U
752 #define DSI_PLL_OUT_DIV4 0x00000002U
753 #define DSI_PLL_OUT_DIV8 0x00000003U
754 /**
755 * @}
756 */
757
758 /** @defgroup DSI_Flags DSI Flags
759 * @{
760 */
761 #define DSI_FLAG_TE DSI_WISR_TEIF
762 #define DSI_FLAG_ER DSI_WISR_ERIF
763 #define DSI_FLAG_BUSY DSI_WISR_BUSY
764 #define DSI_FLAG_PLLLS DSI_WISR_PLLLS
765 #define DSI_FLAG_PLLL DSI_WISR_PLLLIF
766 #define DSI_FLAG_PLLU DSI_WISR_PLLUIF
767 #define DSI_FLAG_RRS DSI_WISR_RRS
768 #define DSI_FLAG_RR DSI_WISR_RRIF
769 /**
770 * @}
771 */
772
773 /** @defgroup DSI_Interrupts DSI Interrupts
774 * @{
775 */
776 #define DSI_IT_TE DSI_WIER_TEIE
777 #define DSI_IT_ER DSI_WIER_ERIE
778 #define DSI_IT_PLLL DSI_WIER_PLLLIE
779 #define DSI_IT_PLLU DSI_WIER_PLLUIE
780 #define DSI_IT_RR DSI_WIER_RRIE
781 /**
782 * @}
783 */
784
785 /** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type
786 * @{
787 */
788 #define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */
789 #define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */
790 #define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */
791 #define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */
792 #define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */
793 /**
794 * @}
795 */
796
797 /** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type
798 * @{
799 */
800 #define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */
801 #define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */
802 /**
803 * @}
804 */
805
806 /** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type
807 * @{
808 */
809 #define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */
810 #define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */
811 #define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */
812 #define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */
813 /**
814 * @}
815 */
816
817 /** @defgroup DSI_Error_Data_Type DSI Error Data Type
818 * @{
819 */
820 #define HAL_DSI_ERROR_NONE 0U
821 #define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */
822 #define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */
823 #define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */
824 #define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */
825 #define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */
826 #define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */
827 #define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */
828 #define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */
829 #define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */
830 #define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */
831 /**
832 * @}
833 */
834
835 /** @defgroup DSI_Lane_Group DSI Lane Group
836 * @{
837 */
838 #define DSI_CLOCK_LANE 0x00000000U
839 #define DSI_DATA_LANES 0x00000001U
840 /**
841 * @}
842 */
843
844 /** @defgroup DSI_Communication_Delay DSI Communication Delay
845 * @{
846 */
847 #define DSI_SLEW_RATE_HSTX 0x00000000U
848 #define DSI_SLEW_RATE_LPTX 0x00000001U
849 #define DSI_HS_DELAY 0x00000002U
850 /**
851 * @}
852 */
853
854 /** @defgroup DSI_CustomLane DSI CustomLane
855 * @{
856 */
857 #define DSI_SWAP_LANE_PINS 0x00000000U
858 #define DSI_INVERT_HS_SIGNAL 0x00000001U
859 /**
860 * @}
861 */
862
863 /** @defgroup DSI_Lane_Select DSI Lane Select
864 * @{
865 */
866 #define DSI_CLOCK_LANE 0x00000000U
867 #define DSI_DATA_LANE0 0x00000001U
868 #define DSI_DATA_LANE1 0x00000002U
869 /**
870 * @}
871 */
872
873 /** @defgroup DSI_PHY_Timing DSI PHY Timing
874 * @{
875 */
876 #define DSI_TCLK_POST 0x00000000U
877 #define DSI_TLPX_CLK 0x00000001U
878 #define DSI_THS_EXIT 0x00000002U
879 #define DSI_TLPX_DATA 0x00000003U
880 #define DSI_THS_ZERO 0x00000004U
881 #define DSI_THS_TRAIL 0x00000005U
882 #define DSI_THS_PREPARE 0x00000006U
883 #define DSI_TCLK_ZERO 0x00000007U
884 #define DSI_TCLK_PREPARE 0x00000008U
885 /**
886 * @}
887 */
888
889 /* Exported macros -----------------------------------------------------------*/
890 /**
891 * @brief Enables the DSI host.
892 * @param __HANDLE__: DSI handle
893 * @retval None.
894 */
895 #define __HAL_DSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DSI_CR_EN)
896
897 /**
898 * @brief Disables the DSI host.
899 * @param __HANDLE__: DSI handle
900 * @retval None.
901 */
902 #define __HAL_DSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DSI_CR_EN)
903
904 /**
905 * @brief Enables the DSI wrapper.
906 * @param __HANDLE__: DSI handle
907 * @retval None.
908 */
909 #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR |= DSI_WCR_DSIEN)
910
911 /**
912 * @brief Disable the DSI wrapper.
913 * @param __HANDLE__: DSI handle
914 * @retval None.
915 */
916 #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR &= ~DSI_WCR_DSIEN)
917
918 /**
919 * @brief Enables the DSI PLL.
920 * @param __HANDLE__: DSI handle
921 * @retval None.
922 */
923 #define __HAL_DSI_PLL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_PLLEN)
924
925 /**
926 * @brief Disables the DSI PLL.
927 * @param __HANDLE__: DSI handle
928 * @retval None.
929 */
930 #define __HAL_DSI_PLL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_PLLEN)
931
932 /**
933 * @brief Enables the DSI regulator.
934 * @param __HANDLE__: DSI handle
935 * @retval None.
936 */
937 #define __HAL_DSI_REG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_REGEN)
938
939 /**
940 * @brief Disables the DSI regulator.
941 * @param __HANDLE__: DSI handle
942 * @retval None.
943 */
944 #define __HAL_DSI_REG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_REGEN)
945
946 /**
947 * @brief Get the DSI pending flags.
948 * @param __HANDLE__: DSI handle.
949 * @param __FLAG__: Get the specified flag.
950 * This parameter can be any combination of the following values:
951 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
952 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
953 * @arg DSI_FLAG_BUSY : Busy Flag
954 * @arg DSI_FLAG_PLLLS: PLL Lock Status
955 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
956 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
957 * @arg DSI_FLAG_RRS : Regulator Ready Flag
958 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
959 * @retval The state of FLAG (SET or RESET).
960 */
961 #define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
962
963 /**
964 * @brief Clears the DSI pending flags.
965 * @param __HANDLE__: DSI handle.
966 * @param __FLAG__: specifies the flag to clear.
967 * This parameter can be any combination of the following values:
968 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
969 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
970 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
971 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
972 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
973 * @retval None
974 */
975 #define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
976
977 /**
978 * @brief Enables the specified DSI interrupts.
979 * @param __HANDLE__: DSI handle.
980 * @param __INTERRUPT__: specifies the DSI interrupt sources to be enabled.
981 * This parameter can be any combination of the following values:
982 * @arg DSI_IT_TE : Tearing Effect Interrupt
983 * @arg DSI_IT_ER : End of Refresh Interrupt
984 * @arg DSI_IT_PLLL: PLL Lock Interrupt
985 * @arg DSI_IT_PLLU: PLL Unlock Interrupt
986 * @arg DSI_IT_RR : Regulator Ready Interrupt
987 * @retval None
988 */
989 #define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__))
990
991 /**
992 * @brief Disables the specified DSI interrupts.
993 * @param __HANDLE__: DSI handle
994 * @param __INTERRUPT__: specifies the DSI interrupt sources to be disabled.
995 * This parameter can be any combination of the following values:
996 * @arg DSI_IT_TE : Tearing Effect Interrupt
997 * @arg DSI_IT_ER : End of Refresh Interrupt
998 * @arg DSI_IT_PLLL: PLL Lock Interrupt
999 * @arg DSI_IT_PLLU: PLL Unlock Interrupt
1000 * @arg DSI_IT_RR : Regulator Ready Interrupt
1001 * @retval None
1002 */
1003 #define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
1004
1005 /**
1006 * @brief Checks whether the specified DSI interrupt has occurred or not.
1007 * @param __HANDLE__: DSI handle
1008 * @param __INTERRUPT__: specifies the DSI interrupt source to check.
1009 * This parameter can be one of the following values:
1010 * @arg DSI_IT_TE : Tearing Effect Interrupt
1011 * @arg DSI_IT_ER : End of Refresh Interrupt
1012 * @arg DSI_IT_PLLL: PLL Lock Interrupt
1013 * @arg DSI_IT_PLLU: PLL Unlock Interrupt
1014 * @arg DSI_IT_RR : Regulator Ready Interrupt
1015 * @retval The state of INTERRUPT (SET or RESET).
1016 */
1017 #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
1018
1019 /* Exported functions --------------------------------------------------------*/
1020 /** @defgroup DSI_Exported_Functions DSI Exported Functions
1021 * @{
1022 */
1023 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
1024 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
1025 void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
1026 void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
1027
1028 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
1029 void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
1030 void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
1031 void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
1032
1033 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
1034 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
1035 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
1036 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd);
1037 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
1038 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers);
1039 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts);
1040 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
1041 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
1042 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
1043 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
1044 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
1045 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
1046 uint32_t ChannelID,
1047 uint32_t Mode,
1048 uint32_t Param1,
1049 uint32_t Param2);
1050 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
1051 uint32_t ChannelID,
1052 uint32_t Mode,
1053 uint32_t NbParams,
1054 uint32_t Param1,
1055 uint8_t* ParametersTable);
1056 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
1057 uint32_t ChannelNbr,
1058 uint8_t* Array,
1059 uint32_t Size,
1060 uint32_t Mode,
1061 uint32_t DCSCmd,
1062 uint8_t* ParametersTable);
1063 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
1064 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
1065 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
1066 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
1067
1068 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
1069 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
1070
1071 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value);
1072 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
1073 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
1074 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State);
1075 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value);
1076 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
1077 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
1078 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
1079 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
1080 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
1081
1082 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
1083 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
1084 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
1085 /**
1086 * @}
1087 */
1088
1089 /* Private types -------------------------------------------------------------*/
1090 /** @defgroup DSI_Private_Types DSI Private Types
1091 * @{
1092 */
1093
1094 /**
1095 * @}
1096 */
1097
1098 /* Private defines -----------------------------------------------------------*/
1099 /** @defgroup DSI_Private_Defines DSI Private Defines
1100 * @{
1101 */
1102
1103 /**
1104 * @}
1105 */
1106
1107 /* Private variables ---------------------------------------------------------*/
1108 /** @defgroup DSI_Private_Variables DSI Private Variables
1109 * @{
1110 */
1111
1112 /**
1113 * @}
1114 */
1115
1116 /* Private constants ---------------------------------------------------------*/
1117 /** @defgroup DSI_Private_Constants DSI Private Constants
1118 * @{
1119 */
1120 #define DSI_MAX_RETURN_PKT_SIZE ((uint32_t)0x00000037U) /*!< Maximum return packet configuration */
1121 /**
1122 * @}
1123 */
1124
1125 /* Private macros ------------------------------------------------------------*/
1126 /** @defgroup DSI_Private_Macros DSI Private Macros
1127 * @{
1128 */
1129 #define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U))
1130 #define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \
1131 ((IDF) == DSI_PLL_IN_DIV2) || \
1132 ((IDF) == DSI_PLL_IN_DIV3) || \
1133 ((IDF) == DSI_PLL_IN_DIV4) || \
1134 ((IDF) == DSI_PLL_IN_DIV5) || \
1135 ((IDF) == DSI_PLL_IN_DIV6) || \
1136 ((IDF) == DSI_PLL_IN_DIV7))
1137 #define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \
1138 ((ODF) == DSI_PLL_OUT_DIV2) || \
1139 ((ODF) == DSI_PLL_OUT_DIV4) || \
1140 ((ODF) == DSI_PLL_OUT_DIV8))
1141 #define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
1142 #define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
1143 #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
1144 #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U)
1145 #define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
1146 #define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
1147 #define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
1148 #define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
1149 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
1150 ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
1151 ((VideoModeType) == DSI_VID_MODE_BURST))
1152 #define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
1153 #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
1154 #define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
1155 #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
1156 #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
1157 #define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
1158 #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
1159 #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
1160 #define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
1161 #define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
1162 #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
1163 #define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
1164 #define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
1165 #define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
1166 #define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
1167 #define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
1168 #define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
1169 #define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
1170 #define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
1171 #define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
1172 #define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
1173 #define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
1174 #define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
1175 #define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
1176 #define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
1177 #define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
1178 #define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
1179 #define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
1180 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
1181 ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
1182 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
1183 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \
1184 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
1185 #define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \
1186 ((MODE) == DSI_GEN_LONG_PKT_WRITE))
1187 #define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \
1188 ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
1189 ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
1190 ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
1191 #define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
1192 #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
1193 #define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
1194 #define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
1195 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \
1196 ((Timing) == DSI_TLPX_CLK ) || \
1197 ((Timing) == DSI_THS_EXIT ) || \
1198 ((Timing) == DSI_TLPX_DATA ) || \
1199 ((Timing) == DSI_THS_ZERO ) || \
1200 ((Timing) == DSI_THS_TRAIL ) || \
1201 ((Timing) == DSI_THS_PREPARE ) || \
1202 ((Timing) == DSI_TCLK_ZERO ) || \
1203 ((Timing) == DSI_TCLK_PREPARE))
1204
1205 /**
1206 * @}
1207 */
1208
1209 /* Private functions prototypes ----------------------------------------------*/
1210 /** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
1211 * @{
1212 */
1213
1214 /**
1215 * @}
1216 */
1217
1218 /* Private functions ---------------------------------------------------------*/
1219 /** @defgroup DSI_Private_Functions DSI Private Functions
1220 * @{
1221 */
1222
1223 /**
1224 * @}
1225 */
1226
1227 /**
1228 * @}
1229 */
1230
1231 /**
1232 * @}
1233 */
1234 #endif /* STM32F469xx || STM32F479xx */
1235
1236 #ifdef __cplusplus
1237 }
1238 #endif
1239
1240 #endif /* __STM32F4xx_HAL_DSI_H */
1241
1242 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/