lib/main/STM32F4/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_ll_system.h
   4   * @author  MCD Application Team
   5   * @version V1.7.1
   6   * @date    14-April-2017
   7   * @brief   Header file of SYSTEM LL module.
   8   @verbatim
   9   ==============================================================================
  10                      ##### How to use this driver #####
  11   ==============================================================================
  12     [..]
  13     The LL SYSTEM driver contains a set of generic APIs that can be
  14     used by user:
  15       (+) Some of the FLASH features need to be handled in the SYSTEM file.
  16       (+) Access to DBGCMU registers
  17       (+) Access to SYSCFG registers
  18
  19   @endverbatim
  20   ******************************************************************************
  21   * @attention
  22   *
  23   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  24   *
  25   * Redistribution and use in source and binary forms, with or without modification,
  26   * are permitted provided that the following conditions are met:
  27   *   1. Redistributions of source code must retain the above copyright notice,
  28   *      this list of conditions and the following disclaimer.
  29   *   2. Redistributions in binary form must reproduce the above copyright notice,
  30   *      this list of conditions and the following disclaimer in the documentation
  31   *      and/or other materials provided with the distribution.
  32   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  33   *      may be used to endorse or promote products derived from this software
  34   *      without specific prior written permission.
  35   *
  36   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  37   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  38   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  39   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  40   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  41   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  42   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  43   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  44   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  45   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  46   *
  47   ******************************************************************************
  48   */
  49
  50 /* Define to prevent recursive inclusion -------------------------------------*/
  51 #ifndef __STM32F4xx_LL_SYSTEM_H
  52 #define __STM32F4xx_LL_SYSTEM_H
  53
  54 #ifdef __cplusplus
  55 extern "C" {
  56 #endif
  57
  58 /* Includes ------------------------------------------------------------------*/
  59 #include "stm32f4xx.h"
  60
  61 /** @addtogroup STM32F4xx_LL_Driver
  62   * @{
  63   */
  64
  65 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
  66
  67 /** @defgroup SYSTEM_LL SYSTEM
  68   * @{
  69   */
  70
  71 /* Private types -------------------------------------------------------------*/
  72 /* Private variables ---------------------------------------------------------*/
  73
  74 /* Private constants ---------------------------------------------------------*/
  75 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
  76   * @{
  77   */
  78
  79 /**
  80   * @}
  81   */
  82
  83 /* Private macros ------------------------------------------------------------*/
  84
  85 /* Exported types ------------------------------------------------------------*/
  86 /* Exported constants --------------------------------------------------------*/
  87 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
  88   * @{
  89   */
  90
  91 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
  92 * @{
  93 */
  94 #define LL_SYSCFG_REMAP_FLASH              (uint32_t)0x00000000                                  /*!< Main Flash memory mapped at 0x00000000              */
  95 #define LL_SYSCFG_REMAP_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0                              /*!< System Flash memory mapped at 0x00000000            */
  96 #if defined(FSMC_Bank1)
  97 #define LL_SYSCFG_REMAP_FSMC               SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000                          */
  98 #endif /* FSMC_Bank1 */
  99 #if defined(FMC_Bank1)
 100 #define LL_SYSCFG_REMAP_FMC                SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000                          */
 101 #endif /* FMC_Bank1 */
 102 #define LL_SYSCFG_REMAP_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000                          */
 103 /**
 104   * @}
 105   */
 106
 107 #if defined(SYSCFG_PMC_MII_RMII_SEL)
 108  /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC
 109 * @{
 110 */
 111 #define LL_SYSCFG_PMC_ETHMII               (uint32_t)0x00000000                                /*!< ETH Media MII interface */
 112 #define LL_SYSCFG_PMC_ETHRMII              (uint32_t)SYSCFG_PMC_MII_RMII_SEL                   /*!< ETH Media RMII interface */
 113
 114 /**
 115   * @}
 116   */
 117 #endif /* SYSCFG_PMC_MII_RMII_SEL */
 118
 119
 120
 121 #if defined(SYSCFG_MEMRMP_UFB_MODE)
 122 /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
 123   * @{
 124   */
 125 #define LL_SYSCFG_BANKMODE_BANK1          (uint32_t)0x00000000       /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)
 126                                                                       and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/
 127 #define LL_SYSCFG_BANKMODE_BANK2          SYSCFG_MEMRMP_UFB_MODE     /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM)
 128                                                                       and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */
 129 /**
 130   * @}
 131   */
 132 #endif /* SYSCFG_MEMRMP_UFB_MODE */
 133 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
 134   * @{
 135   */
 136 #if defined(SYSCFG_CFGR_FMPI2C1_SCL)
 137 #define LL_SYSCFG_I2C_FASTMODEPLUS_SCL         SYSCFG_CFGR_FMPI2C1_SCL   /*!< Enable Fast Mode Plus on FMPI2C_SCL pin */
 138 #define LL_SYSCFG_I2C_FASTMODEPLUS_SDA         SYSCFG_CFGR_FMPI2C1_SDA   /*!< Enable Fast Mode Plus on FMPI2C_SDA pin*/
 139 #endif /* SYSCFG_CFGR_FMPI2C1_SCL */
 140 /**
 141   * @}
 142   */
 143
 144 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
 145   * @{
 146   */
 147 #define LL_SYSCFG_EXTI_PORTA               (uint32_t)0               /*!< EXTI PORT A                        */
 148 #define LL_SYSCFG_EXTI_PORTB               (uint32_t)1               /*!< EXTI PORT B                        */
 149 #define LL_SYSCFG_EXTI_PORTC               (uint32_t)2               /*!< EXTI PORT C                        */
 150 #define LL_SYSCFG_EXTI_PORTD               (uint32_t)3               /*!< EXTI PORT D                        */
 151 #define LL_SYSCFG_EXTI_PORTE               (uint32_t)4               /*!< EXTI PORT E                        */
 152 #if defined(GPIOF)
 153 #define LL_SYSCFG_EXTI_PORTF               (uint32_t)5               /*!< EXTI PORT F                        */
 154 #endif /* GPIOF */
 155 #if defined(GPIOG)
 156 #define LL_SYSCFG_EXTI_PORTG               (uint32_t)6               /*!< EXTI PORT G                        */
 157 #endif /* GPIOG */
 158 #define LL_SYSCFG_EXTI_PORTH               (uint32_t)7               /*!< EXTI PORT H                        */
 159 #if defined(GPIOI)
 160 #define LL_SYSCFG_EXTI_PORTI               (uint32_t)8               /*!< EXTI PORT I                        */
 161 #endif /* GPIOI */
 162 #if defined(GPIOJ)
 163 #define LL_SYSCFG_EXTI_PORTJ               (uint32_t)9               /*!< EXTI PORT J                        */
 164 #endif /* GPIOJ */
 165 #if defined(GPIOK)
 166 #define LL_SYSCFG_EXTI_PORTK               (uint32_t)10              /*!< EXTI PORT k                        */
 167 #endif /* GPIOK */
 168 /**
 169   * @}
 170   */
 171
 172 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
 173   * @{
 174   */
 175 #define LL_SYSCFG_EXTI_LINE0               (uint32_t)(0x000FU << 16 | 0)  /*!< EXTI_POSITION_0  | EXTICR[0] */
 176 #define LL_SYSCFG_EXTI_LINE1               (uint32_t)(0x00F0U << 16 | 0)  /*!< EXTI_POSITION_4  | EXTICR[0] */
 177 #define LL_SYSCFG_EXTI_LINE2               (uint32_t)(0x0F00U << 16 | 0)  /*!< EXTI_POSITION_8  | EXTICR[0] */
 178 #define LL_SYSCFG_EXTI_LINE3               (uint32_t)(0xF000U << 16 | 0)  /*!< EXTI_POSITION_12 | EXTICR[0] */
 179 #define LL_SYSCFG_EXTI_LINE4               (uint32_t)(0x000FU << 16 | 1)  /*!< EXTI_POSITION_0  | EXTICR[1] */
 180 #define LL_SYSCFG_EXTI_LINE5               (uint32_t)(0x00F0U << 16 | 1)  /*!< EXTI_POSITION_4  | EXTICR[1] */
 181 #define LL_SYSCFG_EXTI_LINE6               (uint32_t)(0x0F00U << 16 | 1)  /*!< EXTI_POSITION_8  | EXTICR[1] */
 182 #define LL_SYSCFG_EXTI_LINE7               (uint32_t)(0xF000U << 16 | 1)  /*!< EXTI_POSITION_12 | EXTICR[1] */
 183 #define LL_SYSCFG_EXTI_LINE8               (uint32_t)(0x000FU << 16 | 2)  /*!< EXTI_POSITION_0  | EXTICR[2] */
 184 #define LL_SYSCFG_EXTI_LINE9               (uint32_t)(0x00F0U << 16 | 2)  /*!< EXTI_POSITION_4  | EXTICR[2] */
 185 #define LL_SYSCFG_EXTI_LINE10              (uint32_t)(0x0F00U << 16 | 2)  /*!< EXTI_POSITION_8  | EXTICR[2] */
 186 #define LL_SYSCFG_EXTI_LINE11              (uint32_t)(0xF000U << 16 | 2)  /*!< EXTI_POSITION_12 | EXTICR[2] */
 187 #define LL_SYSCFG_EXTI_LINE12              (uint32_t)(0x000FU << 16 | 3)  /*!< EXTI_POSITION_0  | EXTICR[3] */
 188 #define LL_SYSCFG_EXTI_LINE13              (uint32_t)(0x00F0U << 16 | 3)  /*!< EXTI_POSITION_4  | EXTICR[3] */
 189 #define LL_SYSCFG_EXTI_LINE14              (uint32_t)(0x0F00U << 16 | 3)  /*!< EXTI_POSITION_8  | EXTICR[3] */
 190 #define LL_SYSCFG_EXTI_LINE15              (uint32_t)(0xF000U << 16 | 3)  /*!< EXTI_POSITION_12 | EXTICR[3] */
 191 /**
 192   * @}
 193   */
 194
 195 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
 196   * @{
 197   */
 198 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
 199 #define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CFGR2_LOCKUP_LOCK   /*!< Enables and locks the LOCKUP output of CortexM4
 200                                                                       with Break Input of TIM1/8                                    */
 201 #define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR2_PVD_LOCK      /*!< Enables and locks the PVD connection with TIM1/8 Break Input
 202                                                                       and also the PVDE and PLS bits of the Power Control Interface  */
 203 #endif /* SYSCFG_CFGR2_CLL */
 204 /**
 205   * @}
 206   */
 207
 208 #if defined(SYSCFG_MCHDLYCR_BSCKSEL)
 209 /** @defgroup SYSTEM_LL_DFSDM_BitStream_ClockSource SYSCFG MCHDLY BCKKSEL
 210   * @{
 211   */
 212 #define LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1          (uint32_t)0x00000000
 213 #define LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2           SYSCFG_MCHDLYCR_BSCKSEL
 214 /**
 215   * @}
 216   */
 217 /** @defgroup SYSTEM_LL_DFSDM_MCHDLYEN              SYSCFG MCHDLY MCHDLYEN
 218   * @{
 219   */
 220 #define LL_SYSCFG_DFSDM1_MCHDLYEN                  SYSCFG_MCHDLYCR_MCHDLY1EN
 221 #define LL_SYSCFG_DFSDM2_MCHDLYEN                  SYSCFG_MCHDLYCR_MCHDLY2EN
 222 /**
 223   * @}
 224   */
 225 /** @defgroup SYSTEM_LL_DFSDM_DataIn0_Source       SYSCFG MCHDLY DFSDMD0SEL
 226   * @{
 227   */
 228 #define LL_SYSCFG_DFSDM1_DataIn0                   SYSCFG_MCHDLYCR_DFSDM1D0SEL
 229 #define LL_SYSCFG_DFSDM2_DataIn0                   SYSCFG_MCHDLYCR_DFSDM2D0SEL
 230
 231 #define LL_SYSCFG_DFSDM1_DataIn0_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | 0x00000000)
 232 #define LL_SYSCFG_DFSDM1_DataIn0_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D0SEL)
 233 #define LL_SYSCFG_DFSDM2_DataIn0_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | 0x00000000)
 234 #define LL_SYSCFG_DFSDM2_DataIn0_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D0SEL)
 235 /**
 236   * @}
 237   */
 238 /** @defgroup SYSTEM_LL_DFSDM_DataIn2_Source       SYSCFG MCHDLY DFSDMD2SEL
 239   * @{
 240   */
 241 #define LL_SYSCFG_DFSDM1_DataIn2                   SYSCFG_MCHDLYCR_DFSDM1D2SEL
 242 #define LL_SYSCFG_DFSDM2_DataIn2                   SYSCFG_MCHDLYCR_DFSDM2D2SEL
 243
 244 #define LL_SYSCFG_DFSDM1_DataIn2_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | 0x00000000)
 245 #define LL_SYSCFG_DFSDM1_DataIn2_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D2SEL)
 246 #define LL_SYSCFG_DFSDM2_DataIn2_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | 0x00000000)
 247 #define LL_SYSCFG_DFSDM2_DataIn2_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D2SEL)
 248 /**
 249   * @}
 250   */
 251 /** @defgroup SYSTEM_LL_DFSDM1_TIM4OC2_BitstreamDistribution  SYSCFG MCHDLY DFSDM1CK02SEL
 252   * @{
 253   */
 254 #define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0           (uint32_t)0x00000000
 255 #define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2           SYSCFG_MCHDLYCR_DFSDM1CK02SEL
 256 /**
 257   * @}
 258   */
 259 /** @defgroup SYSTEM_LL_DFSDM1_TIM4OC1_BitstreamDistribution  SYSCFG MCHDLY DFSDM1CK13SEL
 260   * @{
 261   */
 262 #define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1           (uint32_t)0x00000000
 263 #define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3           SYSCFG_MCHDLYCR_DFSDM1CK13SEL
 264 /**
 265   * @}
 266   */
 267 /** @defgroup SYSTEM_LL_DFSDM1_CLKIN_SourceSelection SYSCFG MCHDLY DFSDMCFG
 268   * @{
 269   */
 270 #define LL_SYSCFG_DFSDM1_CKIN_PAD                 (uint32_t)0x00000000
 271 #define LL_SYSCFG_DFSDM1_CKIN_DM                  SYSCFG_MCHDLYCR_DFSDM1CFG
 272 /**
 273   * @}
 274   */
 275 /** @defgroup SYSTEM_LL_DFSDM1_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM1CKOSEL
 276   * @{
 277   */
 278 #define LL_SYSCFG_DFSDM1_CKOUT                    (uint32_t)0x00000000
 279 #define LL_SYSCFG_DFSDM1_CKOUT_M27                SYSCFG_MCHDLYCR_DFSDM1CKOSEL
 280 /**
 281   * @}
 282   */
 283
 284 /** @defgroup SYSTEM_LL_DFSDM2_DataIn4_SourceSelection SYSCFG MCHDLY DFSDM2D4SEL
 285   * @{
 286   */
 287 #define LL_SYSCFG_DFSDM2_DataIn4_PAD              (uint32_t)0x00000000
 288 #define LL_SYSCFG_DFSDM2_DataIn4_DM               SYSCFG_MCHDLYCR_DFSDM2D4SEL
 289 /**
 290   * @}
 291   */
 292 /** @defgroup SYSTEM_LL_DFSDM2_DataIn6_SourceSelection SYSCFG MCHDLY DFSDM2D6SEL
 293   * @{
 294   */
 295 #define LL_SYSCFG_DFSDM2_DataIn6_PAD              (uint32_t)0x00000000
 296 #define LL_SYSCFG_DFSDM2_DataIn6_DM               SYSCFG_MCHDLYCR_DFSDM2D6SEL
 297 /**
 298   * @}
 299   */
 300 /** @defgroup SYSTEM_LL_DFSDM2_TIM3OC4_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK04SEL
 301   * @{
 302   */
 303 #define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0           (uint32_t)0x00000000
 304 #define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4           SYSCFG_MCHDLYCR_DFSDM2CK04SEL
 305 /**
 306   * @}
 307   */
 308 /** @defgroup SYSTEM_LL_DFSDM2_TIM3OC3_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK15SEL
 309   * @{
 310   */
 311 #define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1           (uint32_t)0x00000000
 312 #define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5           SYSCFG_MCHDLYCR_DFSDM2CK15SEL
 313 /**
 314   * @}
 315   */
 316 /** @defgroup SYSTEM_LL_DFSDM2_TIM3OC2_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK26SEL
 317   * @{
 318   */
 319 #define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2           (uint32_t)0x00000000
 320 #define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6           SYSCFG_MCHDLYCR_DFSDM2CK26SEL
 321 /**
 322   * @}
 323   */
 324 /** @defgroup SYSTEM_LL_DFSDM2_TIM3OC1_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK37SEL
 325   * @{
 326   */
 327 #define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3           (uint32_t)0x00000000
 328 #define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7           SYSCFG_MCHDLYCR_DFSDM2CK37SEL
 329 /**
 330   * @}
 331   */
 332 /** @defgroup SYSTEM_LL_DFSDM2_CLKIN_SourceSelection SYSCFG MCHDLY DFSDM2CFG
 333   * @{
 334   */
 335 #define LL_SYSCFG_DFSDM2_CKIN_PAD                 (uint32_t)0x00000000
 336 #define LL_SYSCFG_DFSDM2_CKIN_DM                  SYSCFG_MCHDLYCR_DFSDM2CFG
 337 /**
 338   * @}
 339   */
 340 /** @defgroup SYSTEM_LL_DFSDM2_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM2CKOSEL
 341   * @{
 342   */
 343 #define LL_SYSCFG_DFSDM2_CKOUT                    (uint32_t)0x00000000
 344 #define LL_SYSCFG_DFSDM2_CKOUT_M27                SYSCFG_MCHDLYCR_DFSDM2CKOSEL
 345 /**
 346   * @}
 347   */
 348 #endif /* SYSCFG_MCHDLYCR_BSCKSEL */
 349
 350 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
 351   * @{
 352   */
 353 #define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
 354 #define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
 355 #define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
 356 #define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
 357 #define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
 358 /**
 359   * @}
 360   */
 361
 362 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
 363   * @{
 364   */
 365 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
 366 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1_FZ_DBG_TIM2_STOP          /*!< TIM2 counter stopped when core is halted */
 367 #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
 368 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
 369 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1_FZ_DBG_TIM3_STOP          /*!< TIM3 counter stopped when core is halted */
 370 #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
 371 #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
 372 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1_FZ_DBG_TIM4_STOP          /*!< TIM4 counter stopped when core is halted */
 373 #endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
 374 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1_FZ_DBG_TIM5_STOP          /*!< TIM5 counter stopped when core is halted */
 375 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
 376 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1_FZ_DBG_TIM6_STOP          /*!< TIM6 counter stopped when core is halted */
 377 #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
 378 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
 379 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1_FZ_DBG_TIM7_STOP          /*!< TIM7 counter stopped when core is halted */
 380 #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
 381 #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
 382 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_APB1_FZ_DBG_TIM12_STOP         /*!< TIM12 counter stopped when core is halted */
 383 #endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
 384 #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
 385 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_APB1_FZ_DBG_TIM13_STOP         /*!< TIM13 counter stopped when core is halted */
 386 #endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
 387 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
 388 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_APB1_FZ_DBG_TIM14_STOP         /*!< TIM14 counter stopped when core is halted */
 389 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
 390 #if defined(DBGMCU_APB1_FZ_DBG_LPTIM_STOP)
 391 #define LL_DBGMCU_APB1_GRP1_LPTIM_STOP     DBGMCU_APB1_FZ_DBG_LPTIM_STOP         /*!< LPTIM counter stopped when core is halted */
 392 #endif /* DBGMCU_APB1_FZ_DBG_LPTIM_STOP */
 393 #define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1_FZ_DBG_RTC_STOP           /*!< RTC counter stopped when core is halted */
 394 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1_FZ_DBG_WWDG_STOP          /*!< Debug Window Watchdog stopped when Core is halted */
 395 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1_FZ_DBG_IWDG_STOP          /*!< Debug Independent Watchdog stopped when Core is halted */
 396 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
 397 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
 398 #if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
 399 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
 400 #endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
 401 #if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)
 402 #define LL_DBGMCU_APB1_GRP1_I2C4_STOP      DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when Core is halted */
 403 #endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */
 404 #if defined(DBGMCU_APB1_FZ_DBG_CAN1_STOP)
 405 #define LL_DBGMCU_APB1_GRP1_CAN1_STOP      DBGMCU_APB1_FZ_DBG_CAN1_STOP          /*!< CAN1 debug stopped when Core is halted  */
 406 #endif /* DBGMCU_APB1_FZ_DBG_CAN1_STOP */
 407 #if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)
 408 #define LL_DBGMCU_APB1_GRP1_CAN2_STOP      DBGMCU_APB1_FZ_DBG_CAN2_STOP          /*!< CAN2 debug stopped when Core is halted  */
 409 #endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */
 410 #if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)
 411 #define LL_DBGMCU_APB1_GRP1_CAN3_STOP      DBGMCU_APB1_FZ_DBG_CAN3_STOP          /*!< CAN3 debug stopped when Core is halted  */
 412 #endif /* DBGMCU_APB1_FZ_DBG_CAN3_STOP */
 413 /**
 414   * @}
 415   */
 416
 417 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
 418   * @{
 419   */
 420 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2_FZ_DBG_TIM1_STOP   /*!< TIM1 counter stopped when core is halted */
 421 #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
 422 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2_FZ_DBG_TIM8_STOP   /*!< TIM8 counter stopped when core is halted */
 423 #endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
 424 #define LL_DBGMCU_APB2_GRP1_TIM9_STOP      DBGMCU_APB2_FZ_DBG_TIM9_STOP   /*!< TIM9 counter stopped when core is halted */
 425 #if defined(DBGMCU_APB2_FZ_DBG_TIM10_STOP)
 426 #define LL_DBGMCU_APB2_GRP1_TIM10_STOP     DBGMCU_APB2_FZ_DBG_TIM10_STOP   /*!< TIM10 counter stopped when core is halted */
 427 #endif /* DBGMCU_APB2_FZ_DBG_TIM10_STOP */
 428 #define LL_DBGMCU_APB2_GRP1_TIM11_STOP     DBGMCU_APB2_FZ_DBG_TIM11_STOP   /*!< TIM11 counter stopped when core is halted */
 429 /**
 430   * @}
 431   */
 432
 433 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
 434   * @{
 435   */
 436 #define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */
 437 #define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */
 438 #define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */
 439 #define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */
 440 #define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */
 441 #define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait state */
 442 #define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */
 443 #define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH seven wait states */
 444 #define LL_FLASH_LATENCY_8                 FLASH_ACR_LATENCY_8WS   /*!< FLASH eight wait states */
 445 #define LL_FLASH_LATENCY_9                 FLASH_ACR_LATENCY_9WS   /*!< FLASH nine wait states */
 446 #define LL_FLASH_LATENCY_10                FLASH_ACR_LATENCY_10WS   /*!< FLASH ten wait states */
 447 #define LL_FLASH_LATENCY_11                FLASH_ACR_LATENCY_11WS   /*!< FLASH eleven wait states */
 448 #define LL_FLASH_LATENCY_12                FLASH_ACR_LATENCY_12WS   /*!< FLASH twelve wait states */
 449 #define LL_FLASH_LATENCY_13                FLASH_ACR_LATENCY_13WS   /*!< FLASH thirteen wait states */
 450 #define LL_FLASH_LATENCY_14                FLASH_ACR_LATENCY_14WS   /*!< FLASH fourteen wait states */
 451 #define LL_FLASH_LATENCY_15                FLASH_ACR_LATENCY_15WS   /*!< FLASH fifteen wait states */
 452 /**
 453   * @}
 454   */
 455
 456 /**
 457   * @}
 458   */
 459
 460 /* Exported macro ------------------------------------------------------------*/
 461
 462 /* Exported functions --------------------------------------------------------*/
 463 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
 464   * @{
 465   */
 466
 467 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
 468   * @{
 469   */
 470 /**
 471   * @brief  Set memory mapping at address 0x00000000
 472   * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_SetRemapMemory
 473   * @param  Memory This parameter can be one of the following values:
 474   *         @arg @ref LL_SYSCFG_REMAP_FLASH
 475   *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
 476   *         @arg @ref LL_SYSCFG_REMAP_SRAM
 477   *         @arg @ref LL_SYSCFG_REMAP_FSMC (*)
 478   *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
 479   * @retval None
 480   */
 481 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
 482 {
 483   MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
 484 }
 485
 486 /**
 487   * @brief  Get memory mapping at address 0x00000000
 488   * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_GetRemapMemory
 489   * @retval Returned value can be one of the following values:
 490   *         @arg @ref LL_SYSCFG_REMAP_FLASH
 491   *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
 492   *         @arg @ref LL_SYSCFG_REMAP_SRAM
 493   *         @arg @ref LL_SYSCFG_REMAP_FSMC (*)
 494   *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
 495   */
 496 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
 497 {
 498   return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
 499 }
 500
 501 #if defined(SYSCFG_MEMRMP_SWP_FMC)
 502 /**
 503   * @brief  Enables the FMC Memory Mapping Swapping
 504   * @rmtoll SYSCFG_MEMRMP SWP_FMC      LL_SYSCFG_EnableFMCMemorySwapping
 505   * @note   SDRAM is accessible at 0x60000000 and NOR/RAM
 506   *         is accessible at 0xC0000000
 507   * @retval None
 508   */
 509 __STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)
 510 {
 511   SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0);
 512 }
 513
 514 /**
 515   * @brief  Disables the FMC Memory Mapping Swapping
 516   * @rmtoll SYSCFG_MEMRMP SWP_FMC      LL_SYSCFG_DisableFMCMemorySwapping
 517   * @note   SDRAM is accessible at 0xC0000000 (default mapping)
 518   *         and NOR/RAM is accessible at 0x60000000 (default mapping)
 519   * @retval None
 520   */
 521 __STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void)
 522 {
 523   CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC);
 524 }
 525
 526 #endif /* SYSCFG_MEMRMP_SWP_FMC */
 527 /**
 528   * @brief  Enables the Compensation cell Power Down
 529   * @rmtoll SYSCFG_CMPCR CMP_PD      LL_SYSCFG_EnableCompensationCell
 530   * @note   The I/O compensation cell can be used only when the device supply
 531   *         voltage ranges from 2.4 to 3.6 V
 532   * @retval None
 533   */
 534 __STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
 535 {
 536   SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
 537 }
 538
 539 /**
 540   * @brief  Disables the Compensation cell Power Down
 541   * @rmtoll SYSCFG_CMPCR CMP_PD      LL_SYSCFG_DisableCompensationCell
 542   * @note   The I/O compensation cell can be used only when the device supply
 543   *         voltage ranges from 2.4 to 3.6 V
 544   * @retval None
 545   */
 546 __STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
 547 {
 548   CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
 549 }
 550
 551 /**
 552   * @brief  Get Compensation Cell ready Flag
 553   * @rmtoll SYSCFG_CMPCR READY  LL_SYSCFG_IsActiveFlag_CMPCR
 554   * @retval State of bit (1 or 0).
 555   */
 556 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
 557 {
 558   return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
 559 }
 560
 561 #if defined(SYSCFG_PMC_MII_RMII_SEL)
 562 /**
 563   * @brief  Select Ethernet PHY interface
 564   * @rmtoll SYSCFG_PMC MII_RMII_SEL       LL_SYSCFG_SetPHYInterface
 565   * @param  Interface This parameter can be one of the following values:
 566   *         @arg @ref LL_SYSCFG_PMC_ETHMII
 567   *         @arg @ref LL_SYSCFG_PMC_ETHRMII
 568   * @retval None
 569   */
 570 __STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
 571 {
 572   MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);
 573 }
 574
 575 /**
 576   * @brief  Get Ethernet PHY interface
 577   * @rmtoll SYSCFG_PMC MII_RMII_SEL       LL_SYSCFG_GetPHYInterface
 578   * @retval Returned value can be one of the following values:
 579   *         @arg @ref LL_SYSCFG_PMC_ETHMII
 580   *         @arg @ref LL_SYSCFG_PMC_ETHRMII
 581   * @retval None
 582   */
 583 __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
 584 {
 585   return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
 586 }
 587 #endif /* SYSCFG_PMC_MII_RMII_SEL */
 588
 589
 590
 591 #if defined(SYSCFG_MEMRMP_UFB_MODE)
 592 /**
 593   * @brief  Select Flash bank mode (Bank flashed at 0x08000000)
 594   * @rmtoll SYSCFG_MEMRMP UFB_MODE       LL_SYSCFG_SetFlashBankMode
 595   * @param  Bank This parameter can be one of the following values:
 596   *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
 597   *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
 598   * @retval None
 599   */
 600 __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
 601 {
 602   MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank);
 603 }
 604
 605 /**
 606   * @brief  Get Flash bank mode (Bank flashed at 0x08000000)
 607   * @rmtoll SYSCFG_MEMRMP UFB_MODE       LL_SYSCFG_GetFlashBankMode
 608   * @retval Returned value can be one of the following values:
 609   *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
 610   *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
 611   */
 612 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
 613 {
 614   return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE));
 615 }
 616 #endif /* SYSCFG_MEMRMP_UFB_MODE */
 617
 618 #if defined(SYSCFG_CFGR_FMPI2C1_SCL)
 619 /**
 620   * @brief  Enable the I2C fast mode plus driving capability.
 621   * @rmtoll SYSCFG_CFGR FMPI2C1_SCL   LL_SYSCFG_EnableFastModePlus\n
 622   *         SYSCFG_CFGR FMPI2C1_SDA   LL_SYSCFG_EnableFastModePlus
 623   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
 624   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
 625   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
 626   *         (*) value not defined in all devices
 627   * @retval None
 628   */
 629 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
 630 {
 631   SET_BIT(SYSCFG->CFGR, ConfigFastModePlus);
 632 }
 633
 634 /**
 635   * @brief  Disable the I2C fast mode plus driving capability.
 636   * @rmtoll SYSCFG_CFGR FMPI2C1_SCL  LL_SYSCFG_DisableFastModePlus\n
 637   *         SYSCFG_CFGR FMPI2C1_SDA  LL_SYSCFG_DisableFastModePlus\n
 638   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
 639   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
 640   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
 641   *         (*) value not defined in all devices
 642   * @retval None
 643   */
 644 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
 645 {
 646   CLEAR_BIT(SYSCFG->CFGR, ConfigFastModePlus);
 647 }
 648 #endif /* SYSCFG_CFGR_FMPI2C1_SCL */
 649
 650 /**
 651   * @brief  Configure source input for the EXTI external interrupt.
 652   * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_SetEXTISource\n
 653   *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n
 654   *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n
 655   *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource
 656   * @param  Port This parameter can be one of the following values:
 657   *         @arg @ref LL_SYSCFG_EXTI_PORTA
 658   *         @arg @ref LL_SYSCFG_EXTI_PORTB
 659   *         @arg @ref LL_SYSCFG_EXTI_PORTC
 660   *         @arg @ref LL_SYSCFG_EXTI_PORTD
 661   *         @arg @ref LL_SYSCFG_EXTI_PORTE
 662   *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)
 663   *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
 664   *         @arg @ref LL_SYSCFG_EXTI_PORTH
 665   *
 666   *         (*) value not defined in all devices
 667   * @param  Line This parameter can be one of the following values:
 668   *         @arg @ref LL_SYSCFG_EXTI_LINE0
 669   *         @arg @ref LL_SYSCFG_EXTI_LINE1
 670   *         @arg @ref LL_SYSCFG_EXTI_LINE2
 671   *         @arg @ref LL_SYSCFG_EXTI_LINE3
 672   *         @arg @ref LL_SYSCFG_EXTI_LINE4
 673   *         @arg @ref LL_SYSCFG_EXTI_LINE5
 674   *         @arg @ref LL_SYSCFG_EXTI_LINE6
 675   *         @arg @ref LL_SYSCFG_EXTI_LINE7
 676   *         @arg @ref LL_SYSCFG_EXTI_LINE8
 677   *         @arg @ref LL_SYSCFG_EXTI_LINE9
 678   *         @arg @ref LL_SYSCFG_EXTI_LINE10
 679   *         @arg @ref LL_SYSCFG_EXTI_LINE11
 680   *         @arg @ref LL_SYSCFG_EXTI_LINE12
 681   *         @arg @ref LL_SYSCFG_EXTI_LINE13
 682   *         @arg @ref LL_SYSCFG_EXTI_LINE14
 683   *         @arg @ref LL_SYSCFG_EXTI_LINE15
 684   * @retval None
 685   */
 686 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
 687 {
 688   MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
 689 }
 690
 691 /**
 692   * @brief  Get the configured defined for specific EXTI Line
 693   * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n
 694   *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n
 695   *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n
 696   *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource
 697   * @param  Line This parameter can be one of the following values:
 698   *         @arg @ref LL_SYSCFG_EXTI_LINE0
 699   *         @arg @ref LL_SYSCFG_EXTI_LINE1
 700   *         @arg @ref LL_SYSCFG_EXTI_LINE2
 701   *         @arg @ref LL_SYSCFG_EXTI_LINE3
 702   *         @arg @ref LL_SYSCFG_EXTI_LINE4
 703   *         @arg @ref LL_SYSCFG_EXTI_LINE5
 704   *         @arg @ref LL_SYSCFG_EXTI_LINE6
 705   *         @arg @ref LL_SYSCFG_EXTI_LINE7
 706   *         @arg @ref LL_SYSCFG_EXTI_LINE8
 707   *         @arg @ref LL_SYSCFG_EXTI_LINE9
 708   *         @arg @ref LL_SYSCFG_EXTI_LINE10
 709   *         @arg @ref LL_SYSCFG_EXTI_LINE11
 710   *         @arg @ref LL_SYSCFG_EXTI_LINE12
 711   *         @arg @ref LL_SYSCFG_EXTI_LINE13
 712   *         @arg @ref LL_SYSCFG_EXTI_LINE14
 713   *         @arg @ref LL_SYSCFG_EXTI_LINE15
 714   * @retval Returned value can be one of the following values:
 715   *         @arg @ref LL_SYSCFG_EXTI_PORTA
 716   *         @arg @ref LL_SYSCFG_EXTI_PORTB
 717   *         @arg @ref LL_SYSCFG_EXTI_PORTC
 718   *         @arg @ref LL_SYSCFG_EXTI_PORTD
 719   *         @arg @ref LL_SYSCFG_EXTI_PORTE
 720   *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)
 721   *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
 722   *         @arg @ref LL_SYSCFG_EXTI_PORTH
 723   *         (*) value not defined in all devices
 724   */
 725 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
 726 {
 727   return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
 728 }
 729
 730 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
 731 /**
 732   * @brief  Set connections to TIM1/8 break inputs
 733   * @rmtoll SYSCFG_CFGR2 LockUp Lock           LL_SYSCFG_SetTIMBreakInputs \n
 734   *         SYSCFG_CFGR2 PVD Lock              LL_SYSCFG_SetTIMBreakInputs
 735   * @param  Break This parameter can be a combination of the following values:
 736   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
 737   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
 738   * @retval None
 739   */
 740 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
 741 {
 742   MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break);
 743 }
 744
 745 /**
 746   * @brief  Get connections to TIM1/8 Break inputs
 747   * @rmtoll SYSCFG_CFGR2 LockUp Lock           LL_SYSCFG_SetTIMBreakInputs \n
 748   *         SYSCFG_CFGR2 PVD Lock              LL_SYSCFG_SetTIMBreakInputs
 749   * @retval Returned value can be can be a combination of the following values:
 750   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
 751   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
 752   */
 753 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
 754 {
 755   return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK));
 756 }
 757 #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
 758 #if defined(SYSCFG_MCHDLYCR_BSCKSEL)
 759 /**
 760   * @brief  Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
 761   * @rmtoll SYSCFG_MCHDLYCR BSCKSEL        LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection
 762   * @param  ClockSource This parameter can be one of the following values:
 763   *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
 764   *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
 765   * @retval None
 766   */
 767 __STATIC_INLINE void LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection(uint32_t ClockSource)
 768 {
 769   MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL, ClockSource);
 770 }
 771 /**
 772   * @brief  Get the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
 773   * @rmtoll SYSCFG_MCHDLYCR BSCKSEL       LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection
 774   * @retval Returned value can be one of the following values:
 775   *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
 776   *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
 777   * @retval None
 778   */
 779 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void)
 780 {
 781   return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL));
 782 }
 783 /**
 784   * @brief  Enables the DFSDM1 or DFSDM2 Delay clock
 785   * @rmtoll SYSCFG_MCHDLYCR MCHDLYEN      LL_SYSCFG_DFSDM_EnableDelayClock
 786   * @param MCHDLY This paramater can be one of the following values
 787   *         @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
 788   *         @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
 789   * @retval None
 790   */
 791 __STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY)
 792 {
 793   SET_BIT(SYSCFG->MCHDLYCR, MCHDLY);
 794 }
 795
 796 /**
 797   * @brief  Disables the DFSDM1 or the DFSDM2 Delay clock
 798   * @rmtoll SYSCFG_MCHDLYCR MCHDLY1EN      LL_SYSCFG_DFSDM1_DisableDelayClock
 799   * @param MCHDLY This paramater can be one of the following values
 800   *         @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
 801   *         @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
 802   * @retval None
 803   */
 804 __STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY)
 805 {
 806   CLEAR_BIT(SYSCFG->MCHDLYCR, MCHDLY);
 807 }
 808
 809 /**
 810   * @brief  Select the source for DFSDM1 or DFSDM2 DatIn0
 811   * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL        LL_SYSCFG_DFSDM_SetDataIn0Source
 812   * @param  Source This parameter can be one of the following values:
 813   *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
 814   *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
 815   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
 816   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
 817   * @retval None
 818   */
 819 __STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn0Source(uint32_t Source)
 820 {
 821   MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
 822 }
 823 /**
 824   * @brief  Get the source for DFSDM1 or DFSDM2 DatIn0.
 825   * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL       LL_SYSCFG_DFSDM_GetDataIn0Source
 826   * @param  Source This parameter can be one of the following values:
 827   *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0
 828   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0
 829   * @retval Returned value can be one of the following values:
 830   *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
 831   *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
 832   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
 833   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
 834   * @retval None
 835   */
 836 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source)
 837 {
 838   return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
 839 }
 840 /**
 841   * @brief  Select the source for DFSDM1 or DFSDM2 DatIn2
 842   * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL        LL_SYSCFG_DFSDM_SetDataIn2Source
 843   * @param  Source This parameter can be one of the following values:
 844   *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
 845   *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
 846   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
 847   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
 848   * @retval None
 849   */
 850 __STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn2Source(uint32_t Source)
 851 {
 852   MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
 853 }
 854 /**
 855   * @brief  Get the source for DFSDM1 or DFSDM2 DatIn2.
 856   * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL       LL_SYSCFG_DFSDM_GetDataIn2Source
 857   * @param  Source This parameter can be one of the following values:
 858   *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2
 859   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2
 860   * @retval Returned value can be one of the following values:
 861   *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
 862   *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
 863   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
 864   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
 865   * @retval None
 866   */
 867 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source)
 868 {
 869   return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
 870 }
 871
 872 /**
 873   * @brief  Select the distribution of the bitsream lock gated by TIM4 OC2
 874   * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK02SEL        LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution
 875   * @param  Source This parameter can be one of the following values:
 876   *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
 877   *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
 878   * @retval None
 879   */
 880 __STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t Source)
 881 {
 882   MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source);
 883 }
 884 /**
 885   * @brief  Get the distribution of the bitsream lock gated by TIM4 OC2
 886   * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL       LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution
 887   * @retval Returned value can be one of the following values:
 888   *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
 889   *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
 890   * @retval None
 891   */
 892 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void)
 893 {
 894   return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL));
 895 }
 896
 897 /**
 898   * @brief  Select the distribution of the bitsream lock gated by TIM4 OC1
 899   * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK13SEL        LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution
 900   * @param  Source This parameter can be one of the following values:
 901   *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
 902   *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
 903   * @retval None
 904   */
 905 __STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t Source)
 906 {
 907   MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source);
 908 }
 909 /**
 910   * @brief  Get the distribution of the bitsream lock gated by TIM4 OC1
 911   * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL       LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution
 912   * @retval Returned value can be one of the following values:
 913   *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
 914   *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
 915   * @retval None
 916   */
 917 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void)
 918 {
 919   return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL));
 920 }
 921
 922 /**
 923   * @brief  Select the DFSDM1 Clock In
 924   * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG        LL_SYSCFG_DFSDM1_SetClockInSourceSelection
 925   * @param  ClockSource This parameter can be one of the following values:
 926   *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
 927   *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
 928   * @retval None
 929   */
 930 __STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockInSourceSelection(uint32_t ClockSource)
 931 {
 932   MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG, ClockSource);
 933 }
 934 /**
 935   * @brief  GET the DFSDM1 Clock In
 936   * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG       LL_SYSCFG_DFSDM1_GetClockInSourceSelection
 937   * @retval Returned value can be one of the following values:
 938   *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
 939   *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
 940   * @retval None
 941   */
 942 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void)
 943 {
 944   return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG));
 945 }
 946
 947 /**
 948   * @brief  Select the DFSDM1 Clock Out
 949   * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL        LL_SYSCFG_DFSDM1_SetClockOutSourceSelection
 950   * @param  ClockSource This parameter can be one of the following values:
 951   *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT
 952   *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
 953   * @retval None
 954   */
 955 __STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockOutSourceSelection(uint32_t ClockSource)
 956 {
 957   MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL, ClockSource);
 958 }
 959 /**
 960   * @brief  GET the DFSDM1 Clock Out
 961   * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL       LL_SYSCFG_DFSDM1_GetClockOutSourceSelection
 962   * @retval Returned value can be one of the following values:
 963   *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT
 964   *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
 965   * @retval None
 966   */
 967 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockOutSourceSelection(void)
 968 {
 969   return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL));
 970 }
 971
 972 /**
 973   * @brief  Enables the DFSDM2 Delay clock
 974   * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN      LL_SYSCFG_DFSDM2_EnableDelayClock
 975   * @retval None
 976   */
 977 __STATIC_INLINE void LL_SYSCFG_DFSDM2_EnableDelayClock(void)
 978 {
 979   SET_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
 980 }
 981
 982 /**
 983   * @brief  Disables the DFSDM2 Delay clock
 984   * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN      LL_SYSCFG_DFSDM2_DisableDelayClock
 985   * @retval None
 986   */
 987 __STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void)
 988 {
 989   CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
 990 }
 991 /**
 992   * @brief  Select the source for DFSDM2 DatIn0
 993   * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL        LL_SYSCFG_DFSDM2_SetDataIn0Source
 994   * @param  Source This parameter can be one of the following values:
 995   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
 996   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
 997   * @retval None
 998   */
 999 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn0Source(uint32_t Source)
1000 {
1001   MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL, Source);
1002 }
1003 /**
1004   * @brief  Get the source for DFSDM2 DatIn0.
1005   * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL       LL_SYSCFG_DFSDM2_GetDataIn0Source
1006   * @retval Returned value can be one of the following values:
1007   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
1008   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
1009   * @retval None
1010   */
1011 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void)
1012 {
1013   return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL));
1014 }
1015
1016 /**
1017   * @brief  Select the source for DFSDM2 DatIn2
1018   * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL        LL_SYSCFG_DFSDM2_SetDataIn2Source
1019   * @param  Source This parameter can be one of the following values:
1020   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
1021   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
1022   * @retval None
1023   */
1024 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn2Source(uint32_t Source)
1025 {
1026   MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL, Source);
1027 }
1028 /**
1029   * @brief  Get the source for DFSDM2 DatIn2.
1030   * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL       LL_SYSCFG_DFSDM2_GetDataIn2Source
1031   * @retval Returned value can be one of the following values:
1032   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
1033   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
1034   * @retval None
1035   */
1036 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void)
1037 {
1038   return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL));
1039 }
1040
1041 /**
1042   * @brief  Select the source for DFSDM2 DatIn4
1043   * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL        LL_SYSCFG_DFSDM2_SetDataIn4Source
1044   * @param  Source This parameter can be one of the following values:
1045   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
1046   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
1047   * @retval None
1048   */
1049 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn4Source(uint32_t Source)
1050 {
1051   MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL, Source);
1052 }
1053 /**
1054   * @brief  Get the source for DFSDM2 DatIn4.
1055   * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL       LL_SYSCFG_DFSDM2_GetDataIn4Source
1056   * @retval Returned value can be one of the following values:
1057   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
1058   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
1059   * @retval None
1060   */
1061 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void)
1062 {
1063   return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL));
1064 }
1065
1066 /**
1067   * @brief  Select the source for DFSDM2 DatIn6
1068   * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL        LL_SYSCFG_DFSDM2_SetDataIn6Source
1069   * @param  Source This parameter can be one of the following values:
1070   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
1071   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
1072   * @retval None
1073   */
1074 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn6Source(uint32_t Source)
1075 {
1076   MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL, Source);
1077 }
1078 /**
1079   * @brief  Get the source for DFSDM2 DatIn6.
1080   * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL       LL_SYSCFG_DFSDM2_GetDataIn6Source
1081   * @retval Returned value can be one of the following values:
1082   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
1083   *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
1084   * @retval None
1085   */
1086 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void)
1087 {
1088   return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL));
1089 }
1090
1091 /**
1092   * @brief  Select the distribution of the bitsream lock gated by TIM3 OC4
1093   * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL        LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution
1094   * @param  Source This parameter can be one of the following values:
1095   *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
1096   *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
1097   * @retval None
1098   */
1099 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t Source)
1100 {
1101   MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source);
1102 }
1103 /**
1104   * @brief  Get the distribution of the bitsream lock gated by TIM3 OC4
1105   * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL       LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution
1106   * @retval Returned value can be one of the following values:
1107   *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
1108   *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
1109   * @retval None
1110   */
1111 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void)
1112 {
1113   return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL));
1114 }
1115
1116 /**
1117   * @brief  Select the distribution of the bitsream lock gated by TIM3 OC3
1118   * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK15SEL        LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution
1119   * @param  Source This parameter can be one of the following values:
1120   *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
1121   *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
1122   * @retval None
1123   */
1124 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t Source)
1125 {
1126   MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source);
1127 }
1128 /**
1129   * @brief  Get the distribution of the bitsream lock gated by TIM3 OC4
1130   * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL       LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution
1131   * @retval Returned value can be one of the following values:
1132   *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
1133   *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
1134   * @retval None
1135   */
1136 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void)
1137 {
1138   return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL));
1139 }
1140
1141 /**
1142   * @brief  Select the distribution of the bitsream lock gated by TIM3 OC2
1143   * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK26SEL        LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution
1144   * @param  Source This parameter can be one of the following values:
1145   *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
1146   *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
1147   * @retval None
1148   */
1149 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t Source)
1150 {
1151   MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source);
1152 }
1153 /**
1154   * @brief  Get the distribution of the bitsream lock gated by TIM3 OC2
1155   * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL       LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution
1156   * @retval Returned value can be one of the following values:
1157   *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
1158   *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
1159   * @retval None
1160   */
1161 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void)
1162 {
1163   return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL));
1164 }
1165
1166 /**
1167   * @brief  Select the distribution of the bitsream lock gated by TIM3 OC1
1168   * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL        LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution
1169   * @param  Source This parameter can be one of the following values:
1170   *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
1171   *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
1172   * @retval None
1173   */
1174 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t Source)
1175 {
1176   MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source);
1177 }
1178 /**
1179   * @brief  Get the distribution of the bitsream lock gated by TIM3 OC1
1180   * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL       LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution
1181   * @retval Returned value can be one of the following values:
1182   *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
1183   *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
1184   * @retval None
1185   */
1186 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void)
1187 {
1188   return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL));
1189 }
1190
1191 /**
1192   * @brief  Select the DFSDM2 Clock In
1193   * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG        LL_SYSCFG_DFSDM2_SetClockInSourceSelection
1194   * @param  ClockSource This parameter can be one of the following values:
1195   *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
1196   *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
1197   * @retval None
1198   */
1199 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockInSourceSelection(uint32_t ClockSource)
1200 {
1201   MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG, ClockSource);
1202 }
1203 /**
1204   * @brief  GET the DFSDM2 Clock In
1205   * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG       LL_SYSCFG_DFSDM2_GetClockInSourceSelection
1206   * @retval Returned value can be one of the following values:
1207   *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
1208   *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
1209   * @retval None
1210   */
1211 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void)
1212 {
1213   return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG));
1214 }
1215
1216 /**
1217   * @brief  Select the DFSDM2 Clock Out
1218   * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL        LL_SYSCFG_DFSDM2_SetClockOutSourceSelection
1219   * @param  ClockSource This parameter can be one of the following values:
1220   *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT
1221   *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
1222   * @retval None
1223   */
1224 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockOutSourceSelection(uint32_t ClockSource)
1225 {
1226   MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL, ClockSource);
1227 }
1228 /**
1229   * @brief  GET the DFSDM2 Clock Out
1230   * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL       LL_SYSCFG_DFSDM2_GetClockOutSourceSelection
1231   * @retval Returned value can be one of the following values:
1232   *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT
1233   *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
1234   * @retval None
1235   */
1236 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockOutSourceSelection(void)
1237 {
1238   return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL));
1239 }
1240
1241 #endif /* SYSCFG_MCHDLYCR_BSCKSEL */
1242 /**
1243   * @}
1244   */
1245
1246
1247 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1248   * @{
1249   */
1250
1251 /**
1252   * @brief  Return the device identifier
1253   * @note For STM32F405/407xx and STM32F415/417xx devices, the device ID is 0x413
1254   * @note For STM32F42xxx and STM32F43xxx devices, the device ID is 0x419
1255   * @note For STM32F401xx devices, the device ID is 0x423
1256   * @note For STM32F401xx devices, the device ID is 0x433
1257   * @note For STM32F411xx devices, the device ID is 0x431
1258   * @note For STM32F410xx devices, the device ID is 0x458
1259   * @note For STM32F412xx devices, the device ID is 0x441
1260   * @note For STM32F413xx and STM32423xx devices, the device ID is 0x463
1261   * @note For STM32F446xx devices, the device ID is 0x421
1262   * @note For STM32F469xx and STM32F479xx devices, the device ID is 0x434
1263   * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
1264   * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
1265   */
1266 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1267 {
1268   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1269 }
1270
1271 /**
1272   * @brief  Return the device revision identifier
1273   * @note This field indicates the revision of the device.
1274           For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001, rev1 -> 0x1003, rev2 ->0x1007, revY -> 0x100F for STM32F405/407xx and STM32F415/417xx devices
1275           For example, it is read as RevA -> 0x1000, Cat 2 revY -> 0x1003, rev1 -> 0x1007, rev3 ->0x2001 for STM32F42xxx and STM32F43xxx devices
1276           For example, it is read as RevZ -> 0x1000, Cat 2 revA -> 0x1001 for STM32F401xB/C devices
1277           For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 for STM32F401xD/E devices
1278           For example, it is read as RevA -> 0x1000 for STM32F411xx,STM32F413/423xx,STM32F469/423xx, STM32F446xx and STM32F410xx devices
1279           For example, it is read as RevZ -> 0x1001, Cat 2 revB -> 0x2000, revC -> 0x3000 for STM32F412xx devices
1280   * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
1281   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1282   */
1283 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1284 {
1285   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1286 }
1287
1288 /**
1289   * @brief  Enable the Debug Module during SLEEP mode
1290   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
1291   * @retval None
1292   */
1293 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
1294 {
1295   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1296 }
1297
1298 /**
1299   * @brief  Disable the Debug Module during SLEEP mode
1300   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
1301   * @retval None
1302   */
1303 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
1304 {
1305   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1306 }
1307
1308 /**
1309   * @brief  Enable the Debug Module during STOP mode
1310   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
1311   * @retval None
1312   */
1313 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1314 {
1315   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1316 }
1317
1318 /**
1319   * @brief  Disable the Debug Module during STOP mode
1320   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
1321   * @retval None
1322   */
1323 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1324 {
1325   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1326 }
1327
1328 /**
1329   * @brief  Enable the Debug Module during STANDBY mode
1330   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
1331   * @retval None
1332   */
1333 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1334 {
1335   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1336 }
1337
1338 /**
1339   * @brief  Disable the Debug Module during STANDBY mode
1340   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
1341   * @retval None
1342   */
1343 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1344 {
1345   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1346 }
1347
1348 /**
1349   * @brief  Set Trace pin assignment control
1350   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\n
1351   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment
1352   * @param  PinAssignment This parameter can be one of the following values:
1353   *         @arg @ref LL_DBGMCU_TRACE_NONE
1354   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
1355   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1356   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1357   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1358   * @retval None
1359   */
1360 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1361 {
1362   MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
1363 }
1364
1365 /**
1366   * @brief  Get Trace pin assignment control
1367   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\n
1368   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment
1369   * @retval Returned value can be one of the following values:
1370   *         @arg @ref LL_DBGMCU_TRACE_NONE
1371   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
1372   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1373   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1374   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1375   */
1376 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
1377 {
1378   return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
1379 }
1380
1381 /**
1382   * @brief  Freeze APB1 peripherals (group1 peripherals)
1383   * @rmtoll DBGMCU_APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1384   *         DBGMCU_APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1385   *         DBGMCU_APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1386   *         DBGMCU_APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1387   *         DBGMCU_APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1388   *         DBGMCU_APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1389   *         DBGMCU_APB1_FZ      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1390   *         DBGMCU_APB1_FZ      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1391   *         DBGMCU_APB1_FZ      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1392   *         DBGMCU_APB1_FZ      DBG_LPTIM_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1393   *         DBGMCU_APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1394   *         DBGMCU_APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1395   *         DBGMCU_APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1396   *         DBGMCU_APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1397   *         DBGMCU_APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1398   *         DBGMCU_APB1_FZ      DBG_I2C3_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1399   *         DBGMCU_APB1_FZ      DBG_I2C4_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1400   *         DBGMCU_APB1_FZ      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1401   *         DBGMCU_APB1_FZ      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1402   *         DBGMCU_APB1_FZ      DBG_CAN3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph
1403   * @param  Periphs This parameter can be a combination of the following values:
1404   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
1405   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1406   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1407   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1408   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
1409   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1410   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
1411   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
1412   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
1413   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
1414   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1415   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1416   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1417   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1418   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1419   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
1420   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
1421   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
1422   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
1423   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
1424   *
1425   *         (*) value not defined in all devices.
1426   * @retval None
1427   */
1428 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1429 {
1430   SET_BIT(DBGMCU->APB1FZ, Periphs);
1431 }
1432
1433 /**
1434   * @brief  Unfreeze APB1 peripherals (group1 peripherals)
1435   * @rmtoll DBGMCU_APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1436   *         DBGMCU_APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1437   *         DBGMCU_APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1438   *         DBGMCU_APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1439   *         DBGMCU_APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1440   *         DBGMCU_APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1441   *         DBGMCU_APB1_FZ      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1442   *         DBGMCU_APB1_FZ      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1443   *         DBGMCU_APB1_FZ      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1444   *         DBGMCU_APB1_FZ      DBG_LPTIM_STOP         LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1445   *         DBGMCU_APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1446   *         DBGMCU_APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1447   *         DBGMCU_APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1448   *         DBGMCU_APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1449   *         DBGMCU_APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1450   *         DBGMCU_APB1_FZ      DBG_I2C3_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1451   *         DBGMCU_APB1_FZ      DBG_I2C4_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1452   *         DBGMCU_APB1_FZ      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1453   *         DBGMCU_APB1_FZ      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1454   *         DBGMCU_APB1_FZ      DBG_CAN3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1455   * @param  Periphs This parameter can be a combination of the following values:
1456   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
1457   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1458   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1459   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1460   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
1461   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1462   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
1463   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
1464   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
1465   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
1466   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1467   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1468   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1469   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1470   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1471   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
1472   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
1473   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
1474   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
1475   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
1476   *
1477   *         (*) value not defined in all devices.
1478   * @retval None
1479   */
1480 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1481 {
1482   CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
1483 }
1484
1485 /**
1486   * @brief  Freeze APB2 peripherals
1487   * @rmtoll DBGMCU_APB2_FZ      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1488   *         DBGMCU_APB2_FZ      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1489   *         DBGMCU_APB2_FZ      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1490   *         DBGMCU_APB2_FZ      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1491   *         DBGMCU_APB2_FZ      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph
1492   * @param  Periphs This parameter can be a combination of the following values:
1493   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1494   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1495   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
1496   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
1497   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
1498   *
1499   *         (*) value not defined in all devices.
1500   * @retval None
1501   */
1502 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1503 {
1504   SET_BIT(DBGMCU->APB2FZ, Periphs);
1505 }
1506
1507 /**
1508   * @brief  Unfreeze APB2 peripherals
1509   * @rmtoll DBGMCU_APB2_FZ      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1510   *         DBGMCU_APB2_FZ      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1511   *         DBGMCU_APB2_FZ      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1512   *         DBGMCU_APB2_FZ      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1513   *         DBGMCU_APB2_FZ      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1514   * @param  Periphs This parameter can be a combination of the following values:
1515   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1516   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1517   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
1518   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
1519   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
1520   *
1521   *         (*) value not defined in all devices.
1522   * @retval None
1523   */
1524 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1525 {
1526   CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
1527 }
1528 /**
1529   * @}
1530   */
1531
1532 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1533   * @{
1534   */
1535
1536 /**
1537   * @brief  Set FLASH Latency
1538   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
1539   * @param  Latency This parameter can be one of the following values:
1540   *         @arg @ref LL_FLASH_LATENCY_0
1541   *         @arg @ref LL_FLASH_LATENCY_1
1542   *         @arg @ref LL_FLASH_LATENCY_2
1543   *         @arg @ref LL_FLASH_LATENCY_3
1544   *         @arg @ref LL_FLASH_LATENCY_4
1545   *         @arg @ref LL_FLASH_LATENCY_5
1546   *         @arg @ref LL_FLASH_LATENCY_6
1547   *         @arg @ref LL_FLASH_LATENCY_7
1548   *         @arg @ref LL_FLASH_LATENCY_8
1549   *         @arg @ref LL_FLASH_LATENCY_9
1550   *         @arg @ref LL_FLASH_LATENCY_10
1551   *         @arg @ref LL_FLASH_LATENCY_11
1552   *         @arg @ref LL_FLASH_LATENCY_12
1553   *         @arg @ref LL_FLASH_LATENCY_13
1554   *         @arg @ref LL_FLASH_LATENCY_14
1555   *         @arg @ref LL_FLASH_LATENCY_15
1556   * @retval None
1557   */
1558 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1559 {
1560   MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1561 }
1562
1563 /**
1564   * @brief  Get FLASH Latency
1565   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
1566   * @retval Returned value can be one of the following values:
1567   *         @arg @ref LL_FLASH_LATENCY_0
1568   *         @arg @ref LL_FLASH_LATENCY_1
1569   *         @arg @ref LL_FLASH_LATENCY_2
1570   *         @arg @ref LL_FLASH_LATENCY_3
1571   *         @arg @ref LL_FLASH_LATENCY_4
1572   *         @arg @ref LL_FLASH_LATENCY_5
1573   *         @arg @ref LL_FLASH_LATENCY_6
1574   *         @arg @ref LL_FLASH_LATENCY_7
1575   *         @arg @ref LL_FLASH_LATENCY_8
1576   *         @arg @ref LL_FLASH_LATENCY_9
1577   *         @arg @ref LL_FLASH_LATENCY_10
1578   *         @arg @ref LL_FLASH_LATENCY_11
1579   *         @arg @ref LL_FLASH_LATENCY_12
1580   *         @arg @ref LL_FLASH_LATENCY_13
1581   *         @arg @ref LL_FLASH_LATENCY_14
1582   *         @arg @ref LL_FLASH_LATENCY_15
1583   */
1584 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1585 {
1586   return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1587 }
1588
1589 /**
1590   * @brief  Enable Prefetch
1591   * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_EnablePrefetch
1592   * @retval None
1593   */
1594 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1595 {
1596   SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1597 }
1598
1599 /**
1600   * @brief  Disable Prefetch
1601   * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_DisablePrefetch
1602   * @retval None
1603   */
1604 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1605 {
1606   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1607 }
1608
1609 /**
1610   * @brief  Check if Prefetch buffer is enabled
1611   * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_IsPrefetchEnabled
1612   * @retval State of bit (1 or 0).
1613   */
1614 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1615 {
1616   return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
1617 }
1618
1619 /**
1620   * @brief  Enable Instruction cache
1621   * @rmtoll FLASH_ACR    ICEN          LL_FLASH_EnableInstCache
1622   * @retval None
1623   */
1624 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
1625 {
1626   SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1627 }
1628
1629 /**
1630   * @brief  Disable Instruction cache
1631   * @rmtoll FLASH_ACR    ICEN          LL_FLASH_DisableInstCache
1632   * @retval None
1633   */
1634 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
1635 {
1636   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1637 }
1638
1639 /**
1640   * @brief  Enable Data cache
1641   * @rmtoll FLASH_ACR    DCEN          LL_FLASH_EnableDataCache
1642   * @retval None
1643   */
1644 __STATIC_INLINE void LL_FLASH_EnableDataCache(void)
1645 {
1646   SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1647 }
1648
1649 /**
1650   * @brief  Disable Data cache
1651   * @rmtoll FLASH_ACR    DCEN          LL_FLASH_DisableDataCache
1652   * @retval None
1653   */
1654 __STATIC_INLINE void LL_FLASH_DisableDataCache(void)
1655 {
1656   CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1657 }
1658
1659 /**
1660   * @brief  Enable Instruction cache reset
1661   * @note  bit can be written only when the instruction cache is disabled
1662   * @rmtoll FLASH_ACR    ICRST         LL_FLASH_EnableInstCacheReset
1663   * @retval None
1664   */
1665 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
1666 {
1667   SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1668 }
1669
1670 /**
1671   * @brief  Disable Instruction cache reset
1672   * @rmtoll FLASH_ACR    ICRST         LL_FLASH_DisableInstCacheReset
1673   * @retval None
1674   */
1675 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
1676 {
1677   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1678 }
1679
1680 /**
1681   * @brief  Enable Data cache reset
1682   * @note bit can be written only when the data cache is disabled
1683   * @rmtoll FLASH_ACR    DCRST         LL_FLASH_EnableDataCacheReset
1684   * @retval None
1685   */
1686 __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
1687 {
1688   SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1689 }
1690
1691 /**
1692   * @brief  Disable Data cache reset
1693   * @rmtoll FLASH_ACR    DCRST         LL_FLASH_DisableDataCacheReset
1694   * @retval None
1695   */
1696 __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
1697 {
1698   CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1699 }
1700
1701
1702 /**
1703   * @}
1704   */
1705
1706 /**
1707   * @}
1708   */
1709
1710 /**
1711   * @}
1712   */
1713
1714 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
1715
1716 /**
1717   * @}
1718   */
1719
1720 #ifdef __cplusplus
1721 }
1722 #endif
1723
1724 #endif /* __STM32F4xx_LL_SYSTEM_H */
1725
1726 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/