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[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_hal_dma2d.c
blob17030558488678ea082097a125fa84e6cd958038
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_dma2d.c
4 * @author MCD Application Team
5 * @brief DMA2D HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the DMA2D peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State and Errors functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### How to use this driver #####
16 ==============================================================================
17 [..]
18 (#) Program the required configuration through the following parameters:
19 the transfer mode, the output color mode and the output offset using
20 HAL_DMA2D_Init() function.
21
22 (#) Program the required configuration through the following parameters:
23 the input color mode, the input color, the input alpha value, the alpha mode,
24 the red/blue swap mode, the inverted alpha mode and the input offset using
25 HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
26
27 *** Polling mode IO operation ***
28 =================================
29 [..]
30 (#) Configure pdata parameter (explained hereafter), destination and data length
31 and enable the transfer using HAL_DMA2D_Start().
32 (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
33 user can specify the value of timeout according to his end application.
34
35 *** Interrupt mode IO operation ***
36 ===================================
37 [..]
38 (#) Configure pdata parameter, destination and data length and enable
39 the transfer using HAL_DMA2D_Start_IT().
40 (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
41 (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
42 add his own function by customization of function pointer XferCpltCallback (member
43 of DMA2D handle structure).
44 (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback
45 XferErrorCallback.
46
47 -@- In Register-to-Memory transfer mode, pdata parameter is the register
48 color, in Memory-to-memory or Memory-to-Memory with pixel format
49 conversion pdata is the source address.
50
51 -@- Configure the foreground source address, the background source address,
52 the destination and data length then Enable the transfer using
53 HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
54 in interrupt mode.
55
56 -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
57 are used if the memory to memory with blending transfer mode is selected.
58
59 (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
60 mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
61
62 (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent().
63
64 (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
65 consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
66 and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
67 HAL_DMA2D_DisableDeadTime().
68
69 (#) The transfer can be suspended, resumed and aborted using the following
70 functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
71
72 (#) The CLUT loading can be suspended, resumed and aborted using the following
73 functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
74 HAL_DMA2D_CLUTLoading_Abort().
75
76 (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
77
78 (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
79
80 *** DMA2D HAL driver macros list ***
81 =============================================
82 [..]
83 Below the list of most used macros in DMA2D HAL driver :
84
85 (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
86 (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
87 (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
88 (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
89 (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
90 (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
91
92 *** Callback registration ***
93 ===================================
94 [..]
95 (#) The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1
96 allows the user to configure dynamically the driver callbacks.
97 Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback.
98
99 (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks:
100 (+) XferCpltCallback : callback for transfer complete.
101 (+) XferErrorCallback : callback for transfer error.
102 (+) LineEventCallback : callback for line event.
103 (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
104 (+) MspInitCallback : DMA2D MspInit.
105 (+) MspDeInitCallback : DMA2D MspDeInit.
106 This function takes as parameters the HAL peripheral handle, the Callback ID
107 and a pointer to the user callback function.
108
109 (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
110 weak (surcharged) function.
111 @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
112 and the Callback ID.
113 This function allows to reset following callbacks:
114 (+) XferCpltCallback : callback for transfer complete.
115 (+) XferErrorCallback : callback for transfer error.
116 (+) LineEventCallback : callback for line event.
117 (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
118 (+) MspInitCallback : DMA2D MspInit.
119 (+) MspDeInitCallback : DMA2D MspDeInit.
120
121 (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
122 all callbacks are reset to the corresponding legacy weak (surcharged) functions:
123 examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
124 Exception done for MspInit and MspDeInit callbacks that are respectively
125 reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
126 and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
127 If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
128 keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
129
130 Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
131 as weak (surcharged) functions. They must be defined by the user to be resorted to.
132
133 Callbacks can be registered/unregistered in READY state only.
134 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
135 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
136 during the Init/DeInit.
137 In that case first register the MspInit/MspDeInit user callbacks
138 using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit
139 or @ref HAL_DMA2D_Init function.
140
141 When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
142 not defined, the callback registering feature is not available
143 and weak (surcharged) callbacks are used.
144
145 [..]
146 (@) You can refer to the DMA2D HAL driver header file for more useful macros
147
148 @endverbatim
149 ******************************************************************************
150 * @attention
151 *
152 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
153 * All rights reserved.</center></h2>
154 *
155 * This software component is licensed by ST under BSD 3-Clause license,
156 * the "License"; You may not use this file except in compliance with the
157 * License. You may obtain a copy of the License at:
158 * opensource.org/licenses/BSD-3-Clause
159 *
160 ******************************************************************************
161 */
162
163 /* Includes ------------------------------------------------------------------*/
164 #include "stm32h7xx_hal.h"
165
166 #ifdef HAL_DMA2D_MODULE_ENABLED
167 #if defined (DMA2D)
168
169 /** @addtogroup STM32H7xx_HAL_Driver
170 * @{
171 */
172
173 /** @defgroup DMA2D DMA2D
174 * @brief DMA2D HAL module driver
175 * @{
176 */
177
178 /* Private types -------------------------------------------------------------*/
179 /* Private define ------------------------------------------------------------*/
180 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
181 * @{
182 */
183
184 /** @defgroup DMA2D_TimeOut DMA2D Time Out
185 * @{
186 */
187 #define DMA2D_TIMEOUT_ABORT (1000U) /*!< 1s */
188 #define DMA2D_TIMEOUT_SUSPEND (1000U) /*!< 1s */
189 /**
190 * @}
191 */
192
193 /**
194 * @}
195 */
196
197 /* Private variables ---------------------------------------------------------*/
198 /* Private constants ---------------------------------------------------------*/
199 /* Private macro -------------------------------------------------------------*/
200 /* Private function prototypes -----------------------------------------------*/
201 /** @addtogroup DMA2D_Private_Functions DMA2D Private Functions
202 * @{
203 */
204 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
205 /**
206 * @}
207 */
208
209 /* Private functions ---------------------------------------------------------*/
210 /* Exported functions --------------------------------------------------------*/
211 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
212 * @{
213 */
214
215 /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
216 * @brief Initialization and Configuration functions
217 *
218 @verbatim
219 ===============================================================================
220 ##### Initialization and Configuration functions #####
221 ===============================================================================
222 [..] This section provides functions allowing to:
223 (+) Initialize and configure the DMA2D
224 (+) De-initialize the DMA2D
225
226 @endverbatim
227 * @{
228 */
229
230 /**
231 * @brief Initialize the DMA2D according to the specified
232 * parameters in the DMA2D_InitTypeDef and create the associated handle.
233 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
234 * the configuration information for the DMA2D.
235 * @retval HAL status
236 */
237 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
238 {
239 /* Check the DMA2D peripheral state */
240 if(hdma2d == NULL)
241 {
242 return HAL_ERROR;
243 }
244
245 /* Check the parameters */
246 assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
247 assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
248 assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
249 assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
250 assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->Init.AlphaInverted));
251 assert_param(IS_DMA2D_RB_SWAP(hdma2d->Init.RedBlueSwap));
252 assert_param(IS_DMA2D_LOM_MODE(hdma2d->Init.LineOffsetMode));
253 assert_param(IS_DMA2D_BYTES_SWAP(hdma2d->Init.BytesSwap));
254
255 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
256 if (hdma2d->State == HAL_DMA2D_STATE_RESET)
257 {
258 /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */
259 hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
260 hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
261 if(hdma2d->MspInitCallback == NULL)
262 {
263 hdma2d->MspInitCallback = HAL_DMA2D_MspInit;
264 }
265
266 /* Init the low level hardware */
267 hdma2d->MspInitCallback(hdma2d);
268 }
269 #else
270 if(hdma2d->State == HAL_DMA2D_STATE_RESET)
271 {
272 /* Allocate lock resource and initialize it */
273 hdma2d->Lock = HAL_UNLOCKED;
274 /* Init the low level hardware */
275 HAL_DMA2D_MspInit(hdma2d);
276 }
277 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
278
279 /* Change DMA2D peripheral state */
280 hdma2d->State = HAL_DMA2D_STATE_BUSY;
281
282 /* DMA2D CR register configuration -------------------------------------------*/
283 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE | DMA2D_CR_LOM, hdma2d->Init.Mode | hdma2d->Init.LineOffsetMode);
284
285 /* DMA2D OPFCCR register configuration ---------------------------------------*/
286 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB, hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap);
287
288 /* DMA2D OOR register configuration ------------------------------------------*/
289 MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
290 /* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/
291 MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
292
293
294 /* Update error code */
295 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
296
297 /* Initialize the DMA2D state*/
298 hdma2d->State = HAL_DMA2D_STATE_READY;
299
300 return HAL_OK;
301 }
302
303 /**
304 * @brief Deinitializes the DMA2D peripheral registers to their default reset
305 * values.
306 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
307 * the configuration information for the DMA2D.
308 * @retval None
309 */
310
311 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
312 {
313
314 /* Check the DMA2D peripheral state */
315 if(hdma2d == NULL)
316 {
317 return HAL_ERROR;
318 }
319
320 /* Before aborting any DMA2D transfer or CLUT loading, check
321 first whether or not DMA2D clock is enabled */
322 if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
323 {
324 /* Abort DMA2D transfer if any */
325 if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
326 {
327 if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
328 {
329 /* Issue when aborting DMA2D transfer */
330 return HAL_ERROR;
331 }
332 }
333 else
334 {
335 /* Abort background CLUT loading if any */
336 if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
337 {
338 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
339 {
340 /* Issue when aborting background CLUT loading */
341 return HAL_ERROR;
342 }
343 }
344 else
345 {
346 /* Abort foreground CLUT loading if any */
347 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
348 {
349 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
350 {
351 /* Issue when aborting foreground CLUT loading */
352 return HAL_ERROR;
353 }
354 }
355 }
356 }
357 }
358
359 /* Reset DMA2D control registers*/
360 hdma2d->Instance->CR = 0U;
361 hdma2d->Instance->IFCR = 0x3FU;
362 hdma2d->Instance->FGOR = 0U;
363 hdma2d->Instance->BGOR = 0U;
364 hdma2d->Instance->FGPFCCR = 0U;
365 hdma2d->Instance->BGPFCCR = 0U;
366 hdma2d->Instance->OPFCCR = 0U;
367
368 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
369
370 if(hdma2d->MspDeInitCallback == NULL)
371 {
372 hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
373 }
374
375 /* DeInit the low level hardware */
376 hdma2d->MspDeInitCallback(hdma2d);
377
378 #else
379 /* Carry on with de-initialization of low level hardware */
380 HAL_DMA2D_MspDeInit(hdma2d);
381 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
382
383 /* Update error code */
384 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
385
386 /* Initialize the DMA2D state*/
387 hdma2d->State = HAL_DMA2D_STATE_RESET;
388
389 /* Release Lock */
390 __HAL_UNLOCK(hdma2d);
391
392 return HAL_OK;
393 }
394
395 /**
396 * @brief Initializes the DMA2D MSP.
397 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
398 * the configuration information for the DMA2D.
399 * @retval None
400 */
401 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
402 {
403 /* Prevent unused argument(s) compilation warning */
404 UNUSED(hdma2d);
405
406 /* NOTE : This function should not be modified; when the callback is needed,
407 the HAL_DMA2D_MspInit can be implemented in the user file.
408 */
409 }
410
411 /**
412 * @brief DeInitializes the DMA2D MSP.
413 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
414 * the configuration information for the DMA2D.
415 * @retval None
416 */
417 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
418 {
419 /* Prevent unused argument(s) compilation warning */
420 UNUSED(hdma2d);
421
422 /* NOTE : This function should not be modified; when the callback is needed,
423 the HAL_DMA2D_MspDeInit can be implemented in the user file.
424 */
425 }
426
427 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
428 /**
429 * @brief Register a User DMA2D Callback
430 * To be used instead of the weak (surcharged) predefined callback
431 * @param hdma2d DMA2D handle
432 * @param CallbackID ID of the callback to be registered
433 * This parameter can be one of the following values:
434 * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
435 * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
436 * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
437 * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
438 * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
439 * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
440 * @param pCallback pointer to the Callback function
441 * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
442 * @retval status
443 */
444 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback)
445 {
446 HAL_StatusTypeDef status = HAL_OK;
447
448 if(pCallback == NULL)
449 {
450 /* Update the error code */
451 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
452 return HAL_ERROR;
453 }
454 /* Process locked */
455 __HAL_LOCK(hdma2d);
456
457 if(HAL_DMA2D_STATE_READY == hdma2d->State)
458 {
459 switch (CallbackID)
460 {
461 case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
462 hdma2d->XferCpltCallback = pCallback;
463 break;
464
465 case HAL_DMA2D_TRANSFERERROR_CB_ID :
466 hdma2d->XferErrorCallback = pCallback;
467 break;
468
469 case HAL_DMA2D_LINEEVENT_CB_ID :
470 hdma2d->LineEventCallback = pCallback;
471 break;
472
473 case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
474 hdma2d->CLUTLoadingCpltCallback = pCallback;
475 break;
476
477 case HAL_DMA2D_MSPINIT_CB_ID :
478 hdma2d->MspInitCallback = pCallback;
479 break;
480
481 case HAL_DMA2D_MSPDEINIT_CB_ID :
482 hdma2d->MspDeInitCallback = pCallback;
483 break;
484
485 default :
486 /* Update the error code */
487 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
488 /* update return status */
489 status = HAL_ERROR;
490 break;
491 }
492 }
493 else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
494 {
495 switch (CallbackID)
496 {
497 case HAL_DMA2D_MSPINIT_CB_ID :
498 hdma2d->MspInitCallback = pCallback;
499 break;
500
501 case HAL_DMA2D_MSPDEINIT_CB_ID :
502 hdma2d->MspDeInitCallback = pCallback;
503 break;
504
505 default :
506 /* Update the error code */
507 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
508 /* update return status */
509 status = HAL_ERROR;
510 break;
511 }
512 }
513 else
514 {
515 /* Update the error code */
516 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
517 /* update return status */
518 status = HAL_ERROR;
519 }
520
521 /* Release Lock */
522 __HAL_UNLOCK(hdma2d);
523 return status;
524 }
525
526 /**
527 * @brief Unregister a DMA2D Callback
528 * DMA2D Callback is redirected to the weak (surcharged) predefined callback
529 * @param hdma2d DMA2D handle
530 * @param CallbackID ID of the callback to be unregistered
531 * This parameter can be one of the following values:
532 * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
533 * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
534 * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
535 * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
536 * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
537 * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
538 * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
539 * @retval status
540 */
541 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
542 {
543 HAL_StatusTypeDef status = HAL_OK;
544
545 /* Process locked */
546 __HAL_LOCK(hdma2d);
547
548 if(HAL_DMA2D_STATE_READY == hdma2d->State)
549 {
550 switch (CallbackID)
551 {
552 case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
553 hdma2d->XferCpltCallback = NULL;
554 break;
555
556 case HAL_DMA2D_TRANSFERERROR_CB_ID :
557 hdma2d->XferErrorCallback = NULL;
558 break;
559
560 case HAL_DMA2D_LINEEVENT_CB_ID :
561 hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
562 break;
563
564 case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
565 hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
566 break;
567
568 case HAL_DMA2D_MSPINIT_CB_ID :
569 hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
570 break;
571
572 case HAL_DMA2D_MSPDEINIT_CB_ID :
573 hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
574 break;
575
576 default :
577 /* Update the error code */
578 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
579 /* update return status */
580 status = HAL_ERROR;
581 break;
582 }
583 }
584 else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
585 {
586 switch (CallbackID)
587 {
588 case HAL_DMA2D_MSPINIT_CB_ID :
589 hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
590 break;
591
592 case HAL_DMA2D_MSPDEINIT_CB_ID :
593 hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
594 break;
595
596 default :
597 /* Update the error code */
598 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
599 /* update return status */
600 status = HAL_ERROR;
601 break;
602 }
603 }
604 else
605 {
606 /* Update the error code */
607 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
608 /* update return status */
609 status = HAL_ERROR;
610 }
611
612 /* Release Lock */
613 __HAL_UNLOCK(hdma2d);
614 return status;
615 }
616 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
617
618 /**
619 * @}
620 */
621
622
623 /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
624 * @brief IO operation functions
625 *
626 @verbatim
627 ===============================================================================
628 ##### IO operation functions #####
629 ===============================================================================
630 [..] This section provides functions allowing to:
631 (+) Configure the pdata, destination address and data size then
632 start the DMA2D transfer.
633 (+) Configure the source for foreground and background, destination address
634 and data size then start a MultiBuffer DMA2D transfer.
635 (+) Configure the pdata, destination address and data size then
636 start the DMA2D transfer with interrupt.
637 (+) Configure the source for foreground and background, destination address
638 and data size then start a MultiBuffer DMA2D transfer with interrupt.
639 (+) Abort DMA2D transfer.
640 (+) Suspend DMA2D transfer.
641 (+) Resume DMA2D transfer.
642 (+) Enable CLUT transfer.
643 (+) Configure CLUT loading then start transfer in polling mode.
644 (+) Configure CLUT loading then start transfer in interrupt mode.
645 (+) Abort DMA2D CLUT loading.
646 (+) Suspend DMA2D CLUT loading.
647 (+) Resume DMA2D CLUT loading.
648 (+) Poll for transfer complete.
649 (+) handle DMA2D interrupt request.
650 (+) Transfer watermark callback.
651 (+) CLUT Transfer Complete callback.
652
653
654 @endverbatim
655 * @{
656 */
657
658 /**
659 * @brief Start the DMA2D Transfer.
660 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
661 * the configuration information for the DMA2D.
662 * @param pdata Configure the source memory Buffer address if
663 * Memory-to-Memory or Memory-to-Memory with pixel format
664 * conversion mode is selected, or configure
665 * the color value if Register-to-Memory mode is selected.
666 * @param DstAddress The destination memory Buffer address.
667 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
668 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
669 * @retval HAL status
670 */
671 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
672 {
673 /* Check the parameters */
674 assert_param(IS_DMA2D_LINE(Height));
675 assert_param(IS_DMA2D_PIXEL(Width));
676
677 /* Process locked */
678 __HAL_LOCK(hdma2d);
679
680 /* Change DMA2D peripheral state */
681 hdma2d->State = HAL_DMA2D_STATE_BUSY;
682
683 /* Configure the source, destination address and the data size */
684 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
685
686 /* Enable the Peripheral */
687 __HAL_DMA2D_ENABLE(hdma2d);
688
689 return HAL_OK;
690 }
691
692 /**
693 * @brief Start the DMA2D Transfer with interrupt enabled.
694 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
695 * the configuration information for the DMA2D.
696 * @param pdata Configure the source memory Buffer address if
697 * the Memory-to-Memory or Memory-to-Memory with pixel format
698 * conversion mode is selected, or configure
699 * the color value if Register-to-Memory mode is selected.
700 * @param DstAddress The destination memory Buffer address.
701 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
702 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
703 * @retval HAL status
704 */
705 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
706 {
707 /* Check the parameters */
708 assert_param(IS_DMA2D_LINE(Height));
709 assert_param(IS_DMA2D_PIXEL(Width));
710
711 /* Process locked */
712 __HAL_LOCK(hdma2d);
713
714 /* Change DMA2D peripheral state */
715 hdma2d->State = HAL_DMA2D_STATE_BUSY;
716
717 /* Configure the source, destination address and the data size */
718 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
719
720 /* Enable the transfer complete, transfer error and configuration error interrupts */
721 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
722
723 /* Enable the Peripheral */
724 __HAL_DMA2D_ENABLE(hdma2d);
725
726 return HAL_OK;
727 }
728
729 /**
730 * @brief Start the multi-source DMA2D Transfer.
731 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
732 * the configuration information for the DMA2D.
733 * @param SrcAddress1 The source memory Buffer address for the foreground layer.
734 * @param SrcAddress2 The source memory Buffer address for the background layer.
735 * @param DstAddress The destination memory Buffer address.
736 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
737 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
738 * @retval HAL status
739 */
740 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
741 {
742 /* Check the parameters */
743 assert_param(IS_DMA2D_LINE(Height));
744 assert_param(IS_DMA2D_PIXEL(Width));
745
746 /* Process locked */
747 __HAL_LOCK(hdma2d);
748
749 /* Change DMA2D peripheral state */
750 hdma2d->State = HAL_DMA2D_STATE_BUSY;
751
752 if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
753 {
754 /*blending & fixed FG*/
755 WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
756 /* Configure the source, destination address and the data size */
757 DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height);
758 }
759 else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG)
760 {
761 /*blending & fixed BG*/
762 WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2);
763 /* Configure the source, destination address and the data size */
764 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
765 }
766 else
767 {
768 /* Configure DMA2D Stream source2 address */
769 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
770
771 /* Configure the source, destination address and the data size */
772 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
773 }
774
775 /* Enable the Peripheral */
776 __HAL_DMA2D_ENABLE(hdma2d);
777
778 return HAL_OK;
779 }
780
781 /**
782 * @brief Start the multi-source DMA2D Transfer with interrupt enabled.
783 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
784 * the configuration information for the DMA2D.
785 * @param SrcAddress1 The source memory Buffer address for the foreground layer.
786 * @param SrcAddress2 The source memory Buffer address for the background layer.
787 * @param DstAddress The destination memory Buffer address.
788 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
789 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
790 * @retval HAL status
791 */
792 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
793 {
794 /* Check the parameters */
795 assert_param(IS_DMA2D_LINE(Height));
796 assert_param(IS_DMA2D_PIXEL(Width));
797
798 /* Process locked */
799 __HAL_LOCK(hdma2d);
800
801 /* Change DMA2D peripheral state */
802 hdma2d->State = HAL_DMA2D_STATE_BUSY;
803
804 if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
805 {
806 /*blending & fixed FG*/
807 WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
808 /* Configure the source, destination address and the data size */
809 DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height);
810 }
811 else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG)
812 {
813 /*blending & fixed BG*/
814 WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2);
815 /* Configure the source, destination address and the data size */
816 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
817 }
818 else
819 {
820 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
821
822 /* Configure the source, destination address and the data size */
823 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
824 }
825
826 /* Enable the transfer complete, transfer error and configuration error interrupts */
827 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
828
829 /* Enable the Peripheral */
830 __HAL_DMA2D_ENABLE(hdma2d);
831
832 return HAL_OK;
833 }
834
835 /**
836 * @brief Abort the DMA2D Transfer.
837 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
838 * the configuration information for the DMA2D.
839 * @retval HAL status
840 */
841 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
842 {
843 uint32_t tickstart;
844
845 /* Abort the DMA2D transfer */
846 /* START bit is reset to make sure not to set it again, in the event the HW clears it
847 between the register read and the register write by the CPU (writing 0 has no
848 effect on START bitvalue) */
849 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
850
851 /* Get tick */
852 tickstart = HAL_GetTick();
853
854 /* Check if the DMA2D is effectively disabled */
855 while((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
856 {
857 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
858 {
859 /* Update error code */
860 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
861
862 /* Change the DMA2D state */
863 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
864
865 /* Process Unlocked */
866 __HAL_UNLOCK(hdma2d);
867
868 return HAL_TIMEOUT;
869 }
870 }
871
872 /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
873 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
874
875 /* Change the DMA2D state*/
876 hdma2d->State = HAL_DMA2D_STATE_READY;
877
878 /* Process Unlocked */
879 __HAL_UNLOCK(hdma2d);
880
881 return HAL_OK;
882 }
883
884 /**
885 * @brief Suspend the DMA2D Transfer.
886 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
887 * the configuration information for the DMA2D.
888 * @retval HAL status
889 */
890 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
891 {
892 uint32_t tickstart;
893
894 /* Suspend the DMA2D transfer */
895 /* START bit is reset to make sure not to set it again, in the event the HW clears it
896 between the register read and the register write by the CPU (writing 0 has no
897 effect on START bitvalue). */
898 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
899
900 /* Get tick */
901 tickstart = HAL_GetTick();
902
903 /* Check if the DMA2D is effectively suspended */
904 while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)
905 {
906 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
907 {
908 /* Update error code */
909 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
910
911 /* Change the DMA2D state */
912 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
913
914 return HAL_TIMEOUT;
915 }
916 }
917
918 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
919 if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
920 {
921 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
922 }
923 else
924 {
925 /* Make sure SUSP bit is cleared since it is meaningless
926 when no tranfer is on-going */
927 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
928 }
929
930 return HAL_OK;
931 }
932
933 /**
934 * @brief Resume the DMA2D Transfer.
935 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
936 * the configuration information for the DMA2D.
937 * @retval HAL status
938 */
939 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
940 {
941 /* Check the SUSP and START bits */
942 if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
943 {
944 /* Ongoing transfer is suspended: change the DMA2D state before resuming */
945 hdma2d->State = HAL_DMA2D_STATE_BUSY;
946 }
947
948 /* Resume the DMA2D transfer */
949 /* START bit is reset to make sure not to set it again, in the event the HW clears it
950 between the register read and the register write by the CPU (writing 0 has no
951 effect on START bitvalue). */
952 CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
953
954 return HAL_OK;
955 }
956
957
958 /**
959 * @brief Enable the DMA2D CLUT Transfer.
960 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
961 * the configuration information for the DMA2D.
962 * @param LayerIdx DMA2D Layer index.
963 * This parameter can be one of the following values:
964 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
965 * @retval HAL status
966 */
967 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
968 {
969 /* Check the parameters */
970 assert_param(IS_DMA2D_LAYER(LayerIdx));
971
972 /* Process locked */
973 __HAL_LOCK(hdma2d);
974
975 /* Change DMA2D peripheral state */
976 hdma2d->State = HAL_DMA2D_STATE_BUSY;
977
978 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
979 {
980 /* Enable the background CLUT loading */
981 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
982 }
983 else
984 {
985 /* Enable the foreground CLUT loading */
986 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
987 }
988
989 return HAL_OK;
990 }
991
992 /**
993 * @brief Start DMA2D CLUT Loading.
994 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
995 * the configuration information for the DMA2D.
996 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
997 * the configuration information for the color look up table.
998 * @param LayerIdx DMA2D Layer index.
999 * This parameter can be one of the following values:
1000 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1001 * @retval HAL status
1002 */
1003 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx)
1004 {
1005 /* Check the parameters */
1006 assert_param(IS_DMA2D_LAYER(LayerIdx));
1007 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
1008 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
1009
1010 /* Process locked */
1011 __HAL_LOCK(hdma2d);
1012
1013 /* Change DMA2D peripheral state */
1014 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1015
1016 /* Configure the CLUT of the background DMA2D layer */
1017 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1018 {
1019 /* Write background CLUT memory address */
1020 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
1021
1022 /* Write background CLUT size and CLUT color mode */
1023 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1024 ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1025
1026 /* Enable the CLUT loading for the background */
1027 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1028 }
1029 /* Configure the CLUT of the foreground DMA2D layer */
1030 else
1031 {
1032 /* Write foreground CLUT memory address */
1033 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
1034
1035 /* Write foreground CLUT size and CLUT color mode */
1036 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1037 ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1038
1039 /* Enable the CLUT loading for the foreground */
1040 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1041 }
1042
1043 return HAL_OK;
1044 }
1045
1046 /**
1047 * @brief Start DMA2D CLUT Loading with interrupt enabled.
1048 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1049 * the configuration information for the DMA2D.
1050 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1051 * the configuration information for the color look up table.
1052 * @param LayerIdx DMA2D Layer index.
1053 * This parameter can be one of the following values:
1054 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1055 * @retval HAL status
1056 */
1057 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx)
1058 {
1059 /* Check the parameters */
1060 assert_param(IS_DMA2D_LAYER(LayerIdx));
1061 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
1062 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
1063
1064 /* Process locked */
1065 __HAL_LOCK(hdma2d);
1066
1067 /* Change DMA2D peripheral state */
1068 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1069
1070 /* Configure the CLUT of the background DMA2D layer */
1071 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1072 {
1073 /* Write background CLUT memory address */
1074 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
1075
1076 /* Write background CLUT size and CLUT color mode */
1077 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1078 ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1079
1080 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1081 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1082
1083 /* Enable the CLUT loading for the background */
1084 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1085 }
1086 /* Configure the CLUT of the foreground DMA2D layer */
1087 else
1088 {
1089 /* Write foreground CLUT memory address */
1090 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
1091
1092 /* Write foreground CLUT size and CLUT color mode */
1093 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1094 ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1095
1096 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1097 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1098
1099 /* Enable the CLUT loading for the foreground */
1100 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1101 }
1102
1103 return HAL_OK;
1104 }
1105
1106 /**
1107 * @brief Start DMA2D CLUT Loading.
1108 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1109 * the configuration information for the DMA2D.
1110 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1111 * the configuration information for the color look up table.
1112 * @param LayerIdx DMA2D Layer index.
1113 * This parameter can be one of the following values:
1114 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1115 * @note API obsolete and maintained for compatibility with legacy. User is
1116 * invited to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from
1117 * code compactness, code size and improved heap usage.
1118 * @retval HAL status
1119 */
1120 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1121 {
1122 /* Check the parameters */
1123 assert_param(IS_DMA2D_LAYER(LayerIdx));
1124 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1125 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1126
1127 /* Process locked */
1128 __HAL_LOCK(hdma2d);
1129
1130 /* Change DMA2D peripheral state */
1131 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1132
1133 /* Configure the CLUT of the background DMA2D layer */
1134 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1135 {
1136 /* Write background CLUT memory address */
1137 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1138
1139 /* Write background CLUT size and CLUT color mode */
1140 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1141 ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1142
1143 /* Enable the CLUT loading for the background */
1144 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1145 }
1146 /* Configure the CLUT of the foreground DMA2D layer */
1147 else
1148 {
1149 /* Write foreground CLUT memory address */
1150 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1151
1152 /* Write foreground CLUT size and CLUT color mode */
1153 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1154 ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1155
1156 /* Enable the CLUT loading for the foreground */
1157 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1158 }
1159
1160 return HAL_OK;
1161 }
1162
1163 /**
1164 * @brief Start DMA2D CLUT Loading with interrupt enabled.
1165 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1166 * the configuration information for the DMA2D.
1167 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1168 * the configuration information for the color look up table.
1169 * @param LayerIdx DMA2D Layer index.
1170 * This parameter can be one of the following values:
1171 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1172 * @note API obsolete and maintained for compatibility with legacy. User is
1173 * invited to resort to HAL_DMA2D_CLUTStartLoad_IT() instead to benefit
1174 * from code compactness, code size and improved heap usage.
1175 * @retval HAL status
1176 */
1177 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1178 {
1179 /* Check the parameters */
1180 assert_param(IS_DMA2D_LAYER(LayerIdx));
1181 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1182 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1183
1184 /* Process locked */
1185 __HAL_LOCK(hdma2d);
1186
1187 /* Change DMA2D peripheral state */
1188 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1189
1190 /* Configure the CLUT of the background DMA2D layer */
1191 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1192 {
1193 /* Write background CLUT memory address */
1194 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1195
1196 /* Write background CLUT size and CLUT color mode */
1197 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1198 ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1199
1200 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1201 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1202
1203 /* Enable the CLUT loading for the background */
1204 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1205 }
1206 /* Configure the CLUT of the foreground DMA2D layer */
1207 else
1208 {
1209 /* Write foreground CLUT memory address */
1210 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1211
1212 /* Write foreground CLUT size and CLUT color mode */
1213 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1214 ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1215
1216 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1217 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1218
1219 /* Enable the CLUT loading for the foreground */
1220 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1221 }
1222
1223 return HAL_OK;
1224 }
1225
1226 /**
1227 * @brief Abort the DMA2D CLUT loading.
1228 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1229 * the configuration information for the DMA2D.
1230 * @param LayerIdx DMA2D Layer index.
1231 * This parameter can be one of the following values:
1232 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1233 * @retval HAL status
1234 */
1235 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1236 {
1237 uint32_t tickstart;
1238 const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
1239
1240 /* Abort the CLUT loading */
1241 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
1242
1243 /* If foreground CLUT loading is considered, update local variables */
1244 if(LayerIdx == DMA2D_FOREGROUND_LAYER)
1245 {
1246 reg = &(hdma2d->Instance->FGPFCCR);
1247 }
1248
1249
1250 /* Get tick */
1251 tickstart = HAL_GetTick();
1252
1253 /* Check if the CLUT loading is aborted */
1254 while((*reg & DMA2D_BGPFCCR_START) != 0U)
1255 {
1256 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
1257 {
1258 /* Update error code */
1259 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1260
1261 /* Change the DMA2D state */
1262 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1263
1264 /* Process Unlocked */
1265 __HAL_UNLOCK(hdma2d);
1266
1267 return HAL_TIMEOUT;
1268 }
1269 }
1270
1271 /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
1272 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1273
1274 /* Change the DMA2D state*/
1275 hdma2d->State = HAL_DMA2D_STATE_READY;
1276
1277 /* Process Unlocked */
1278 __HAL_UNLOCK(hdma2d);
1279
1280 return HAL_OK;
1281 }
1282
1283 /**
1284 * @brief Suspend the DMA2D CLUT loading.
1285 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1286 * the configuration information for the DMA2D.
1287 * @param LayerIdx DMA2D Layer index.
1288 * This parameter can be one of the following values:
1289 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1290 * @retval HAL status
1291 */
1292 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1293 {
1294 uint32_t tickstart;
1295 uint32_t loadsuspended;
1296 const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
1297
1298 /* Suspend the CLUT loading */
1299 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1300
1301 /* If foreground CLUT loading is considered, update local variables */
1302 if(LayerIdx == DMA2D_FOREGROUND_LAYER)
1303 {
1304 reg = &(hdma2d->Instance->FGPFCCR);
1305 }
1306
1307 /* Get tick */
1308 tickstart = HAL_GetTick();
1309
1310 /* Check if the CLUT loading is suspended */
1311 loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
1312 loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
1313 while (loadsuspended == 0UL)
1314 {
1315 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
1316 {
1317 /* Update error code */
1318 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1319
1320 /* Change the DMA2D state */
1321 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1322
1323 return HAL_TIMEOUT;
1324 }
1325 loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
1326 loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
1327 }
1328
1329 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
1330 if ((*reg & DMA2D_BGPFCCR_START) != 0U)
1331 {
1332 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
1333 }
1334 else
1335 {
1336 /* Make sure SUSP bit is cleared since it is meaningless
1337 when no tranfer is on-going */
1338 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1339 }
1340
1341 return HAL_OK;
1342 }
1343
1344 /**
1345 * @brief Resume the DMA2D CLUT loading.
1346 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1347 * the configuration information for the DMA2D.
1348 * @param LayerIdx DMA2D Layer index.
1349 * This parameter can be one of the following values:
1350 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1351 * @retval HAL status
1352 */
1353 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1354 {
1355 /* Check the SUSP and START bits for background or foreground CLUT loading */
1356 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1357 {
1358 /* Background CLUT loading suspension check */
1359 if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
1360 {
1361 if((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
1362 {
1363 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
1364 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1365 }
1366 }
1367 }
1368 else
1369 {
1370 /* Foreground CLUT loading suspension check */
1371 if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
1372 {
1373 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
1374 {
1375 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
1376 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1377 }
1378 }
1379 }
1380
1381 /* Resume the CLUT loading */
1382 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1383
1384 return HAL_OK;
1385 }
1386
1387
1388 /**
1389
1390 * @brief Polling for transfer complete or CLUT loading.
1391 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1392 * the configuration information for the DMA2D.
1393 * @param Timeout Timeout duration
1394 * @retval HAL status
1395 */
1396 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
1397 {
1398 uint32_t tickstart;
1399 uint32_t layer_start;
1400 __IO uint32_t isrflags = 0x0U;
1401
1402 /* Polling for DMA2D transfer */
1403 if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
1404 {
1405 /* Get tick */
1406 tickstart = HAL_GetTick();
1407
1408 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
1409 {
1410 isrflags = READ_REG(hdma2d->Instance->ISR);
1411 if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
1412 {
1413 if ((isrflags & DMA2D_FLAG_CE) != 0U)
1414 {
1415 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1416 }
1417 if ((isrflags & DMA2D_FLAG_TE) != 0U)
1418 {
1419 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1420 }
1421 /* Clear the transfer and configuration error flags */
1422 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1423
1424 /* Change DMA2D state */
1425 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1426
1427 /* Process unlocked */
1428 __HAL_UNLOCK(hdma2d);
1429
1430 return HAL_ERROR;
1431 }
1432 /* Check for the Timeout */
1433 if(Timeout != HAL_MAX_DELAY)
1434 {
1435 if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
1436 {
1437 /* Update error code */
1438 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1439
1440 /* Change the DMA2D state */
1441 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1442
1443 /* Process unlocked */
1444 __HAL_UNLOCK(hdma2d);
1445
1446 return HAL_TIMEOUT;
1447 }
1448 }
1449 }
1450 }
1451 /* Polling for CLUT loading (foreground or background) */
1452 layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
1453 layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
1454 if (layer_start != 0U)
1455 {
1456 /* Get tick */
1457 tickstart = HAL_GetTick();
1458
1459 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
1460 {
1461 isrflags = READ_REG(hdma2d->Instance->ISR);
1462 if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
1463 {
1464 if ((isrflags & DMA2D_FLAG_CAE) != 0U)
1465 {
1466 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1467 }
1468 if ((isrflags & DMA2D_FLAG_CE) != 0U)
1469 {
1470 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1471 }
1472 if ((isrflags & DMA2D_FLAG_TE) != 0U)
1473 {
1474 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1475 }
1476 /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
1477 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1478
1479 /* Change DMA2D state */
1480 hdma2d->State= HAL_DMA2D_STATE_ERROR;
1481
1482 /* Process unlocked */
1483 __HAL_UNLOCK(hdma2d);
1484
1485 return HAL_ERROR;
1486 }
1487 /* Check for the Timeout */
1488 if(Timeout != HAL_MAX_DELAY)
1489 {
1490 if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
1491 {
1492 /* Update error code */
1493 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1494
1495 /* Change the DMA2D state */
1496 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
1497
1498 /* Process unlocked */
1499 __HAL_UNLOCK(hdma2d);
1500
1501 return HAL_TIMEOUT;
1502 }
1503 }
1504 }
1505 }
1506
1507 /* Clear the transfer complete and CLUT loading flags */
1508 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
1509
1510 /* Change DMA2D state */
1511 hdma2d->State = HAL_DMA2D_STATE_READY;
1512
1513 /* Process unlocked */
1514 __HAL_UNLOCK(hdma2d);
1515
1516 return HAL_OK;
1517 }
1518 /**
1519 * @brief Handle DMA2D interrupt request.
1520 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1521 * the configuration information for the DMA2D.
1522 * @retval HAL status
1523 */
1524 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
1525 {
1526 uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
1527 uint32_t crflags = READ_REG(hdma2d->Instance->CR);
1528
1529 /* Transfer Error Interrupt management ***************************************/
1530 if ((isrflags & DMA2D_FLAG_TE) != 0U)
1531 {
1532 if ((crflags & DMA2D_IT_TE) != 0U)
1533 {
1534 /* Disable the transfer Error interrupt */
1535 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
1536
1537 /* Update error code */
1538 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1539
1540 /* Clear the transfer error flag */
1541 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
1542
1543 /* Change DMA2D state */
1544 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1545
1546 /* Process Unlocked */
1547 __HAL_UNLOCK(hdma2d);
1548
1549 if(hdma2d->XferErrorCallback != NULL)
1550 {
1551 /* Transfer error Callback */
1552 hdma2d->XferErrorCallback(hdma2d);
1553 }
1554 }
1555 }
1556 /* Configuration Error Interrupt management **********************************/
1557 if ((isrflags & DMA2D_FLAG_CE) != 0U)
1558 {
1559 if ((crflags & DMA2D_IT_CE) != 0U)
1560 {
1561 /* Disable the Configuration Error interrupt */
1562 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
1563
1564 /* Clear the Configuration error flag */
1565 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
1566
1567 /* Update error code */
1568 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1569
1570 /* Change DMA2D state */
1571 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1572
1573 /* Process Unlocked */
1574 __HAL_UNLOCK(hdma2d);
1575
1576 if(hdma2d->XferErrorCallback != NULL)
1577 {
1578 /* Transfer error Callback */
1579 hdma2d->XferErrorCallback(hdma2d);
1580 }
1581 }
1582 }
1583 /* CLUT access Error Interrupt management ***********************************/
1584 if ((isrflags & DMA2D_FLAG_CAE) != 0U)
1585 {
1586 if ((crflags & DMA2D_IT_CAE) != 0U)
1587 {
1588 /* Disable the CLUT access error interrupt */
1589 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
1590
1591 /* Clear the CLUT access error flag */
1592 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
1593
1594 /* Update error code */
1595 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1596
1597 /* Change DMA2D state */
1598 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1599
1600 /* Process Unlocked */
1601 __HAL_UNLOCK(hdma2d);
1602
1603 if(hdma2d->XferErrorCallback != NULL)
1604 {
1605 /* Transfer error Callback */
1606 hdma2d->XferErrorCallback(hdma2d);
1607 }
1608 }
1609 }
1610 /* Transfer watermark Interrupt management **********************************/
1611 if ((isrflags & DMA2D_FLAG_TW) != 0U)
1612 {
1613 if ((crflags & DMA2D_IT_TW) != 0U)
1614 {
1615 /* Disable the transfer watermark interrupt */
1616 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
1617
1618 /* Clear the transfer watermark flag */
1619 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
1620
1621 /* Transfer watermark Callback */
1622 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
1623 hdma2d->LineEventCallback(hdma2d);
1624 #else
1625 HAL_DMA2D_LineEventCallback(hdma2d);
1626 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
1627
1628 }
1629 }
1630 /* Transfer Complete Interrupt management ************************************/
1631 if ((isrflags & DMA2D_FLAG_TC) != 0U)
1632 {
1633 if ((crflags & DMA2D_IT_TC) != 0U)
1634 {
1635 /* Disable the transfer complete interrupt */
1636 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
1637
1638 /* Clear the transfer complete flag */
1639 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
1640
1641 /* Update error code */
1642 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1643
1644 /* Change DMA2D state */
1645 hdma2d->State = HAL_DMA2D_STATE_READY;
1646
1647 /* Process Unlocked */
1648 __HAL_UNLOCK(hdma2d);
1649
1650 if(hdma2d->XferCpltCallback != NULL)
1651 {
1652 /* Transfer complete Callback */
1653 hdma2d->XferCpltCallback(hdma2d);
1654 }
1655 }
1656 }
1657 /* CLUT Transfer Complete Interrupt management ******************************/
1658 if ((isrflags & DMA2D_FLAG_CTC) != 0U)
1659 {
1660 if ((crflags & DMA2D_IT_CTC) != 0U)
1661 {
1662 /* Disable the CLUT transfer complete interrupt */
1663 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
1664
1665 /* Clear the CLUT transfer complete flag */
1666 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
1667
1668 /* Update error code */
1669 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1670
1671 /* Change DMA2D state */
1672 hdma2d->State = HAL_DMA2D_STATE_READY;
1673
1674 /* Process Unlocked */
1675 __HAL_UNLOCK(hdma2d);
1676
1677 /* CLUT Transfer complete Callback */
1678 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
1679 hdma2d->CLUTLoadingCpltCallback(hdma2d);
1680 #else
1681 HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
1682 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
1683 }
1684 }
1685
1686 }
1687
1688 /**
1689 * @brief Transfer watermark callback.
1690 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1691 * the configuration information for the DMA2D.
1692 * @retval None
1693 */
1694 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
1695 {
1696 /* Prevent unused argument(s) compilation warning */
1697 UNUSED(hdma2d);
1698
1699 /* NOTE : This function should not be modified; when the callback is needed,
1700 the HAL_DMA2D_LineEventCallback can be implemented in the user file.
1701 */
1702 }
1703
1704 /**
1705 * @brief CLUT Transfer Complete callback.
1706 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1707 * the configuration information for the DMA2D.
1708 * @retval None
1709 */
1710 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
1711 {
1712 /* Prevent unused argument(s) compilation warning */
1713 UNUSED(hdma2d);
1714
1715 /* NOTE : This function should not be modified; when the callback is needed,
1716 the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
1717 */
1718 }
1719
1720 /**
1721 * @}
1722 */
1723
1724 /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
1725 * @brief Peripheral Control functions
1726 *
1727 @verbatim
1728 ===============================================================================
1729 ##### Peripheral Control functions #####
1730 ===============================================================================
1731 [..] This section provides functions allowing to:
1732 (+) Configure the DMA2D foreground or background layer parameters.
1733 (+) Configure the DMA2D CLUT transfer.
1734 (+) Configure the line watermark
1735 (+) Configure the dead time value.
1736 (+) Enable or disable the dead time value functionality.
1737
1738
1739 @endverbatim
1740 * @{
1741 */
1742
1743 /**
1744 * @brief Configure the DMA2D Layer according to the specified
1745 * parameters in the DMA2D_HandleTypeDef.
1746 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1747 * the configuration information for the DMA2D.
1748 * @param LayerIdx DMA2D Layer index.
1749 * This parameter can be one of the following values:
1750 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1751 * @retval HAL status
1752 */
1753 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1754 {
1755 DMA2D_LayerCfgTypeDef *pLayerCfg;
1756 uint32_t regMask, regValue;
1757
1758 /* Check the parameters */
1759 assert_param(IS_DMA2D_LAYER(LayerIdx));
1760 assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
1761 if(hdma2d->Init.Mode != DMA2D_R2M)
1762 {
1763 assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode));
1764 if(hdma2d->Init.Mode != DMA2D_M2M)
1765 {
1766 assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
1767 }
1768 }
1769 assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
1770 assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
1771
1772 if((LayerIdx == DMA2D_FOREGROUND_LAYER) && (hdma2d->LayerCfg[LayerIdx].InputColorMode == DMA2D_INPUT_YCBCR))
1773 {
1774 assert_param(IS_DMA2D_CHROMA_SUB_SAMPLING(hdma2d->LayerCfg[LayerIdx].ChromaSubSampling));
1775 }
1776
1777 /* Process locked */
1778 __HAL_LOCK(hdma2d);
1779
1780 /* Change DMA2D peripheral state */
1781 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1782
1783 pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
1784
1785 /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
1786 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\
1787 (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
1788 regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
1789
1790
1791 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1792 {
1793 regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
1794 }
1795 else
1796 {
1797 regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
1798 }
1799
1800 /* Configure the background DMA2D layer */
1801 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1802 {
1803 /* Write DMA2D BGPFCCR register */
1804 MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
1805
1806 /* DMA2D BGOR register configuration -------------------------------------*/
1807 WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
1808
1809 /* DMA2D BGCOLR register configuration -------------------------------------*/
1810 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1811 {
1812 WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
1813 }
1814 }
1815 /* Configure the foreground DMA2D layer */
1816 else
1817 {
1818
1819 if(pLayerCfg->InputColorMode == DMA2D_INPUT_YCBCR)
1820 {
1821 regValue |= (pLayerCfg->ChromaSubSampling << DMA2D_FGPFCCR_CSS_Pos);
1822 regMask |= DMA2D_FGPFCCR_CSS;
1823 }
1824
1825 /* Write DMA2D FGPFCCR register */
1826 MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
1827
1828 /* DMA2D FGOR register configuration -------------------------------------*/
1829 WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
1830
1831 /* DMA2D FGCOLR register configuration -------------------------------------*/
1832 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1833 {
1834 WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
1835 }
1836 }
1837 /* Initialize the DMA2D state*/
1838 hdma2d->State = HAL_DMA2D_STATE_READY;
1839
1840 /* Process unlocked */
1841 __HAL_UNLOCK(hdma2d);
1842
1843 return HAL_OK;
1844 }
1845
1846 /**
1847 * @brief Configure the DMA2D CLUT Transfer.
1848 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1849 * the configuration information for the DMA2D.
1850 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1851 * the configuration information for the color look up table.
1852 * @param LayerIdx DMA2D Layer index.
1853 * This parameter can be one of the following values:
1854 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1855 * @note API obsolete and maintained for compatibility with legacy. User is invited
1856 * to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from code compactness,
1857 * code size and improved heap usage.
1858 * @retval HAL status
1859 */
1860 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1861 {
1862 /* Check the parameters */
1863 assert_param(IS_DMA2D_LAYER(LayerIdx));
1864 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1865 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1866
1867 /* Process locked */
1868 __HAL_LOCK(hdma2d);
1869
1870 /* Change DMA2D peripheral state */
1871 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1872
1873 /* Configure the CLUT of the background DMA2D layer */
1874 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1875 {
1876 /* Write background CLUT memory address */
1877 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1878
1879 /* Write background CLUT size and CLUT color mode */
1880 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1881 ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1882 }
1883 /* Configure the CLUT of the foreground DMA2D layer */
1884 else
1885 {
1886 /* Write foreground CLUT memory address */
1887 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1888
1889 /* Write foreground CLUT size and CLUT color mode */
1890 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1891 ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1892 }
1893
1894 /* Set the DMA2D state to Ready*/
1895 hdma2d->State = HAL_DMA2D_STATE_READY;
1896
1897 /* Process unlocked */
1898 __HAL_UNLOCK(hdma2d);
1899
1900 return HAL_OK;
1901 }
1902
1903
1904 /**
1905 * @brief Configure the line watermark.
1906 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1907 * the configuration information for the DMA2D.
1908 * @param Line Line Watermark configuration (maximum 16-bit long value expected).
1909 * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
1910 * @note The transfer watermark interrupt is disabled once it has occurred.
1911 * @retval HAL status
1912 */
1913
1914 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
1915 {
1916 /* Check the parameters */
1917 assert_param(IS_DMA2D_LINEWATERMARK(Line));
1918
1919 if (Line > DMA2D_LWR_LW)
1920 {
1921 return HAL_ERROR;
1922 }
1923 else
1924 {
1925 /* Process locked */
1926 __HAL_LOCK(hdma2d);
1927
1928 /* Change DMA2D peripheral state */
1929 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1930
1931 /* Sets the Line watermark configuration */
1932 WRITE_REG(hdma2d->Instance->LWR, Line);
1933
1934 /* Enable the Line interrupt */
1935 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
1936
1937 /* Initialize the DMA2D state*/
1938 hdma2d->State = HAL_DMA2D_STATE_READY;
1939
1940 /* Process unlocked */
1941 __HAL_UNLOCK(hdma2d);
1942
1943 return HAL_OK;
1944 }
1945 }
1946
1947 /**
1948 * @brief Enable DMA2D dead time feature.
1949 * @param hdma2d DMA2D handle.
1950 * @retval HAL status
1951 */
1952 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1953 {
1954 /* Process Locked */
1955 __HAL_LOCK(hdma2d);
1956
1957 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1958
1959 /* Set DMA2D_AMTCR EN bit */
1960 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
1961
1962 hdma2d->State = HAL_DMA2D_STATE_READY;
1963
1964 /* Process Unlocked */
1965 __HAL_UNLOCK(hdma2d);
1966
1967 return HAL_OK;
1968 }
1969
1970 /**
1971 * @brief Disable DMA2D dead time feature.
1972 * @param hdma2d DMA2D handle.
1973 * @retval HAL status
1974 */
1975 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1976 {
1977 /* Process Locked */
1978 __HAL_LOCK(hdma2d);
1979
1980 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1981
1982 /* Clear DMA2D_AMTCR EN bit */
1983 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
1984
1985 hdma2d->State = HAL_DMA2D_STATE_READY;
1986
1987 /* Process Unlocked */
1988 __HAL_UNLOCK(hdma2d);
1989
1990 return HAL_OK;
1991 }
1992
1993 /**
1994 * @brief Configure dead time.
1995 * @note The dead time value represents the guaranteed minimum number of cycles between
1996 * two consecutive transactions on the AHB bus.
1997 * @param hdma2d DMA2D handle.
1998 * @param DeadTime dead time value.
1999 * @retval HAL status
2000 */
2001 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
2002 {
2003 /* Process Locked */
2004 __HAL_LOCK(hdma2d);
2005
2006 hdma2d->State = HAL_DMA2D_STATE_BUSY;
2007
2008 /* Set DMA2D_AMTCR DT field */
2009 MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos));
2010
2011 hdma2d->State = HAL_DMA2D_STATE_READY;
2012
2013 /* Process Unlocked */
2014 __HAL_UNLOCK(hdma2d);
2015
2016 return HAL_OK;
2017 }
2018
2019 /**
2020 * @}
2021 */
2022
2023
2024 /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
2025 * @brief Peripheral State functions
2026 *
2027 @verbatim
2028 ===============================================================================
2029 ##### Peripheral State and Errors functions #####
2030 ===============================================================================
2031 [..]
2032 This subsection provides functions allowing to:
2033 (+) Get the DMA2D state
2034 (+) Get the DMA2D error code
2035
2036 @endverbatim
2037 * @{
2038 */
2039
2040 /**
2041 * @brief Return the DMA2D state
2042 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
2043 * the configuration information for the DMA2D.
2044 * @retval HAL state
2045 */
2046 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
2047 {
2048 return hdma2d->State;
2049 }
2050
2051 /**
2052 * @brief Return the DMA2D error code
2053 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
2054 * the configuration information for DMA2D.
2055 * @retval DMA2D Error Code
2056 */
2057 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
2058 {
2059 return hdma2d->ErrorCode;
2060 }
2061
2062 /**
2063 * @}
2064 */
2065
2066 /**
2067 * @}
2068 */
2069
2070
2071 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
2072 * @{
2073 */
2074
2075 /**
2076 * @brief Set the DMA2D transfer parameters.
2077 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
2078 * the configuration information for the specified DMA2D.
2079 * @param pdata The source memory Buffer address
2080 * @param DstAddress The destination memory Buffer address
2081 * @param Width The width of data to be transferred from source to destination.
2082 * @param Height The height of data to be transferred from source to destination.
2083 * @retval HAL status
2084 */
2085 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
2086 {
2087 uint32_t tmp;
2088 uint32_t tmp1;
2089 uint32_t tmp2;
2090 uint32_t tmp3;
2091 uint32_t tmp4;
2092
2093 /* Configure DMA2D data size */
2094 MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos)));
2095
2096 /* Configure DMA2D destination address */
2097 WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
2098
2099 /* Register to memory DMA2D mode selected */
2100 if (hdma2d->Init.Mode == DMA2D_R2M)
2101 {
2102 tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
2103 tmp2 = pdata & DMA2D_OCOLR_RED_1;
2104 tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
2105 tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
2106
2107 /* Prepare the value to be written to the OCOLR register according to the color mode */
2108 if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
2109 {
2110 tmp = (tmp3 | tmp2 | tmp1| tmp4);
2111 }
2112 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
2113 {
2114 tmp = (tmp3 | tmp2 | tmp4);
2115 }
2116 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
2117 {
2118 tmp2 = (tmp2 >> 19U);
2119 tmp3 = (tmp3 >> 10U);
2120 tmp4 = (tmp4 >> 3U );
2121 tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
2122 }
2123 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
2124 {
2125 tmp1 = (tmp1 >> 31U);
2126 tmp2 = (tmp2 >> 19U);
2127 tmp3 = (tmp3 >> 11U);
2128 tmp4 = (tmp4 >> 3U );
2129 tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
2130 }
2131 else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
2132 {
2133 tmp1 = (tmp1 >> 28U);
2134 tmp2 = (tmp2 >> 20U);
2135 tmp3 = (tmp3 >> 12U);
2136 tmp4 = (tmp4 >> 4U );
2137 tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
2138 }
2139 /* Write to DMA2D OCOLR register */
2140 WRITE_REG(hdma2d->Instance->OCOLR, tmp);
2141 }
2142 else if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) /*M2M_blending with fixed color FG DMA2D Mode selected*/
2143 {
2144 WRITE_REG(hdma2d->Instance->BGMAR , pdata);
2145 }
2146 else /* M2M, M2M_PFC,M2M_Blending or M2M_blending with fixed color BG DMA2D Mode */
2147 {
2148 /* Configure DMA2D source address */
2149 WRITE_REG(hdma2d->Instance->FGMAR, pdata);
2150 }
2151 }
2152
2153 /**
2154 * @}
2155 */
2156
2157 /**
2158 * @}
2159 */
2160
2161 /**
2162 * @}
2163 */
2164 #endif /* DMA2D */
2165 #endif /* HAL_DMA2D_MODULE_ENABLED */
2166
2167 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/