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[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_hal_hrtim.c
blob914930c6097c9f26ac588785d11d4e1fbce5ffa9
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_hrtim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the High Resolution Timer (HRTIM) peripheral:
8 * + HRTIM Initialization
9 * + Timer Time Base Unit Configuration
10 * + Simple Time Base Start/Stop
11 * + Simple Time Base Start/Stop Interrupt
12 * + Simple Time Base Start/Stop DMA Request
13 * + Simple Output Compare/PWM Channel Configuration
14 * + Simple Output Compare/PWM Channel Start/Stop Interrupt
15 * + Simple Output Compare/PWM Channel Start/Stop DMA Request
16 * + Simple Input Capture Channel Configuration
17 * + Simple Input Capture Channel Start/Stop Interrupt
18 * + Simple Input Capture Channel Start/Stop DMA Request
19 * + Simple One Pulse Channel Configuration
20 * + Simple One Pulse Channel Start/Stop Interrupt
21 * + HRTIM External Synchronization Configuration
22 * + HRTIM Burst Mode Controller Configuration
23 * + HRTIM Burst Mode Controller Enabling
24 * + HRTIM External Events Conditioning Configuration
25 * + HRTIM Faults Conditioning Configuration
26 * + HRTIM Faults Enabling
27 * + HRTIM ADC trigger Configuration
28 * + Waveform Timer Configuration
29 * + Waveform Event Filtering Configuration
30 * + Waveform Dead Time Insertion Configuration
31 * + Waveform Chopper Mode Configuration
32 * + Waveform Compare Unit Configuration
33 * + Waveform Capture Unit Configuration
34 * + Waveform Output Configuration
35 * + Waveform Counter Start/Stop
36 * + Waveform Counter Start/Stop Interrupt
37 * + Waveform Counter Start/Stop DMA Request
38 * + Waveform Output Enabling
39 * + Waveform Output Level Set/Get
40 * + Waveform Output State Get
41 * + Waveform Burst DMA Operation Configuration
42 * + Waveform Burst DMA Operation Start
43 * + Waveform Timer Counter Software Reset
44 * + Waveform Capture Software Trigger
45 * + Waveform Burst Mode Controller Software Trigger
46 * + Waveform Timer Pre-loadable Registers Update Enabling
47 * + Waveform Timer Pre-loadable Registers Software Update
48 * + Waveform Timer Delayed Protection Status Get
49 * + Waveform Timer Burst Status Get
50 * + Waveform Timer Push-Pull Status Get
51 * + Peripheral State Get
52 @verbatim
53 ==============================================================================
54 ##### Simple mode v.s. waveform mode #####
55 ==============================================================================
56 [..] The HRTIM HAL API is split into 2 categories:
57 (#)Simple functions: these functions allow for using a HRTIM timer as a
58 general purpose timer with high resolution capabilities.
59 HRTIM simple modes are managed through the set of functions named
60 HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
61 to the one defined for the TIM peripheral. When a HRTIM timer operates in
62 simple mode, only a very limited set of HRTIM features are used.
63 Following simple modes are proposed:
64 (++)Output compare mode,
65 (++)PWM output mode,
66 (++)Input capture mode,
67 (++)One pulse mode.
68 (#)Waveform functions: These functions allow taking advantage of the HRTIM
69 flexibility to produce numerous types of control signal. When a HRTIM timer
70 operates in waveform mode, all the HRTIM features are accessible without
71 any restriction. HRTIM waveform modes are managed through the set of
72 functions named HAL_HRTIM_Waveform<Function>
73 ##### How to use this driver #####
74 ==============================================================================
75 [..]
76 (#)Initialize the HRTIM low level resources by implementing the
77 HAL_HRTIM_MspInit() function:
78 (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
79 (##)Connect HRTIM pins to MCU I/Os
80 (+++) Enable the clock for the HRTIM GPIOs using the following
81 function: __HAL_RCC_GPIOx_CLK_ENABLE()
82 (+++) Configure these GPIO pins in Alternate Function mode using
83 HAL_GPIO_Init()
84 (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
85 (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
86 (+++)Initialize the DMA handle
87 (+++)Associate the initialized DMA handle to the appropriate DMA
88 handle of the HRTIM handle using __HAL_LINKDMA()
89 (+++)Initialize the DMA channel using HAL_DMA_Init()
90 (+++)Configure the priority and enable the NVIC for the transfer
91 complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
92 and HAL_NVIC_EnableIRQ()
93 (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
94 (+++)Configure the priority and enable the NVIC for the concerned
95 HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
96
97 (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
98 structure (field of the HRTIM handle) specifies which global interrupt of
99 whole HRTIM must be enabled (Burst mode period, System fault, Faults).
100 It also contains the HRTIM external synchronization configuration. HRTIM
101 can act as a master (generating a synchronization signal) or as a slave
102 (waiting for a trigger to be synchronized).
103
104 (#) Configure HRTIM resources shared by all HRTIM timers
105 (##)Burst Mode Controller:
106 (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
107 controller: operating mode (continuous or one-shot mode), clock
108 (source, prescaler) , trigger(s), period, idle duration.
109 (##)External Events Conditioning:
110 (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
111 external event channel: source, polarity, edge-sensitivity.
112 External event can be used as triggers (timer reset, input
113 capture, burst mode, ADC triggers, delayed protection)
114 They can also be used to set or reset timer outputs. Up to
115 10 event channels are available.
116 (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
117 event sampling clock (used for digital filtering).
118 (##)Fault Conditioning:
119 (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
120 fault channel: source, polarity, edge-sensitivity. Fault
121 channels are used to disable the outputs in case of an
122 abnormal operation. Up to 5 fault channels are available.
123 (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
124 sampling clock (used for digital filtering).
125 (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
126 circuitry. By default all fault inputs are disabled.
127 (##)ADC trigger:
128 (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
129 the update of the ADC trigger register and the ADC trigger.
130 4 independent triggers are available to start both the regular
131 and the injected sequencers of the 2 ADCs
132
133 (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
134 function must be called whatever the HRTIM timer operating mode is
135 (simple v.s. waveform). It configures mainly:
136 (##)The HRTIM timer counter operating mode (continuous v.s. one shot)
137 (##)The HRTIM timer clock prescaler
138 (##)The HRTIM timer period
139 (##)The HRTIM timer repetition counter
140
141 *** If the HRTIM timer operates in simple mode ***
142 ===================================================
143 [..]
144 (#) Start or Stop simple timers
145 (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
146 HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
147 HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
148 (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
149 HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
150 HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
151 HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
152 (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
153 HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
154 HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
155 HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
156 (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
157 HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
158 HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
159 HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
160 (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
161 HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
162 HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().
163
164 *** If the HRTIM timer operates in waveform mode ***
165 ====================================================
166 [..]
167 (#) Completes waveform timer configuration
168 (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer
169 operating in wave form mode mainly consists in:
170 (+++)Enabling the HRTIM timer interrupts and DMA requests.
171 (+++)Enabling the half mode for the HRTIM timer.
172 (+++)Defining how the HRTIM timer reacts to external synchronization input.
173 (+++)Enabling the push-pull mode for the HRTIM timer.
174 (+++)Enabling the fault channels for the HRTIM timer.
175 (+++)Enabling the dead-time insertion for the HRTIM timer.
176 (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs
177 on which the delayed protection are applied).
178 (+++)Specifying the HRTIM timer update and reset triggers.
179 (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling).
180 (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
181 event blanking and windowing circuitry of a HRTIM timer:
182 (+++)Blanking: to mask external events during a defined time period a defined time period
183 (+++)Windowing, to enable external events only during a defined time period
184 (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion
185 unit for a HRTIM timer. Allows to generate a couple of
186 complementary signals from a single reference waveform,
187 with programmable delays between active state.
188 (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
189 the high-frequency carrier signal added on top of the timing
190 unit output. Chopper mode can be enabled or disabled for each
191 timer output separately (see HAL_HRTIM_WaveformOutputConfig()).
192 (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
193 controller. Allows having multiple HRTIM registers updated
194 with a single DMA request. The burst DMA operation is started
195 by calling HAL_HRTIM_BurstDMATransfer().
196 (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
197 of a HRTIM timer. This operation consists in setting the
198 compare value and possibly specifying the auto delayed mode
199 for compare units 2 and 4 (allows to have compare events
200 generated relatively to capture events). Note that when auto
201 delayed mode is needed, the capture unit associated to the
202 compare unit must be configured separately.
203 (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
204 of a HRTIM timer. This operation consists in specifying the
205 source(s) triggering the capture (timer register update event,
206 external event, timer output set/reset event, other HRTIM
207 timer related events).
208 (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer
209 output mainly consists in:
210 (+++)Setting the output polarity (active high or active low),
211 (+++)Defining the set/reset crossbar for the output,
212 (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states.,
213
214 (#) Set waveform timer output(s) level
215 (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
216 active or inactive level. For example, when deadtime insertion
217 is enabled it is necessary to force the output level by software
218 to have the outputs in a complementary state as soon as the RUN mode is entered.
219
220 (#) Enable or Disable waveform timer output(s)
221 (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
222
223 (#) Start or Stop waveform HRTIM timer(s).
224 (++)HAL_HRTIM_WaveformCountStart(),HAL_HRTIM_WaveformCountStop(),
225 (++)HAL_HRTIM_WaveformCountStart_IT(),HAL_HRTIM_WaveformCountStop_IT(),
226 (++)HAL_HRTIM_WaveformCountStart_DMA(),HAL_HRTIM_WaveformCountStop_DMA(),
227 (#) Burst mode controller enabling:
228 (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
229 burst mode controller.
230
231 (#) Some HRTIM operations can be triggered by software:
232 (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
233 trigs the burst operation.
234 (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
235 capture of the HRTIM timer counter.
236 (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
237 update of the pre-loadable registers of the HRTIM timer
238 (++)HAL_HRTIM_SoftwareReset():calling this function resets the
239 HRTIM timer counter.
240
241 (#) Some functions can be used any time to retrieve HRTIM timer related
242 information
243 (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
244 capture register of the designated capture unit.
245 (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
246 (ACTIVE/INACTIVE) of the designated timer output.
247 (++)HAL_HRTIM_WaveformGetOutputState():returns actual state
248 (IDLE/RUN/FAULT) of the designated timer output.
249 (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
250 (ACTIVE/INACTIVE) of the designated output when the delayed
251 protection was triggered.
252 (++)HAL_HRTIM_GetBurstStatus(): returns the actual status
253 (ACTIVE/INACTIVE) of the burst mode controller.
254 (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
255 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
256 the push-pull status indicates on which output the signal is currently
257 active (e.g signal applied on output 1 and output 2 forced
258 inactive or vice versa).
259 (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
260 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
261 the idle push-pull status indicates during which period the
262 delayed protection request occurred (e.g. protection occurred
263 when the output 1 was active and output 2 forced inactive or
264 vice versa).
265
266 (#) Some functions can be used any time to retrieve actual HRTIM status
267 (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
268
269 *** Callback registration ***
270 =============================
271 [..]
272 The compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS when set to 1
273 allows the user to configure dynamically the driver callbacks.
274 Use Functions HAL_HRTIM_RegisterCallback() or HAL_HRTIM_TIMxRegisterCallback()
275 to register an interrupt callback.
276
277 [..]
278 Function HAL_HRTIM_RegisterCallback() allows to register following callbacks:
279 (+) Fault1Callback : Fault 1 interrupt callback function
280 (+) Fault2Callback : Fault 2 interrupt callback function
281 (+) Fault3Callback : Fault 3 interrupt callback function
282 (+) Fault4Callback : Fault 4 interrupt callback function
283 (+) Fault5Callback : Fault 5 interrupt callback function
284 (+) SystemFaultCallback : System fault interrupt callback function
285 (+) BurstModePeriodCallback : Burst mode period interrupt callback function
286 (+) SynchronizationEventCallback : Sync Input interrupt callback function
287 (+) ErrorCallback : DMA error callback function
288 (+) MspInitCallback : HRTIM MspInit callback function
289 (+) MspDeInitCallback : HRTIM MspInit callback function
290
291 [..]
292 Function HAL_HRTIM_TIMxRegisterCallback() allows to register following callbacks:
293 (+) RegistersUpdateCallback : Timer x Update interrupt callback function
294 (+) RepetitionEventCallback : Timer x Repetition interrupt callback function
295 (+) Compare1EventCallback : Timer x Compare 1 match interrupt callback function
296 (+) Compare2EventCallback : Timer x Compare 2 match interrupt callback function
297 (+) Compare3EventCallback : Timer x Compare 3 match interrupt callback function
298 (+) Compare4EventCallback : Timer x Compare 4 match interrupt callback function
299 (+) Capture1EventCallback : Timer x Capture 1 interrupts callback function
300 (+) Capture2EventCallback : Timer x Capture 2 interrupts callback function
301 (+) DelayedProtectionCallback : Timer x Delayed protection interrupt callback function
302 (+) CounterResetCallback : Timer x counter reset/roll-over interrupt callback function
303 (+) Output1SetCallback : Timer x output 1 set interrupt callback function
304 (+) Output1ResetCallback : Timer x output 1 reset interrupt callback function
305 (+) Output2SetCallback : Timer x output 2 set interrupt callback function
306 (+) Output2ResetCallback : Timer x output 2 reset interrupt callback function
307 (+) BurstDMATransferCallback : Timer x Burst DMA completed interrupt callback function
308
309 [..]
310 Both functions take as parameters the HAL peripheral handle, the Callback ID
311 and a pointer to the user callback function.
312
313 [..]
314 Use function HAL_HRTIM_UnRegisterCallback or HAL_HRTIM_TIMxUnRegisterCallback
315 to reset a callback to the default weak function. Both functions take as parameters
316 the HAL peripheral handle and the Callback ID.
317
318 [..]
319 By default, after the HAL_HRTIM_Init() and when the state is HAL_HRTIM_STATE_RESET
320 all callbacks are set to the corresponding weak functions (e.g HAL_HRTIM_Fault1Callback)
321 Exception done for MspInit and MspDeInit functions that are reset to the legacy
322 weak functions in the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() only when these
323 callbacks are null (not registered beforehand). If MspInit or MspDeInit are
324 not null, the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() keep and use the user
325 MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
326
327 [..]
328 Callbacks can be registered/unregistered in HAL_HRTIM_STATE_READY state only.
329 Exception done MspInit/MspDeInit functions that can be registered/unregistered
330 in HAL_HRTIM_STATE_READY or HAL_HRTIM_STATE_RESET states, thus registered
331 (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
332 Then, the user first registers the MspInit/MspDeInit user callbacks
333 using HAL_HRTIM_RegisterCallback() before calling HAL_HRTIM_DeInit()
334 or HAL_HRTIM_Init() function.
335
336 [..]
337 When the compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS is set to 0 or
338 not defined, the callback registration feature is not available and all
339 callbacks are set to the corresponding weak functions.
340
341 @endverbatim
342
343 ******************************************************************************
344 * @attention
345 *
346 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
347 * All rights reserved.</center></h2>
348 *
349 * This software component is licensed by ST under BSD 3-Clause license,
350 * the "License"; You may not use this file except in compliance with the
351 * License. You may obtain a copy of the License at:
352 * opensource.org/licenses/BSD-3-Clause
353 *
354 ******************************************************************************
355 */
356
357 /* Includes ------------------------------------------------------------------*/
358 #include "stm32h7xx_hal.h"
359
360 /** @addtogroup STM32H7xx_HAL_Driver
361 * @{
362 */
363
364 #ifdef HAL_HRTIM_MODULE_ENABLED
365
366 #if defined(HRTIM1)
367
368 /** @defgroup HRTIM HRTIM
369 * @brief HRTIM HAL module driver
370 * @{
371 */
372
373 /* Private typedef -----------------------------------------------------------*/
374 /* Private define ------------------------------------------------------------*/
375 /** @defgroup HRTIM_Private_Defines HRTIM Private Define
376 * @{
377 */
378 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
379 HRTIM_FLTR_FLT2EN |\
380 HRTIM_FLTR_FLT3EN |\
381 HRTIM_FLTR_FLT4EN | \
382 HRTIM_FLTR_FLT5EN)
383
384 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
385 HRTIM_TIMUPDATETRIGGER_TIMER_A |\
386 HRTIM_TIMUPDATETRIGGER_TIMER_B |\
387 HRTIM_TIMUPDATETRIGGER_TIMER_C |\
388 HRTIM_TIMUPDATETRIGGER_TIMER_D |\
389 HRTIM_TIMUPDATETRIGGER_TIMER_E)
390
391 #define HRTIM_FLTINR1_FLTxLCK ((HRTIM_FAULTLOCK_READONLY) | \
392 (HRTIM_FAULTLOCK_READONLY << 8U) | \
393 (HRTIM_FAULTLOCK_READONLY << 16U) | \
394 (HRTIM_FAULTLOCK_READONLY << 24U))
395
396 #define HRTIM_FLTINR2_FLTxLCK ((HRTIM_FAULTLOCK_READONLY) | \
397 (HRTIM_FAULTLOCK_READONLY << 8U))
398 /**
399 * @}
400 */
401
402 /* Private macro -------------------------------------------------------------*/
403 /* Private variables ---------------------------------------------------------*/
404 /** @defgroup HRTIM_Private_Variables HRTIM Private Variables
405 * @{
406 */
407 static uint32_t TimerIdxToTimerId[] =
408 {
409 HRTIM_TIMERID_TIMER_A,
410 HRTIM_TIMERID_TIMER_B,
411 HRTIM_TIMERID_TIMER_C,
412 HRTIM_TIMERID_TIMER_D,
413 HRTIM_TIMERID_TIMER_E,
414 HRTIM_TIMERID_MASTER,
415 };
416 /**
417 * @}
418 */
419
420 /* Private function prototypes -----------------------------------------------*/
421 /** @defgroup HRTIM_Private_Functions HRTIM Private Functions
422 * @{
423 */
424 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
425 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
426
427 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
428 uint32_t TimerIdx,
429 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
430
431 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
432 HRTIM_TimerCfgTypeDef * pTimerCfg);
433
434 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
435 uint32_t TimerIdx,
436 HRTIM_TimerCfgTypeDef * pTimerCfg);
437
438
439 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
440 uint32_t TimerIdx,
441 uint32_t CaptureUnit,
442 uint32_t Event);
443
444 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
445 uint32_t TimerIdx,
446 uint32_t Output,
447 HRTIM_OutputCfgTypeDef * pOutputCfg);
448
449 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
450 uint32_t Event,
451 HRTIM_EventCfgTypeDef * pEventCfg);
452
453 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
454 uint32_t TimerIdx,
455 uint32_t Event);
456
457 static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
458 uint32_t TimerIdx,
459 uint32_t OCChannel);
460
461 static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
462 uint32_t TimerIdx,
463 uint32_t OCChannel);
464
465 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
466 uint32_t TimerIdx);
467
468 static uint32_t GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim,
469 DMA_HandleTypeDef * hdma);
470
471 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
472 uint32_t TimerIdx);
473
474 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim);
475
476 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim);
477
478 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
479 uint32_t TimerIdx);
480
481 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
482
483 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
484
485 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
486
487 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
488 /**
489 * @}
490 */
491
492 /* Exported functions ---------------------------------------------------------*/
493 /** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
494 * @{
495 */
496
497 /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
498 * @brief Initialization and Configuration functions
499 @verbatim
500 ===============================================================================
501 ##### Initialization and Time Base Configuration functions #####
502 ===============================================================================
503 [..] This section provides functions allowing to:
504 (+) Initialize a HRTIM instance
505 (+) De-initialize a HRTIM instance
506 (+) Initialize the HRTIM MSP
507 (+) De-initialize the HRTIM MSP
508 (+) Configure the time base unit of a HRTIM timer
509
510 @endverbatim
511 * @{
512 */
513
514 /**
515 * @brief Initialize a HRTIM instance
516 * @param hhrtim pointer to HAL HRTIM handle
517 * @retval HAL status
518 */
519 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
520 {
521 uint8_t timer_idx;
522 uint32_t hrtim_mcr;
523
524 /* Check the HRTIM handle allocation */
525 if(hhrtim == NULL)
526 {
527 return HAL_ERROR;
528 }
529
530 /* Check the parameters */
531 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
532 assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests));
533
534 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
535 if (hhrtim->State == HAL_HRTIM_STATE_RESET)
536 {
537 /* Initialize callback function pointers to their default values */
538 hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
539 hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
540 hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
541 hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
542 hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
543 hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
544 hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
545 hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
546 hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
547 hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
548 hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
549 hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
550 hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
551 hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
552 hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
553 hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
554 hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
555 hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
556 hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
557 hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
558 hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
559 hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
560 hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
561 hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
562
563 if (hhrtim->MspInitCallback == NULL)
564 {
565 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
566 }
567 }
568 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
569
570 /* Set the HRTIM state */
571 hhrtim->State = HAL_HRTIM_STATE_BUSY;
572
573 /* Initialize the DMA handles */
574 hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
575 hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
576 hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
577 hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
578 hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
579 hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
580
581 /* HRTIM output synchronization configuration (if required) */
582 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != (uint32_t)RESET)
583 {
584 /* Check parameters */
585 assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
586 assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
587
588 /* The synchronization output initialization procedure must be done prior
589 to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
590 */
591 if (hhrtim->Instance == HRTIM1)
592 {
593 /* Enable the HRTIM peripheral clock */
594 __HAL_RCC_HRTIM1_CLK_ENABLE();
595 }
596
597 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
598
599 /* Set the event to be sent on the synchronization output */
600 hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
601 hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
602
603 /* Set the polarity of the synchronization output */
604 hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
605 hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
606
607 /* Update the HRTIM registers */
608 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
609 }
610
611 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
612 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
613 hhrtim->MspInitCallback(hhrtim);
614 #else
615 HAL_HRTIM_MspInit(hhrtim);
616 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
617
618 /* HRTIM input synchronization configuration (if required) */
619 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != (uint32_t)RESET)
620 {
621 /* Check parameters */
622 assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
623
624 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
625
626 /* Set the synchronization input source */
627 hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
628 hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
629
630 /* Update the HRTIM registers */
631 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
632 }
633
634 /* Initialize the HRTIM state*/
635 hhrtim->State = HAL_HRTIM_STATE_READY;
636
637 /* Initialize the lock status of the HRTIM HAL API */
638 __HAL_UNLOCK(hhrtim);
639
640 /* Initialize timer related parameters */
641 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
642 timer_idx <= HRTIM_TIMERINDEX_MASTER ;
643 timer_idx++)
644 {
645 hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
646 hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
647 hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
648 hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
649 hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U;
650 hhrtim->TimerParam[timer_idx].DMASize = 0U;
651 }
652
653 return HAL_OK;
654 }
655
656 /**
657 * @brief De-initialize a HRTIM instance
658 * @param hhrtim pointer to HAL HRTIM handle
659 * @retval HAL status
660 */
661 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
662 {
663 /* Check the HRTIM handle allocation */
664 if(hhrtim == NULL)
665 {
666 return HAL_ERROR;
667 }
668
669 /* Check the parameters */
670 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
671
672 /* Set the HRTIM state */
673 hhrtim->State = HAL_HRTIM_STATE_BUSY;
674
675 /* DeInit the low level hardware */
676 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
677 if (hhrtim->MspDeInitCallback == NULL)
678 {
679 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
680 }
681
682 hhrtim->MspDeInitCallback(hhrtim);
683 #else
684 HAL_HRTIM_MspDeInit(hhrtim);
685 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
686
687 hhrtim->State = HAL_HRTIM_STATE_READY;
688
689 return HAL_OK;
690 }
691
692 /**
693 * @brief MSP initialization for a HRTIM instance
694 * @param hhrtim pointer to HAL HRTIM handle
695 * @retval None
696 */
697 __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
698 {
699 /* Prevent unused argument(s) compilation warning */
700 UNUSED(hhrtim);
701
702 /* NOTE: This function should not be modified, when the callback is needed,
703 the HAL_HRTIM_MspInit could be implemented in the user file
704 */
705 }
706
707 /**
708 * @brief MSP de-initialization of a HRTIM instance
709 * @param hhrtim pointer to HAL HRTIM handle
710 * @retval None
711 */
712 __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
713 {
714 /* Prevent unused argument(s) compilation warning */
715 UNUSED(hhrtim);
716
717 /* NOTE: This function should not be modified, when the callback is needed,
718 the HAL_HRTIM_MspDeInit could be implemented in the user file
719 */
720 }
721
722 /**
723 * @brief Configure the time base unit of a timer
724 * @param hhrtim pointer to HAL HRTIM handle
725 * @param TimerIdx Timer index
726 * This parameter can be one of the following values:
727 * @arg HRTIM_TIMERINDEX_MASTER for master timer
728 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
729 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
730 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
731 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
732 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
733 * @param pTimeBaseCfg pointer to the time base configuration structure
734 * @note This function must be called prior starting the timer
735 * @note The time-base unit initialization parameters specify:
736 * The timer counter operating mode (continuous, one shot),
737 * The timer clock prescaler,
738 * The timer period,
739 * The timer repetition counter.
740 * @retval HAL status
741 */
742 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
743 uint32_t TimerIdx,
744 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
745 {
746 /* Check the parameters */
747 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
748 assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
749 assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
750
751 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
752 {
753 return HAL_BUSY;
754 }
755
756 /* Set the HRTIM state */
757 hhrtim->State = HAL_HRTIM_STATE_BUSY;
758
759 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
760 {
761 /* Configure master timer time base unit */
762 HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
763 }
764 else
765 {
766 /* Configure timing unit time base unit */
767 HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
768 }
769
770 /* Set HRTIM state */
771 hhrtim->State = HAL_HRTIM_STATE_READY;
772
773 return HAL_OK;
774 }
775
776 /**
777 * @}
778 */
779
780 /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
781 * @brief Simple time base mode functions.
782 @verbatim
783 ===============================================================================
784 ##### Simple time base mode functions #####
785 ===============================================================================
786 [..] This section provides functions allowing to:
787 (+) Start simple time base
788 (+) Stop simple time base
789 (+) Start simple time base and enable interrupt
790 (+) Stop simple time base and disable interrupt
791 (+) Start simple time base and enable DMA transfer
792 (+) Stop simple time base and disable DMA transfer
793 -@- When a HRTIM timer operates in simple time base mode, the timer
794 counter counts from 0 to the period value.
795
796 @endverbatim
797 * @{
798 */
799
800 /**
801 * @brief Start the counter of a timer operating in simple time base mode.
802 * @param hhrtim pointer to HAL HRTIM handle
803 * @param TimerIdx Timer index.
804 * This parameter can be one of the following values:
805 * @arg HRTIM_TIMERINDEX_MASTER for master timer
806 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
807 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
808 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
809 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
810 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
811 * @retval HAL status
812 */
813 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,
814 uint32_t TimerIdx)
815 {
816 /* Check the parameters */
817 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
818
819 /* Process Locked */
820 __HAL_LOCK(hhrtim);
821
822 hhrtim->State = HAL_HRTIM_STATE_BUSY;
823
824 /* Enable the timer counter */
825 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
826
827 hhrtim->State = HAL_HRTIM_STATE_READY;
828
829 /* Process Unlocked */
830 __HAL_UNLOCK(hhrtim);
831
832 return HAL_OK;
833 }
834
835 /**
836 * @brief Stop the counter of a timer operating in simple time base mode.
837 * @param hhrtim pointer to HAL HRTIM handle
838 * @param TimerIdx Timer index.
839 * This parameter can be one of the following values:
840 * @arg HRTIM_TIMERINDEX_MASTER for master timer
841 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
842 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
843 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
844 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
845 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
846 * @retval HAL status
847 */
848 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,
849 uint32_t TimerIdx)
850 {
851 /* Check the parameters */
852 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
853
854 /* Process Locked */
855 __HAL_LOCK(hhrtim);
856
857 hhrtim->State = HAL_HRTIM_STATE_BUSY;
858
859 /* Disable the timer counter */
860 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
861
862 hhrtim->State = HAL_HRTIM_STATE_READY;
863
864 /* Process Unlocked */
865 __HAL_UNLOCK(hhrtim);
866
867 return HAL_OK;
868 }
869
870 /**
871 * @brief Start the counter of a timer operating in simple time base mode
872 * (Timer repetition interrupt is enabled).
873 * @param hhrtim pointer to HAL HRTIM handle
874 * @param TimerIdx Timer index.
875 * This parameter can be one of the following values:
876 * @arg HRTIM_TIMERINDEX_MASTER for master timer
877 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
878 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
879 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
880 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
881 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
882 * @retval HAL status
883 */
884 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,
885 uint32_t TimerIdx)
886 {
887 /* Check the parameters */
888 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
889
890 /* Process Locked */
891 __HAL_LOCK(hhrtim);
892
893 hhrtim->State = HAL_HRTIM_STATE_BUSY;
894
895 /* Enable the repetition interrupt */
896 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
897 {
898 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
899 }
900 else
901 {
902 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
903 }
904
905 /* Enable the timer counter */
906 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
907
908 hhrtim->State = HAL_HRTIM_STATE_READY;
909
910 /* Process Unlocked */
911 __HAL_UNLOCK(hhrtim);
912
913 return HAL_OK;
914 }
915
916 /**
917 * @brief Stop the counter of a timer operating in simple time base mode
918 * (Timer repetition interrupt is disabled).
919 * @param hhrtim pointer to HAL HRTIM handle
920 * @param TimerIdx Timer index.
921 * This parameter can be one of the following values:
922 * @arg HRTIM_TIMERINDEX_MASTER for master timer
923 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
924 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
925 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
926 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
927 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
928 * @retval HAL status
929 */
930 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
931 uint32_t TimerIdx)
932 {
933 /* Check the parameters */
934 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
935
936 /* Process Locked */
937 __HAL_LOCK(hhrtim);
938
939 hhrtim->State = HAL_HRTIM_STATE_BUSY;
940
941 /* Disable the repetition interrupt */
942 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
943 {
944 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
945 }
946 else
947 {
948 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
949 }
950
951 /* Disable the timer counter */
952 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
953
954 hhrtim->State = HAL_HRTIM_STATE_READY;
955
956 /* Process Unlocked */
957 __HAL_UNLOCK(hhrtim);
958
959 return HAL_OK;
960 }
961
962 /**
963 * @brief Start the counter of a timer operating in simple time base mode
964 * (Timer repetition DMA request is enabled).
965 * @param hhrtim pointer to HAL HRTIM handle
966 * @param TimerIdx Timer index.
967 * This parameter can be one of the following values:
968 * @arg HRTIM_TIMERINDEX_MASTER for master timer
969 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
970 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
971 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
972 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
973 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
974 * @param SrcAddr DMA transfer source address
975 * @param DestAddr DMA transfer destination address
976 * @param Length The length of data items (data size) to be transferred
977 * from source to destination
978 */
979 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
980 uint32_t TimerIdx,
981 uint32_t SrcAddr,
982 uint32_t DestAddr,
983 uint32_t Length)
984 {
985 DMA_HandleTypeDef * hdma;
986
987 /* Check the parameters */
988 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
989
990 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
991 {
992 return HAL_BUSY;
993 }
994 if(hhrtim->State == HAL_HRTIM_STATE_READY)
995 {
996 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
997 {
998 return HAL_ERROR;
999 }
1000 else
1001 {
1002 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1003 }
1004 }
1005
1006 /* Process Locked */
1007 __HAL_LOCK(hhrtim);
1008
1009 /* Get the timer DMA handler */
1010 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1011
1012 if (hdma == NULL)
1013 {
1014 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1015
1016 /* Process Unlocked */
1017 __HAL_UNLOCK(hhrtim);
1018
1019 return HAL_ERROR;
1020 }
1021
1022 /* Set the DMA transfer completed callback */
1023 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1024 {
1025 hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
1026 }
1027 else
1028 {
1029 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1030 }
1031
1032 /* Set the DMA error callback */
1033 hdma->XferErrorCallback = HRTIM_DMAError ;
1034
1035 /* Enable the DMA channel */
1036 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
1037 {
1038 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1039
1040 /* Process Unlocked */
1041 __HAL_UNLOCK(hhrtim);
1042
1043 return HAL_ERROR;
1044 }
1045
1046 /* Enable the timer repetition DMA request */
1047 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1048 {
1049 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1050 }
1051 else
1052 {
1053 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1054 }
1055
1056 /* Enable the timer counter */
1057 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1058
1059 hhrtim->State = HAL_HRTIM_STATE_READY;
1060
1061 /* Process Unlocked */
1062 __HAL_UNLOCK(hhrtim);
1063
1064 return HAL_OK;
1065 }
1066
1067 /**
1068 * @brief Stop the counter of a timer operating in simple time base mode
1069 * (Timer repetition DMA request is disabled).
1070 * @param hhrtim pointer to HAL HRTIM handle
1071 * @param TimerIdx Timer index.
1072 * This parameter can be one of the following values:
1073 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1074 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1075 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1076 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1077 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1078 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1079 * @retval HAL status
1080 */
1081 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
1082 uint32_t TimerIdx)
1083 {
1084 DMA_HandleTypeDef * hdma;
1085
1086 /* Check the parameters */
1087 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1088
1089 /* Process Locked */
1090 __HAL_LOCK(hhrtim);
1091
1092 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1093 {
1094 hhrtim->State = HAL_HRTIM_STATE_READY;
1095
1096 /* Disable the DMA */
1097 if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
1098 {
1099 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1100 }
1101 /* Disable the timer repetition DMA request */
1102 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1103 }
1104 else
1105 {
1106 /* Get the timer DMA handler */
1107 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1108
1109 if (hdma == NULL)
1110 {
1111 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1112 }
1113 else
1114 {
1115 hhrtim->State = HAL_HRTIM_STATE_READY;
1116
1117 /* Disable the DMA */
1118 if (HAL_DMA_Abort(hdma) != HAL_OK)
1119 {
1120 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1121 }
1122
1123 /* Disable the timer repetition DMA request */
1124 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1125 }
1126 }
1127
1128 /* Disable the timer counter */
1129 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1130
1131 /* Process Unlocked */
1132 __HAL_UNLOCK(hhrtim);
1133
1134 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
1135 {
1136 return HAL_ERROR;
1137 }
1138 else
1139 {
1140 return HAL_OK;
1141 }
1142 }
1143
1144 /**
1145 * @}
1146 */
1147
1148 /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
1149 * @brief Simple output compare functions
1150 @verbatim
1151 ===============================================================================
1152 ##### Simple output compare functions #####
1153 ===============================================================================
1154 [..] This section provides functions allowing to:
1155 (+) Configure simple output channel
1156 (+) Start simple output compare
1157 (+) Stop simple output compare
1158 (+) Start simple output compare and enable interrupt
1159 (+) Stop simple output compare and disable interrupt
1160 (+) Start simple output compare and enable DMA transfer
1161 (+) Stop simple output compare and disable DMA transfer
1162 -@- When a HRTIM timer operates in simple output compare mode
1163 the output level is set to a programmable value when a match
1164 is found between the compare register and the counter.
1165 Compare unit 1 is automatically associated to output 1
1166 Compare unit 2 is automatically associated to output 2
1167 @endverbatim
1168 * @{
1169 */
1170
1171 /**
1172 * @brief Configure an output in simple output compare mode
1173 * @param hhrtim pointer to HAL HRTIM handle
1174 * @param TimerIdx Timer index
1175 * This parameter can be one of the following values:
1176 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1177 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1178 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1179 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1180 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1181 * @param OCChannel Timer output
1182 * This parameter can be one of the following values:
1183 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1184 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1185 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1186 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1187 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1188 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1189 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1190 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1191 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1192 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1193 * @param pSimpleOCChannelCfg pointer to the simple output compare output configuration structure
1194 * @note When the timer operates in simple output compare mode:
1195 * Output 1 is implicitly controlled by the compare unit 1
1196 * Output 2 is implicitly controlled by the compare unit 2
1197 * Output Set/Reset crossbar is set according to the selected output compare mode:
1198 * Toggle: SETxyR = RSTxyR = CMPy
1199 * Active: SETxyR = CMPy, RSTxyR = 0
1200 * Inactive: SETxy =0, RSTxy = CMPy
1201 * @retval HAL status
1202 */
1203 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
1204 uint32_t TimerIdx,
1205 uint32_t OCChannel,
1206 HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
1207 {
1208 uint32_t CompareUnit = (uint32_t)RESET;
1209 HRTIM_OutputCfgTypeDef OutputCfg;
1210
1211 /* Check parameters */
1212 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1213 assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
1214 assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOCChannelCfg->Pulse));
1215 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
1216 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
1217
1218 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1219 {
1220 return HAL_BUSY;
1221 }
1222
1223 /* Set HRTIM state */
1224 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1225
1226 /* Configure timer compare unit */
1227 switch (OCChannel)
1228 {
1229 case HRTIM_OUTPUT_TA1:
1230 case HRTIM_OUTPUT_TB1:
1231 case HRTIM_OUTPUT_TC1:
1232 case HRTIM_OUTPUT_TD1:
1233 case HRTIM_OUTPUT_TE1:
1234 {
1235 CompareUnit = HRTIM_COMPAREUNIT_1;
1236 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOCChannelCfg->Pulse;
1237 break;
1238 }
1239 case HRTIM_OUTPUT_TA2:
1240 case HRTIM_OUTPUT_TB2:
1241 case HRTIM_OUTPUT_TC2:
1242 case HRTIM_OUTPUT_TD2:
1243 case HRTIM_OUTPUT_TE2:
1244 {
1245 CompareUnit = HRTIM_COMPAREUNIT_2;
1246 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOCChannelCfg->Pulse;
1247 break;
1248 }
1249 default:
1250 {
1251 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1252
1253 /* Process Unlocked */
1254 __HAL_UNLOCK(hhrtim);
1255
1256 break;
1257 }
1258 }
1259
1260 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
1261 {
1262 return HAL_ERROR;
1263 }
1264
1265 /* Configure timer output */
1266 OutputCfg.Polarity = (pSimpleOCChannelCfg->Polarity & HRTIM_OUTR_POL1);
1267 OutputCfg.IdleLevel = (pSimpleOCChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1);
1268 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
1269 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1270 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1271 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1272
1273 switch (pSimpleOCChannelCfg->Mode)
1274 {
1275 case HRTIM_BASICOCMODE_TOGGLE:
1276 {
1277 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1278 {
1279 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1280 }
1281 else
1282 {
1283 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1284 }
1285 OutputCfg.ResetSource = OutputCfg.SetSource;
1286 break;
1287 }
1288
1289 case HRTIM_BASICOCMODE_ACTIVE:
1290 {
1291 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1292 {
1293 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1294 }
1295 else
1296 {
1297 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1298 }
1299 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1300 break;
1301 }
1302
1303 case HRTIM_BASICOCMODE_INACTIVE:
1304 {
1305 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1306 {
1307 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
1308 }
1309 else
1310 {
1311 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
1312 }
1313 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1314 break;
1315 }
1316
1317 default:
1318 {
1319 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1320 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1321
1322 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1323
1324 /* Process Unlocked */
1325 __HAL_UNLOCK(hhrtim);
1326
1327 break;
1328 }
1329 }
1330
1331 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
1332 {
1333 return HAL_ERROR;
1334 }
1335
1336 HRTIM_OutputConfig(hhrtim,
1337 TimerIdx,
1338 OCChannel,
1339 &OutputCfg);
1340
1341 /* Set HRTIM state */
1342 hhrtim->State = HAL_HRTIM_STATE_READY;
1343
1344 return HAL_OK;
1345 }
1346
1347 /**
1348 * @brief Start the output compare signal generation on the designed timer output
1349 * @param hhrtim pointer to HAL HRTIM handle
1350 * @param TimerIdx Timer index
1351 * This parameter can be one of the following values:
1352 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1353 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1354 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1355 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1356 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1357 * @param OCChannel Timer output
1358 * This parameter can be one of the following values:
1359 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1360 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1361 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1362 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1363 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1364 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1365 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1366 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1367 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1368 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1369 * @retval HAL status
1370 */
1371 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,
1372 uint32_t TimerIdx,
1373 uint32_t OCChannel)
1374 {
1375 /* Check the parameters */
1376 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1377
1378 /* Process Locked */
1379 __HAL_LOCK(hhrtim);
1380
1381 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1382
1383 /* Enable the timer output */
1384 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1385
1386 /* Enable the timer counter */
1387 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1388
1389 hhrtim->State = HAL_HRTIM_STATE_READY;
1390
1391 /* Process Unlocked */
1392 __HAL_UNLOCK(hhrtim);
1393
1394 return HAL_OK;
1395 }
1396
1397 /**
1398 * @brief Stop the output compare signal generation on the designed timer output
1399 * @param hhrtim pointer to HAL HRTIM handle
1400 * @param TimerIdx Timer index
1401 * This parameter can be one of the following values:
1402 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1403 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1404 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1405 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1406 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1407 * @param OCChannel Timer output
1408 * This parameter can be one of the following values:
1409 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1410 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1411 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1412 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1413 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1414 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1415 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1416 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1417 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1418 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1419 * @retval HAL status
1420 */
1421 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,
1422 uint32_t TimerIdx,
1423 uint32_t OCChannel)
1424 {
1425 /* Check the parameters */
1426 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1427
1428 /* Process Locked */
1429 __HAL_LOCK(hhrtim);
1430
1431 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1432
1433 /* Disable the timer output */
1434 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1435
1436 /* Disable the timer counter */
1437 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1438
1439 hhrtim->State = HAL_HRTIM_STATE_READY;
1440
1441 /* Process Unlocked */
1442 __HAL_UNLOCK(hhrtim);
1443
1444 return HAL_OK;
1445 }
1446
1447 /**
1448 * @brief Start the output compare signal generation on the designed timer output
1449 * (Interrupt is enabled (see note note below)).
1450 * @param hhrtim pointer to HAL HRTIM handle
1451 * @param TimerIdx Timer index
1452 * This parameter can be one of the following values:
1453 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1454 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1455 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1456 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1457 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1458 * @param OCChannel Timer output
1459 * This parameter can be one of the following values:
1460 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1461 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1462 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1463 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1464 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1465 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1466 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1467 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1468 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1469 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1470 * @note Interrupt enabling depends on the chosen output compare mode
1471 * Output toggle: compare match interrupt is enabled
1472 * Output set active: output set interrupt is enabled
1473 * Output set inactive: output reset interrupt is enabled
1474 * @retval HAL status
1475 */
1476 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,
1477 uint32_t TimerIdx,
1478 uint32_t OCChannel)
1479 {
1480 uint32_t interrupt;
1481
1482 /* Check the parameters */
1483 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1484
1485 /* Process Locked */
1486 __HAL_LOCK(hhrtim);
1487
1488 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1489
1490 /* Get the interrupt to enable (depends on the output compare mode) */
1491 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1492
1493 /* Enable the timer output */
1494 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1495
1496 /* Enable the timer interrupt (depends on the output compare mode) */
1497 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
1498
1499 /* Enable the timer counter */
1500 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1501
1502 hhrtim->State = HAL_HRTIM_STATE_READY;
1503
1504 /* Process Unlocked */
1505 __HAL_UNLOCK(hhrtim);
1506
1507 return HAL_OK;
1508 }
1509
1510 /**
1511 * @brief Stop the output compare signal generation on the designed timer output
1512 * (Interrupt is disabled).
1513 * @param hhrtim pointer to HAL HRTIM handle
1514 * @param TimerIdx Timer index
1515 * This parameter can be one of the following values:
1516 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1517 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1518 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1519 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1520 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1521 * @param OCChannel Timer output
1522 * This parameter can be one of the following values:
1523 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1524 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1525 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1526 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1527 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1528 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1529 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1530 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1531 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1532 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1533 * @retval HAL status
1534 */
1535 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
1536 uint32_t TimerIdx,
1537 uint32_t OCChannel)
1538 {
1539 uint32_t interrupt;
1540
1541 /* Check the parameters */
1542 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1543
1544 /* Process Locked */
1545 __HAL_LOCK(hhrtim);
1546
1547 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1548
1549 /* Disable the timer output */
1550 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1551
1552 /* Get the interrupt to disable (depends on the output compare mode) */
1553 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1554
1555 /* Disable the timer interrupt */
1556 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
1557
1558 /* Disable the timer counter */
1559 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1560
1561 hhrtim->State = HAL_HRTIM_STATE_READY;
1562
1563 /* Process Unlocked */
1564 __HAL_UNLOCK(hhrtim);
1565
1566 return HAL_OK;
1567 }
1568
1569 /**
1570 * @brief Start the output compare signal generation on the designed timer output
1571 * (DMA request is enabled (see note below)).
1572 * @param hhrtim pointer to HAL HRTIM handle
1573 * @param TimerIdx Timer index
1574 * This parameter can be one of the following values:
1575 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1576 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1577 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1578 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1579 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1580 * @param OCChannel Timer output
1581 * This parameter can be one of the following values:
1582 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1583 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1584 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1585 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1586 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1587 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1588 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1589 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1590 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1591 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1592 * @param SrcAddr DMA transfer source address
1593 * @param DestAddr DMA transfer destination address
1594 * @param Length The length of data items (data size) to be transferred
1595 * from source to destination
1596 * @note DMA request enabling depends on the chosen output compare mode
1597 * Output toggle: compare match DMA request is enabled
1598 * Output set active: output set DMA request is enabled
1599 * Output set inactive: output reset DMA request is enabled
1600 * @retval HAL status
1601 */
1602 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
1603 uint32_t TimerIdx,
1604 uint32_t OCChannel,
1605 uint32_t SrcAddr,
1606 uint32_t DestAddr,
1607 uint32_t Length)
1608 {
1609 DMA_HandleTypeDef * hdma;
1610 uint32_t dma_request;
1611
1612 /* Check the parameters */
1613 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1614
1615 if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
1616 {
1617 return HAL_BUSY;
1618 }
1619 if((hhrtim->State == HAL_HRTIM_STATE_READY))
1620 {
1621 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
1622 {
1623 return HAL_ERROR;
1624 }
1625 else
1626 {
1627 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1628 }
1629 }
1630
1631 /* Process Locked */
1632 __HAL_LOCK(hhrtim);
1633
1634 /* Enable the timer output */
1635 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1636
1637 /* Get the DMA request to enable */
1638 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1639
1640 /* Get the timer DMA handler */
1641 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1642
1643 if (hdma == NULL)
1644 {
1645 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1646
1647 /* Process Unlocked */
1648 __HAL_UNLOCK(hhrtim);
1649
1650 return HAL_ERROR;
1651 }
1652
1653 /* Set the DMA error callback */
1654 hdma->XferErrorCallback = HRTIM_DMAError ;
1655
1656 /* Set the DMA transfer completed callback */
1657 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1658
1659 /* Enable the DMA channel */
1660 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
1661 {
1662 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1663
1664 /* Process Unlocked */
1665 __HAL_UNLOCK(hhrtim);
1666
1667 return HAL_ERROR;
1668 }
1669
1670 /* Enable the timer DMA request */
1671 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
1672
1673 /* Enable the timer counter */
1674 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1675
1676 hhrtim->State = HAL_HRTIM_STATE_READY;
1677
1678 /* Process Unlocked */
1679 __HAL_UNLOCK(hhrtim);
1680
1681 return HAL_OK;
1682 }
1683
1684 /**
1685 * @brief Stop the output compare signal generation on the designed timer output
1686 * (DMA request is disabled).
1687 * @param hhrtim pointer to HAL HRTIM handle
1688 * @param TimerIdx Timer index
1689 * This parameter can be one of the following values:
1690 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1691 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1692 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1693 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1694 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1695 * @param OCChannel Timer output
1696 * This parameter can be one of the following values:
1697 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1698 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1699 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1700 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1701 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1702 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1703 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1704 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1705 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1706 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1707 * @retval HAL status
1708 */
1709 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
1710 uint32_t TimerIdx,
1711 uint32_t OCChannel)
1712 {
1713 uint32_t dma_request;
1714
1715 /* Check the parameters */
1716 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1717
1718 /* Process Locked */
1719 __HAL_LOCK(hhrtim);
1720
1721 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1722
1723 /* Disable the timer output */
1724 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1725
1726 /* Get the timer DMA handler */
1727 /* Disable the DMA */
1728 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
1729 {
1730 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1731
1732 /* Process Unlocked */
1733 __HAL_UNLOCK(hhrtim);
1734
1735 return HAL_ERROR;
1736 }
1737
1738 /* Get the DMA request to disable */
1739 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1740
1741 /* Disable the timer DMA request */
1742 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
1743
1744 /* Disable the timer counter */
1745 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1746
1747 hhrtim->State = HAL_HRTIM_STATE_READY;
1748
1749 /* Process Unlocked */
1750 __HAL_UNLOCK(hhrtim);
1751
1752 return HAL_OK;
1753 }
1754
1755 /**
1756 * @}
1757 */
1758
1759 /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
1760 * @brief Simple PWM output functions
1761 @verbatim
1762 ===============================================================================
1763 ##### Simple PWM output functions #####
1764 ===============================================================================
1765 [..] This section provides functions allowing to:
1766 (+) Configure simple PWM output channel
1767 (+) Start simple PWM output
1768 (+) Stop simple PWM output
1769 (+) Start simple PWM output and enable interrupt
1770 (+) Stop simple PWM output and disable interrupt
1771 (+) Start simple PWM output and enable DMA transfer
1772 (+) Stop simple PWM output and disable DMA transfer
1773 -@- When a HRTIM timer operates in simple PWM output mode
1774 the output level is set to a programmable value when a match is
1775 found between the compare register and the counter and reset when
1776 the timer period is reached. Duty cycle is determined by the
1777 comparison value.
1778 Compare unit 1 is automatically associated to output 1
1779 Compare unit 2 is automatically associated to output 2
1780 @endverbatim
1781 * @{
1782 */
1783
1784 /**
1785 * @brief Configure an output in simple PWM mode
1786 * @param hhrtim pointer to HAL HRTIM handle
1787 * @param TimerIdx Timer index
1788 * This parameter can be one of the following values:
1789 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1790 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1791 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1792 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1793 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1794 * @param PWMChannel Timer output
1795 * This parameter can be one of the following values:
1796 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1797 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1798 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1799 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1800 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1801 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1802 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1803 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1804 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1805 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1806 * @param pSimplePWMChannelCfg pointer to the simple PWM output configuration structure
1807 * @note When the timer operates in simple PWM output mode:
1808 * Output 1 is implicitly controlled by the compare unit 1
1809 * Output 2 is implicitly controlled by the compare unit 2
1810 * Output Set/Reset crossbar is set as follows:
1811 * Output 1: SETx1R = CMP1, RSTx1R = PER
1812 * Output 2: SETx2R = CMP2, RST2R = PER
1813 * @note When Simple PWM mode is used the registers preload mechanism is
1814 * enabled (otherwise the behavior is not guaranteed).
1815 * @retval HAL status
1816 */
1817 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
1818 uint32_t TimerIdx,
1819 uint32_t PWMChannel,
1820 HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
1821 {
1822 HRTIM_OutputCfgTypeDef OutputCfg;
1823 uint32_t hrtim_timcr;
1824
1825 /* Check parameters */
1826 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1827 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
1828 assert_param(IS_HRTIM_OUTPUTPULSE(pSimplePWMChannelCfg->Pulse));
1829 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
1830
1831 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1832 {
1833 return HAL_BUSY;
1834 }
1835
1836 /* Process Locked */
1837 __HAL_LOCK(hhrtim);
1838
1839 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1840
1841 /* Configure timer compare unit */
1842 switch (PWMChannel)
1843 {
1844 case HRTIM_OUTPUT_TA1:
1845 case HRTIM_OUTPUT_TB1:
1846 case HRTIM_OUTPUT_TC1:
1847 case HRTIM_OUTPUT_TD1:
1848 case HRTIM_OUTPUT_TE1:
1849 {
1850 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimplePWMChannelCfg->Pulse;
1851 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1852 break;
1853 }
1854
1855 case HRTIM_OUTPUT_TA2:
1856 case HRTIM_OUTPUT_TB2:
1857 case HRTIM_OUTPUT_TC2:
1858 case HRTIM_OUTPUT_TD2:
1859 case HRTIM_OUTPUT_TE2:
1860 {
1861 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimplePWMChannelCfg->Pulse;
1862 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1863 break;
1864 }
1865 default:
1866 {
1867 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1868 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1869
1870 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1871
1872 /* Process Unlocked */
1873 __HAL_UNLOCK(hhrtim);
1874
1875 break;
1876 }
1877 }
1878
1879 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
1880 {
1881 return HAL_ERROR;
1882 }
1883
1884 /* Configure timer output */
1885 OutputCfg.Polarity = (pSimplePWMChannelCfg->Polarity & HRTIM_OUTR_POL1);
1886 OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel& HRTIM_OUTR_IDLES1);
1887 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
1888 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1889 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1890 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1891 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
1892
1893 HRTIM_OutputConfig(hhrtim,
1894 TimerIdx,
1895 PWMChannel,
1896 &OutputCfg);
1897
1898 /* Enable the registers preload mechanism */
1899 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
1900 hrtim_timcr |= HRTIM_TIMCR_PREEN;
1901 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
1902
1903 hhrtim->State = HAL_HRTIM_STATE_READY;
1904
1905 /* Process Unlocked */
1906 __HAL_UNLOCK(hhrtim);
1907
1908 return HAL_OK;
1909 }
1910
1911 /**
1912 * @brief Start the PWM output signal generation on the designed timer output
1913 * @param hhrtim pointer to HAL HRTIM handle
1914 * @param TimerIdx Timer index
1915 * This parameter can be one of the following values:
1916 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1917 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1918 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1919 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1920 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1921 * @param PWMChannel Timer output
1922 * This parameter can be one of the following values:
1923 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1924 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1925 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1926 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1927 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1928 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1929 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1930 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1931 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1932 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1933 * @retval HAL status
1934 */
1935 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,
1936 uint32_t TimerIdx,
1937 uint32_t PWMChannel)
1938 {
1939 /* Check the parameters */
1940 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1941
1942 /* Process Locked */
1943 __HAL_LOCK(hhrtim);
1944
1945 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1946
1947 /* Enable the timer output */
1948 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
1949
1950 /* Enable the timer counter */
1951 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1952
1953 hhrtim->State = HAL_HRTIM_STATE_READY;
1954
1955 /* Process Unlocked */
1956 __HAL_UNLOCK(hhrtim);
1957
1958 return HAL_OK;
1959 }
1960
1961 /**
1962 * @brief Stop the PWM output signal generation on the designed timer output
1963 * @param hhrtim pointer to HAL HRTIM handle
1964 * @param TimerIdx Timer index
1965 * This parameter can be one of the following values:
1966 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1967 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1968 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1969 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1970 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1971 * @param PWMChannel Timer output
1972 * This parameter can be one of the following values:
1973 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1974 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1975 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1976 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1977 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1978 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1979 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1980 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1981 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1982 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1983 * @retval HAL status
1984 */
1985 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,
1986 uint32_t TimerIdx,
1987 uint32_t PWMChannel)
1988 {
1989 /* Check the parameters */
1990 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1991
1992 /* Process Locked */
1993 __HAL_LOCK(hhrtim);
1994
1995 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1996
1997 /* Disable the timer output */
1998 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
1999
2000 /* Disable the timer counter */
2001 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2002
2003 hhrtim->State = HAL_HRTIM_STATE_READY;
2004
2005 /* Process Unlocked */
2006 __HAL_UNLOCK(hhrtim);
2007
2008 return HAL_OK;
2009 }
2010
2011 /**
2012 * @brief Start the PWM output signal generation on the designed timer output
2013 * (The compare interrupt is enabled).
2014 * @param hhrtim pointer to HAL HRTIM handle
2015 * @param TimerIdx Timer index
2016 * This parameter can be one of the following values:
2017 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2018 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2019 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2020 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2021 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2022 * @param PWMChannel Timer output
2023 * This parameter can be one of the following values:
2024 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2025 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2026 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2027 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2028 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2029 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2030 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2031 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2032 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2033 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2034 * @retval HAL status
2035 */
2036 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
2037 uint32_t TimerIdx,
2038 uint32_t PWMChannel)
2039 {
2040 /* Check the parameters */
2041 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2042
2043 /* Process Locked */
2044 __HAL_LOCK(hhrtim);
2045
2046 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2047
2048 /* Enable the timer output */
2049 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2050
2051 /* Enable the timer interrupt (depends on the PWM output) */
2052 switch (PWMChannel)
2053 {
2054 case HRTIM_OUTPUT_TA1:
2055 case HRTIM_OUTPUT_TB1:
2056 case HRTIM_OUTPUT_TC1:
2057 case HRTIM_OUTPUT_TD1:
2058 case HRTIM_OUTPUT_TE1:
2059 {
2060 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2061 break;
2062 }
2063
2064 case HRTIM_OUTPUT_TA2:
2065 case HRTIM_OUTPUT_TB2:
2066 case HRTIM_OUTPUT_TC2:
2067 case HRTIM_OUTPUT_TD2:
2068 case HRTIM_OUTPUT_TE2:
2069 {
2070 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2071 break;
2072 }
2073
2074 default:
2075 {
2076 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2077
2078 /* Process Unlocked */
2079 __HAL_UNLOCK(hhrtim);
2080
2081 break;
2082 }
2083 }
2084
2085 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2086 {
2087 return HAL_ERROR;
2088 }
2089
2090 /* Enable the timer counter */
2091 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2092
2093 hhrtim->State = HAL_HRTIM_STATE_READY;
2094
2095 /* Process Unlocked */
2096 __HAL_UNLOCK(hhrtim);
2097
2098 return HAL_OK;
2099 }
2100
2101 /**
2102 * @brief Stop the PWM output signal generation on the designed timer output
2103 * (The compare interrupt is disabled).
2104 * @param hhrtim pointer to HAL HRTIM handle
2105 * @param TimerIdx Timer index
2106 * This parameter can be one of the following values:
2107 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2108 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2109 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2110 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2111 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2112 * @param PWMChannel Timer output
2113 * This parameter can be one of the following values:
2114 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2115 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2116 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2117 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2118 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2119 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2120 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2121 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2122 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2123 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2124 * @retval HAL status
2125 */
2126 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
2127 uint32_t TimerIdx,
2128 uint32_t PWMChannel)
2129 {
2130 /* Check the parameters */
2131 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2132
2133 /* Process Locked */
2134 __HAL_LOCK(hhrtim);
2135
2136 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2137
2138 /* Disable the timer output */
2139 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2140
2141 /* Disable the timer interrupt (depends on the PWM output) */
2142 switch (PWMChannel)
2143 {
2144 case HRTIM_OUTPUT_TA1:
2145 case HRTIM_OUTPUT_TB1:
2146 case HRTIM_OUTPUT_TC1:
2147 case HRTIM_OUTPUT_TD1:
2148 case HRTIM_OUTPUT_TE1:
2149 {
2150 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2151 break;
2152 }
2153
2154 case HRTIM_OUTPUT_TA2:
2155 case HRTIM_OUTPUT_TB2:
2156 case HRTIM_OUTPUT_TC2:
2157 case HRTIM_OUTPUT_TD2:
2158 case HRTIM_OUTPUT_TE2:
2159 {
2160 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2161 break;
2162 }
2163
2164 default:
2165 {
2166 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2167
2168 /* Process Unlocked */
2169 __HAL_UNLOCK(hhrtim);
2170
2171 break;
2172 }
2173 }
2174
2175 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2176 {
2177 return HAL_ERROR;
2178 }
2179
2180 /* Disable the timer counter */
2181 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2182
2183 hhrtim->State = HAL_HRTIM_STATE_READY;
2184
2185 /* Process Unlocked */
2186 __HAL_UNLOCK(hhrtim);
2187
2188 return HAL_OK;
2189 }
2190
2191 /**
2192 * @brief Start the PWM output signal generation on the designed timer output
2193 * (The compare DMA request is enabled).
2194 * @param hhrtim pointer to HAL HRTIM handle
2195 * @param TimerIdx Timer index
2196 * This parameter can be one of the following values:
2197 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2198 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2199 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2200 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2201 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2202 * @param PWMChannel Timer output
2203 * This parameter can be one of the following values:
2204 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2205 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2206 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2207 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2208 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2209 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2210 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2211 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2212 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2213 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2214 * @param SrcAddr DMA transfer source address
2215 * @param DestAddr DMA transfer destination address
2216 * @param Length The length of data items (data size) to be transferred
2217 * from source to destination
2218 * @retval HAL status
2219 */
2220 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
2221 uint32_t TimerIdx,
2222 uint32_t PWMChannel,
2223 uint32_t SrcAddr,
2224 uint32_t DestAddr,
2225 uint32_t Length)
2226 {
2227 DMA_HandleTypeDef * hdma;
2228
2229 /* Check the parameters */
2230 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2231
2232 if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
2233 {
2234 return HAL_BUSY;
2235 }
2236 if((hhrtim->State == HAL_HRTIM_STATE_READY))
2237 {
2238 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
2239 {
2240 return HAL_ERROR;
2241 }
2242 else
2243 {
2244 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2245 }
2246 }
2247
2248 /* Process Locked */
2249 __HAL_LOCK(hhrtim);
2250
2251 /* Enable the timer output */
2252 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2253
2254 /* Get the timer DMA handler */
2255 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2256
2257 if (hdma == NULL)
2258 {
2259 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2260
2261 /* Process Unlocked */
2262 __HAL_UNLOCK(hhrtim);
2263
2264 return HAL_ERROR;
2265 }
2266
2267 /* Set the DMA error callback */
2268 hdma->XferErrorCallback = HRTIM_DMAError ;
2269
2270 /* Set the DMA transfer completed callback */
2271 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
2272
2273 /* Enable the DMA channel */
2274 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
2275 {
2276 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2277
2278 /* Process Unlocked */
2279 __HAL_UNLOCK(hhrtim);
2280
2281 return HAL_ERROR;
2282 }
2283
2284 /* Enable the timer DMA request */
2285 switch (PWMChannel)
2286 {
2287 case HRTIM_OUTPUT_TA1:
2288 case HRTIM_OUTPUT_TB1:
2289 case HRTIM_OUTPUT_TC1:
2290 case HRTIM_OUTPUT_TD1:
2291 case HRTIM_OUTPUT_TE1:
2292 {
2293 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2294 break;
2295 }
2296
2297 case HRTIM_OUTPUT_TA2:
2298 case HRTIM_OUTPUT_TB2:
2299 case HRTIM_OUTPUT_TC2:
2300 case HRTIM_OUTPUT_TD2:
2301 case HRTIM_OUTPUT_TE2:
2302 {
2303 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2304 break;
2305 }
2306
2307 default:
2308 {
2309 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2310
2311 /* Process Unlocked */
2312 __HAL_UNLOCK(hhrtim);
2313
2314 break;
2315 }
2316 }
2317
2318 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2319 {
2320 return HAL_ERROR;
2321 }
2322
2323 /* Enable the timer counter */
2324 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2325
2326 hhrtim->State = HAL_HRTIM_STATE_READY;
2327
2328 /* Process Unlocked */
2329 __HAL_UNLOCK(hhrtim);
2330
2331 return HAL_OK;
2332 }
2333
2334 /**
2335 * @brief Stop the PWM output signal generation on the designed timer output
2336 * (The compare DMA request is disabled).
2337 * @param hhrtim pointer to HAL HRTIM handle
2338 * @param TimerIdx Timer index
2339 * This parameter can be one of the following values:
2340 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2341 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2342 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2343 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2344 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2345 * @param PWMChannel Timer output
2346 * This parameter can be one of the following values:
2347 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2348 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2349 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2350 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2351 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2352 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2353 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2354 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2355 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2356 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2357 * @retval HAL status
2358 */
2359 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
2360 uint32_t TimerIdx,
2361 uint32_t PWMChannel)
2362 {
2363 /* Check the parameters */
2364 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2365
2366 /* Process Locked */
2367 __HAL_LOCK(hhrtim);
2368
2369 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2370
2371 /* Disable the timer output */
2372 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2373
2374 /* Get the timer DMA handler */
2375 /* Disable the DMA */
2376 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
2377 {
2378 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2379
2380 /* Process Unlocked */
2381 __HAL_UNLOCK(hhrtim);
2382
2383 return HAL_ERROR;
2384 }
2385
2386 /* Disable the timer DMA request */
2387 switch (PWMChannel)
2388 {
2389 case HRTIM_OUTPUT_TA1:
2390 case HRTIM_OUTPUT_TB1:
2391 case HRTIM_OUTPUT_TC1:
2392 case HRTIM_OUTPUT_TD1:
2393 case HRTIM_OUTPUT_TE1:
2394 {
2395 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2396 break;
2397 }
2398
2399 case HRTIM_OUTPUT_TA2:
2400 case HRTIM_OUTPUT_TB2:
2401 case HRTIM_OUTPUT_TC2:
2402 case HRTIM_OUTPUT_TD2:
2403 case HRTIM_OUTPUT_TE2:
2404 {
2405 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2406 break;
2407 }
2408
2409 default:
2410 {
2411 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2412
2413 /* Process Unlocked */
2414 __HAL_UNLOCK(hhrtim);
2415
2416 break;
2417 }
2418 }
2419
2420 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2421 {
2422 return HAL_ERROR;
2423 }
2424
2425 /* Disable the timer counter */
2426 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2427
2428 hhrtim->State = HAL_HRTIM_STATE_READY;
2429
2430 /* Process Unlocked */
2431 __HAL_UNLOCK(hhrtim);
2432
2433 return HAL_OK;
2434 }
2435
2436 /**
2437 * @}
2438 */
2439
2440 /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
2441 * @brief Simple input capture functions
2442 @verbatim
2443 ===============================================================================
2444 ##### Simple input capture functions #####
2445 ===============================================================================
2446 [..] This section provides functions allowing to:
2447 (+) Configure simple input capture channel
2448 (+) Start simple input capture
2449 (+) Stop simple input capture
2450 (+) Start simple input capture and enable interrupt
2451 (+) Stop simple input capture and disable interrupt
2452 (+) Start simple input capture and enable DMA transfer
2453 (+) Stop simple input capture and disable DMA transfer
2454 -@- When a HRTIM timer operates in simple input capture mode
2455 the Capture Register (HRTIM_CPT1/2xR) is used to latch the
2456 value of the timer counter counter after a transition detected
2457 on a given external event input.
2458 @endverbatim
2459 * @{
2460 */
2461
2462 /**
2463 * @brief Configure a simple capture
2464 * @param hhrtim pointer to HAL HRTIM handle
2465 * @param TimerIdx Timer index
2466 * This parameter can be one of the following values:
2467 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2468 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2469 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2470 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2471 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2472 * @param CaptureChannel Capture unit
2473 * This parameter can be one of the following values:
2474 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2475 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2476 * @param pSimpleCaptureChannelCfg pointer to the simple capture configuration structure
2477 * @note When the timer operates in simple capture mode the capture is trigerred
2478 * by the designated external event and GPIO input is implicitly used as event source.
2479 * The cature can be triggered by a rising edge, a falling edge or both
2480 * edges on event channel.
2481 * @retval HAL status
2482 */
2483 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,
2484 uint32_t TimerIdx,
2485 uint32_t CaptureChannel,
2486 HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
2487 {
2488 HRTIM_EventCfgTypeDef EventCfg;
2489
2490 /* Check parameters */
2491 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2492 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2493 assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
2494 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
2495 pSimpleCaptureChannelCfg->EventPolarity));
2496 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
2497 assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
2498 pSimpleCaptureChannelCfg->EventFilter));
2499
2500 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
2501 {
2502 return HAL_BUSY;
2503 }
2504
2505 /* Process Locked */
2506 __HAL_LOCK(hhrtim);
2507
2508 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2509
2510 /* Configure external event channel */
2511 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
2512 EventCfg.Filter = (pSimpleCaptureChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
2513 EventCfg.Polarity = (pSimpleCaptureChannelCfg->EventPolarity & HRTIM_EECR1_EE1POL);
2514 EventCfg.Sensitivity = (pSimpleCaptureChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS);
2515 EventCfg.Source = HRTIM_EVENTSRC_1;
2516
2517 HRTIM_EventConfig(hhrtim,
2518 pSimpleCaptureChannelCfg->Event,
2519 &EventCfg);
2520
2521 /* Memorize capture trigger (will be configured when the capture is started */
2522 HRTIM_CaptureUnitConfig(hhrtim,
2523 TimerIdx,
2524 CaptureChannel,
2525 pSimpleCaptureChannelCfg->Event);
2526
2527 hhrtim->State = HAL_HRTIM_STATE_READY;
2528
2529 /* Process Unlocked */
2530 __HAL_UNLOCK(hhrtim);
2531
2532 return HAL_OK;
2533 }
2534
2535 /**
2536 * @brief Enable a simple capture on the designed capture unit
2537 * @param hhrtim pointer to HAL HRTIM handle
2538 * @param TimerIdx Timer index
2539 * This parameter can be one of the following values:
2540 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2541 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2542 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2543 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2544 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2545 * @param CaptureChannel Timer output
2546 * This parameter can be one of the following values:
2547 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2548 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2549 * @retval HAL status
2550 * @note The external event triggering the capture is available for all timing
2551 * units. It can be used directly and is active as soon as the timing
2552 * unit counter is enabled.
2553 */
2554 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
2555 uint32_t TimerIdx,
2556 uint32_t CaptureChannel)
2557 {
2558 /* Check the parameters */
2559 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2560 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2561
2562 /* Process Locked */
2563 __HAL_LOCK(hhrtim);
2564
2565 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2566
2567 /* Set the capture unit trigger */
2568 switch (CaptureChannel)
2569 {
2570 case HRTIM_CAPTUREUNIT_1:
2571 {
2572 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2573 break;
2574 }
2575
2576 case HRTIM_CAPTUREUNIT_2:
2577 {
2578 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2579 break;
2580 }
2581
2582 default:
2583 {
2584 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2585
2586 /* Process Unlocked */
2587 __HAL_UNLOCK(hhrtim);
2588
2589 break;
2590 }
2591 }
2592
2593 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2594 {
2595 return HAL_ERROR;
2596 }
2597
2598 /* Enable the timer counter */
2599 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2600
2601 hhrtim->State = HAL_HRTIM_STATE_READY;
2602
2603 /* Process Unlocked */
2604 __HAL_UNLOCK(hhrtim);
2605
2606 return HAL_OK;
2607 }
2608
2609 /**
2610 * @brief Disable a simple capture on the designed capture unit
2611 * @param hhrtim pointer to HAL HRTIM handle
2612 * @param TimerIdx Timer index
2613 * This parameter can be one of the following values:
2614 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2615 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2616 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2617 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2618 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2619 * @param CaptureChannel Timer output
2620 * This parameter can be one of the following values:
2621 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2622 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2623 * @retval HAL status
2624 */
2625 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
2626 uint32_t TimerIdx,
2627 uint32_t CaptureChannel)
2628 {
2629 uint32_t hrtim_cpt1cr;
2630 uint32_t hrtim_cpt2cr;
2631
2632 /* Check the parameters */
2633 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2634 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2635
2636 /* Process Locked */
2637 __HAL_LOCK(hhrtim);
2638
2639 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2640
2641 /* Set the capture unit trigger */
2642 switch (CaptureChannel)
2643 {
2644 case HRTIM_CAPTUREUNIT_1:
2645 {
2646 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2647 break;
2648 }
2649
2650 case HRTIM_CAPTUREUNIT_2:
2651 {
2652 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2653 break;
2654 }
2655
2656 default:
2657 {
2658 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2659
2660 /* Process Unlocked */
2661 __HAL_UNLOCK(hhrtim);
2662
2663 break;
2664 }
2665 }
2666
2667 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2668 {
2669 return HAL_ERROR;
2670 }
2671
2672 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
2673 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
2674
2675 /* Disable the timer counter */
2676 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
2677 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
2678 {
2679 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2680 }
2681
2682 hhrtim->State = HAL_HRTIM_STATE_READY;
2683
2684 /* Process Unlocked */
2685 __HAL_UNLOCK(hhrtim);
2686
2687 return HAL_OK;
2688 }
2689
2690 /**
2691 * @brief Enable a simple capture on the designed capture unit
2692 * (Capture interrupt is enabled).
2693 * @param hhrtim pointer to HAL HRTIM handle
2694 * @param TimerIdx Timer index
2695 * This parameter can be one of the following values:
2696 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2697 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2698 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2699 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2700 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2701 * @param CaptureChannel Timer output
2702 * This parameter can be one of the following values:
2703 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2704 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2705 * @retval HAL status
2706 */
2707 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
2708 uint32_t TimerIdx,
2709 uint32_t CaptureChannel)
2710 {
2711 /* Check the parameters */
2712 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2713 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2714
2715 /* Process Locked */
2716 __HAL_LOCK(hhrtim);
2717
2718 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2719
2720 /* Set the capture unit trigger */
2721 switch (CaptureChannel)
2722 {
2723 case HRTIM_CAPTUREUNIT_1:
2724 {
2725 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2726
2727 /* Enable the capture unit 1 interrupt */
2728 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2729 break;
2730 }
2731
2732 case HRTIM_CAPTUREUNIT_2:
2733 {
2734 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2735
2736 /* Enable the capture unit 2 interrupt */
2737 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2738 break;
2739 }
2740
2741 default:
2742 {
2743 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2744
2745 /* Process Unlocked */
2746 __HAL_UNLOCK(hhrtim);
2747
2748 break;
2749 }
2750 }
2751
2752 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2753 {
2754 return HAL_ERROR;
2755 }
2756
2757 /* Enable the timer counter */
2758 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2759
2760 hhrtim->State = HAL_HRTIM_STATE_READY;
2761
2762 /* Process Unlocked */
2763 __HAL_UNLOCK(hhrtim);
2764
2765 return HAL_OK;
2766 }
2767
2768 /**
2769 * @brief Disable a simple capture on the designed capture unit
2770 * (Capture interrupt is disabled).
2771 * @param hhrtim pointer to HAL HRTIM handle
2772 * @param TimerIdx Timer index
2773 * This parameter can be one of the following values:
2774 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2775 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2776 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2777 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2778 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2779 * @param CaptureChannel Timer output
2780 * This parameter can be one of the following values:
2781 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2782 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2783 * @retval HAL status
2784 */
2785 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
2786 uint32_t TimerIdx,
2787 uint32_t CaptureChannel)
2788 {
2789
2790 uint32_t hrtim_cpt1cr;
2791 uint32_t hrtim_cpt2cr;
2792
2793 /* Check the parameters */
2794 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2795 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2796
2797 /* Process Locked */
2798 __HAL_LOCK(hhrtim);
2799
2800 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2801
2802 /* Set the capture unit trigger */
2803 switch (CaptureChannel)
2804 {
2805 case HRTIM_CAPTUREUNIT_1:
2806 {
2807 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2808
2809 /* Disable the capture unit 1 interrupt */
2810 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2811 break;
2812 }
2813
2814 case HRTIM_CAPTUREUNIT_2:
2815 {
2816 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2817
2818 /* Disable the capture unit 2 interrupt */
2819 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2820 break;
2821 }
2822
2823 default:
2824 {
2825 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2826
2827 /* Process Unlocked */
2828 __HAL_UNLOCK(hhrtim);
2829
2830 break;
2831 }
2832 }
2833
2834 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2835 {
2836 return HAL_ERROR;
2837 }
2838
2839 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
2840 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
2841
2842 /* Disable the timer counter */
2843 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
2844 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
2845 {
2846 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2847 }
2848
2849 hhrtim->State = HAL_HRTIM_STATE_READY;
2850
2851 /* Process Unlocked */
2852 __HAL_UNLOCK(hhrtim);
2853
2854 return HAL_OK;
2855 }
2856
2857 /**
2858 * @brief Enable a simple capture on the designed capture unit
2859 * (Capture DMA request is enabled).
2860 * @param hhrtim pointer to HAL HRTIM handle
2861 * @param TimerIdx Timer index
2862 * This parameter can be one of the following values:
2863 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2864 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2865 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2866 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2867 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2868 * @param CaptureChannel Timer output
2869 * This parameter can be one of the following values:
2870 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2871 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2872 * @param SrcAddr DMA transfer source address
2873 * @param DestAddr DMA transfer destination address
2874 * @param Length The length of data items (data size) to be transferred
2875 * from source to destination
2876 * @retval HAL status
2877 */
2878 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
2879 uint32_t TimerIdx,
2880 uint32_t CaptureChannel,
2881 uint32_t SrcAddr,
2882 uint32_t DestAddr,
2883 uint32_t Length)
2884 {
2885 DMA_HandleTypeDef * hdma;
2886
2887 /* Check the parameters */
2888 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2889 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2890
2891 /* Process Locked */
2892 __HAL_LOCK(hhrtim);
2893
2894 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2895
2896 /* Get the timer DMA handler */
2897 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2898
2899 if (hdma == NULL)
2900 {
2901 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2902
2903 /* Process Unlocked */
2904 __HAL_UNLOCK(hhrtim);
2905
2906 return HAL_ERROR;
2907 }
2908
2909 /* Set the DMA error callback */
2910 hdma->XferErrorCallback = HRTIM_DMAError ;
2911
2912 /* Set the DMA transfer completed callback */
2913 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
2914
2915 /* Enable the DMA channel */
2916 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
2917 {
2918 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2919
2920 /* Process Unlocked */
2921 __HAL_UNLOCK(hhrtim);
2922
2923 return HAL_ERROR;
2924 }
2925
2926 switch (CaptureChannel)
2927 {
2928 case HRTIM_CAPTUREUNIT_1:
2929 {
2930 /* Set the capture unit trigger */
2931 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2932
2933 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
2934 break;
2935 }
2936
2937 case HRTIM_CAPTUREUNIT_2:
2938 {
2939 /* Set the capture unit trigger */
2940 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2941
2942 /* Enable the timer DMA request */
2943 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
2944 break;
2945 }
2946
2947 default:
2948 {
2949 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2950
2951 /* Process Unlocked */
2952 __HAL_UNLOCK(hhrtim);
2953
2954 break;
2955 }
2956 }
2957
2958 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2959 {
2960 return HAL_ERROR;
2961 }
2962
2963 /* Enable the timer counter */
2964 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2965
2966 hhrtim->State = HAL_HRTIM_STATE_READY;
2967
2968 /* Process Unlocked */
2969 __HAL_UNLOCK(hhrtim);
2970
2971 return HAL_OK;
2972 }
2973
2974 /**
2975 * @brief Disable a simple capture on the designed capture unit
2976 * (Capture DMA request is disabled).
2977 * @param hhrtim pointer to HAL HRTIM handle
2978 * @param TimerIdx Timer index
2979 * This parameter can be one of the following values:
2980 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2981 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2982 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2983 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2984 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2985 * @param CaptureChannel Timer output
2986 * This parameter can be one of the following values:
2987 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2988 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2989 * @retval HAL status
2990 */
2991 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
2992 uint32_t TimerIdx,
2993 uint32_t CaptureChannel)
2994 {
2995
2996 uint32_t hrtim_cpt1cr;
2997 uint32_t hrtim_cpt2cr;
2998
2999 /* Check the parameters */
3000 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3001 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
3002
3003 /* Process Locked */
3004 __HAL_LOCK(hhrtim);
3005
3006 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3007
3008 /* Get the timer DMA handler */
3009 /* Disable the DMA */
3010 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
3011 {
3012 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3013
3014 /* Process Unlocked */
3015 __HAL_UNLOCK(hhrtim);
3016
3017 return HAL_ERROR;
3018 }
3019
3020 switch (CaptureChannel)
3021 {
3022 case HRTIM_CAPTUREUNIT_1:
3023 {
3024 /* Reset the capture unit trigger */
3025 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
3026
3027 /* Disable the capture unit 1 DMA request */
3028 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
3029 break;
3030 }
3031
3032 case HRTIM_CAPTUREUNIT_2:
3033 {
3034 /* Reset the capture unit trigger */
3035 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
3036
3037 /* Disable the capture unit 2 DMA request */
3038 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
3039 break;
3040 }
3041
3042 default:
3043 {
3044 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3045
3046 /* Process Unlocked */
3047 __HAL_UNLOCK(hhrtim);
3048
3049 break;
3050 }
3051 }
3052
3053 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3054 {
3055 return HAL_ERROR;
3056 }
3057
3058 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
3059 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
3060
3061 /* Disable the timer counter */
3062 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
3063 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
3064 {
3065 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3066 }
3067
3068 hhrtim->State = HAL_HRTIM_STATE_READY;
3069
3070 /* Process Unlocked */
3071 __HAL_UNLOCK(hhrtim);
3072
3073 return HAL_OK;
3074 }
3075
3076 /**
3077 * @}
3078 */
3079
3080 /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
3081 * @brief Simple one pulse functions
3082 @verbatim
3083 ===============================================================================
3084 ##### Simple one pulse functions #####
3085 ===============================================================================
3086 [..] This section provides functions allowing to:
3087 (+) Configure one pulse channel
3088 (+) Start one pulse generation
3089 (+) Stop one pulse generation
3090 (+) Start one pulse generation and enable interrupt
3091 (+) Stop one pulse generation and disable interrupt
3092 -@- When a HRTIM timer operates in simple one pulse mode
3093 the timer counter is started in response to transition detected
3094 on a given external event input to generate a pulse with a
3095 programmable length after a programmable delay.
3096 @endverbatim
3097 * @{
3098 */
3099
3100 /**
3101 * @brief Configure an output simple one pulse mode
3102 * @param hhrtim pointer to HAL HRTIM handle
3103 * @param TimerIdx Timer index
3104 * This parameter can be one of the following values:
3105 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3106 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3107 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3108 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3109 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3110 * @param OnePulseChannel Timer output
3111 * This parameter can be one of the following values:
3112 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3113 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3114 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3115 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3116 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3117 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3118 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3119 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3120 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3121 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3122 * @param pSimpleOnePulseChannelCfg pointer to the simple one pulse output configuration structure
3123 * @note When the timer operates in simple one pulse mode:
3124 * the timer counter is implicitly started by the reset event,
3125 * the reset of the timer counter is triggered by the designated external event
3126 * GPIO input is implicitly used as event source,
3127 * Output 1 is implicitly controlled by the compare unit 1,
3128 * Output 2 is implicitly controlled by the compare unit 2.
3129 * Output Set/Reset crossbar is set as follows:
3130 * Output 1: SETx1R = CMP1, RSTx1R = PER
3131 * Output 2: SETx2R = CMP2, RST2R = PER
3132 * @retval HAL status
3133 * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
3134 * outputs, the reset event related configuration data provided in the
3135 * second call will override the reset event related configuration data
3136 * provided in the first call.
3137 */
3138 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,
3139 uint32_t TimerIdx,
3140 uint32_t OnePulseChannel,
3141 HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
3142 {
3143 HRTIM_OutputCfgTypeDef OutputCfg;
3144 HRTIM_EventCfgTypeDef EventCfg;
3145
3146 /* Check parameters */
3147 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3148 assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOnePulseChannelCfg->Pulse));
3149 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
3150 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
3151 assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
3152 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
3153 pSimpleOnePulseChannelCfg->EventPolarity));
3154 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
3155 assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
3156 pSimpleOnePulseChannelCfg->EventFilter));
3157
3158 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3159 {
3160 return HAL_BUSY;
3161 }
3162
3163 /* Process Locked */
3164 __HAL_LOCK(hhrtim);
3165
3166 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3167
3168 /* Configure timer compare unit */
3169 switch (OnePulseChannel)
3170 {
3171 case HRTIM_OUTPUT_TA1:
3172 case HRTIM_OUTPUT_TB1:
3173 case HRTIM_OUTPUT_TC1:
3174 case HRTIM_OUTPUT_TD1:
3175 case HRTIM_OUTPUT_TE1:
3176 {
3177 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOnePulseChannelCfg->Pulse;
3178 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
3179 break;
3180 }
3181
3182 case HRTIM_OUTPUT_TA2:
3183 case HRTIM_OUTPUT_TB2:
3184 case HRTIM_OUTPUT_TC2:
3185 case HRTIM_OUTPUT_TD2:
3186 case HRTIM_OUTPUT_TE2:
3187 {
3188 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOnePulseChannelCfg->Pulse;
3189 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
3190 break;
3191 }
3192
3193 default:
3194 {
3195 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
3196 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
3197
3198 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3199
3200 /* Process Unlocked */
3201 __HAL_UNLOCK(hhrtim);
3202
3203 break;
3204 }
3205 }
3206
3207 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3208 {
3209 return HAL_ERROR;
3210 }
3211
3212 /* Configure timer output */
3213 OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1);
3214 OutputCfg.IdleLevel = (pSimpleOnePulseChannelCfg->OutputIdleLevel & HRTIM_OUTR_IDLES1);
3215 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
3216 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
3217 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
3218 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
3219 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
3220
3221 HRTIM_OutputConfig(hhrtim,
3222 TimerIdx,
3223 OnePulseChannel,
3224 &OutputCfg);
3225
3226 /* Configure external event channel */
3227 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
3228 EventCfg.Filter = (pSimpleOnePulseChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
3229 EventCfg.Polarity = (pSimpleOnePulseChannelCfg->EventPolarity & HRTIM_OUTR_POL1);
3230 EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity &HRTIM_EECR1_EE1SNS);
3231 EventCfg.Source = HRTIM_EVENTSRC_1;
3232
3233 HRTIM_EventConfig(hhrtim,
3234 pSimpleOnePulseChannelCfg->Event,
3235 &EventCfg);
3236
3237 /* Configure the timer reset register */
3238 HRTIM_TIM_ResetConfig(hhrtim,
3239 TimerIdx,
3240 pSimpleOnePulseChannelCfg->Event);
3241
3242 hhrtim->State = HAL_HRTIM_STATE_READY;
3243
3244 /* Process Unlocked */
3245 __HAL_UNLOCK(hhrtim);
3246
3247 return HAL_OK;
3248 }
3249
3250 /**
3251 * @brief Enable the simple one pulse signal generation on the designed output
3252 * @param hhrtim pointer to HAL HRTIM handle
3253 * @param TimerIdx Timer index
3254 * This parameter can be one of the following values:
3255 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3256 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3257 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3258 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3259 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3260 * @param OnePulseChannel Timer output
3261 * This parameter can be one of the following values:
3262 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3263 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3264 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3265 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3266 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3267 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3268 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3269 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3270 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3271 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3272 * @retval HAL status
3273 */
3274 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,
3275 uint32_t TimerIdx,
3276 uint32_t OnePulseChannel)
3277 {
3278 /* Check the parameters */
3279 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3280
3281 /* Process Locked */
3282 __HAL_LOCK(hhrtim);
3283
3284 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3285
3286 /* Enable the timer output */
3287 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3288
3289 /* Enable the timer counter */
3290 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3291
3292 hhrtim->State = HAL_HRTIM_STATE_READY;
3293
3294 /* Process Unlocked */
3295 __HAL_UNLOCK(hhrtim);
3296
3297 return HAL_OK;
3298 }
3299
3300 /**
3301 * @brief Disable the simple one pulse signal generation on the designed output
3302 * @param hhrtim pointer to HAL HRTIM handle
3303 * @param TimerIdx Timer index
3304 * This parameter can be one of the following values:
3305 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3306 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3307 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3308 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3309 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3310 * @param OnePulseChannel Timer output
3311 * This parameter can be one of the following values:
3312 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3313 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3314 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3315 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3316 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3317 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3318 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3319 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3320 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3321 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3322 * @retval HAL status
3323 */
3324 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,
3325 uint32_t TimerIdx,
3326 uint32_t OnePulseChannel)
3327 {
3328 /* Check the parameters */
3329 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3330
3331 /* Process Locked */
3332 __HAL_LOCK(hhrtim);
3333
3334 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3335
3336 /* Disable the timer output */
3337 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3338
3339 /* Disable the timer counter */
3340 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3341
3342 hhrtim->State = HAL_HRTIM_STATE_READY;
3343
3344 /* Process Unlocked */
3345 __HAL_UNLOCK(hhrtim);
3346
3347 return HAL_OK;
3348 }
3349
3350 /**
3351 * @brief Enable the simple one pulse signal generation on the designed output
3352 * (The compare interrupt is enabled (pulse start)).
3353 * @param hhrtim pointer to HAL HRTIM handle
3354 * @param TimerIdx Timer index
3355 * This parameter can be one of the following values:
3356 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3357 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3358 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3359 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3360 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3361 * @param OnePulseChannel Timer output
3362 * This parameter can be one of the following values:
3363 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3364 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3365 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3366 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3367 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3368 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3369 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3370 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3371 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3372 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3373 * @retval HAL status
3374 */
3375 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
3376 uint32_t TimerIdx,
3377 uint32_t OnePulseChannel)
3378 {
3379 /* Check the parameters */
3380 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3381
3382 /* Process Locked */
3383 __HAL_LOCK(hhrtim);
3384
3385 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3386
3387 /* Enable the timer output */
3388 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3389
3390 /* Enable the timer interrupt (depends on the OnePulse output) */
3391 switch (OnePulseChannel)
3392 {
3393 case HRTIM_OUTPUT_TA1:
3394 case HRTIM_OUTPUT_TB1:
3395 case HRTIM_OUTPUT_TC1:
3396 case HRTIM_OUTPUT_TD1:
3397 case HRTIM_OUTPUT_TE1:
3398 {
3399 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3400 break;
3401 }
3402
3403 case HRTIM_OUTPUT_TA2:
3404 case HRTIM_OUTPUT_TB2:
3405 case HRTIM_OUTPUT_TC2:
3406 case HRTIM_OUTPUT_TD2:
3407 case HRTIM_OUTPUT_TE2:
3408 {
3409 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3410 break;
3411 }
3412
3413 default:
3414 {
3415 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3416
3417 /* Process Unlocked */
3418 __HAL_UNLOCK(hhrtim);
3419
3420 break;
3421 }
3422 }
3423
3424 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3425 {
3426 return HAL_ERROR;
3427 }
3428
3429 /* Enable the timer counter */
3430 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3431
3432 hhrtim->State = HAL_HRTIM_STATE_READY;
3433
3434 /* Process Unlocked */
3435 __HAL_UNLOCK(hhrtim);
3436
3437 return HAL_OK;
3438 }
3439
3440 /**
3441 * @brief Disable the simple one pulse signal generation on the designed output
3442 * (The compare interrupt is disabled).
3443 * @param hhrtim pointer to HAL HRTIM handle
3444 * @param TimerIdx Timer index
3445 * This parameter can be one of the following values:
3446 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3447 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3448 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3449 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3450 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3451 * @param OnePulseChannel Timer output
3452 * This parameter can be one of the following values:
3453 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3454 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3455 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3456 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3457 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3458 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3459 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3460 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3461 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3462 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3463 * @retval HAL status
3464 */
3465 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
3466 uint32_t TimerIdx,
3467 uint32_t OnePulseChannel)
3468 {
3469 /* Check the parameters */
3470 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3471
3472 /* Process Locked */
3473 __HAL_LOCK(hhrtim);
3474
3475 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3476
3477 /* Disable the timer output */
3478 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3479
3480 /* Disable the timer interrupt (depends on the OnePulse output) */
3481 switch (OnePulseChannel)
3482 {
3483 case HRTIM_OUTPUT_TA1:
3484 case HRTIM_OUTPUT_TB1:
3485 case HRTIM_OUTPUT_TC1:
3486 case HRTIM_OUTPUT_TD1:
3487 case HRTIM_OUTPUT_TE1:
3488 {
3489 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3490 break;
3491 }
3492
3493 case HRTIM_OUTPUT_TA2:
3494 case HRTIM_OUTPUT_TB2:
3495 case HRTIM_OUTPUT_TC2:
3496 case HRTIM_OUTPUT_TD2:
3497 case HRTIM_OUTPUT_TE2:
3498 {
3499 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3500 break;
3501 }
3502
3503 default:
3504 {
3505 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3506
3507 /* Process Unlocked */
3508 __HAL_UNLOCK(hhrtim);
3509
3510 break;
3511 }
3512 }
3513
3514 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3515 {
3516 return HAL_ERROR;
3517 }
3518
3519 /* Disable the timer counter */
3520 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3521
3522 hhrtim->State = HAL_HRTIM_STATE_READY;
3523
3524 /* Process Unlocked */
3525 __HAL_UNLOCK(hhrtim);
3526
3527 return HAL_OK;
3528 }
3529
3530 /**
3531 * @}
3532 */
3533
3534 /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
3535 * @brief HRTIM configuration functions
3536 @verbatim
3537 ===============================================================================
3538 ##### HRTIM configuration functions #####
3539 ===============================================================================
3540 [..] This section provides functions allowing to configure the HRTIM
3541 resources shared by all the HRTIM timers operating in waveform mode:
3542 (+) Configure the burst mode controller
3543 (+) Configure an external event conditioning
3544 (+) Configure the external events sampling clock
3545 (+) Configure a fault conditioning
3546 (+) Enable or disable fault inputs
3547 (+) Configure the faults sampling clock
3548 (+) Configure an ADC trigger
3549
3550 @endverbatim
3551 * @{
3552 */
3553
3554 /**
3555 * @brief Configure the burst mode feature of the HRTIM
3556 * @param hhrtim pointer to HAL HRTIM handle
3557 * @param pBurstModeCfg pointer to the burst mode configuration structure
3558 * @retval HAL status
3559 * @note This function must be called before starting the burst mode
3560 * controller
3561 */
3562 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
3563 HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
3564 {
3565 uint32_t hrtim_bmcr;
3566
3567 /* Check parameters */
3568 assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
3569 assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
3570 assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
3571 assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
3572 assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
3573
3574 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3575 {
3576 return HAL_BUSY;
3577 }
3578
3579 /* Process Locked */
3580 __HAL_LOCK(hhrtim);
3581
3582 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3583
3584 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
3585
3586 /* Set the burst mode operating mode */
3587 hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
3588 hrtim_bmcr |= (pBurstModeCfg->Mode & HRTIM_BMCR_BMOM);
3589
3590 /* Set the burst mode clock source */
3591 hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
3592 hrtim_bmcr |= (pBurstModeCfg->ClockSource & HRTIM_BMCR_BMCLK);
3593
3594 /* Set the burst mode prescaler */
3595 hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
3596 hrtim_bmcr |= pBurstModeCfg->Prescaler;
3597
3598 /* Enable/disable burst mode registers preload */
3599 hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
3600 hrtim_bmcr |= (pBurstModeCfg->PreloadEnable & HRTIM_BMCR_BMPREN);
3601
3602 /* Set the burst mode trigger */
3603 hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
3604
3605 /* Set the burst mode compare value */
3606 hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
3607
3608 /* Set the burst mode period */
3609 hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
3610
3611 /* Update the HRTIM registers */
3612 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
3613
3614 hhrtim->State = HAL_HRTIM_STATE_READY;
3615
3616 /* Process Unlocked */
3617 __HAL_UNLOCK(hhrtim);
3618
3619 return HAL_OK;
3620 }
3621
3622 /**
3623 * @brief Configure the conditioning of an external event
3624 * @param hhrtim pointer to HAL HRTIM handle
3625 * @param Event external event to configure
3626 * This parameter can be one of the following values:
3627 * @arg HRTIM_EVENT_NONE: no external Event
3628 * @arg HRTIM_EVENT_1: External event 1
3629 * @arg HRTIM_EVENT_2: External event 2
3630 * @arg HRTIM_EVENT_3: External event 3
3631 * @arg HRTIM_EVENT_4: External event 4
3632 * @arg HRTIM_EVENT_5: External event 5
3633 * @arg HRTIM_EVENT_6: External event 6
3634 * @arg HRTIM_EVENT_7: External event 7
3635 * @arg HRTIM_EVENT_8: External event 8
3636 * @arg HRTIM_EVENT_9: External event 9
3637 * @arg HRTIM_EVENT_10: External event 10
3638 * @param pEventCfg pointer to the event conditioning configuration structure
3639 * @note This function must be called before starting the timer
3640 * @retval HAL status
3641 */
3642 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
3643 uint32_t Event,
3644 HRTIM_EventCfgTypeDef* pEventCfg)
3645 {
3646 /* Check parameters */
3647 assert_param(IS_HRTIM_EVENT(Event));
3648 assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
3649 assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
3650 assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
3651 assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
3652 assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
3653
3654 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3655 {
3656 return HAL_BUSY;
3657 }
3658
3659 /* Process Locked */
3660 __HAL_LOCK(hhrtim);
3661
3662 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3663
3664 /* Configure the event channel */
3665 HRTIM_EventConfig(hhrtim, Event, pEventCfg);
3666
3667 hhrtim->State = HAL_HRTIM_STATE_READY;
3668
3669 /* Process Unlocked */
3670 __HAL_UNLOCK(hhrtim);
3671
3672 return HAL_OK;
3673 }
3674
3675 /**
3676 * @brief Configure the external event conditioning block prescaler
3677 * @param hhrtim pointer to HAL HRTIM handle
3678 * @param Prescaler Prescaler value
3679 * This parameter can be one of the following values:
3680 * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
3681 * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
3682 * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
3683 * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
3684 * @note This function must be called before starting the timer
3685 * @retval HAL status
3686 */
3687 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
3688 uint32_t Prescaler)
3689 {
3690 /* Check parameters */
3691 assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
3692
3693 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3694 {
3695 return HAL_BUSY;
3696 }
3697
3698 /* Process Locked */
3699 __HAL_LOCK(hhrtim);
3700
3701 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3702
3703 /* Set the external event prescaler */
3704 MODIFY_REG(hhrtim->Instance->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, (Prescaler & HRTIM_EECR3_EEVSD));
3705
3706 hhrtim->State = HAL_HRTIM_STATE_READY;
3707
3708 /* Process Unlocked */
3709 __HAL_UNLOCK(hhrtim);
3710
3711 return HAL_OK;
3712 }
3713
3714 /**
3715 * @brief Configure the conditioning of fault input
3716 * @param hhrtim pointer to HAL HRTIM handle
3717 * @param Fault fault input to configure
3718 * This parameter can be one of the following values:
3719 * @arg HRTIM_FAULT_1: Fault input 1
3720 * @arg HRTIM_FAULT_2: Fault input 2
3721 * @arg HRTIM_FAULT_3: Fault input 3
3722 * @arg HRTIM_FAULT_4: Fault input 4
3723 * @arg HRTIM_FAULT_5: Fault input 5
3724 * @param pFaultCfg pointer to the fault conditioning configuration structure
3725 * @note This function must be called before starting the timer and before
3726 * enabling faults inputs
3727 * @retval HAL status
3728 */
3729 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
3730 uint32_t Fault,
3731 HRTIM_FaultCfgTypeDef* pFaultCfg)
3732 {
3733 uint32_t hrtim_fltinr1;
3734 uint32_t hrtim_fltinr2;
3735
3736 /* Check parameters */
3737 assert_param(IS_HRTIM_FAULT(Fault));
3738 assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
3739 assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
3740 assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
3741 assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
3742
3743 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3744 {
3745 return HAL_BUSY;
3746 }
3747
3748 /* Process Locked */
3749 __HAL_LOCK(hhrtim);
3750
3751 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3752
3753 /* Configure fault channel */
3754 hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
3755 hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
3756
3757 switch (Fault)
3758 {
3759 case HRTIM_FAULT_1:
3760 {
3761 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
3762 hrtim_fltinr1 |= (pFaultCfg->Polarity & HRTIM_FLTINR1_FLT1P);
3763 hrtim_fltinr1 |= (pFaultCfg->Source & HRTIM_FLTINR1_FLT1SRC);
3764 hrtim_fltinr1 |= (pFaultCfg->Filter & HRTIM_FLTINR1_FLT1F);
3765 hrtim_fltinr1 |= (pFaultCfg->Lock & HRTIM_FLTINR1_FLT1LCK);
3766 break;
3767 }
3768
3769 case HRTIM_FAULT_2:
3770 {
3771 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
3772 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR1_FLT2P);
3773 hrtim_fltinr1 |= ((pFaultCfg->Source << 8U) & HRTIM_FLTINR1_FLT2SRC);
3774 hrtim_fltinr1 |= ((pFaultCfg->Filter << 8U) & HRTIM_FLTINR1_FLT2F);
3775 hrtim_fltinr1 |= ((pFaultCfg->Lock << 8U) & HRTIM_FLTINR1_FLT2LCK);
3776 break;
3777 }
3778
3779 case HRTIM_FAULT_3:
3780 {
3781 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
3782 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 16U) & HRTIM_FLTINR1_FLT3P);
3783 hrtim_fltinr1 |= ((pFaultCfg->Source << 16U) & HRTIM_FLTINR1_FLT3SRC);
3784 hrtim_fltinr1 |= ((pFaultCfg->Filter << 16U) & HRTIM_FLTINR1_FLT3F);
3785 hrtim_fltinr1 |= ((pFaultCfg->Lock << 16U) & HRTIM_FLTINR1_FLT3LCK);
3786 break;
3787 }
3788
3789 case HRTIM_FAULT_4:
3790 {
3791 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
3792 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 24U) & HRTIM_FLTINR1_FLT4P);
3793 hrtim_fltinr1 |= ((pFaultCfg->Source << 24U) & HRTIM_FLTINR1_FLT4SRC);
3794 hrtim_fltinr1 |= ((pFaultCfg->Filter << 24U) & HRTIM_FLTINR1_FLT4F);
3795 hrtim_fltinr1 |= ((pFaultCfg->Lock << 24U) & HRTIM_FLTINR1_FLT4LCK);
3796 break;
3797 }
3798
3799 case HRTIM_FAULT_5:
3800 {
3801 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
3802 hrtim_fltinr2 |= (pFaultCfg->Polarity & HRTIM_FLTINR2_FLT5P);
3803 hrtim_fltinr2 |= (pFaultCfg->Source & HRTIM_FLTINR2_FLT5SRC);
3804 hrtim_fltinr2 |= (pFaultCfg->Filter & HRTIM_FLTINR2_FLT5F);
3805 hrtim_fltinr2 |= (pFaultCfg->Lock & HRTIM_FLTINR2_FLT5LCK);
3806 break;
3807 }
3808
3809 default:
3810 {
3811 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3812
3813 /* Process Unlocked */
3814 __HAL_UNLOCK(hhrtim);
3815
3816 break;
3817 }
3818 }
3819
3820 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3821 {
3822 return HAL_ERROR;
3823 }
3824
3825 /* Update the HRTIM registers except LOCK bit */
3826 hhrtim->Instance->sCommonRegs.FLTINR1 = (hrtim_fltinr1 & (~(HRTIM_FLTINR1_FLTxLCK)));
3827 hhrtim->Instance->sCommonRegs.FLTINR2 = (hrtim_fltinr2 & (~(HRTIM_FLTINR2_FLTxLCK)));
3828
3829 /* Update the HRTIM registers LOCK bit */
3830 SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1,(hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK));
3831 SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2,(hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK));
3832
3833 hhrtim->State = HAL_HRTIM_STATE_READY;
3834
3835 /* Process Unlocked */
3836 __HAL_UNLOCK(hhrtim);
3837
3838 return HAL_OK;
3839 }
3840
3841 /**
3842 * @brief Configure the fault conditioning block prescaler
3843 * @param hhrtim pointer to HAL HRTIM handle
3844 * @param Prescaler Prescaler value
3845 * This parameter can be one of the following values:
3846 * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
3847 * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
3848 * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
3849 * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
3850 * @retval HAL status
3851 * @note This function must be called before starting the timer and before
3852 * enabling faults inputs
3853 */
3854 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
3855 uint32_t Prescaler)
3856 {
3857 /* Check parameters */
3858 assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
3859
3860 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3861 {
3862 return HAL_BUSY;
3863 }
3864
3865 /* Process Locked */
3866 __HAL_LOCK(hhrtim);
3867
3868 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3869
3870 /* Set the external event prescaler */
3871 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, (Prescaler & HRTIM_FLTINR2_FLTSD));
3872
3873 hhrtim->State = HAL_HRTIM_STATE_READY;
3874
3875 /* Process Unlocked */
3876 __HAL_UNLOCK(hhrtim);
3877
3878 return HAL_OK;
3879 }
3880
3881 /**
3882 * @brief Enable or disables the HRTIMx Fault mode.
3883 * @param hhrtim pointer to HAL HRTIM handle
3884 * @param Faults fault input(s) to enable or disable
3885 * This parameter can be any combination of the following values:
3886 * @arg HRTIM_FAULT_1: Fault input 1
3887 * @arg HRTIM_FAULT_2: Fault input 2
3888 * @arg HRTIM_FAULT_3: Fault input 3
3889 * @arg HRTIM_FAULT_4: Fault input 4
3890 * @arg HRTIM_FAULT_5: Fault input 5
3891 * @param Enable Fault(s) enabling
3892 * This parameter can be one of the following values:
3893 * @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
3894 * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
3895 * @retval None
3896 */
3897 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
3898 uint32_t Faults,
3899 uint32_t Enable)
3900 {
3901 /* Check parameters */
3902 assert_param(IS_HRTIM_FAULT(Faults));
3903 assert_param(IS_HRTIM_FAULTMODECTL(Enable));
3904
3905 if ((Faults & HRTIM_FAULT_1) != (uint32_t)RESET)
3906 {
3907 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT1E, (Enable & HRTIM_FLTINR1_FLT1E));
3908 }
3909 if ((Faults & HRTIM_FAULT_2) != (uint32_t)RESET)
3910 {
3911 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT2E, ((Enable << 8U) & HRTIM_FLTINR1_FLT2E));
3912 }
3913 if ((Faults & HRTIM_FAULT_3) != (uint32_t)RESET)
3914 {
3915 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT3E, ((Enable << 16U) & HRTIM_FLTINR1_FLT3E));
3916 }
3917 if ((Faults & HRTIM_FAULT_4) != (uint32_t)RESET)
3918 {
3919 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT4E, ((Enable << 24U) & HRTIM_FLTINR1_FLT4E));
3920 }
3921 if ((Faults & HRTIM_FAULT_5) != (uint32_t)RESET)
3922 {
3923 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLT5E, ((Enable) & HRTIM_FLTINR2_FLT5E));
3924 }
3925 }
3926
3927 /**
3928 * @brief Configure both the ADC trigger register update source and the ADC
3929 * trigger source.
3930 * @param hhrtim pointer to HAL HRTIM handle
3931 * @param ADCTrigger ADC trigger to configure
3932 * This parameter can be one of the following values:
3933 * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
3934 * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
3935 * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
3936 * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
3937 * @param pADCTriggerCfg pointer to the ADC trigger configuration structure
3938 * @retval HAL status
3939 * @note This function must be called before starting the timer
3940 */
3941 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
3942 uint32_t ADCTrigger,
3943 HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
3944 {
3945 uint32_t hrtim_cr1;
3946
3947 /* Check parameters */
3948 assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
3949 assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
3950
3951 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3952 {
3953 return HAL_BUSY;
3954 }
3955
3956 /* Process Locked */
3957 __HAL_LOCK(hhrtim);
3958
3959 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3960
3961 /* Set the ADC trigger update source */
3962 hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
3963
3964 switch (ADCTrigger)
3965 {
3966 case HRTIM_ADCTRIGGER_1:
3967 {
3968 hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
3969 hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
3970
3971 /* Set the ADC trigger 1 source */
3972 hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
3973 break;
3974 }
3975
3976 case HRTIM_ADCTRIGGER_2:
3977 {
3978 hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
3979 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC);
3980
3981 /* Set the ADC trigger 2 source */
3982 hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
3983 break;
3984 }
3985
3986 case HRTIM_ADCTRIGGER_3:
3987 {
3988 hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
3989 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC);
3990
3991 /* Set the ADC trigger 3 source */
3992 hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
3993 break;
3994 }
3995
3996 case HRTIM_ADCTRIGGER_4:
3997 {
3998 hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
3999 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC);
4000
4001 /* Set the ADC trigger 4 source */
4002 hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
4003 break;
4004 }
4005
4006 default:
4007 {
4008 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4009
4010 /* Process Unlocked */
4011 __HAL_UNLOCK(hhrtim);
4012
4013 break;
4014 }
4015 }
4016
4017 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4018 {
4019 return HAL_ERROR;
4020 }
4021
4022 /* Update the HRTIM registers */
4023 hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
4024
4025 hhrtim->State = HAL_HRTIM_STATE_READY;
4026
4027 /* Process Unlocked */
4028 __HAL_UNLOCK(hhrtim);
4029
4030 return HAL_OK;
4031 }
4032
4033
4034 /**
4035 * @}
4036 */
4037
4038 /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
4039 * @brief HRTIM timer configuration and control functions
4040 @verbatim
4041 ===============================================================================
4042 ##### HRTIM timer configuration and control functions #####
4043 ===============================================================================
4044 [..] This section provides functions used to configure and control a
4045 HRTIM timer operating in waveform mode:
4046 (+) Configure HRTIM timer general behavior
4047 (+) Configure HRTIM timer event filtering
4048 (+) Configure HRTIM timer deadtime insertion
4049 (+) Configure HRTIM timer chopper mode
4050 (+) Configure HRTIM timer burst DMA
4051 (+) Configure HRTIM timer compare unit
4052 (+) Configure HRTIM timer capture unit
4053 (+) Configure HRTIM timer output
4054 (+) Set HRTIM timer output level
4055 (+) Enable HRTIM timer output
4056 (+) Disable HRTIM timer output
4057 (+) Start HRTIM timer
4058 (+) Stop HRTIM timer
4059 (+) Start HRTIM timer and enable interrupt
4060 (+) Stop HRTIM timer and disable interrupt
4061 (+) Start HRTIM timer and enable DMA transfer
4062 (+) Stop HRTIM timer and disable DMA transfer
4063 (+) Enable or disable the burst mode controller
4064 (+) Start the burst mode controller (by software)
4065 (+) Trigger a Capture (by software)
4066 (+) Update the HRTIM timer preloadable registers (by software)
4067 (+) Reset the HRTIM timer counter (by software)
4068 (+) Start a burst DMA transfer
4069 (+) Enable timer register update
4070 (+) Disable timer register update
4071
4072 @endverbatim
4073 * @{
4074 */
4075
4076 /**
4077 * @brief Configure the general behavior of a timer operating in waveform mode
4078 * @param hhrtim pointer to HAL HRTIM handle
4079 * @param TimerIdx Timer index
4080 * This parameter can be one of the following values:
4081 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4082 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4083 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4084 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4085 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4086 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4087 * @param pTimerCfg pointer to the timer configuration structure
4088 * @note When the timer operates in waveform mode, all the features supported by
4089 * the HRTIM are available without any limitation.
4090 * @retval HAL status
4091 * @note This function must be called before starting the timer
4092 */
4093 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
4094 uint32_t TimerIdx,
4095 HRTIM_TimerCfgTypeDef * pTimerCfg)
4096 {
4097 /* Check parameters */
4098 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
4099
4100 /* Relevant for all HRTIM timers, including the master */
4101 assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
4102 assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
4103 assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
4104 assert_param(IS_HRTIM_DACSYNC(pTimerCfg->DACSynchro));
4105 assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
4106 assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
4107 assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
4108
4109 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4110 {
4111 return HAL_BUSY;
4112 }
4113
4114 /* Process Locked */
4115 __HAL_LOCK(hhrtim);
4116
4117 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4118
4119 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
4120 {
4121 /* Check parameters */
4122 assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
4123 assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
4124 assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
4125
4126 /* Configure master timer */
4127 HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
4128 }
4129 else
4130 {
4131 /* Check parameters */
4132 assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
4133 assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
4134 assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
4135 assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
4136 assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
4137 assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
4138 assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
4139 pTimerCfg->DeadTimeInsertion));
4140 assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
4141 pTimerCfg->DelayedProtectionMode));
4142 assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
4143 assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
4144 assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
4145
4146 /* Configure timing unit */
4147 HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
4148 }
4149
4150 /* Update timer parameters */
4151 hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
4152 hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
4153 hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
4154 hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
4155 hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
4156
4157 /* Force a software update */
4158 HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
4159
4160 hhrtim->State = HAL_HRTIM_STATE_READY;
4161
4162 /* Process Unlocked */
4163 __HAL_UNLOCK(hhrtim);
4164
4165 return HAL_OK;
4166 }
4167
4168 /**
4169 * @brief Configure the event filtering capabilities of a timer (blanking, windowing)
4170 * @param hhrtim pointer to HAL HRTIM handle
4171 * @param TimerIdx Timer index
4172 * This parameter can be one of the following values:
4173 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4174 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4175 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4176 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4177 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4178 * @param Event external event for which timer event filtering must be configured
4179 * This parameter can be one of the following values:
4180 * @arg HRTIM_EVENT_1: External event 1
4181 * @arg HRTIM_EVENT_2: External event 2
4182 * @arg HRTIM_EVENT_3: External event 3
4183 * @arg HRTIM_EVENT_4: External event 4
4184 * @arg HRTIM_EVENT_5: External event 5
4185 * @arg HRTIM_EVENT_6: External event 6
4186 * @arg HRTIM_EVENT_7: External event 7
4187 * @arg HRTIM_EVENT_8: External event 8
4188 * @arg HRTIM_EVENT_9: External event 9
4189 * @arg HRTIM_EVENT_10: External event 10
4190 * @param pTimerEventFilteringCfg pointer to the timer event filtering configuration structure
4191 * @note This function must be called before starting the timer
4192 * @retval HAL status
4193 */
4194 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,
4195 uint32_t TimerIdx,
4196 uint32_t Event,
4197 HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
4198 {
4199 /* Check parameters */
4200 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4201 assert_param(IS_HRTIM_EVENT(Event));
4202 assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
4203
4204 assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
4205
4206 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4207 {
4208 return HAL_BUSY;
4209 }
4210
4211 /* Process Locked */
4212 __HAL_LOCK(hhrtim);
4213
4214 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4215
4216 /* Configure timer event filtering capabilities */
4217 switch (Event)
4218 {
4219 case HRTIM_EVENT_NONE:
4220 {
4221 CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1);
4222 CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2);
4223 break;
4224 }
4225
4226 case HRTIM_EVENT_1:
4227 {
4228 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch));
4229 break;
4230 }
4231
4232 case HRTIM_EVENT_2:
4233 {
4234 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) );
4235 break;
4236 }
4237
4238 case HRTIM_EVENT_3:
4239 {
4240 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) );
4241 break;
4242 }
4243
4244 case HRTIM_EVENT_4:
4245 {
4246 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) );
4247 break;
4248 }
4249
4250 case HRTIM_EVENT_5:
4251 {
4252 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) );
4253 break;
4254 }
4255
4256 case HRTIM_EVENT_6:
4257 {
4258 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) );
4259 break;
4260 }
4261
4262 case HRTIM_EVENT_7:
4263 {
4264 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) );
4265 break;
4266 }
4267
4268 case HRTIM_EVENT_8:
4269 {
4270 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) );
4271 break;
4272 }
4273
4274 case HRTIM_EVENT_9:
4275 {
4276 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) );
4277 break;
4278 }
4279
4280 case HRTIM_EVENT_10:
4281 {
4282 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) );
4283 break;
4284 }
4285
4286 default:
4287 {
4288 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4289
4290 /* Process Unlocked */
4291 __HAL_UNLOCK(hhrtim);
4292
4293 break;
4294 }
4295 }
4296
4297 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4298 {
4299 return HAL_ERROR;
4300 }
4301
4302 hhrtim->State = HAL_HRTIM_STATE_READY;
4303
4304 /* Process Unlocked */
4305 __HAL_UNLOCK(hhrtim);
4306
4307 return HAL_OK;
4308 }
4309
4310 /**
4311 * @brief Configure the dead-time insertion feature for a timer
4312 * @param hhrtim pointer to HAL HRTIM handle
4313 * @param TimerIdx Timer index
4314 * This parameter can be one of the following values:
4315 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4316 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4317 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4318 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4319 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4320 * @param pDeadTimeCfg pointer to the deadtime insertion configuration structure
4321 * @retval HAL status
4322 * @note This function must be called before starting the timer
4323 */
4324 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
4325 uint32_t TimerIdx,
4326 HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
4327 {
4328 uint32_t hrtim_dtr;
4329
4330 /* Check parameters */
4331 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4332 assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
4333 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
4334 assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
4335 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
4336 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
4337 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
4338 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
4339
4340 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4341 {
4342 return HAL_BUSY;
4343 }
4344
4345 /* Process Locked */
4346 __HAL_LOCK(hhrtim);
4347
4348 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4349
4350 /* Set timer deadtime configuration */
4351 hrtim_dtr = (pDeadTimeCfg->Prescaler & HRTIM_DTR_DTPRSC);
4352 hrtim_dtr |= (pDeadTimeCfg->RisingValue & HRTIM_DTR_DTR);
4353 hrtim_dtr |= (pDeadTimeCfg->RisingSign & HRTIM_DTR_SDTR);
4354 hrtim_dtr |= (pDeadTimeCfg->RisingSignLock & HRTIM_DTR_DTRSLK);
4355 hrtim_dtr |= (pDeadTimeCfg->RisingLock & HRTIM_DTR_DTRLK);
4356 hrtim_dtr |= ((pDeadTimeCfg->FallingValue << 16U) & HRTIM_DTR_DTF);
4357 hrtim_dtr |= (pDeadTimeCfg->FallingSign & HRTIM_DTR_SDTF);
4358 hrtim_dtr |= (pDeadTimeCfg->FallingSignLock & HRTIM_DTR_DTFSLK);
4359 hrtim_dtr |= (pDeadTimeCfg->FallingLock & HRTIM_DTR_DTFLK);
4360
4361 /* Update the HRTIM registers */
4362 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR, (
4363 HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
4364 HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
4365 HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr);
4366
4367 hhrtim->State = HAL_HRTIM_STATE_READY;
4368
4369 /* Process Unlocked */
4370 __HAL_UNLOCK(hhrtim);
4371
4372 return HAL_OK;
4373 }
4374
4375 /**
4376 * @brief Configure the chopper mode feature for a timer
4377 * @param hhrtim pointer to HAL HRTIM handle
4378 * @param TimerIdx Timer index
4379 * This parameter can be one of the following values:
4380 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4381 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4382 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4383 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4384 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4385 * @param pChopperModeCfg pointer to the chopper mode configuration structure
4386 * @retval HAL status
4387 * @note This function must be called before configuring the timer output(s)
4388 */
4389 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
4390 uint32_t TimerIdx,
4391 HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
4392 {
4393 uint32_t hrtim_chpr;
4394
4395 /* Check parameters */
4396 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4397 assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
4398 assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
4399 assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
4400
4401 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4402 {
4403 return HAL_BUSY;
4404 }
4405
4406 /* Process Locked */
4407 __HAL_LOCK(hhrtim);
4408
4409 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4410
4411 /* Set timer choppe mode configuration */
4412 hrtim_chpr = (pChopperModeCfg->CarrierFreq & HRTIM_CHPR_CARFRQ);
4413 hrtim_chpr |= (pChopperModeCfg->DutyCycle & HRTIM_CHPR_CARDTY);
4414 hrtim_chpr |= (pChopperModeCfg->StartPulse & HRTIM_CHPR_STRPW);
4415
4416 /* Update the HRTIM registers */
4417 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR, (HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY |
4418 HRTIM_CHPR_STRPW) ,
4419 hrtim_chpr);
4420
4421 hhrtim->State = HAL_HRTIM_STATE_READY;
4422
4423 /* Process Unlocked */
4424 __HAL_UNLOCK(hhrtim);
4425
4426 return HAL_OK;
4427 }
4428
4429 /**
4430 * @brief Configure the burst DMA controller for a timer
4431 * @param hhrtim pointer to HAL HRTIM handle
4432 * @param TimerIdx Timer index
4433 * This parameter can be one of the following values:
4434 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4435 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4436 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4437 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4438 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4439 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4440 * @param RegistersToUpdate registers to be written by DMA
4441 * This parameter can be any combination of the following values:
4442 * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
4443 * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
4444 * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
4445 * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
4446 * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
4447 * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
4448 * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
4449 * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
4450 * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
4451 * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
4452 * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
4453 * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
4454 * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
4455 * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
4456 * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
4457 * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
4458 * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
4459 * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
4460 * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
4461 * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
4462 * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
4463 * @retval HAL status
4464 * @note This function must be called before starting the timer
4465 */
4466 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
4467 uint32_t TimerIdx,
4468 uint32_t RegistersToUpdate)
4469 {
4470 /* Check parameters */
4471 assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
4472
4473 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4474 {
4475 return HAL_BUSY;
4476 }
4477
4478 /* Process Locked */
4479 __HAL_LOCK(hhrtim);
4480
4481 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4482
4483 /* Set the burst DMA timer update register */
4484 switch (TimerIdx)
4485 {
4486 case HRTIM_TIMERINDEX_TIMER_A:
4487 {
4488 hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
4489 break;
4490 }
4491
4492 case HRTIM_TIMERINDEX_TIMER_B:
4493 {
4494 hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
4495 break;
4496 }
4497
4498 case HRTIM_TIMERINDEX_TIMER_C:
4499 {
4500 hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
4501 break;
4502 }
4503
4504 case HRTIM_TIMERINDEX_TIMER_D:
4505 {
4506 hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
4507 break;
4508 }
4509
4510 case HRTIM_TIMERINDEX_TIMER_E:
4511 {
4512 hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
4513 break;
4514 }
4515
4516 case HRTIM_TIMERINDEX_MASTER:
4517 {
4518 hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
4519 break;
4520 }
4521
4522 default:
4523 {
4524 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4525
4526 /* Process Unlocked */
4527 __HAL_UNLOCK(hhrtim);
4528
4529 break;
4530 }
4531 }
4532
4533 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4534 {
4535 return HAL_ERROR;
4536 }
4537
4538 hhrtim->State = HAL_HRTIM_STATE_READY;
4539
4540 /* Process Unlocked */
4541 __HAL_UNLOCK(hhrtim);
4542
4543 return HAL_OK;
4544 }
4545
4546 /**
4547 * @brief Configure the compare unit of a timer operating in waveform mode
4548 * @param hhrtim pointer to HAL HRTIM handle
4549 * @param TimerIdx Timer index
4550 * This parameter can be one of the following values:
4551 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4552 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4553 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4554 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4555 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4556 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4557 * @param CompareUnit Compare unit to configure
4558 * This parameter can be one of the following values:
4559 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
4560 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
4561 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
4562 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
4563 * @param pCompareCfg pointer to the compare unit configuration structure
4564 * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
4565 * application has to configure separately the capture unit. Capture unit
4566 * to configure in that case depends on the compare unit auto delayed mode
4567 * is applied to (see below):
4568 * Auto delayed on output compare 2: capture unit 1 must be configured
4569 * Auto delayed on output compare 4: capture unit 2 must be configured
4570 * @retval HAL status
4571 * @note This function must be called before starting the timer
4572 */
4573 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
4574 uint32_t TimerIdx,
4575 uint32_t CompareUnit,
4576 HRTIM_CompareCfgTypeDef* pCompareCfg)
4577 {
4578 /* Check parameters */
4579 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
4580
4581 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4582 {
4583 return HAL_BUSY;
4584 }
4585
4586 /* Process Locked */
4587 __HAL_LOCK(hhrtim);
4588
4589 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4590
4591 /* Configure the compare unit */
4592 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
4593 {
4594 switch (CompareUnit)
4595 {
4596 case HRTIM_COMPAREUNIT_1:
4597 {
4598 hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
4599 break;
4600 }
4601
4602 case HRTIM_COMPAREUNIT_2:
4603 {
4604 hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
4605 break;
4606 }
4607
4608 case HRTIM_COMPAREUNIT_3:
4609 {
4610 hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
4611 break;
4612 }
4613
4614 case HRTIM_COMPAREUNIT_4:
4615 {
4616 hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
4617 break;
4618 }
4619
4620 default:
4621 {
4622 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4623
4624 /* Process Unlocked */
4625 __HAL_UNLOCK(hhrtim);
4626
4627 break;
4628 }
4629 }
4630
4631 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4632 {
4633 return HAL_ERROR;
4634 }
4635
4636 }
4637 else
4638 {
4639 switch (CompareUnit)
4640 {
4641 case HRTIM_COMPAREUNIT_1:
4642 {
4643 /* Set the compare value */
4644 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
4645 break;
4646 }
4647
4648 case HRTIM_COMPAREUNIT_2:
4649 {
4650 /* Check parameters */
4651 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
4652
4653 /* Set the compare value */
4654 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
4655
4656 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
4657 {
4658 /* Configure auto-delayed mode */
4659 /* DELCMP2 bitfield must be reset when reprogrammed from one value */
4660 /* to the other to reinitialize properly the auto-delayed mechanism */
4661 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
4662 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
4663
4664 /* Set the compare value for timeout compare unit (if any) */
4665 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
4666 {
4667 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
4668 }
4669 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
4670 {
4671 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
4672 }
4673 else
4674 {
4675 /* nothing to do */
4676 }
4677 }
4678 else
4679 {
4680 /* Clear HRTIM_TIMxCR.DELCMP2 bitfield */
4681 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U);
4682 }
4683 break;
4684 }
4685
4686 case HRTIM_COMPAREUNIT_3:
4687 {
4688 /* Set the compare value */
4689 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
4690 break;
4691 }
4692
4693 case HRTIM_COMPAREUNIT_4:
4694 {
4695 /* Check parameters */
4696 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
4697
4698 /* Set the compare value */
4699 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
4700
4701 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
4702 {
4703 /* Configure auto-delayed mode */
4704 /* DELCMP4 bitfield must be reset when reprogrammed from one value */
4705 /* to the other to reinitialize properly the auto-delayed mechanism */
4706 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
4707 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U);
4708
4709 /* Set the compare value for timeout compare unit (if any) */
4710 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
4711 {
4712 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
4713 }
4714 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
4715 {
4716 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
4717 }
4718 else
4719 {
4720 /* nothing to do */
4721 }
4722 }
4723 else
4724 {
4725 /* Clear HRTIM_TIMxCR.DELCMP4 bitfield */
4726 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U);
4727 }
4728 break;
4729 }
4730
4731 default:
4732 {
4733 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4734
4735 /* Process Unlocked */
4736 __HAL_UNLOCK(hhrtim);
4737
4738 break;
4739 }
4740 }
4741
4742 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4743 {
4744 return HAL_ERROR;
4745 }
4746
4747 }
4748 hhrtim->State = HAL_HRTIM_STATE_READY;
4749
4750 /* Process Unlocked */
4751 __HAL_UNLOCK(hhrtim);
4752
4753 return HAL_OK;
4754 }
4755
4756 /**
4757 * @brief Configure the capture unit of a timer operating in waveform mode
4758 * @param hhrtim pointer to HAL HRTIM handle
4759 * @param TimerIdx Timer index
4760 * This parameter can be one of the following values:
4761 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4762 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4763 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4764 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4765 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4766 * @param CaptureUnit Capture unit to configure
4767 * This parameter can be one of the following values:
4768 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
4769 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
4770 * @param pCaptureCfg pointer to the compare unit configuration structure
4771 * @retval HAL status
4772 * @note This function must be called before starting the timer
4773 */
4774 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
4775 uint32_t TimerIdx,
4776 uint32_t CaptureUnit,
4777 HRTIM_CaptureCfgTypeDef* pCaptureCfg)
4778 {
4779 /* Check parameters */
4780 assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger));
4781
4782
4783 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4784 {
4785 return HAL_BUSY;
4786 }
4787
4788 /* Process Locked */
4789 __HAL_LOCK(hhrtim);
4790
4791 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4792
4793 /* Configure the capture unit */
4794 switch (CaptureUnit)
4795 {
4796 case HRTIM_CAPTUREUNIT_1:
4797 {
4798 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, pCaptureCfg->Trigger);
4799 break;
4800 }
4801
4802 case HRTIM_CAPTUREUNIT_2:
4803 {
4804 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, pCaptureCfg->Trigger);
4805 break;
4806 }
4807
4808 default:
4809 {
4810 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4811
4812 /* Process Unlocked */
4813 __HAL_UNLOCK(hhrtim);
4814
4815 break;
4816 }
4817 }
4818
4819 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4820 {
4821 return HAL_ERROR;
4822 }
4823
4824
4825 hhrtim->State = HAL_HRTIM_STATE_READY;
4826
4827 /* Process Unlocked */
4828 __HAL_UNLOCK(hhrtim);
4829
4830 return HAL_OK;
4831 }
4832
4833 /**
4834 * @brief Configure the output of a timer operating in waveform mode
4835 * @param hhrtim pointer to HAL HRTIM handle
4836 * @param TimerIdx Timer index
4837 * This parameter can be one of the following values:
4838 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4839 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4840 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4841 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4842 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4843 * @param Output Timer output
4844 * This parameter can be one of the following values:
4845 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
4846 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
4847 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
4848 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
4849 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
4850 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
4851 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
4852 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
4853 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
4854 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
4855 * @param pOutputCfg pointer to the timer output configuration structure
4856 * @retval HAL status
4857 * @note This function must be called before configuring the timer and after
4858 * configuring the deadtime insertion feature (if required).
4859 */
4860 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
4861 uint32_t TimerIdx,
4862 uint32_t Output,
4863 HRTIM_OutputCfgTypeDef * pOutputCfg)
4864 {
4865 /* Check parameters */
4866 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
4867 assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
4868 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
4869 assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
4870 assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
4871 assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
4872 assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
4873
4874 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4875 {
4876 return HAL_BUSY;
4877 }
4878
4879 /* Process Locked */
4880 __HAL_LOCK(hhrtim);
4881
4882 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4883
4884 /* Configure the timer output */
4885 HRTIM_OutputConfig(hhrtim,
4886 TimerIdx,
4887 Output,
4888 pOutputCfg);
4889
4890 hhrtim->State = HAL_HRTIM_STATE_READY;
4891
4892 /* Process Unlocked */
4893 __HAL_UNLOCK(hhrtim);
4894
4895 return HAL_OK;
4896 }
4897
4898 /**
4899 * @brief Force the timer output to its active or inactive state
4900 * @param hhrtim pointer to HAL HRTIM handle
4901 * @param TimerIdx Timer index
4902 * This parameter can be one of the following values:
4903 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4904 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4905 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4906 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4907 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4908 * @param Output Timer output
4909 * This parameter can be one of the following values:
4910 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
4911 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
4912 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
4913 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
4914 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
4915 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
4916 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
4917 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
4918 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
4919 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
4920 * @param OutputLevel indicates whether the output is forced to its active or inactive level
4921 * This parameter can be one of the following values:
4922 * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
4923 * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
4924 * @retval HAL status
4925 * @note The 'software set/reset trigger' bit in the output set/reset registers
4926 * is automatically reset by hardware
4927 */
4928 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
4929 uint32_t TimerIdx,
4930 uint32_t Output,
4931 uint32_t OutputLevel)
4932 {
4933 /* Check parameters */
4934 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
4935 assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
4936
4937 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4938 {
4939 return HAL_BUSY;
4940 }
4941
4942 /* Process Locked */
4943 __HAL_LOCK(hhrtim);
4944
4945 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4946
4947 /* Force timer output level */
4948 switch (Output)
4949 {
4950 case HRTIM_OUTPUT_TA1:
4951 case HRTIM_OUTPUT_TB1:
4952 case HRTIM_OUTPUT_TC1:
4953 case HRTIM_OUTPUT_TD1:
4954 case HRTIM_OUTPUT_TE1:
4955 {
4956 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
4957 {
4958 /* Force output to its active state */
4959 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R,HRTIM_SET1R_SST);
4960 }
4961 else
4962 {
4963 /* Force output to its inactive state */
4964 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R, HRTIM_RST1R_SRT);
4965 }
4966 break;
4967 }
4968
4969 case HRTIM_OUTPUT_TA2:
4970 case HRTIM_OUTPUT_TB2:
4971 case HRTIM_OUTPUT_TC2:
4972 case HRTIM_OUTPUT_TD2:
4973 case HRTIM_OUTPUT_TE2:
4974 {
4975 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
4976 {
4977 /* Force output to its active state */
4978 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R, HRTIM_SET2R_SST);
4979 }
4980 else
4981 {
4982 /* Force output to its inactive state */
4983 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R, HRTIM_RST2R_SRT);
4984 }
4985 break;
4986 }
4987
4988 default:
4989 {
4990 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4991
4992 /* Process Unlocked */
4993 __HAL_UNLOCK(hhrtim);
4994
4995 break;
4996 }
4997 }
4998
4999 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
5000 {
5001 return HAL_ERROR;
5002 }
5003
5004 hhrtim->State = HAL_HRTIM_STATE_READY;
5005
5006 /* Process Unlocked */
5007 __HAL_UNLOCK(hhrtim);
5008
5009 return HAL_OK;
5010 }
5011
5012 /**
5013 * @brief Enable the generation of the waveform signal on the designated output(s)
5014 * Outputs can be combined (ORed) to allow for simultaneous output enabling.
5015 * @param hhrtim pointer to HAL HRTIM handle
5016 * @param OutputsToStart Timer output(s) to enable
5017 * This parameter can be any combination of the following values:
5018 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
5019 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
5020 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
5021 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
5022 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
5023 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
5024 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
5025 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
5026 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
5027 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
5028 * @retval HAL status
5029 */
5030 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,
5031 uint32_t OutputsToStart)
5032 {
5033 /* Check the parameters */
5034 assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
5035
5036 /* Process Locked */
5037 __HAL_LOCK(hhrtim);
5038
5039 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5040
5041 /* Enable the HRTIM outputs */
5042 hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
5043
5044 hhrtim->State = HAL_HRTIM_STATE_READY;
5045
5046 /* Process Unlocked */
5047 __HAL_UNLOCK(hhrtim);
5048
5049 return HAL_OK;
5050 }
5051
5052 /**
5053 * @brief Disable the generation of the waveform signal on the designated output(s)
5054 * Outputs can be combined (ORed) to allow for simultaneous output disabling.
5055 * @param hhrtim pointer to HAL HRTIM handle
5056 * @param OutputsToStop Timer output(s) to disable
5057 * This parameter can be any combination of the following values:
5058 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
5059 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
5060 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
5061 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
5062 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
5063 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
5064 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
5065 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
5066 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
5067 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
5068 * @retval HAL status
5069 */
5070 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,
5071 uint32_t OutputsToStop)
5072 {
5073 /* Check the parameters */
5074 assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
5075
5076 /* Process Locked */
5077 __HAL_LOCK(hhrtim);
5078
5079 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5080
5081 /* Enable the HRTIM outputs */
5082 hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
5083
5084 hhrtim->State = HAL_HRTIM_STATE_READY;
5085
5086 /* Process Unlocked */
5087 __HAL_UNLOCK(hhrtim);
5088
5089 return HAL_OK;
5090 }
5091
5092 /**
5093 * @brief Start the counter of the designated timer(s) operating in waveform mode
5094 * Timers can be combined (ORed) to allow for simultaneous counter start.
5095 * @param hhrtim pointer to HAL HRTIM handle
5096 * @param Timers Timer counter(s) to start
5097 * This parameter can be any combination of the following values:
5098 * @arg HRTIM_TIMERID_MASTER
5099 * @arg HRTIM_TIMERID_TIMER_A
5100 * @arg HRTIM_TIMERID_TIMER_B
5101 * @arg HRTIM_TIMERID_TIMER_C
5102 * @arg HRTIM_TIMERID_TIMER_D
5103 * @arg HRTIM_TIMERID_TIMER_E
5104 * @retval HAL status
5105 */
5106 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim,
5107 uint32_t Timers)
5108 {
5109 /* Check the parameters */
5110 assert_param(IS_HRTIM_TIMERID(Timers));
5111
5112 /* Process Locked */
5113 __HAL_LOCK(hhrtim);
5114
5115 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5116
5117 /* Enable timer(s) counter */
5118 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
5119
5120 hhrtim->State = HAL_HRTIM_STATE_READY;
5121
5122 /* Process Unlocked */
5123 __HAL_UNLOCK(hhrtim);
5124
5125 return HAL_OK;
5126 }
5127
5128 /**
5129 * @brief Stop the counter of the designated timer(s) operating in waveform mode
5130 * Timers can be combined (ORed) to allow for simultaneous counter stop.
5131 * @param hhrtim pointer to HAL HRTIM handle
5132 * @param Timers Timer counter(s) to stop
5133 * This parameter can be any combination of the following values:
5134 * @arg HRTIM_TIMERID_MASTER
5135 * @arg HRTIM_TIMERID_TIMER_A
5136 * @arg HRTIM_TIMERID_TIMER_B
5137 * @arg HRTIM_TIMERID_TIMER_C
5138 * @arg HRTIM_TIMERID_TIMER_D
5139 * @arg HRTIM_TIMERID_TIMER_E
5140 * @retval HAL status
5141 * @note The counter of a timer is stopped only if all timer outputs are disabled
5142 */
5143 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim,
5144 uint32_t Timers)
5145 {
5146 /* Check the parameters */
5147 assert_param(IS_HRTIM_TIMERID(Timers));
5148
5149 /* Process Locked */
5150 __HAL_LOCK(hhrtim);
5151
5152 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5153
5154 /* Disable timer(s) counter */
5155 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
5156
5157 hhrtim->State = HAL_HRTIM_STATE_READY;
5158
5159 /* Process Unlocked */
5160 __HAL_UNLOCK(hhrtim);
5161
5162 return HAL_OK;
5163 }
5164
5165 /**
5166 * @brief Start the counter of the designated timer(s) operating in waveform mode
5167 * Timers can be combined (ORed) to allow for simultaneous counter start.
5168 * @param hhrtim pointer to HAL HRTIM handle
5169 * @param Timers Timer counter(s) to start
5170 * This parameter can be any combination of the following values:
5171 * @arg HRTIM_TIMERID_MASTER
5172 * @arg HRTIM_TIMERID_TIMER_A
5173 * @arg HRTIM_TIMERID_TIMER_B
5174 * @arg HRTIM_TIMERID_TIMER_C
5175 * @arg HRTIM_TIMERID_TIMER_D
5176 * @arg HRTIM_TIMERID_TIMER_E
5177 * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
5178 * to the timers to start are enabled within this function.
5179 * Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
5180 * function.
5181 * @retval HAL status
5182 */
5183 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim,
5184 uint32_t Timers)
5185 {
5186 uint8_t timer_idx;
5187
5188 /* Check the parameters */
5189 assert_param(IS_HRTIM_TIMERID(Timers));
5190
5191 /* Process Locked */
5192 __HAL_LOCK(hhrtim);
5193
5194 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5195
5196 /* Enable HRTIM interrupts (if required) */
5197 __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
5198
5199 /* Enable master timer related interrupts (if required) */
5200 if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
5201 {
5202 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
5203 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
5204 }
5205
5206 /* Enable timing unit related interrupts (if required) */
5207 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5208 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5209 timer_idx++)
5210 {
5211 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
5212 {
5213 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
5214 timer_idx,
5215 hhrtim->TimerParam[timer_idx].InterruptRequests);
5216 }
5217 }
5218
5219 /* Enable timer(s) counter */
5220 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
5221
5222 hhrtim->State = HAL_HRTIM_STATE_READY;
5223
5224 /* Process Unlocked */
5225 __HAL_UNLOCK(hhrtim);
5226
5227 return HAL_OK;}
5228
5229 /**
5230 * @brief Stop the counter of the designated timer(s) operating in waveform mode
5231 * Timers can be combined (ORed) to allow for simultaneous counter stop.
5232 * @param hhrtim pointer to HAL HRTIM handle
5233 * @param Timers Timer counter(s) to stop
5234 * This parameter can be any combination of the following values:
5235 * @arg HRTIM_TIMERID_MASTER
5236 * @arg HRTIM_TIMERID_TIMER_A
5237 * @arg HRTIM_TIMERID_TIMER_B
5238 * @arg HRTIM_TIMERID_TIMER_C
5239 * @arg HRTIM_TIMERID_TIMER_D
5240 * @arg HRTIM_TIMERID_TIMER_E
5241 * @retval HAL status
5242 * @note The counter of a timer is stopped only if all timer outputs are disabled
5243 * @note All enabled timer related interrupts are disabled.
5244 */
5245 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim,
5246 uint32_t Timers)
5247 {
5248 /* ++ WA */
5249 __IO uint32_t delai = (uint32_t)(0x17FU);
5250 /* -- WA */
5251
5252 uint8_t timer_idx;
5253
5254 /* Check the parameters */
5255 assert_param(IS_HRTIM_TIMERID(Timers));
5256
5257 /* Process Locked */
5258 __HAL_LOCK(hhrtim);
5259
5260 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5261
5262 /* Disable HRTIM interrupts (if required) */
5263 __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
5264
5265 /* Disable master timer related interrupts (if required) */
5266 if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
5267 {
5268 /* Interrupts enable flag must be cleared one by one */
5269 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
5270 }
5271
5272 /* Disable timing unit related interrupts (if required) */
5273 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5274 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5275 timer_idx++)
5276 {
5277 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
5278 {
5279 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
5280 }
5281 }
5282
5283 /* ++ WA */
5284 do { delai--; } while (delai != 0U);
5285 /* -- WA */
5286
5287 /* Disable timer(s) counter */
5288 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
5289
5290 hhrtim->State = HAL_HRTIM_STATE_READY;
5291
5292 /* Process Unlocked */
5293 __HAL_UNLOCK(hhrtim);
5294
5295 return HAL_OK;
5296 }
5297
5298 /**
5299 * @brief Start the counter of the designated timer(s) operating in waveform mode
5300 * Timers can be combined (ORed) to allow for simultaneous counter start.
5301 * @param hhrtim pointer to HAL HRTIM handle
5302 * @param Timers Timer counter(s) to start
5303 * This parameter can be any combination of the following values:
5304 * @arg HRTIM_TIMERID_MASTER
5305 * @arg HRTIM_TIMERID_TIMER_A
5306 * @arg HRTIM_TIMERID_TIMER_B
5307 * @arg HRTIM_TIMERID_TIMER_C
5308 * @arg HRTIM_TIMERID_TIMER_D
5309 * @arg HRTIM_TIMERID_TIMER_E
5310 * @retval HAL status
5311 * @note This function enables the dma request(s) mentionned in the timer
5312 * configuration data structure for every timers to start.
5313 * @note The source memory address, the destination memory address and the
5314 * size of each DMA transfer are specified at timer configuration time
5315 * (see HAL_HRTIM_WaveformTimerConfig)
5316 */
5317 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim,
5318 uint32_t Timers)
5319 {
5320 uint8_t timer_idx;
5321 DMA_HandleTypeDef * hdma;
5322
5323 /* Check the parameters */
5324 assert_param(IS_HRTIM_TIMERID(Timers));
5325
5326 if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
5327 {
5328 return HAL_BUSY;
5329 }
5330
5331 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5332
5333 /* Process Locked */
5334 __HAL_LOCK(hhrtim);
5335
5336 if (((Timers & HRTIM_TIMERID_MASTER) != (uint32_t)RESET) &&
5337 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
5338 {
5339 /* Set the DMA error callback */
5340 hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
5341
5342 /* Set the DMA transfer completed callback */
5343 hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
5344
5345 /* Enable the DMA channel */
5346 if (HAL_DMA_Start_IT(hhrtim->hdmaMaster,
5347 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
5348 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
5349 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK)
5350 {
5351 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5352
5353 /* Process Unlocked */
5354 __HAL_UNLOCK(hhrtim);
5355
5356 return HAL_ERROR;
5357 }
5358
5359 /* Enable the timer DMA request */
5360 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
5361 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
5362 }
5363
5364 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5365 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5366 timer_idx++)
5367 {
5368 if (((Timers & TimerIdxToTimerId[timer_idx]) != (uint32_t)RESET) &&
5369 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
5370 {
5371 /* Get the timer DMA handler */
5372 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
5373
5374 if (hdma == NULL)
5375 {
5376 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5377
5378 /* Process Unlocked */
5379 __HAL_UNLOCK(hhrtim);
5380
5381 return HAL_ERROR;
5382 }
5383
5384 /* Set the DMA error callback */
5385 hdma->XferErrorCallback = HRTIM_DMAError ;
5386
5387 /* Set the DMA transfer completed callback */
5388 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
5389
5390 /* Enable the DMA channel */
5391 if (HAL_DMA_Start_IT(hdma,
5392 hhrtim->TimerParam[timer_idx].DMASrcAddress,
5393 hhrtim->TimerParam[timer_idx].DMADstAddress,
5394 hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK)
5395 {
5396 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5397
5398 /* Process Unlocked */
5399 __HAL_UNLOCK(hhrtim);
5400
5401 return HAL_ERROR;
5402 }
5403
5404 /* Enable the timer DMA request */
5405 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
5406 timer_idx,
5407 hhrtim->TimerParam[timer_idx].DMARequests);
5408 }
5409 }
5410
5411 /* Enable the timer counter */
5412 __HAL_HRTIM_ENABLE(hhrtim, Timers);
5413
5414 hhrtim->State = HAL_HRTIM_STATE_READY;
5415
5416 /* Process Unlocked */
5417 __HAL_UNLOCK(hhrtim);
5418
5419 return HAL_OK;
5420 }
5421
5422 /**
5423 * @brief Stop the counter of the designated timer(s) operating in waveform mode
5424 * Timers can be combined (ORed) to allow for simultaneous counter stop.
5425 * @param hhrtim pointer to HAL HRTIM handle
5426 * @param Timers Timer counter(s) to stop
5427 * This parameter can be any combination of the following values:
5428 * @arg HRTIM_TIMERID_MASTER
5429 * @arg HRTIM_TIMERID_TIMER_A
5430 * @arg HRTIM_TIMERID_TIMER_B
5431 * @arg HRTIM_TIMERID_TIMER_C
5432 * @arg HRTIM_TIMERID_TIMER_D
5433 * @arg HRTIM_TIMERID_TIMER_E
5434 * @retval HAL status
5435 * @note The counter of a timer is stopped only if all timer outputs are disabled
5436 * @note All enabled timer related DMA requests are disabled.
5437 */
5438 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim,
5439 uint32_t Timers)
5440 {
5441 uint8_t timer_idx;
5442
5443 /* Check the parameters */
5444 assert_param(IS_HRTIM_TIMERID(Timers));
5445
5446 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5447
5448 if (((Timers & HRTIM_TIMERID_MASTER) != 0U) &&
5449 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
5450 {
5451 /* Disable the DMA */
5452 if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
5453 {
5454 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5455 }
5456 else
5457 {
5458 hhrtim->State = HAL_HRTIM_STATE_READY;
5459 /* Disable the DMA request(s) */
5460 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
5461 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
5462 }
5463 }
5464
5465 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5466 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5467 timer_idx++)
5468 {
5469 if (((Timers & TimerIdxToTimerId[timer_idx]) != 0U) &&
5470 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
5471 {
5472 /* Get the timer DMA handler */
5473 /* Disable the DMA */
5474 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx)) != HAL_OK)
5475 {
5476 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5477 }
5478 else
5479 {
5480 hhrtim->State = HAL_HRTIM_STATE_READY;
5481
5482 /* Disable the DMA request(s) */
5483 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
5484 timer_idx,
5485 hhrtim->TimerParam[timer_idx].DMARequests);
5486 }
5487 }
5488 }
5489
5490 /* Disable the timer counter */
5491 __HAL_HRTIM_DISABLE(hhrtim, Timers);
5492
5493 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
5494 {
5495 return HAL_ERROR;
5496 }
5497 else
5498 {
5499 return HAL_OK;
5500 }
5501 }
5502
5503 /**
5504 * @brief Enable or disables the HRTIM burst mode controller.
5505 * @param hhrtim pointer to HAL HRTIM handle
5506 * @param Enable Burst mode controller enabling
5507 * This parameter can be one of the following values:
5508 * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
5509 * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
5510 * @retval HAL status
5511 * @note This function must be called after starting the timer(s)
5512 */
5513 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,
5514 uint32_t Enable)
5515 {
5516 /* Check parameters */
5517 assert_param(IS_HRTIM_BURSTMODECTL(Enable));
5518
5519 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5520 {
5521 return HAL_BUSY;
5522 }
5523
5524 /* Process Locked */
5525 __HAL_LOCK(hhrtim);
5526
5527 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5528
5529 /* Enable/Disable the burst mode controller */
5530 MODIFY_REG(hhrtim->Instance->sCommonRegs.BMCR, HRTIM_BMCR_BME, Enable);
5531
5532 hhrtim->State = HAL_HRTIM_STATE_READY;
5533
5534 /* Process Unlocked */
5535 __HAL_UNLOCK(hhrtim);
5536
5537 return HAL_OK;
5538 }
5539
5540 /**
5541 * @brief Trig the burst mode operation.
5542 * @param hhrtim pointer to HAL HRTIM handle
5543 * @retval HAL status
5544 */
5545 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
5546 {
5547 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5548 {
5549 return HAL_BUSY;
5550 }
5551
5552 /* Process Locked */
5553 __HAL_LOCK(hhrtim);
5554
5555 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5556
5557 /* Software trigger of the burst mode controller */
5558 SET_BIT(hhrtim->Instance->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
5559
5560 hhrtim->State = HAL_HRTIM_STATE_READY;
5561
5562 /* Process Unlocked */
5563 __HAL_UNLOCK(hhrtim);
5564
5565 return HAL_OK;
5566 }
5567
5568 /**
5569 * @brief Trig a software capture on the designed capture unit
5570 * @param hhrtim pointer to HAL HRTIM handle
5571 * @param TimerIdx Timer index
5572 * This parameter can be one of the following values:
5573 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5574 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5575 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5576 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5577 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5578 * @param CaptureUnit Capture unit to trig
5579 * This parameter can be one of the following values:
5580 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
5581 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
5582 * @retval HAL status
5583 * @note The 'software capture' bit in the capure configuration register is
5584 * automatically reset by hardware
5585 */
5586 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
5587 uint32_t TimerIdx,
5588 uint32_t CaptureUnit)
5589 {
5590 /* Check parameters */
5591 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5592 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
5593
5594 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5595 {
5596 return HAL_BUSY;
5597 }
5598
5599 /* Process Locked */
5600 __HAL_LOCK(hhrtim);
5601
5602 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5603
5604 /* Force a software capture on concerned capture unit */
5605 switch (CaptureUnit)
5606 {
5607 case HRTIM_CAPTUREUNIT_1:
5608 {
5609 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, HRTIM_CPT1CR_SWCPT);
5610 break;
5611 }
5612
5613 case HRTIM_CAPTUREUNIT_2:
5614 {
5615 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, HRTIM_CPT2CR_SWCPT);
5616 break;
5617 }
5618
5619 default:
5620 {
5621 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5622
5623 /* Process Unlocked */
5624 __HAL_UNLOCK(hhrtim);
5625
5626 break;
5627 }
5628 }
5629
5630 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
5631 {
5632 return HAL_ERROR;
5633 }
5634
5635 hhrtim->State = HAL_HRTIM_STATE_READY;
5636
5637 /* Process Unlocked */
5638 __HAL_UNLOCK(hhrtim);
5639
5640 return HAL_OK;
5641 }
5642
5643 /**
5644 * @brief Trig the update of the registers of one or several timers
5645 * @param hhrtim pointer to HAL HRTIM handle
5646 * @param Timers timers concerned with the software register update
5647 * This parameter can be any combination of the following values:
5648 * @arg HRTIM_TIMERUPDATE_MASTER
5649 * @arg HRTIM_TIMERUPDATE_A
5650 * @arg HRTIM_TIMERUPDATE_B
5651 * @arg HRTIM_TIMERUPDATE_C
5652 * @arg HRTIM_TIMERUPDATE_D
5653 * @arg HRTIM_TIMERUPDATE_E
5654 * @retval HAL status
5655 * @note The 'software update' bits in the HRTIM conrol register 2 register are
5656 * automatically reset by hardware
5657 */
5658 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
5659 uint32_t Timers)
5660 {
5661 /* Check parameters */
5662 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5663
5664 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5665 {
5666 return HAL_BUSY;
5667 }
5668
5669 /* Process Locked */
5670 __HAL_LOCK(hhrtim);
5671
5672 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5673
5674 /* Force timer(s) registers update */
5675 hhrtim->Instance->sCommonRegs.CR2 |= Timers;
5676
5677 hhrtim->State = HAL_HRTIM_STATE_READY;
5678
5679 /* Process Unlocked */
5680 __HAL_UNLOCK(hhrtim);
5681
5682 return HAL_OK;
5683 }
5684
5685 /**
5686 * @brief Trig the reset of one or several timers
5687 * @param hhrtim pointer to HAL HRTIM handle
5688 * @param Timers timers concerned with the software counter reset
5689 * This parameter can be any combination of the following values:
5690 * @arg HRTIM_TIMERRESET_MASTER
5691 * @arg HRTIM_TIMERRESET_TIMER_A
5692 * @arg HRTIM_TIMERRESET_TIMER_B
5693 * @arg HRTIM_TIMERRESET_TIMER_C
5694 * @arg HRTIM_TIMERRESET_TIMER_D
5695 * @arg HRTIM_TIMERRESET_TIMER_E
5696 * @retval HAL status
5697 * @note The 'software reset' bits in the HRTIM conrol register 2 are
5698 * automatically reset by hardware
5699 */
5700 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
5701 uint32_t Timers)
5702 {
5703 /* Check parameters */
5704 assert_param(IS_HRTIM_TIMERRESET(Timers));
5705
5706 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5707 {
5708 return HAL_BUSY;
5709 }
5710
5711 /* Process Locked */
5712 __HAL_LOCK(hhrtim);
5713
5714 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5715
5716 /* Force timer(s) registers reset */
5717 hhrtim->Instance->sCommonRegs.CR2 = Timers;
5718
5719 hhrtim->State = HAL_HRTIM_STATE_READY;
5720
5721 /* Process Unlocked */
5722 __HAL_UNLOCK(hhrtim);
5723
5724 return HAL_OK;
5725 }
5726
5727 /**
5728 * @brief Start a burst DMA operation to update HRTIM control registers content
5729 * @param hhrtim pointer to HAL HRTIM handle
5730 * @param TimerIdx Timer index
5731 * This parameter can be one of the following values:
5732 * @arg HRTIM_TIMERINDEX_MASTER for master timer
5733 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5734 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5735 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5736 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5737 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5738 * @param BurstBufferAddress address of the buffer the HRTIM control registers
5739 * content will be updated from.
5740 * @param BurstBufferLength size (in WORDS) of the burst buffer.
5741 * @retval HAL status
5742 * @note The TimerIdx parameter determines the dma channel to be used by the
5743 * DMA burst controller (see below)
5744 * HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
5745 * HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
5746 * HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
5747 * HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
5748 * HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
5749 * HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
5750 */
5751 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
5752 uint32_t TimerIdx,
5753 uint32_t BurstBufferAddress,
5754 uint32_t BurstBufferLength)
5755 {
5756 DMA_HandleTypeDef * hdma;
5757
5758 /* Check the parameters */
5759 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
5760
5761 if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
5762 {
5763 return HAL_BUSY;
5764 }
5765 if((hhrtim->State == HAL_HRTIM_STATE_READY))
5766 {
5767 if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
5768 {
5769 return HAL_ERROR;
5770 }
5771 else
5772 {
5773 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5774 }
5775 }
5776
5777 /* Process Locked */
5778 __HAL_LOCK(hhrtim);
5779
5780 /* Get the timer DMA handler */
5781 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
5782
5783 if (hdma == NULL)
5784 {
5785 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5786
5787 /* Process Unlocked */
5788 __HAL_UNLOCK(hhrtim);
5789
5790 return HAL_ERROR;
5791 }
5792
5793 /* Set the DMA transfer completed callback */
5794 hdma->XferCpltCallback = HRTIM_BurstDMACplt;
5795
5796 /* Set the DMA error callback */
5797 hdma->XferErrorCallback = HRTIM_DMAError ;
5798
5799 /* Enable the DMA channel */
5800 if (HAL_DMA_Start_IT(hdma,
5801 BurstBufferAddress,
5802 (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR),
5803 BurstBufferLength) != HAL_OK)
5804 {
5805 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5806
5807 /* Process Unlocked */
5808 __HAL_UNLOCK(hhrtim);
5809
5810 return HAL_ERROR;
5811 }
5812
5813 hhrtim->State = HAL_HRTIM_STATE_READY;
5814
5815 /* Process Unlocked */
5816 __HAL_UNLOCK(hhrtim);
5817
5818 return HAL_OK;
5819 }
5820
5821 /**
5822 * @brief Enable the transfer from preload to active registers for one
5823 * or several timing units (including master timer).
5824 * @param hhrtim pointer to HAL HRTIM handle
5825 * @param Timers Timer(s) concerned by the register preload enabling command
5826 * This parameter can be any combination of the following values:
5827 * @arg HRTIM_TIMERUPDATE_MASTER
5828 * @arg HRTIM_TIMERUPDATE_A
5829 * @arg HRTIM_TIMERUPDATE_B
5830 * @arg HRTIM_TIMERUPDATE_C
5831 * @arg HRTIM_TIMERUPDATE_D
5832 * @arg HRTIM_TIMERUPDATE_E
5833 * @retval HAL status
5834 */
5835 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
5836 uint32_t Timers)
5837 {
5838 /* Check the parameters */
5839 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5840
5841 /* Process Locked */
5842 __HAL_LOCK(hhrtim);
5843
5844 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5845
5846 /* Enable timer(s) registers update */
5847 hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
5848
5849 hhrtim->State = HAL_HRTIM_STATE_READY;
5850
5851 /* Process Unlocked */
5852 __HAL_UNLOCK(hhrtim);
5853
5854 return HAL_OK;
5855 }
5856
5857 /**
5858 * @brief Disable the transfer from preload to active registers for one
5859 * or several timing units (including master timer).
5860 * @param hhrtim pointer to HAL HRTIM handle
5861 * @param Timers Timer(s) concerned by the register preload disabling command
5862 * This parameter can be any combination of the following values:
5863 * @arg HRTIM_TIMERUPDATE_MASTER
5864 * @arg HRTIM_TIMERUPDATE_A
5865 * @arg HRTIM_TIMERUPDATE_B
5866 * @arg HRTIM_TIMERUPDATE_C
5867 * @arg HRTIM_TIMERUPDATE_D
5868 * @arg HRTIM_TIMERUPDATE_E
5869 * @retval HAL status
5870 */
5871 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
5872 uint32_t Timers)
5873 {
5874 /* Check the parameters */
5875 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5876
5877 /* Process Locked */
5878 __HAL_LOCK(hhrtim);
5879
5880 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5881
5882 /* Enable timer(s) registers update */
5883 hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
5884
5885 hhrtim->State = HAL_HRTIM_STATE_READY;
5886
5887 /* Process Unlocked */
5888 __HAL_UNLOCK(hhrtim);
5889
5890 return HAL_OK;
5891 }
5892
5893 /**
5894 * @}
5895 */
5896
5897 /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
5898 * @brief Peripheral State functions
5899 @verbatim
5900 ===============================================================================
5901 ##### Peripheral State functions #####
5902 ===============================================================================
5903 [..] This section provides functions used to get HRTIM or HRTIM timer
5904 specific information:
5905 (+) Get HRTIM HAL state
5906 (+) Get captured value
5907 (+) Get HRTIM timer output level
5908 (+) Get HRTIM timer output state
5909 (+) Get delayed protection status
5910 (+) Get burst status
5911 (+) Get current push-pull status
5912 (+) Get idle push-pull status
5913
5914 @endverbatim
5915 * @{
5916 */
5917
5918 /**
5919 * @brief Return the HRTIM HAL state
5920 * @param hhrtim pointer to HAL HRTIM handle
5921 * @retval HAL state
5922 */
5923 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim)
5924 {
5925 /* Return HRTIM state */
5926 return hhrtim->State;
5927 }
5928
5929 /**
5930 * @brief Return actual value of the capture register of the designated capture unit
5931 * @param hhrtim pointer to HAL HRTIM handle
5932 * @param TimerIdx Timer index
5933 * This parameter can be one of the following values:
5934 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5935 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5936 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5937 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5938 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5939 * @param CaptureUnit Capture unit to trig
5940 * This parameter can be one of the following values:
5941 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
5942 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
5943 * @retval Captured value
5944 */
5945 uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
5946 uint32_t TimerIdx,
5947 uint32_t CaptureUnit)
5948 {
5949 uint32_t captured_value;
5950
5951 /* Check parameters */
5952 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5953 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
5954
5955 /* Read captured value */
5956 switch (CaptureUnit)
5957 {
5958 case HRTIM_CAPTUREUNIT_1:
5959 {
5960 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
5961 break;
5962 }
5963
5964 case HRTIM_CAPTUREUNIT_2:
5965 {
5966 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
5967 break;
5968 }
5969
5970 default:
5971 {
5972 captured_value = 0xFFFFFFFFUL;
5973
5974 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5975
5976 /* Process Unlocked */
5977 __HAL_UNLOCK(hhrtim);
5978 break;
5979 }
5980
5981 }
5982
5983 return captured_value;
5984 }
5985
5986
5987 /**
5988 * @brief Return actual level (active or inactive) of the designated output
5989 * @param hhrtim pointer to HAL HRTIM handle
5990 * @param TimerIdx Timer index
5991 * This parameter can be one of the following values:
5992 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5993 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5994 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5995 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5996 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5997 * @param Output Timer output
5998 * This parameter can be one of the following values:
5999 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6000 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6001 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6002 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6003 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6004 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6005 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6006 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6007 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6008 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6009 * @retval Output level
6010 * @note Returned output level is taken before the output stage (chopper,
6011 * polarity).
6012 */
6013 uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
6014 uint32_t TimerIdx,
6015 uint32_t Output)
6016 {
6017 uint32_t output_level = (uint32_t)RESET;
6018
6019 /* Check parameters */
6020 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6021
6022 /* Read the output level */
6023 switch (Output)
6024 {
6025 case HRTIM_OUTPUT_TA1:
6026 case HRTIM_OUTPUT_TB1:
6027 case HRTIM_OUTPUT_TC1:
6028 case HRTIM_OUTPUT_TD1:
6029 case HRTIM_OUTPUT_TE1:
6030 {
6031 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != (uint32_t)RESET)
6032 {
6033 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
6034 }
6035 else
6036 {
6037 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
6038 }
6039 break;
6040 }
6041
6042 case HRTIM_OUTPUT_TA2:
6043 case HRTIM_OUTPUT_TB2:
6044 case HRTIM_OUTPUT_TC2:
6045 case HRTIM_OUTPUT_TD2:
6046 case HRTIM_OUTPUT_TE2:
6047 {
6048 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != (uint32_t)RESET)
6049 {
6050 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
6051 }
6052 else
6053 {
6054 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
6055 }
6056 break;
6057 }
6058
6059 default:
6060 {
6061 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6062
6063 /* Process Unlocked */
6064 __HAL_UNLOCK(hhrtim);
6065
6066 break;
6067 }
6068 }
6069
6070 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
6071 {
6072 return (uint32_t)HAL_ERROR;
6073 }
6074
6075 return output_level;
6076 }
6077
6078 /**
6079 * @brief Return actual state (RUN, IDLE, FAULT) of the designated output
6080 * @param hhrtim pointer to HAL HRTIM handle
6081 * @param TimerIdx Timer index
6082 * This parameter can be one of the following values:
6083 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6084 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6085 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6086 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6087 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6088 * @param Output Timer output
6089 * This parameter can be one of the following values:
6090 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6091 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6092 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6093 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6094 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6095 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6096 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6097 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6098 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6099 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6100 * @retval Output state
6101 */
6102 uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
6103 uint32_t TimerIdx,
6104 uint32_t Output)
6105 {
6106 uint32_t output_bit = (uint32_t)RESET;
6107 uint32_t output_state;
6108
6109 /* Check parameters */
6110 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6111
6112 /* Set output state according to output control status and output disable status */
6113 switch (Output)
6114 {
6115 case HRTIM_OUTPUT_TA1:
6116 {
6117 output_bit = HRTIM_OENR_TA1OEN;
6118 break;
6119 }
6120
6121 case HRTIM_OUTPUT_TA2:
6122 {
6123 output_bit = HRTIM_OENR_TA2OEN;
6124 break;
6125 }
6126
6127 case HRTIM_OUTPUT_TB1:
6128 {
6129 output_bit = HRTIM_OENR_TB1OEN;
6130 break;
6131 }
6132
6133 case HRTIM_OUTPUT_TB2:
6134 {
6135 output_bit = HRTIM_OENR_TB2OEN;
6136 break;
6137 }
6138
6139 case HRTIM_OUTPUT_TC1:
6140 {
6141 output_bit = HRTIM_OENR_TC1OEN;
6142 break;
6143 }
6144
6145 case HRTIM_OUTPUT_TC2:
6146 {
6147 output_bit = HRTIM_OENR_TC2OEN;
6148 break;
6149 }
6150
6151 case HRTIM_OUTPUT_TD1:
6152 {
6153 output_bit = HRTIM_OENR_TD1OEN;
6154 break;
6155 }
6156
6157 case HRTIM_OUTPUT_TD2:
6158 {
6159 output_bit = HRTIM_OENR_TD2OEN;
6160 break;
6161 }
6162
6163 case HRTIM_OUTPUT_TE1:
6164 {
6165 output_bit = HRTIM_OENR_TE1OEN;
6166 break;
6167 }
6168
6169 case HRTIM_OUTPUT_TE2:
6170 {
6171 output_bit = HRTIM_OENR_TE2OEN;
6172 break;
6173 }
6174
6175 default:
6176 {
6177 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6178
6179 /* Process Unlocked */
6180 __HAL_UNLOCK(hhrtim);
6181
6182 break;
6183 }
6184 }
6185
6186 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
6187 {
6188 return (uint32_t)HAL_ERROR;
6189 }
6190
6191 if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != (uint32_t)RESET)
6192 {
6193 /* Output is enabled: output in RUN state (whatever ouput disable status is)*/
6194 output_state = HRTIM_OUTPUTSTATE_RUN;
6195 }
6196 else
6197 {
6198 if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != (uint32_t)RESET)
6199 {
6200 /* Output is disabled: output in FAULT state */
6201 output_state = HRTIM_OUTPUTSTATE_FAULT;
6202 }
6203 else
6204 {
6205 /* Output is disabled: output in IDLE state */
6206 output_state = HRTIM_OUTPUTSTATE_IDLE;
6207 }
6208 }
6209
6210 return(output_state);
6211 }
6212
6213 /**
6214 * @brief Return the level (active or inactive) of the designated output
6215 * when the delayed protection was triggered.
6216 * @param hhrtim pointer to HAL HRTIM handle
6217 * @param TimerIdx Timer index
6218 * This parameter can be one of the following values:
6219 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6220 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6221 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6222 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6223 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6224 * @param Output Timer output
6225 * This parameter can be one of the following values:
6226 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6227 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6228 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6229 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6230 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6231 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6232 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6233 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6234 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6235 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6236 * @retval Delayed protection status
6237 */
6238 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim,
6239 uint32_t TimerIdx,
6240 uint32_t Output)
6241 {
6242 uint32_t delayed_protection_status = (uint32_t)RESET;
6243
6244 /* Check parameters */
6245 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6246
6247 /* Read the delayed protection status */
6248 switch (Output)
6249 {
6250 case HRTIM_OUTPUT_TA1:
6251 case HRTIM_OUTPUT_TB1:
6252 case HRTIM_OUTPUT_TC1:
6253 case HRTIM_OUTPUT_TD1:
6254 case HRTIM_OUTPUT_TE1:
6255 {
6256 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != (uint32_t)RESET)
6257 {
6258 /* Output 1 was active when the delayed idle protection was triggered */
6259 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
6260 }
6261 else
6262 {
6263 /* Output 1 was inactive when the delayed idle protection was triggered */
6264 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
6265 }
6266 break;
6267 }
6268
6269 case HRTIM_OUTPUT_TA2:
6270 case HRTIM_OUTPUT_TB2:
6271 case HRTIM_OUTPUT_TC2:
6272 case HRTIM_OUTPUT_TD2:
6273 case HRTIM_OUTPUT_TE2:
6274 {
6275 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != (uint32_t)RESET)
6276 {
6277 /* Output 2 was active when the delayed idle protection was triggered */
6278 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
6279 }
6280 else
6281 {
6282 /* Output 2 was inactive when the delayed idle protection was triggered */
6283 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
6284 }
6285 break;
6286 }
6287
6288 default:
6289 {
6290 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6291
6292 /* Process Unlocked */
6293 __HAL_UNLOCK(hhrtim);
6294
6295 break;
6296 }
6297 }
6298
6299 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
6300 {
6301 return (uint32_t)HAL_ERROR;
6302 }
6303
6304 return delayed_protection_status;
6305 }
6306
6307 /**
6308 * @brief Return the actual status (active or inactive) of the burst mode controller
6309 * @param hhrtim pointer to HAL HRTIM handle
6310 * @retval Burst mode controller status
6311 */
6312 uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim)
6313 {
6314 uint32_t burst_mode_status;
6315
6316 /* Read burst mode status */
6317 burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
6318
6319 return burst_mode_status;
6320 }
6321
6322 /**
6323 * @brief Indicate on which output the signal is currently active (when the
6324 * push pull mode is enabled).
6325 * @param hhrtim pointer to HAL HRTIM handle
6326 * @param TimerIdx Timer index
6327 * This parameter can be one of the following values:
6328 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6329 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6330 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6331 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6332 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6333 * @retval Burst mode controller status
6334 */
6335 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim,
6336 uint32_t TimerIdx)
6337 {
6338 uint32_t current_pushpull_status;
6339
6340 /* Check the parameters */
6341 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6342
6343 /* Read current push pull status */
6344 current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
6345
6346 return current_pushpull_status;
6347 }
6348
6349
6350 /**
6351 * @brief Indicate on which output the signal was applied, in push-pull mode,
6352 balanced fault mode or delayed idle mode, when the protection was triggered.
6353 * @param hhrtim pointer to HAL HRTIM handle
6354 * @param TimerIdx Timer index
6355 * This parameter can be one of the following values:
6356 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6357 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6358 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6359 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6360 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6361 * @retval Idle Push Pull Status
6362 */
6363 uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim,
6364 uint32_t TimerIdx)
6365 {
6366 uint32_t idle_pushpull_status;
6367
6368 /* Check the parameters */
6369 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6370
6371 /* Read current push pull status */
6372 idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
6373
6374 return idle_pushpull_status;
6375 }
6376
6377 /**
6378 * @}
6379 */
6380
6381 /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
6382 * @brief Functions called when HRTIM generates an interrupt
6383 * 7 interrupts can be generated by the master timer:
6384 * - Master timer registers update
6385 * - Synchronization event received
6386 * - Master timer repetition event
6387 * - Master Compare 1 to 4 event
6388 * 14 interrupts can be generated by each timing unit:
6389 * - Delayed protection triggered
6390 * - Counter reset or roll-over event
6391 * - Output 1 and output 2 reset (transition active to inactive)
6392 * - Output 1 and output 2 set (transition inactive to active)
6393 * - Capture 1 and 2 events
6394 * - Timing unit registers update
6395 * - Repetition event
6396 * - Compare 1 to 4 event
6397 * 7 global interrupts are generated for the whole HRTIM:
6398 * - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
6399 * - Burst mode period completed
6400 @verbatim
6401 ===============================================================================
6402 ##### HRTIM interrupts handling #####
6403 ===============================================================================
6404 [..]
6405 This subsection provides a set of functions allowing to manage the HRTIM
6406 interrupts:
6407 (+) HRTIM interrupt handler
6408 (+) Callback function called when Fault1 interrupt occurs
6409 (+) Callback function called when Fault2 interrupt occurs
6410 (+) Callback function called when Fault3 interrupt occurs
6411 (+) Callback function called when Fault4 interrupt occurs
6412 (+) Callback function called when Fault5 interrupt occurs
6413 (+) Callback function called when system Fault interrupt occurs
6414 (+) Callback function called when burst mode period interrupt occurs
6415 (+) Callback function called when synchronization input interrupt occurs
6416 (+) Callback function called when a timer register update interrupt occurs
6417 (+) Callback function called when a timer repetition interrupt occurs
6418 (+) Callback function called when a compare 1 match interrupt occurs
6419 (+) Callback function called when a compare 2 match interrupt occurs
6420 (+) Callback function called when a compare 3 match interrupt occurs
6421 (+) Callback function called when a compare 4 match interrupt occurs
6422 (+) Callback function called when a capture 1 interrupt occurs
6423 (+) Callback function called when a capture 2 interrupt occurs
6424 (+) Callback function called when a delayed protection interrupt occurs
6425 (+) Callback function called when a timer counter reset interrupt occurs
6426 (+) Callback function called when a timer output 1 set interrupt occurs
6427 (+) Callback function called when a timer output 1 reset interrupt occurs
6428 (+) Callback function called when a timer output 2 set interrupt occurs
6429 (+) Callback function called when a timer output 2 reset interrupt occurs
6430 (+) Callback function called when a timer output 2 reset interrupt occurs
6431 (+) Callback function called upon completion of a burst DMA transfer
6432 (+) HRTIM callback function registration
6433 (+) HRTIM callback function unregistration
6434 (+) HRTIM Timer x callback function registration
6435 (+) HRTIM Timer x callback function unregistration
6436
6437 @endverbatim
6438 * @{
6439 */
6440
6441 /**
6442 * @brief This function handles HRTIM interrupt request.
6443 * @param hhrtim pointer to HAL HRTIM handle
6444 * @param TimerIdx Timer index
6445 * This parameter can be any value of HRTIM_Timer_Index
6446 * @retval None
6447 */
6448 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
6449 uint32_t TimerIdx)
6450 {
6451 /* HRTIM interrupts handling */
6452 if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
6453 {
6454 HRTIM_HRTIM_ISR(hhrtim);
6455 }
6456 else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
6457 {
6458 /* Master related interrupts handling */
6459 HRTIM_Master_ISR(hhrtim);
6460 }
6461 else
6462 {
6463 /* Timing unit related interrupts handling */
6464 HRTIM_Timer_ISR(hhrtim, TimerIdx);
6465 }
6466
6467 }
6468
6469 /**
6470 * @brief Callback function invoked when a fault 1 interrupt occurred
6471 * @param hhrtim pointer to HAL HRTIM handle * @retval None
6472 * @retval None
6473 */
6474 __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
6475 {
6476 /* Prevent unused argument(s) compilation warning */
6477 UNUSED(hhrtim);
6478
6479 /* NOTE : This function should not be modified, when the callback is needed,
6480 the HAL_HRTIM_Fault1Callback could be implemented in the user file
6481 */
6482 }
6483
6484 /**
6485 * @brief Callback function invoked when a fault 2 interrupt occurred
6486 * @param hhrtim pointer to HAL HRTIM handle
6487 * @retval None
6488 */
6489 __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
6490 {
6491 /* Prevent unused argument(s) compilation warning */
6492 UNUSED(hhrtim);
6493
6494 /* NOTE : This function should not be modified, when the callback is needed,
6495 the HAL_HRTIM_Fault2Callback could be implemented in the user file
6496 */
6497 }
6498
6499 /**
6500 * @brief Callback function invoked when a fault 3 interrupt occurred
6501 * @param hhrtim pointer to HAL HRTIM handle
6502 * @retval None
6503 */
6504 __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
6505 {
6506 /* Prevent unused argument(s) compilation warning */
6507 UNUSED(hhrtim);
6508
6509 /* NOTE : This function should not be modified, when the callback is needed,
6510 the HAL_HRTIM_Fault3Callback could be implemented in the user file
6511 */
6512 }
6513
6514 /**
6515 * @brief Callback function invoked when a fault 4 interrupt occurred
6516 * @param hhrtim pointer to HAL HRTIM handle
6517 * @retval None
6518 */
6519 __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
6520 {
6521 /* Prevent unused argument(s) compilation warning */
6522 UNUSED(hhrtim);
6523
6524 /* NOTE : This function should not be modified, when the callback is needed,
6525 the HAL_HRTIM_Fault4Callback could be implemented in the user file
6526 */
6527 }
6528
6529 /**
6530 * @brief Callback function invoked when a fault 5 interrupt occurred
6531 * @param hhrtim pointer to HAL HRTIM handle
6532 * @retval None
6533 */
6534 __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
6535 {
6536 /* Prevent unused argument(s) compilation warning */
6537 UNUSED(hhrtim);
6538
6539 /* NOTE : This function should not be modified, when the callback is needed,
6540 the HAL_HRTIM_Fault5Callback could be implemented in the user file
6541 */
6542 }
6543
6544 /**
6545 * @brief Callback function invoked when a system fault interrupt occurred
6546 * @param hhrtim pointer to HAL HRTIM handle
6547 * @retval None
6548 */
6549 __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
6550 {
6551 /* Prevent unused argument(s) compilation warning */
6552 UNUSED(hhrtim);
6553
6554 /* NOTE : This function should not be modified, when the callback is needed,
6555 the HAL_HRTIM_SystemFaultCallback could be implemented in the user file
6556 */
6557 }
6558
6559 /**
6560 * @brief Callback function invoked when the end of the burst mode period is reached
6561 * @param hhrtim pointer to HAL HRTIM handle
6562 * @retval None
6563 */
6564 __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
6565 {
6566 /* Prevent unused argument(s) compilation warning */
6567 UNUSED(hhrtim);
6568
6569 /* NOTE : This function should not be modified, when the callback is needed,
6570 the HAL_HRTIM_BurstModeCallback could be implemented in the user file
6571 */
6572 }
6573
6574 /**
6575 * @brief Callback function invoked when a synchronization input event is received
6576 * @param hhrtim pointer to HAL HRTIM handle
6577 * @retval None
6578 */
6579 __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
6580 {
6581 /* Prevent unused argument(s) compilation warning */
6582 UNUSED(hhrtim);
6583
6584 /* NOTE : This function should not be modified, when the callback is needed,
6585 the HAL_HRTIM_SynchronizationEventCallback could be implemented in the user file
6586 */
6587 }
6588
6589 /**
6590 * @brief Callback function invoked when timer registers are updated
6591 * @param hhrtim pointer to HAL HRTIM handle
6592 * @param TimerIdx Timer index
6593 * This parameter can be one of the following values:
6594 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6595 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6596 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6597 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6598 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6599 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6600 * @retval None
6601 */
6602 __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,
6603 uint32_t TimerIdx)
6604 {
6605 /* Prevent unused argument(s) compilation warning */
6606 UNUSED(hhrtim);
6607 UNUSED(TimerIdx);
6608
6609 /* NOTE : This function should not be modified, when the callback is needed,
6610 the HAL_HRTIM_Master_RegistersUpdateCallback could be implemented in the user file
6611 */
6612 }
6613
6614 /**
6615 * @brief Callback function invoked when timer repetition period has elapsed
6616 * @param hhrtim pointer to HAL HRTIM handle
6617 * @param TimerIdx Timer index
6618 * This parameter can be one of the following values:
6619 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6620 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6621 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6622 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6623 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6624 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6625 * @retval None
6626 */
6627 __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,
6628 uint32_t TimerIdx)
6629 {
6630 /* Prevent unused argument(s) compilation warning */
6631 UNUSED(hhrtim);
6632 UNUSED(TimerIdx);
6633
6634 /* NOTE : This function should not be modified, when the callback is needed,
6635 the HAL_HRTIM_Master_RepetitionEventCallback could be implemented in the user file
6636 */
6637 }
6638
6639 /**
6640 * @brief Callback function invoked when the timer counter matches the value
6641 * programmed in the compare 1 register
6642 * @param hhrtim pointer to HAL HRTIM handle
6643 * @param TimerIdx Timer index
6644 * This parameter can be one of the following values:
6645 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6646 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6647 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6648 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6649 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6650 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6651 * @retval None
6652 */
6653 __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,
6654 uint32_t TimerIdx)
6655 {
6656 /* Prevent unused argument(s) compilation warning */
6657 UNUSED(hhrtim);
6658 UNUSED(TimerIdx);
6659
6660 /* NOTE : This function should not be modified, when the callback is needed,
6661 the HAL_HRTIM_Master_Compare1EventCallback could be implemented in the user file
6662 */
6663 }
6664
6665 /**
6666 * @brief Callback function invoked when the timer counter matches the value
6667 * programmed in the compare 2 register
6668 * @param hhrtim pointer to HAL HRTIM handle
6669 * @retval None
6670 * @param TimerIdx Timer index
6671 * This parameter can be one of the following values:
6672 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6673 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6674 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6675 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6676 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6677 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6678 */
6679 __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,
6680 uint32_t TimerIdx)
6681 {
6682 /* Prevent unused argument(s) compilation warning */
6683 UNUSED(hhrtim);
6684 UNUSED(TimerIdx);
6685
6686 /* NOTE : This function should not be modified, when the callback is needed,
6687 the HAL_HRTIM_Master_Compare2EventCallback could be implemented in the user file
6688 */
6689 }
6690
6691 /**
6692 * @brief Callback function invoked when the timer counter matches the value
6693 * programmed in the compare 3 register
6694 * @param hhrtim pointer to HAL HRTIM handle
6695 * @param TimerIdx Timer index
6696 * This parameter can be one of the following values:
6697 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6698 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6699 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6700 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6701 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6702 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6703 * @retval None
6704 */
6705 __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,
6706 uint32_t TimerIdx)
6707 {
6708 /* Prevent unused argument(s) compilation warning */
6709 UNUSED(hhrtim);
6710 UNUSED(TimerIdx);
6711
6712 /* NOTE : This function should not be modified, when the callback is needed,
6713 the HAL_HRTIM_Master_Compare3EventCallback could be implemented in the user file
6714 */
6715 }
6716
6717 /**
6718 * @brief Callback function invoked when the timer counter matches the value
6719 * programmed in the compare 4 register.
6720 * @param hhrtim pointer to HAL HRTIM handle
6721 * @param TimerIdx Timer index
6722 * This parameter can be one of the following values:
6723 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6724 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6725 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6726 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6727 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6728 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6729 * @retval None
6730 */
6731 __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,
6732 uint32_t TimerIdx)
6733 {
6734 /* Prevent unused argument(s) compilation warning */
6735 UNUSED(hhrtim);
6736 UNUSED(TimerIdx);
6737
6738 /* NOTE : This function should not be modified, when the callback is needed,
6739 the HAL_HRTIM_Master_Compare4EventCallback could be implemented in the user file
6740 */
6741 }
6742
6743 /**
6744 * @brief Callback function invoked when the timer x capture 1 event occurs
6745 * @param hhrtim pointer to HAL HRTIM handle
6746 * @param TimerIdx Timer index
6747 * This parameter can be one of the following values:
6748 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6749 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6750 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6751 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6752 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6753 * @retval None
6754 */
6755 __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,
6756 uint32_t TimerIdx)
6757 {
6758 /* Prevent unused argument(s) compilation warning */
6759 UNUSED(hhrtim);
6760 UNUSED(TimerIdx);
6761
6762 /* NOTE : This function should not be modified, when the callback is needed,
6763 the HAL_HRTIM_Timer_Capture1EventCallback could be implemented in the user file
6764 */
6765 }
6766
6767 /**
6768 * @brief Callback function invoked when the timer x capture 2 event occurs
6769 * @param hhrtim pointer to HAL HRTIM handle
6770 * @param TimerIdx Timer index
6771 * This parameter can be one of the following values:
6772 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6773 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6774 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6775 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6776 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6777 * @retval None
6778 */
6779 __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,
6780 uint32_t TimerIdx)
6781 {
6782 /* Prevent unused argument(s) compilation warning */
6783 UNUSED(hhrtim);
6784 UNUSED(TimerIdx);
6785
6786 /* NOTE : This function should not be modified, when the callback is needed,
6787 the HAL_HRTIM_Timer_Capture2EventCallback could be implemented in the user file
6788 */
6789 }
6790
6791 /**
6792 * @brief Callback function invoked when the delayed idle or balanced idle mode is
6793 * entered.
6794 * @param hhrtim pointer to HAL HRTIM handle
6795 * @param TimerIdx Timer index
6796 * This parameter can be one of the following values:
6797 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6798 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6799 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6800 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6801 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6802 * @retval None
6803 */
6804 __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,
6805 uint32_t TimerIdx)
6806 {
6807 /* Prevent unused argument(s) compilation warning */
6808 UNUSED(hhrtim);
6809 UNUSED(TimerIdx);
6810
6811 /* NOTE : This function should not be modified, when the callback is needed,
6812 the HAL_HRTIM_Timer_DelayedProtectionCallback could be implemented in the user file
6813 */
6814 }
6815
6816 /**
6817 * @brief Callback function invoked when the timer x counter reset/roll-over
6818 * event occurs.
6819 * @param hhrtim pointer to HAL HRTIM handle
6820 * @param TimerIdx Timer index
6821 * This parameter can be one of the following values:
6822 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6823 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6824 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6825 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6826 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6827 * @retval None
6828 */
6829 __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,
6830 uint32_t TimerIdx)
6831 {
6832 /* Prevent unused argument(s) compilation warning */
6833 UNUSED(hhrtim);
6834 UNUSED(TimerIdx);
6835
6836 /* NOTE : This function should not be modified, when the callback is needed,
6837 the HAL_HRTIM_Timer_CounterResetCallback could be implemented in the user file
6838 */
6839 }
6840
6841 /**
6842 * @brief Callback function invoked when the timer x output 1 is set
6843 * @param hhrtim pointer to HAL HRTIM handle
6844 * @param TimerIdx Timer index
6845 * This parameter can be one of the following values:
6846 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6847 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6848 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6849 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6850 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6851 * @retval None
6852 */
6853 __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,
6854 uint32_t TimerIdx)
6855 {
6856 /* Prevent unused argument(s) compilation warning */
6857 UNUSED(hhrtim);
6858 UNUSED(TimerIdx);
6859
6860 /* NOTE : This function should not be modified, when the callback is needed,
6861 the HAL_HRTIM_Timer_Output1SetCallback could be implemented in the user file
6862 */
6863 }
6864
6865 /**
6866 * @brief Callback function invoked when the timer x output 1 is reset
6867 * @param hhrtim pointer to HAL HRTIM handle
6868 * @param TimerIdx Timer index
6869 * This parameter can be one of the following values:
6870 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6871 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6872 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6873 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6874 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6875 * @retval None
6876 */
6877 __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,
6878 uint32_t TimerIdx)
6879 {
6880 /* Prevent unused argument(s) compilation warning */
6881 UNUSED(hhrtim);
6882 UNUSED(TimerIdx);
6883
6884 /* NOTE : This function should not be modified, when the callback is needed,
6885 the HAL_HRTIM_Timer_Output1ResetCallback could be implemented in the user file
6886 */
6887 }
6888
6889 /**
6890 * @brief Callback function invoked when the timer x output 2 is set
6891 * @param hhrtim pointer to HAL HRTIM handle
6892 * @param TimerIdx Timer index
6893 * This parameter can be one of the following values:
6894 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6895 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6896 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6897 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6898 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6899 * @retval None
6900 */
6901 __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,
6902 uint32_t TimerIdx)
6903 {
6904 /* Prevent unused argument(s) compilation warning */
6905 UNUSED(hhrtim);
6906 UNUSED(TimerIdx);
6907
6908 /* NOTE : This function should not be modified, when the callback is needed,
6909 the HAL_HRTIM_Timer_Output2SetCallback could be implemented in the user file
6910 */
6911 }
6912
6913 /**
6914 * @brief Callback function invoked when the timer x output 2 is reset
6915 * @param hhrtim pointer to HAL HRTIM handle
6916 * @param TimerIdx Timer index
6917 * This parameter can be one of the following values:
6918 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6919 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6920 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6921 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6922 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6923 * @retval None
6924 */
6925 __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,
6926 uint32_t TimerIdx)
6927 {
6928 /* Prevent unused argument(s) compilation warning */
6929 UNUSED(hhrtim);
6930 UNUSED(TimerIdx);
6931
6932 /* NOTE : This function should not be modified, when the callback is needed,
6933 the HAL_HRTIM_Timer_Output2ResetCallback could be implemented in the user file
6934 */
6935 }
6936
6937 /**
6938 * @brief Callback function invoked when a DMA burst transfer is completed
6939 * @param hhrtim pointer to HAL HRTIM handle
6940 * @param TimerIdx Timer index
6941 * This parameter can be one of the following values:
6942 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6943 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6944 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6945 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6946 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6947 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6948 * @retval None
6949 */
6950 __weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,
6951 uint32_t TimerIdx)
6952 {
6953 /* Prevent unused argument(s) compilation warning */
6954 UNUSED(hhrtim);
6955 UNUSED(TimerIdx);
6956
6957 /* NOTE : This function should not be modified, when the callback is needed,
6958 the HAL_HRTIM_BurstDMATransferCallback could be implemented in the user file
6959 */
6960 }
6961
6962 /**
6963 * @brief Callback function invoked when a DMA error occurs
6964 * @param hhrtim pointer to HAL HRTIM handle
6965 * @retval None
6966 */
6967 __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
6968 {
6969 /* Prevent unused argument(s) compilation warning */
6970 UNUSED(hhrtim);
6971
6972 /* NOTE : This function should not be modified, when the callback is needed,
6973 the HAL_HRTIM_ErrorCallback could be implemented in the user file
6974 */
6975 }
6976
6977 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
6978 /**
6979 * @brief HRTIM callback function registration
6980 * @param hhrtim pointer to HAL HRTIM handle
6981 * @param CallbackID ID of the HRTIM callback function to register
6982 * This parameter can be one of the following values:
6983 * @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
6984 * @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
6985 * @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
6986 * @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
6987 * @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
6988 * @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
6989 * @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
6990 * @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
6991 * @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
6992 * @arg HAL_HRTIM_MSPINIT_CB_ID
6993 * @arg HAL_HRTIM_MSPDEINIT_CB_ID
6994 * @param pCallback Callback function pointer
6995 * @retval HAL status
6996 */
6997 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim,
6998 HAL_HRTIM_CallbackIDTypeDef CallbackID,
6999 pHRTIM_CallbackTypeDef pCallback)
7000 {
7001 HAL_StatusTypeDef status = HAL_OK;
7002
7003 if (pCallback == NULL)
7004 {
7005 /* Update the state */
7006 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7007
7008 return HAL_ERROR;
7009 }
7010
7011 /* Process locked */
7012 __HAL_LOCK(hhrtim);
7013
7014 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7015 {
7016 switch (CallbackID)
7017 {
7018 case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
7019 hhrtim->Fault1Callback = pCallback;
7020 break;
7021
7022 case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
7023 hhrtim->Fault2Callback = pCallback;
7024 break;
7025
7026 case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
7027 hhrtim->Fault3Callback = pCallback;
7028 break;
7029
7030 case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
7031 hhrtim->Fault4Callback = pCallback;
7032 break;
7033
7034 case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
7035 hhrtim->Fault5Callback = pCallback;
7036 break;
7037
7038 case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
7039 hhrtim->SystemFaultCallback = pCallback;
7040 break;
7041
7042
7043 case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
7044 hhrtim->BurstModePeriodCallback = pCallback;
7045 break;
7046
7047 case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
7048 hhrtim->SynchronizationEventCallback = pCallback;
7049 break;
7050
7051 case HAL_HRTIM_ERRORCALLBACK_CB_ID :
7052 hhrtim->ErrorCallback = pCallback;
7053 break;
7054
7055 case HAL_HRTIM_MSPINIT_CB_ID :
7056 hhrtim->MspInitCallback = pCallback;
7057 break;
7058
7059 case HAL_HRTIM_MSPDEINIT_CB_ID :
7060 hhrtim->MspDeInitCallback = pCallback;
7061 break;
7062
7063 default :
7064 /* Update the state */
7065 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7066
7067 /* Return error status */
7068 status = HAL_ERROR;
7069 break;
7070 }
7071 }
7072 else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
7073 {
7074 switch (CallbackID)
7075 {
7076 case HAL_HRTIM_MSPINIT_CB_ID :
7077 hhrtim->MspInitCallback = pCallback;
7078 break;
7079
7080 case HAL_HRTIM_MSPDEINIT_CB_ID :
7081 hhrtim->MspDeInitCallback = pCallback;
7082 break;
7083
7084 default :
7085 /* Update the state */
7086 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7087
7088 /* Return error status */
7089 status = HAL_ERROR;
7090 break;
7091 }
7092 }
7093 else
7094 {
7095 /* Update the state */
7096 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7097
7098 /* Return error status */
7099 status = HAL_ERROR;
7100 }
7101
7102 /* Release Lock */
7103 __HAL_UNLOCK(hhrtim);
7104
7105 return status;
7106 }
7107
7108 /**
7109 * @brief HRTIM callback function un-registration
7110 * @param hhrtim pointer to HAL HRTIM handle
7111 * @param CallbackID ID of the HRTIM callback function to unregister
7112 * This parameter can be one of the following values:
7113 * @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
7114 * @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
7115 * @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
7116 * @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
7117 * @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
7118 * @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
7119 * @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
7120 * @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
7121 * @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
7122 * @arg HAL_HRTIM_MSPINIT_CB_ID
7123 * @arg HAL_HRTIM_MSPDEINIT_CB_ID
7124 * @retval HAL status
7125 */
7126 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
7127 HAL_HRTIM_CallbackIDTypeDef CallbackID)
7128 {
7129 HAL_StatusTypeDef status = HAL_OK;
7130
7131 /* Process locked */
7132 __HAL_LOCK(hhrtim);
7133
7134 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7135 {
7136 switch (CallbackID)
7137 {
7138 case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
7139 hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
7140 break;
7141
7142 case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
7143 hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
7144 break;
7145
7146 case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
7147 hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
7148 break;
7149
7150 case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
7151 hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
7152 break;
7153
7154 case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
7155 hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
7156 break;
7157
7158 case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
7159 hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
7160 break;
7161
7162
7163 case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
7164 hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
7165 break;
7166
7167 case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
7168 hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
7169 break;
7170
7171 case HAL_HRTIM_ERRORCALLBACK_CB_ID :
7172 hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
7173 break;
7174
7175 case HAL_HRTIM_MSPINIT_CB_ID :
7176 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
7177 break;
7178
7179 case HAL_HRTIM_MSPDEINIT_CB_ID :
7180 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
7181 break;
7182
7183 default :
7184 /* Update the state */
7185 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7186
7187 /* Return error status */
7188 status = HAL_ERROR;
7189 break;
7190 }
7191 }
7192 else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
7193 {
7194 switch (CallbackID)
7195 {
7196 case HAL_HRTIM_MSPINIT_CB_ID :
7197 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
7198 break;
7199
7200 case HAL_HRTIM_MSPDEINIT_CB_ID :
7201 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
7202 break;
7203
7204 default :
7205 /* Update the state */
7206 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7207
7208 /* Return error status */
7209 status = HAL_ERROR;
7210 break;
7211 }
7212 }
7213 else
7214 {
7215 /* Update the state */
7216 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7217
7218 /* Return error status */
7219 status = HAL_ERROR;
7220 }
7221
7222 /* Release Lock */
7223 __HAL_UNLOCK(hhrtim);
7224
7225 return status;
7226 }
7227
7228 /**
7229 * @brief HRTIM Timer x callback function registration
7230 * @param hhrtim pointer to HAL HRTIM handle
7231 * @param CallbackID ID of the HRTIM Timer x callback function to register
7232 * This parameter can be one of the following values:
7233 * @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
7234 * @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
7235 * @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
7236 * @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
7237 * @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
7238 * @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
7239 * @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
7240 * @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
7241 * @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
7242 * @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
7243 * @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
7244 * @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
7245 * @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
7246 * @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
7247 * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
7248 * @param pCallback Callback function pointer
7249 * @retval HAL status
7250 */
7251 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
7252 HAL_HRTIM_CallbackIDTypeDef CallbackID,
7253 pHRTIM_TIMxCallbackTypeDef pCallback)
7254 {
7255 HAL_StatusTypeDef status = HAL_OK;
7256
7257 if (pCallback == NULL)
7258 {
7259 /* Update the state */
7260 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7261
7262 return HAL_ERROR;
7263 }
7264
7265 /* Process locked */
7266 __HAL_LOCK(hhrtim);
7267
7268 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7269 {
7270 switch (CallbackID)
7271 {
7272 case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
7273 hhrtim->RegistersUpdateCallback = pCallback;
7274 break;
7275
7276 case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
7277 hhrtim->RepetitionEventCallback = pCallback;
7278 break;
7279
7280 case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
7281 hhrtim->Compare1EventCallback = pCallback;
7282 break;
7283
7284 case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
7285 hhrtim->Compare2EventCallback = pCallback;
7286 break;
7287
7288 case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
7289 hhrtim->Compare3EventCallback = pCallback;
7290 break;
7291
7292 case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
7293 hhrtim->Compare4EventCallback = pCallback;
7294 break;
7295
7296 case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
7297 hhrtim->Capture1EventCallback = pCallback;
7298 break;
7299
7300 case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
7301 hhrtim->Capture2EventCallback = pCallback;
7302 break;
7303
7304 case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
7305 hhrtim->DelayedProtectionCallback = pCallback;
7306 break;
7307
7308 case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
7309 hhrtim->CounterResetCallback = pCallback;
7310 break;
7311
7312 case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
7313 hhrtim->Output1SetCallback = pCallback;
7314 break;
7315
7316 case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
7317 hhrtim->Output1ResetCallback = pCallback;
7318 break;
7319
7320 case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
7321 hhrtim->Output2SetCallback = pCallback;
7322 break;
7323
7324 case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
7325 hhrtim->Output2ResetCallback = pCallback;
7326 break;
7327
7328 case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
7329 hhrtim->BurstDMATransferCallback = pCallback;
7330 break;
7331
7332 default :
7333 /* Update the state */
7334 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7335
7336 /* Return error status */
7337 status = HAL_ERROR;
7338 break;
7339 }
7340 }
7341 else
7342 {
7343 /* Update the state */
7344 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7345
7346 /* Return error status */
7347 status = HAL_ERROR;
7348 }
7349
7350 /* Release Lock */
7351 __HAL_UNLOCK(hhrtim);
7352
7353 return status;
7354 }
7355
7356 /**
7357 * @brief HRTIM Timer x callback function un-registration
7358 * @param hhrtim pointer to HAL HRTIM handle
7359 * @param CallbackID ID of the HRTIM callback Timer x function to unregister
7360 * This parameter can be one of the following values:
7361 * @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
7362 * @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
7363 * @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
7364 * @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
7365 * @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
7366 * @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
7367 * @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
7368 * @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
7369 * @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
7370 * @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
7371 * @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
7372 * @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
7373 * @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
7374 * @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
7375 * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
7376 * @retval HAL status
7377 */
7378 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
7379 HAL_HRTIM_CallbackIDTypeDef CallbackID)
7380 {
7381 HAL_StatusTypeDef status = HAL_OK;
7382
7383 /* Process locked */
7384 __HAL_LOCK(hhrtim);
7385
7386 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7387 {
7388 switch (CallbackID)
7389 {
7390 case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
7391 hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
7392 break;
7393
7394 case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
7395 hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
7396 break;
7397
7398 case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
7399 hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
7400 break;
7401
7402 case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
7403 hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
7404 break;
7405
7406 case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
7407 hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
7408 break;
7409
7410 case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
7411 hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
7412 break;
7413
7414 case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
7415 hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
7416 break;
7417
7418 case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
7419 hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
7420 break;
7421
7422 case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
7423 hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
7424 break;
7425
7426 case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
7427 hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
7428 break;
7429
7430 case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
7431 hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
7432 break;
7433
7434 case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
7435 hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
7436 break;
7437
7438 case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
7439 hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
7440 break;
7441
7442 case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
7443 hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
7444 break;
7445
7446 case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
7447 hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
7448 break;
7449
7450 default :
7451 /* Update the state */
7452 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7453
7454 /* Return error status */
7455 status = HAL_ERROR;
7456 break;
7457 }
7458 }
7459 else
7460 {
7461 /* Update the state */
7462 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7463
7464 /* Return error status */
7465 status = HAL_ERROR;
7466 }
7467
7468 /* Release Lock */
7469 __HAL_UNLOCK(hhrtim);
7470
7471 return status;
7472 }
7473 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
7474 /**
7475 * @}
7476 */
7477
7478 /**
7479 * @}
7480 */
7481
7482 /** @addtogroup HRTIM_Private_Functions
7483 * @{
7484 */
7485
7486 /**
7487 * @brief Configure the master timer time base
7488 * @param hhrtim pointer to HAL HRTIM handle
7489 * @param pTimeBaseCfg pointer to the time base configuration structure
7490 * @retval None
7491 */
7492 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
7493 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
7494 {
7495 uint32_t hrtim_mcr;
7496
7497 /* Configure master timer */
7498 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
7499
7500 /* Set the prescaler ratio */
7501 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
7502 hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
7503
7504 /* Set the operating mode */
7505 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
7506 hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
7507
7508 /* Update the HRTIM registers */
7509 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
7510 hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
7511 hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
7512 }
7513
7514 /**
7515 * @brief Configure timing unit (Timer A to Timer E) time base
7516 * @param hhrtim pointer to HAL HRTIM handle
7517 * @param TimerIdx Timer index
7518 * @param pTimeBaseCfg pointer to the time base configuration structure
7519 * @retval None
7520 */
7521 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
7522 uint32_t TimerIdx ,
7523 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
7524 {
7525 uint32_t hrtim_timcr;
7526
7527 /* Configure master timing unit */
7528 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
7529
7530 /* Set the prescaler ratio */
7531 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
7532 hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
7533
7534 /* Set the operating mode */
7535 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
7536 hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
7537
7538 /* Update the HRTIM registers */
7539 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
7540 hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
7541 hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
7542 }
7543
7544 /**
7545 * @brief Configure the master timer in waveform mode
7546 * @param hhrtim pointer to HAL HRTIM handle
7547 * @param pTimerCfg pointer to the timer configuration data structure
7548 * @retval None
7549 */
7550 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
7551 HRTIM_TimerCfgTypeDef * pTimerCfg)
7552 {
7553 uint32_t hrtim_mcr;
7554 uint32_t hrtim_bmcr;
7555
7556 /* Configure master timer */
7557 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
7558 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
7559
7560 /* Enable/Disable the half mode */
7561 hrtim_mcr &= ~(HRTIM_MCR_HALF);
7562 hrtim_mcr |= pTimerCfg->HalfModeEnable;
7563
7564 /* Enable/Disable the timer start upon synchronization event reception */
7565 hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
7566 hrtim_mcr |= pTimerCfg->StartOnSync;
7567
7568 /* Enable/Disable the timer reset upon synchronization event reception */
7569 hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
7570 hrtim_mcr |= pTimerCfg->ResetOnSync;
7571
7572 /* Enable/Disable the DAC synchronization event generation */
7573 hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
7574 hrtim_mcr |= pTimerCfg->DACSynchro;
7575
7576 /* Enable/Disable preload meachanism for timer registers */
7577 hrtim_mcr &= ~(HRTIM_MCR_PREEN);
7578 hrtim_mcr |= pTimerCfg->PreloadEnable;
7579
7580 /* Master timer registers update handling */
7581 hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
7582 hrtim_mcr |= (pTimerCfg->UpdateGating << 2U);
7583
7584 /* Enable/Disable registers update on repetition */
7585 hrtim_mcr &= ~(HRTIM_MCR_MREPU);
7586 hrtim_mcr |= pTimerCfg->RepetitionUpdate;
7587
7588 /* Set the timer burst mode */
7589 hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
7590 hrtim_bmcr |= pTimerCfg->BurstMode;
7591
7592 /* Update the HRTIM registers */
7593 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
7594 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
7595 }
7596
7597 /**
7598 * @brief Configure timing unit (Timer A to Timer E) in waveform mode
7599 * @param hhrtim pointer to HAL HRTIM handle
7600 * @param TimerIdx Timer index
7601 * @param pTimerCfg pointer to the timer configuration data structure
7602 * @retval None
7603 */
7604 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
7605 uint32_t TimerIdx,
7606 HRTIM_TimerCfgTypeDef * pTimerCfg)
7607 {
7608 uint32_t hrtim_timcr;
7609 uint32_t hrtim_timfltr;
7610 uint32_t hrtim_timoutr;
7611 uint32_t hrtim_timrstr;
7612 uint32_t hrtim_bmcr;
7613
7614 /* UPDGAT bitfield must be reset before programming a new value */
7615 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
7616
7617 /* Configure timing unit (Timer A to Timer E) */
7618 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
7619 hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
7620 hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
7621 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
7622
7623 /* Enable/Disable the half mode */
7624 hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
7625 hrtim_timcr |= pTimerCfg->HalfModeEnable;
7626
7627 /* Enable/Disable the timer start upon synchronization event reception */
7628 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
7629 hrtim_timcr |= pTimerCfg->StartOnSync;
7630
7631 /* Enable/Disable the timer reset upon synchronization event reception */
7632 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
7633 hrtim_timcr |= pTimerCfg->ResetOnSync;
7634
7635 /* Enable/Disable the DAC synchronization event generation */
7636 hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
7637 hrtim_timcr |= pTimerCfg->DACSynchro;
7638
7639 /* Enable/Disable preload meachanism for timer registers */
7640 hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
7641 hrtim_timcr |= pTimerCfg->PreloadEnable;
7642
7643 /* Timing unit registers update handling */
7644 hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
7645 hrtim_timcr |= pTimerCfg->UpdateGating;
7646
7647 /* Enable/Disable registers update on repetition */
7648 hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
7649 if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
7650 {
7651 hrtim_timcr |= HRTIM_TIMCR_TREPU;
7652 }
7653
7654 /* Set the push-pull mode */
7655 hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
7656 hrtim_timcr |= pTimerCfg->PushPull;
7657
7658 /* Enable/Disable registers update on timer counter reset */
7659 hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
7660 hrtim_timcr |= pTimerCfg->ResetUpdate;
7661
7662 /* Set the timer update trigger */
7663 hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
7664 hrtim_timcr |= pTimerCfg->UpdateTrigger;
7665
7666 /* Enable/Disable the fault channel at timer level */
7667 hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
7668 hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
7669
7670 /* Lock/Unlock fault sources at timer level */
7671 hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
7672 hrtim_timfltr |= pTimerCfg->FaultLock;
7673
7674 /* The deadtime cannot be used simultaneously with the push-pull mode */
7675 if (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_DISABLED)
7676 {
7677 /* Enable/Disable dead time insertion at timer level */
7678 hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
7679 hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
7680 }
7681
7682 /* Enable/Disable delayed protection at timer level
7683 Delayed Idle is available whatever the timer operating mode (regular, push-pull)
7684 Balanced Idle is only available in push-pull mode
7685 */
7686 if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
7687 && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
7688 || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
7689 {
7690 hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
7691 hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
7692 }
7693
7694 /* Set the timer counter reset trigger */
7695 hrtim_timrstr = pTimerCfg->ResetTrigger;
7696
7697 /* Set the timer burst mode */
7698 switch (TimerIdx)
7699 {
7700 case HRTIM_TIMERINDEX_TIMER_A:
7701 {
7702 hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
7703 hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U);
7704 break;
7705 }
7706
7707 case HRTIM_TIMERINDEX_TIMER_B:
7708 {
7709 hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
7710 hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U);
7711 break;
7712 }
7713
7714 case HRTIM_TIMERINDEX_TIMER_C:
7715 {
7716 hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
7717 hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U);
7718 break;
7719 }
7720
7721 case HRTIM_TIMERINDEX_TIMER_D:
7722 {
7723 hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
7724 hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U);
7725 break;
7726 }
7727
7728 case HRTIM_TIMERINDEX_TIMER_E:
7729 {
7730 hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
7731 hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U);
7732 break;
7733 }
7734
7735 default:
7736 break;
7737 }
7738
7739 /* Update the HRTIM registers */
7740 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
7741 hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
7742 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
7743 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
7744 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
7745 }
7746
7747 /**
7748 * @brief Configure a capture unit
7749 * @param hhrtim pointer to HAL HRTIM handle
7750 * @param TimerIdx Timer index
7751 * @param CaptureUnit Capture unit identifier
7752 * @param Event Event reference
7753 * @retval None
7754 */
7755 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
7756 uint32_t TimerIdx,
7757 uint32_t CaptureUnit,
7758 uint32_t Event)
7759 {
7760 uint32_t CaptureTrigger = 0xFFFFFFFFU;
7761
7762 switch (Event)
7763 {
7764 case HRTIM_EVENT_1:
7765 {
7766 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
7767 break;
7768 }
7769
7770 case HRTIM_EVENT_2:
7771 {
7772 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
7773 break;
7774 }
7775
7776 case HRTIM_EVENT_3:
7777 {
7778 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
7779 break;
7780 }
7781
7782 case HRTIM_EVENT_4:
7783 {
7784 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
7785 break;
7786 }
7787
7788 case HRTIM_EVENT_5:
7789 {
7790 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
7791 break;
7792 }
7793
7794 case HRTIM_EVENT_6:
7795 {
7796 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
7797 break;
7798 }
7799
7800 case HRTIM_EVENT_7:
7801 {
7802 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
7803 break;
7804 }
7805
7806 case HRTIM_EVENT_8:
7807 {
7808 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
7809 break;
7810 }
7811
7812 case HRTIM_EVENT_9:
7813 {
7814 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
7815 break;
7816 }
7817
7818 case HRTIM_EVENT_10:
7819 {
7820 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
7821 break;
7822 }
7823
7824 default:
7825 break;
7826 }
7827
7828 switch (CaptureUnit)
7829 {
7830 case HRTIM_CAPTUREUNIT_1:
7831 {
7832 hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
7833 break;
7834 }
7835
7836 case HRTIM_CAPTUREUNIT_2:
7837 {
7838 hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
7839 break;
7840 }
7841
7842 default:
7843 break;
7844 }
7845 }
7846
7847 /**
7848 * @brief Configure the output of a timing unit
7849 * @param hhrtim pointer to HAL HRTIM handle
7850 * @param TimerIdx Timer index
7851 * @param Output timing unit output identifier
7852 * @param pOutputCfg pointer to the output configuration data structure
7853 * @retval None
7854 */
7855 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
7856 uint32_t TimerIdx,
7857 uint32_t Output,
7858 HRTIM_OutputCfgTypeDef * pOutputCfg)
7859 {
7860 uint32_t hrtim_outr;
7861 uint32_t hrtim_dtr;
7862
7863 uint32_t shift = 0U;
7864
7865 hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
7866 hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
7867
7868 switch (Output)
7869 {
7870 case HRTIM_OUTPUT_TA1:
7871 case HRTIM_OUTPUT_TB1:
7872 case HRTIM_OUTPUT_TC1:
7873 case HRTIM_OUTPUT_TD1:
7874 case HRTIM_OUTPUT_TE1:
7875 {
7876 /* Set the output set/reset crossbar */
7877 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
7878 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
7879 break;
7880 }
7881
7882 case HRTIM_OUTPUT_TA2:
7883 case HRTIM_OUTPUT_TB2:
7884 case HRTIM_OUTPUT_TC2:
7885 case HRTIM_OUTPUT_TD2:
7886 case HRTIM_OUTPUT_TE2:
7887 {
7888 /* Set the output set/reset crossbar */
7889 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
7890 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
7891 shift = 16U;
7892 break;
7893 }
7894
7895 default:
7896 break;
7897 }
7898
7899 /* Clear output config */
7900 hrtim_outr &= ~((HRTIM_OUTR_POL1 |
7901 HRTIM_OUTR_IDLM1 |
7902 HRTIM_OUTR_IDLES1|
7903 HRTIM_OUTR_FAULT1|
7904 HRTIM_OUTR_CHP1 |
7905 HRTIM_OUTR_DIDL1) << shift);
7906
7907 /* Set the polarity */
7908 hrtim_outr |= (pOutputCfg->Polarity << shift);
7909
7910 /* Set the IDLE mode */
7911 hrtim_outr |= (pOutputCfg->IdleMode << shift);
7912
7913 /* Set the IDLE state */
7914 hrtim_outr |= (pOutputCfg->IdleLevel << shift);
7915
7916 /* Set the FAULT state */
7917 hrtim_outr |= (pOutputCfg->FaultLevel << shift);
7918
7919 /* Set the chopper mode */
7920 hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
7921
7922 /* Set the burst mode entry mode : deadtime insertion when entering the idle
7923 state during a burst mode operation is allowed only under the following
7924 conditions:
7925 - the outputs is active during the burst mode (IDLES=1U)
7926 - positive deadtimes (SDTR/SDTF set to 0U)
7927 */
7928 if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
7929 ((hrtim_dtr & HRTIM_DTR_SDTR) == (uint32_t)RESET) &&
7930 ((hrtim_dtr & HRTIM_DTR_SDTF) == (uint32_t)RESET))
7931 {
7932 hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
7933 }
7934
7935 /* Update HRTIM register */
7936 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
7937 }
7938
7939 /**
7940 * @brief Configure an external event channel
7941 * @param hhrtim pointer to HAL HRTIM handle
7942 * @param Event Event channel identifier
7943 * @param pEventCfg pointer to the event channel configuration data structure
7944 * @retval None
7945 */
7946 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
7947 uint32_t Event,
7948 HRTIM_EventCfgTypeDef *pEventCfg)
7949 {
7950 uint32_t hrtim_eecr1;
7951 uint32_t hrtim_eecr2;
7952 uint32_t hrtim_eecr3;
7953
7954 /* Configure external event channel */
7955 hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
7956 hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
7957 hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
7958
7959 switch (Event)
7960 {
7961 case HRTIM_EVENT_NONE:
7962 {
7963 /* Update the HRTIM registers */
7964 hhrtim->Instance->sCommonRegs.EECR1 = 0U;
7965 hhrtim->Instance->sCommonRegs.EECR2 = 0U;
7966 hhrtim->Instance->sCommonRegs.EECR3 = 0U;
7967 break;
7968 }
7969
7970 case HRTIM_EVENT_1:
7971 {
7972 hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
7973 hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC);
7974 hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
7975 hrtim_eecr1 |= (pEventCfg->Sensitivity & HRTIM_EECR1_EE1SNS);
7976 /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
7977 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7978 /* Update the HRTIM registers (EE1FAST bit) */
7979 hrtim_eecr1 |= (pEventCfg->FastMode & HRTIM_EECR1_EE1FAST);
7980 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7981 break;
7982 }
7983
7984 case HRTIM_EVENT_2:
7985 {
7986 hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
7987 hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC);
7988 hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR1_EE2POL);
7989 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR1_EE2SNS);
7990 /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
7991 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7992 /* Update the HRTIM registers (EE2FAST bit) */
7993 hrtim_eecr1 |= ((pEventCfg->FastMode << 6U) & HRTIM_EECR1_EE2FAST);
7994 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7995 break;
7996 }
7997
7998 case HRTIM_EVENT_3:
7999 {
8000 hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
8001 hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC);
8002 hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR1_EE3POL);
8003 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR1_EE3SNS);
8004 /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
8005 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8006 /* Update the HRTIM registers (EE3FAST bit) */
8007 hrtim_eecr1 |= ((pEventCfg->FastMode << 12U) & HRTIM_EECR1_EE3FAST);
8008 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8009 break;
8010 }
8011
8012 case HRTIM_EVENT_4:
8013 {
8014 hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
8015 hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC);
8016 hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR1_EE4POL);
8017 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR1_EE4SNS);
8018 /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
8019 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8020 /* Update the HRTIM registers (EE4FAST bit) */
8021 hrtim_eecr1 |= ((pEventCfg->FastMode << 18U) & HRTIM_EECR1_EE4FAST);
8022 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8023 break;
8024 }
8025
8026 case HRTIM_EVENT_5:
8027 {
8028 hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
8029 hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC);
8030 hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR1_EE5POL);
8031 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR1_EE5SNS);
8032 /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
8033 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8034 /* Update the HRTIM registers (EE5FAST bit) */
8035 hrtim_eecr1 |= ((pEventCfg->FastMode << 24U) & HRTIM_EECR1_EE5FAST);
8036 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8037 break;
8038 }
8039
8040 case HRTIM_EVENT_6:
8041 {
8042 hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
8043 hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC);
8044 hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
8045 hrtim_eecr2 |= (pEventCfg->Sensitivity & HRTIM_EECR2_EE6SNS);
8046 hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
8047 hrtim_eecr3 |= (pEventCfg->Filter & HRTIM_EECR3_EE6F);
8048 /* Update the HRTIM registers */
8049 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8050 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8051 break;
8052 }
8053
8054 case HRTIM_EVENT_7:
8055 {
8056 hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
8057 hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC);
8058 hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR2_EE7POL);
8059 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR2_EE7SNS);
8060 hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
8061 hrtim_eecr3 |= ((pEventCfg->Filter << 6U) & HRTIM_EECR3_EE7F);
8062 /* Update the HRTIM registers */
8063 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8064 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8065 break;
8066 }
8067
8068 case HRTIM_EVENT_8:
8069 {
8070 hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
8071 hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC);
8072 hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL);
8073 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS);
8074 hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
8075 hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F );
8076 /* Update the HRTIM registers */
8077 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8078 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8079 break;
8080 }
8081
8082 case HRTIM_EVENT_9:
8083 {
8084 hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
8085 hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC);
8086 hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR2_EE9POL);
8087 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR2_EE9SNS);
8088 hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
8089 hrtim_eecr3 |= ((pEventCfg->Filter << 18U) & HRTIM_EECR3_EE9F);
8090 /* Update the HRTIM registers */
8091 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8092 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8093 break;
8094 }
8095
8096 case HRTIM_EVENT_10:
8097 {
8098 hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
8099 hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC);
8100 hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR2_EE10POL);
8101 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR2_EE10SNS);
8102 hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
8103 hrtim_eecr3 |= ((pEventCfg->Filter << 24U) & HRTIM_EECR3_EE10F);
8104 /* Update the HRTIM registers */
8105 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8106 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8107 break;
8108 }
8109
8110 default:
8111 break;
8112 }
8113 }
8114
8115 /**
8116 * @brief Configure the timer counter reset
8117 * @param hhrtim pointer to HAL HRTIM handle
8118 * @param TimerIdx Timer index
8119 * @param Event Event channel identifier
8120 * @retval None
8121 */
8122 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
8123 uint32_t TimerIdx,
8124 uint32_t Event)
8125 {
8126 switch (Event)
8127 {
8128 case HRTIM_EVENT_1:
8129 {
8130 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
8131 break;
8132 }
8133
8134 case HRTIM_EVENT_2:
8135 {
8136 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
8137 break;
8138 }
8139
8140 case HRTIM_EVENT_3:
8141 {
8142 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
8143 break;
8144 }
8145
8146 case HRTIM_EVENT_4:
8147 {
8148 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
8149 break;
8150 }
8151
8152 case HRTIM_EVENT_5:
8153 {
8154 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
8155 break;
8156 }
8157
8158 case HRTIM_EVENT_6:
8159 {
8160 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
8161 break;
8162 }
8163
8164 case HRTIM_EVENT_7:
8165 {
8166 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
8167 break;
8168 }
8169
8170 case HRTIM_EVENT_8:
8171 {
8172 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
8173 break;
8174 }
8175
8176 case HRTIM_EVENT_9:
8177 {
8178 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
8179 break;
8180 }
8181
8182 case HRTIM_EVENT_10:
8183 {
8184 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
8185 break;
8186 }
8187
8188 default:
8189 break;
8190 }
8191 }
8192
8193 /**
8194 * @brief Return the interrupt to enable or disable according to the
8195 * OC mode.
8196 * @param hhrtim pointer to HAL HRTIM handle
8197 * @param TimerIdx Timer index
8198 * @param OCChannel Timer output
8199 * This parameter can be one of the following values:
8200 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
8201 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
8202 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
8203 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
8204 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
8205 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
8206 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
8207 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
8208 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
8209 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
8210 * @retval Interrupt to enable or disable
8211 */
8212 static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
8213 uint32_t TimerIdx,
8214 uint32_t OCChannel)
8215 {
8216 uint32_t hrtim_set;
8217 uint32_t hrtim_reset;
8218 uint32_t interrupt = 0U;
8219
8220 switch (OCChannel)
8221 {
8222 case HRTIM_OUTPUT_TA1:
8223 case HRTIM_OUTPUT_TB1:
8224 case HRTIM_OUTPUT_TC1:
8225 case HRTIM_OUTPUT_TD1:
8226 case HRTIM_OUTPUT_TE1:
8227 {
8228 /* Retreives actual OC mode and set interrupt accordingly */
8229 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
8230 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
8231
8232 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8233 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8234 {
8235 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8236 interrupt = HRTIM_TIM_IT_CMP1;
8237 }
8238 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8239 (hrtim_reset == 0U))
8240 {
8241 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8242 interrupt = HRTIM_TIM_IT_SET1;
8243 }
8244 else if ((hrtim_set == 0U) &&
8245 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8246 {
8247 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8248 interrupt = HRTIM_TIM_IT_RST1;
8249 }
8250 else
8251 {
8252 /* nothing to do */
8253 }
8254 break;
8255 }
8256
8257 case HRTIM_OUTPUT_TA2:
8258 case HRTIM_OUTPUT_TB2:
8259 case HRTIM_OUTPUT_TC2:
8260 case HRTIM_OUTPUT_TD2:
8261 case HRTIM_OUTPUT_TE2:
8262 {
8263 /* Retreives actual OC mode and set interrupt accordingly */
8264 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
8265 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
8266
8267 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8268 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8269 {
8270 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8271 interrupt = HRTIM_TIM_IT_CMP2;
8272 }
8273 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8274 (hrtim_reset == 0U))
8275 {
8276 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8277 interrupt = HRTIM_TIM_IT_SET2;
8278 }
8279 else if ((hrtim_set == 0U) &&
8280 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8281 {
8282 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8283 interrupt = HRTIM_TIM_IT_RST2;
8284 }
8285 else
8286 {
8287 /* nothing to do */
8288 }
8289 break;
8290 }
8291
8292 default:
8293 break;
8294 }
8295
8296 return interrupt;
8297 }
8298
8299 /**
8300 * @brief Return the DMA request to enable or disable according to the
8301 * OC mode.
8302 * @param hhrtim pointer to HAL HRTIM handle
8303 * @param TimerIdx Timer index
8304 * @param OCChannel Timer output
8305 * This parameter can be one of the following values:
8306 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
8307 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
8308 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
8309 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
8310 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
8311 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
8312 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
8313 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
8314 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
8315 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
8316 * @retval DMA request to enable or disable
8317 */
8318 static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
8319 uint32_t TimerIdx,
8320 uint32_t OCChannel)
8321 {
8322 uint32_t hrtim_set;
8323 uint32_t hrtim_reset;
8324 uint32_t dma_request = 0U;
8325
8326 switch (OCChannel)
8327 {
8328 case HRTIM_OUTPUT_TA1:
8329 case HRTIM_OUTPUT_TB1:
8330 case HRTIM_OUTPUT_TC1:
8331 case HRTIM_OUTPUT_TD1:
8332 case HRTIM_OUTPUT_TE1:
8333 {
8334 /* Retreives actual OC mode and set dma_request accordingly */
8335 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
8336 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
8337
8338 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8339 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8340 {
8341 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8342 dma_request = HRTIM_TIM_DMA_CMP1;
8343 }
8344 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8345 (hrtim_reset == 0U))
8346 {
8347 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8348 dma_request = HRTIM_TIM_DMA_SET1;
8349 }
8350 else if ((hrtim_set == 0U) &&
8351 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8352 {
8353 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8354 dma_request = HRTIM_TIM_DMA_RST1;
8355 }
8356 else
8357 {
8358 /* nothing to do */
8359 }
8360 break;
8361 }
8362
8363 case HRTIM_OUTPUT_TA2:
8364 case HRTIM_OUTPUT_TB2:
8365 case HRTIM_OUTPUT_TC2:
8366 case HRTIM_OUTPUT_TD2:
8367 case HRTIM_OUTPUT_TE2:
8368 {
8369 /* Retreives actual OC mode and set dma_request accordingly */
8370 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
8371 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
8372
8373 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8374 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8375 {
8376 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8377 dma_request = HRTIM_TIM_DMA_CMP2;
8378 }
8379 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8380 (hrtim_reset == 0U))
8381 {
8382 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8383 dma_request = HRTIM_TIM_DMA_SET2;
8384 }
8385 else if ((hrtim_set == 0U) &&
8386 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8387 {
8388 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8389 dma_request = HRTIM_TIM_DMA_RST2;
8390 }
8391 else
8392 {
8393 /* nothing to do */
8394 }
8395 break;
8396 }
8397
8398 default:
8399 break;
8400 }
8401
8402 return dma_request;
8403 }
8404
8405 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
8406 uint32_t TimerIdx)
8407 {
8408 DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL;
8409
8410 switch (TimerIdx)
8411 {
8412 case HRTIM_TIMERINDEX_MASTER:
8413 {
8414 hdma = hhrtim->hdmaMaster;
8415 break;
8416 }
8417
8418 case HRTIM_TIMERINDEX_TIMER_A:
8419 {
8420 hdma = hhrtim->hdmaTimerA;
8421 break;
8422 }
8423
8424 case HRTIM_TIMERINDEX_TIMER_B:
8425 {
8426 hdma = hhrtim->hdmaTimerB;
8427 break;
8428 }
8429
8430 case HRTIM_TIMERINDEX_TIMER_C:
8431 {
8432 hdma = hhrtim->hdmaTimerC;
8433 break;
8434 }
8435
8436 case HRTIM_TIMERINDEX_TIMER_D:
8437 {
8438 hdma = hhrtim->hdmaTimerD;
8439 break;
8440 }
8441
8442 case HRTIM_TIMERINDEX_TIMER_E:
8443 {
8444 hdma = hhrtim->hdmaTimerE;
8445 break;
8446 }
8447
8448 default:
8449 break;
8450 }
8451
8452 return hdma;
8453 }
8454
8455 static uint32_t GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim,
8456 DMA_HandleTypeDef * hdma)
8457 {
8458 uint32_t timed_idx = 0xFFFFFFFFU;
8459
8460 if (hdma == hhrtim->hdmaMaster)
8461 {
8462 timed_idx = HRTIM_TIMERINDEX_MASTER;
8463 }
8464 else if (hdma == hhrtim->hdmaTimerA)
8465 {
8466 timed_idx = HRTIM_TIMERINDEX_TIMER_A;
8467 }
8468 else if (hdma == hhrtim->hdmaTimerB)
8469 {
8470 timed_idx = HRTIM_TIMERINDEX_TIMER_B;
8471 }
8472 else if (hdma == hhrtim->hdmaTimerC)
8473 {
8474 timed_idx = HRTIM_TIMERINDEX_TIMER_C;
8475 }
8476 else if (hdma == hhrtim->hdmaTimerD)
8477 {
8478 timed_idx = HRTIM_TIMERINDEX_TIMER_D;
8479 }
8480 else if (hdma == hhrtim->hdmaTimerE)
8481 {
8482 timed_idx = HRTIM_TIMERINDEX_TIMER_E;
8483 }
8484 else
8485 {
8486 /* nothing to do */
8487 }
8488 return timed_idx;
8489 }
8490
8491 /**
8492 * @brief Force an immediate transfer from the preload to the active
8493 * registers.
8494 * @param hhrtim pointer to HAL HRTIM handle
8495 * @param TimerIdx Timer index
8496 * @retval None
8497 */
8498 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
8499 uint32_t TimerIdx)
8500 {
8501 switch (TimerIdx)
8502 {
8503 case HRTIM_TIMERINDEX_MASTER:
8504 {
8505 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
8506 break;
8507 }
8508
8509 case HRTIM_TIMERINDEX_TIMER_A:
8510 {
8511 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
8512 break;
8513 }
8514
8515 case HRTIM_TIMERINDEX_TIMER_B:
8516 {
8517 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
8518 break;
8519 }
8520
8521 case HRTIM_TIMERINDEX_TIMER_C:
8522 {
8523 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
8524 break;
8525 }
8526
8527 case HRTIM_TIMERINDEX_TIMER_D:
8528 {
8529 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
8530 break;
8531 }
8532
8533 case HRTIM_TIMERINDEX_TIMER_E:
8534 {
8535 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
8536 break;
8537 }
8538
8539 default:
8540 break;
8541 }
8542 }
8543
8544
8545 /**
8546 * @brief HRTIM interrupts service routine
8547 * @param hhrtim pointer to HAL HRTIM handle
8548 * @retval None
8549 */
8550 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
8551 {
8552 /* Fault 1 event */
8553 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT1) != (uint32_t)RESET)
8554 {
8555 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT1) != RESET)
8556 {
8557 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
8558
8559 /* Invoke Fault 1 event callback */
8560 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8561 hhrtim->Fault1Callback(hhrtim);
8562 #else
8563 HAL_HRTIM_Fault1Callback(hhrtim);
8564 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8565 }
8566 }
8567
8568 /* Fault 2 event */
8569 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT2) != (uint32_t)RESET)
8570 {
8571 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT2) != RESET)
8572 {
8573 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
8574
8575 /* Invoke Fault 2 event callback */
8576 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8577 hhrtim->Fault2Callback(hhrtim);
8578 #else
8579 HAL_HRTIM_Fault2Callback(hhrtim);
8580 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8581 }
8582 }
8583
8584 /* Fault 3 event */
8585 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT3) != (uint32_t)RESET)
8586 {
8587 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT3) != RESET)
8588 {
8589 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
8590
8591 /* Invoke Fault 3 event callback */
8592 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8593 hhrtim->Fault3Callback(hhrtim);
8594 #else
8595 HAL_HRTIM_Fault3Callback(hhrtim);
8596 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8597 }
8598 }
8599
8600 /* Fault 4 event */
8601 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT4) != (uint32_t)RESET)
8602 {
8603 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT4) != RESET)
8604 {
8605 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
8606
8607 /* Invoke Fault 4 event callback */
8608 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8609 hhrtim->Fault4Callback(hhrtim);
8610 #else
8611 HAL_HRTIM_Fault4Callback(hhrtim);
8612 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8613 }
8614 }
8615
8616 /* Fault 5 event */
8617 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT5) != (uint32_t)RESET)
8618 {
8619 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT5) != RESET)
8620 {
8621 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
8622
8623 /* Invoke Fault 5 event callback */
8624 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8625 hhrtim->Fault5Callback(hhrtim);
8626 #else
8627 HAL_HRTIM_Fault5Callback(hhrtim);
8628 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8629 }
8630 }
8631
8632 /* System fault event */
8633 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_SYSFLT) != (uint32_t)RESET)
8634 {
8635 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_SYSFLT) != RESET)
8636 {
8637 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
8638
8639 /* Invoke System fault event callback */
8640 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8641 hhrtim->SystemFaultCallback(hhrtim);
8642 #else
8643 HAL_HRTIM_SystemFaultCallback(hhrtim);
8644 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8645 }
8646 }
8647 }
8648
8649 /**
8650 * @brief Master timer interrupts service routine
8651 * @param hhrtim pointer to HAL HRTIM handle
8652 * @retval None
8653 */
8654 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
8655 {
8656 /* Burst mode period event */
8657 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_BMPER) != (uint32_t)RESET)
8658 {
8659 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_BMPER) != RESET)
8660 {
8661 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
8662
8663 /* Invoke Burst mode period event callback */
8664 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8665 hhrtim->BurstModePeriodCallback(hhrtim);
8666 #else
8667 HAL_HRTIM_BurstModePeriodCallback(hhrtim);
8668 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8669 }
8670 }
8671
8672 /* Master timer compare 1 event */
8673 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET)
8674 {
8675 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP1) != RESET)
8676 {
8677 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
8678
8679 /* Invoke compare 1 event callback */
8680 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8681 hhrtim->Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8682 #else
8683 HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8684 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8685 }
8686 }
8687
8688 /* Master timer compare 2 event */
8689 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET)
8690 {
8691 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP2) != RESET)
8692 {
8693 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
8694
8695 /* Invoke compare 2 event callback */
8696 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8697 hhrtim->Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8698 #else
8699 HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8700 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8701 }
8702 }
8703
8704 /* Master timer compare 3 event */
8705 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET)
8706 {
8707 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP3) != RESET)
8708 {
8709 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
8710
8711 /* Invoke compare 3 event callback */
8712 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8713 hhrtim->Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8714 #else
8715 HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8716 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8717 }
8718 }
8719
8720 /* Master timer compare 4 event */
8721 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET)
8722 {
8723 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP4) != RESET)
8724 {
8725 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
8726
8727 /* Invoke compare 4 event callback */
8728 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8729 hhrtim->Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8730 #else
8731 HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8732 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8733 }
8734 }
8735
8736 /* Master timer repetition event */
8737 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET)
8738 {
8739 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MREP) != RESET)
8740 {
8741 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
8742
8743 /* Invoke repetition event callback */
8744 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8745 hhrtim->RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8746 #else
8747 HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8748 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8749 }
8750 }
8751
8752 /* Synchronization input event */
8753 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET)
8754 {
8755 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_SYNC) != RESET)
8756 {
8757 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
8758
8759 /* Invoke synchronization event callback */
8760 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8761 hhrtim->SynchronizationEventCallback(hhrtim);
8762 #else
8763 HAL_HRTIM_SynchronizationEventCallback(hhrtim);
8764 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8765 }
8766 }
8767
8768 /* Master timer registers update event */
8769 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET)
8770 {
8771 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MUPD) != RESET)
8772 {
8773 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
8774
8775 /* Invoke registers update event callback */
8776 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8777 hhrtim->RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8778 #else
8779 HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8780 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8781 }
8782 }
8783 }
8784
8785 /**
8786 * @brief Timer interrupts service routine
8787 * @param hhrtim pointer to HAL HRTIM handle
8788 * @param TimerIdx Timer index
8789 * This parameter can be one of the following values:
8790 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8791 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8792 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8793 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8794 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8795 * @retval None
8796 */
8797 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
8798 uint32_t TimerIdx)
8799 {
8800 /* Timer compare 1 event */
8801 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET)
8802 {
8803 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1) != RESET)
8804 {
8805 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
8806
8807 /* Invoke compare 1 event callback */
8808 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8809 hhrtim->Compare1EventCallback(hhrtim, TimerIdx);
8810 #else
8811 HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
8812 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8813 }
8814 }
8815
8816 /* Timer compare 2 event */
8817 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET)
8818 {
8819 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2) != RESET)
8820 {
8821 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
8822
8823 /* Invoke compare 2 event callback */
8824 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8825 hhrtim->Compare2EventCallback(hhrtim, TimerIdx);
8826 #else
8827 HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
8828 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8829 }
8830 }
8831
8832 /* Timer compare 3 event */
8833 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET)
8834 {
8835 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3) != RESET)
8836 {
8837 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
8838
8839 /* Invoke compare 3 event callback */
8840 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8841 hhrtim->Compare3EventCallback(hhrtim, TimerIdx);
8842 #else
8843 HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
8844 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8845 }
8846 }
8847
8848 /* Timer compare 4 event */
8849 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET)
8850 {
8851 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4) != RESET)
8852 {
8853 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
8854
8855 /* Invoke compare 4 event callback */
8856 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8857 hhrtim->Compare4EventCallback(hhrtim, TimerIdx);
8858 #else
8859 HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
8860 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8861 }
8862 }
8863
8864 /* Timer repetition event */
8865 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_REP) != (uint32_t)RESET)
8866 {
8867 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_REP) != RESET)
8868 {
8869 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
8870
8871 /* Invoke repetition event callback */
8872 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8873 hhrtim->RepetitionEventCallback(hhrtim, TimerIdx);
8874 #else
8875 HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
8876 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8877 }
8878 }
8879
8880 /* Timer registers update event */
8881 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET)
8882 {
8883 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD) != RESET)
8884 {
8885 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
8886
8887 /* Invoke registers update event callback */
8888 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8889 hhrtim->RegistersUpdateCallback(hhrtim, TimerIdx);
8890 #else
8891 HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
8892 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8893 }
8894 }
8895
8896 /* Timer capture 1 event */
8897 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET)
8898 {
8899 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1) != RESET)
8900 {
8901 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
8902
8903 /* Invoke capture 1 event callback */
8904 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8905 hhrtim->Capture1EventCallback(hhrtim, TimerIdx);
8906 #else
8907 HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
8908 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8909 }
8910 }
8911
8912 /* Timer capture 2 event */
8913 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET)
8914 {
8915 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2) != RESET)
8916 {
8917 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
8918
8919 /* Invoke capture 2 event callback */
8920 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8921 hhrtim->Capture2EventCallback(hhrtim, TimerIdx);
8922 #else
8923 HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
8924 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8925 }
8926 }
8927
8928 /* Timer output 1 set event */
8929 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET)
8930 {
8931 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1) != RESET)
8932 {
8933 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
8934
8935 /* Invoke output 1 set event callback */
8936 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8937 hhrtim->Output1SetCallback(hhrtim, TimerIdx);
8938 #else
8939 HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
8940 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8941 }
8942 }
8943
8944 /* Timer output 1 reset event */
8945 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET)
8946 {
8947 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1) != RESET)
8948 {
8949 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
8950
8951 /* Invoke output 1 reset event callback */
8952 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8953 hhrtim->Output1ResetCallback(hhrtim, TimerIdx);
8954 #else
8955 HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
8956 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8957 }
8958 }
8959
8960 /* Timer output 2 set event */
8961 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET)
8962 {
8963 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2) != RESET)
8964 {
8965 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
8966
8967 /* Invoke output 2 set event callback */
8968 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8969 hhrtim->Output2SetCallback(hhrtim, TimerIdx);
8970 #else
8971 HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
8972 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8973 }
8974 }
8975
8976 /* Timer output 2 reset event */
8977 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET)
8978 {
8979 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2) != RESET)
8980 {
8981 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
8982
8983 /* Invoke output 2 reset event callback */
8984 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8985 hhrtim->Output2ResetCallback(hhrtim, TimerIdx);
8986 #else
8987 HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
8988 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8989 }
8990 }
8991
8992 /* Timer reset event */
8993 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST) != (uint32_t)RESET)
8994 {
8995 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST) != RESET)
8996 {
8997 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
8998
8999 /* Invoke timer reset callback */
9000 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9001 hhrtim->CounterResetCallback(hhrtim, TimerIdx);
9002 #else
9003 HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
9004 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9005 }
9006 }
9007
9008 /* Delayed protection event */
9009 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET)
9010 {
9011 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT) != RESET)
9012 {
9013 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
9014
9015 /* Invoke delayed protection callback */
9016 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9017 hhrtim->DelayedProtectionCallback(hhrtim, TimerIdx);
9018 #else
9019 HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
9020 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9021 }
9022 }
9023 }
9024
9025 /**
9026 * @brief DMA callback invoked upon master timer related DMA request completion
9027 * @param hdma pointer to DMA handle.
9028 * @retval None
9029 */
9030 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
9031 {
9032 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9033
9034 if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET)
9035 {
9036 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9037 hrtim->Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9038 #else
9039 HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9040 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9041 }
9042 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != (uint32_t)RESET)
9043 {
9044 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9045 hrtim->Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9046 #else
9047 HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9048 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9049 }
9050 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != (uint32_t)RESET)
9051 {
9052 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9053 hrtim->Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9054 #else
9055 HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9056 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9057 }
9058 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != (uint32_t)RESET)
9059 {
9060 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9061 hrtim->Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9062 #else
9063 HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9064 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9065 }
9066 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != (uint32_t)RESET)
9067 {
9068 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9069 hrtim->SynchronizationEventCallback(hrtim);
9070 #else
9071 HAL_HRTIM_SynchronizationEventCallback(hrtim);
9072 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9073 }
9074 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != (uint32_t)RESET)
9075 {
9076 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9077 hrtim->RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9078 #else
9079 HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9080 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9081 }
9082 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != (uint32_t)RESET)
9083 {
9084 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9085 hrtim->RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9086 #else
9087 HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9088 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9089 }
9090 else
9091 {
9092 /* nothing to do */
9093 }
9094 }
9095
9096 /**
9097 * @brief DMA callback invoked upon timer A..E related DMA request completion
9098 * @param hdma pointer to DMA handle.
9099 * @retval None
9100 */
9101 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
9102 {
9103 uint8_t timer_idx;
9104
9105 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9106
9107 timer_idx = (uint8_t)GetTimerIdxFromDMAHandle(hrtim, hdma);
9108
9109 if ( !IS_HRTIM_TIMING_UNIT(timer_idx) ) {return;}
9110
9111 if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != (uint32_t)RESET)
9112 {
9113 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9114 hrtim->Compare1EventCallback(hrtim, timer_idx);
9115 #else
9116 HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
9117 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9118 }
9119 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != (uint32_t)RESET)
9120 {
9121 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9122 hrtim->Compare2EventCallback(hrtim, timer_idx);
9123 #else
9124 HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
9125 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9126 }
9127 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != (uint32_t)RESET)
9128 {
9129 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9130 hrtim->Compare3EventCallback(hrtim, timer_idx);
9131 #else
9132 HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
9133 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9134 }
9135 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != (uint32_t)RESET)
9136 {
9137 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9138 hrtim->Compare4EventCallback(hrtim, timer_idx);
9139 #else
9140 HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
9141 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9142 }
9143 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != (uint32_t)RESET)
9144 {
9145 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9146 hrtim->RegistersUpdateCallback(hrtim, timer_idx);
9147 #else
9148 HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
9149 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9150 }
9151 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != (uint32_t)RESET)
9152 {
9153 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9154 hrtim->Capture1EventCallback(hrtim, timer_idx);
9155 #else
9156 HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
9157 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9158 }
9159 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != (uint32_t)RESET)
9160 {
9161 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9162 hrtim->Capture2EventCallback(hrtim, timer_idx);
9163 #else
9164 HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
9165 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9166 }
9167 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != (uint32_t)RESET)
9168 {
9169 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9170 hrtim->Output1SetCallback(hrtim, timer_idx);
9171 #else
9172 HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
9173 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9174 }
9175 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != (uint32_t)RESET)
9176 {
9177 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9178 hrtim->Output1ResetCallback(hrtim, timer_idx);
9179 #else
9180 HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
9181 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9182 }
9183 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != (uint32_t)RESET)
9184 {
9185 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9186 hrtim->Output2SetCallback(hrtim, timer_idx);
9187 #else
9188 HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
9189 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9190 }
9191 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != (uint32_t)RESET)
9192 {
9193 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9194 hrtim->Output2ResetCallback(hrtim, timer_idx);
9195 #else
9196 HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
9197 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9198 }
9199 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != (uint32_t)RESET)
9200 {
9201 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9202 hrtim->CounterResetCallback(hrtim, timer_idx);
9203 #else
9204 HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
9205 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9206 }
9207 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != (uint32_t)RESET)
9208 {
9209 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9210 hrtim->DelayedProtectionCallback(hrtim, timer_idx);
9211 #else
9212 HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
9213 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9214 }
9215 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != (uint32_t)RESET)
9216 {
9217 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9218 hrtim->RepetitionEventCallback(hrtim, timer_idx);
9219 #else
9220 HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
9221 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9222 }
9223 else
9224 {
9225 /* nothing to do */
9226 }
9227 }
9228
9229 /**
9230 * @brief DMA error callback
9231 * @param hdma pointer to DMA handle.
9232 * @retval None
9233 */
9234 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
9235 {
9236 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9237
9238 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9239 hrtim->ErrorCallback(hrtim);
9240 #else
9241 HAL_HRTIM_ErrorCallback(hrtim);
9242 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9243 }
9244
9245 /**
9246 * @brief DMA callback invoked upon burst DMA transfer completion
9247 * @param hdma pointer to DMA handle.
9248 * @retval None
9249 */
9250 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
9251 {
9252 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9253
9254 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9255 hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
9256 #else
9257 HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
9258 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9259 }
9260
9261 /**
9262 * @}
9263 */
9264
9265 /**
9266 * @}
9267 */
9268
9269 #endif /* HRTIM1 */
9270
9271 #endif /* HAL_HRTIM_MODULE_ENABLED */
9272
9273 /**
9274 * @}
9275 */
9276
9277 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/