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[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_hal_i2s.c
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1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_i2s.c
4 * @author MCD Application Team
5 * @brief I2S HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 @verbatim
12 ===============================================================================
13 ##### How to use this driver #####
14 ===============================================================================
15 [..]
16 The I2S HAL driver can be used as follow:
17
18 (#) Declare a I2S_HandleTypeDef handle structure.
19 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
20 (##) Enable the SPIx interface clock.
21 (##) I2S pins configuration:
22 (+++) Enable the clock for the I2S GPIOs.
23 (+++) Configure these I2S pins as alternate function pull-up.
24 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
25 and HAL_I2S_Receive_IT() APIs).
26 (+++) Configure the I2Sx interrupt priority.
27 (+++) Enable the NVIC I2S IRQ handle.
28 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
29 and HAL_I2S_Receive_DMA() APIs:
30 (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
31 (+++) Enable the DMAx interface clock.
32 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
33 (+++) Configure the DMA Tx/Rx Stream/Channel.
34 (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
35 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
36 DMA Tx/Rx Stream/Channel.
37
38 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
39 using HAL_I2S_Init() function.
40
41 -@- The specific I2S interrupts (Transmission complete interrupt,
42 RXNE interrupt and Error Interrupts) will be managed using the macros
43 __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
44
45 (+@) External clock source is configured after setting correctly
46 the define constant EXTERNAL_CLOCK_VALUE in the stm32h7xx_hal_conf.h file.
47
48 (#) Three mode of operations are available within this driver :
49
50 *** Polling mode IO operation ***
51 =================================
52 [..]
53 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
54 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
55
56 *** Interrupt mode IO operation ***
57 ===================================
58 [..]
59 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
60 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
61 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
62 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
63 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
64 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
65 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
66 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
67 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
68 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
69 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
70 add his own code by customization of function pointer HAL_I2S_ErrorCallback
71
72 *** DMA mode IO operation ***
73 ==============================
74 [..]
75 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
76 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
77 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
78 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
79 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
80 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
81 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
82 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
83 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
84 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
85 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
86 add his own code by customization of function pointer HAL_I2S_ErrorCallback
87 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
88 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
89 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
90
91 *** I2S HAL driver macros list ***
92 ===================================
93 [..]
94 Below the list of most used macros in I2S HAL driver.
95
96 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
97 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
98 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
99 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
100 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
101
102 [..]
103 (@) You can refer to the I2S HAL driver header file for more useful macros
104
105 *** I2S HAL driver macros list ***
106 ===================================
107 [..]
108 Callback registration:
109
110 (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1UL
111 allows the user to configure dynamically the driver callbacks.
112 Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
113
114 Function HAL_I2S_RegisterCallback() allows to register following callbacks:
115 (+) TxCpltCallback : I2S Tx Completed callback
116 (+) RxCpltCallback : I2S Rx Completed callback
117 (+) TxRxCpltCallback : I2S TxRx Completed callback
118 (+) TxHalfCpltCallback : I2S Tx Half Completed callback
119 (+) RxHalfCpltCallback : I2S Rx Half Completed callback
120 (+) ErrorCallback : I2S Error callback
121 (+) MspInitCallback : I2S Msp Init callback
122 (+) MspDeInitCallback : I2S Msp DeInit callback
123 This function takes as parameters the HAL peripheral handle, the Callback ID
124 and a pointer to the user callback function.
125
126
127 (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
128 weak function.
129 HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
130 and the Callback ID.
131 This function allows to reset following callbacks:
132 (+) TxCpltCallback : I2S Tx Completed callback
133 (+) RxCpltCallback : I2S Rx Completed callback
134 (+) TxRxCpltCallback : I2S TxRx Completed callback
135 (+) TxHalfCpltCallback : I2S Tx Half Completed callback
136 (+) RxHalfCpltCallback : I2S Rx Half Completed callback
137 (+) ErrorCallback : I2S Error callback
138 (+) MspInitCallback : I2S Msp Init callback
139 (+) MspDeInitCallback : I2S Msp DeInit callback
140
141 By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
142 all callbacks are set to the corresponding weak functions:
143 examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
144 Exception done for MspInit and MspDeInit functions that are
145 reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
146 these callbacks are null (not registered beforehand).
147 If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
148 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
149
150 Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
151 Exception done MspInit/MspDeInit functions that can be registered/unregistered
152 in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
153 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
154 Then, the user first registers the MspInit/MspDeInit user callbacks
155 using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
156 or HAL_I2S_Init() function.
157
158 When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
159 not defined, the callback registering feature is not available
160 and weak (surcharged) callbacks are used.
161
162
163 @endverbatim
164 ******************************************************************************
165 * @attention
166 *
167 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
168 * All rights reserved.</center></h2>
169 *
170 * This software component is licensed by ST under BSD 3-Clause license,
171 * the "License"; You may not use this file except in compliance with the
172 * License. You may obtain a copy of the License at:
173 * opensource.org/licenses/BSD-3-Clause
174 *
175 ******************************************************************************
176 */
177
178 /* Includes ------------------------------------------------------------------*/
179 #include "stm32h7xx_hal.h"
180
181 #ifdef HAL_I2S_MODULE_ENABLED
182
183 /** @addtogroup STM32H7xx_HAL_Driver
184 * @{
185 */
186
187 /** @defgroup I2S I2S
188 * @brief I2S HAL module driver
189 * @{
190 */
191
192 /* Private typedef -----------------------------------------------------------*/
193 /* Private define ------------------------------------------------------------*/
194 #define I2S_TIMEOUT 0xFFFFUL
195
196 /* Private macro -------------------------------------------------------------*/
197 /* Private variables ---------------------------------------------------------*/
198 /* Private function prototypes -----------------------------------------------*/
199 /** @defgroup I2S_Private_Functions I2S Private Functions
200 * @{
201 */
202 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
203 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
204 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
205 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
206 static void I2SEx_DMATxRxCplt(DMA_HandleTypeDef *hdma);
207 static void I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef *hdma);
208 static void I2S_DMAError(DMA_HandleTypeDef *hdma);
209 static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s);
210 static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s);
211 static void I2S_Receive_16Bit_IT(I2S_HandleTypeDef *hi2s);
212 static void I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s);
213 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
214 uint32_t Timeout);
215 /**
216 * @}
217 */
218
219 /* Exported functions ---------------------------------------------------------*/
220
221 /** @defgroup I2S_Exported_Functions I2S Exported Functions
222 * @{
223 */
224
225 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
226 * @brief Initialization and Configuration functions
227 *
228 @verbatim
229 ===============================================================================
230 ##### Initialization and de-initialization functions #####
231 ===============================================================================
232 [..] This subsection provides a set of functions allowing to initialize and
233 de-initialize the I2Sx peripheral in simplex mode:
234
235 (+) User must Implement HAL_I2S_MspInit() function in which he configures
236 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
237
238 (+) Call the function HAL_I2S_Init() to configure the selected device with
239 the selected configuration:
240 (++) Mode
241 (++) Standard
242 (++) Data Format
243 (++) MCLK Output
244 (++) Audio frequency
245 (++) Polarity
246
247 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
248 of the selected I2Sx peripheral.
249 @endverbatim
250 * @{
251 */
252
253 /**
254 * @brief Initializes the I2S according to the specified parameters
255 * in the I2S_InitTypeDef and create the associated handle.
256 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
257 * the configuration information for I2S module
258 * @retval HAL status
259 */
260 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
261 {
262 uint32_t i2sdiv;
263 uint32_t i2sodd;
264 uint32_t packetlength;
265 uint32_t tmp;
266 uint32_t i2sclk;
267 uint32_t ispcm;
268
269 /* Check the I2S handle allocation */
270 if (hi2s == NULL)
271 {
272 return HAL_ERROR;
273 }
274
275 /* Check the I2S parameters */
276 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
277 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
278 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
279 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
280 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
281 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
282 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
283 assert_param(IS_I2S_FIRST_BIT(hi2s->Init.FirstBit));
284 assert_param(IS_I2S_WS_INVERSION(hi2s->Init.WSInversion));
285 assert_param(IS_I2S_DATA_24BIT_ALIGNMENT(hi2s->Init.Data24BitAlignment));
286 assert_param(IS_I2S_MASTER_KEEP_IO_STATE(hi2s->Init.MasterKeepIOState));
287
288 if (hi2s->State == HAL_I2S_STATE_RESET)
289 {
290 /* Allocate lock resource and initialize it */
291 hi2s->Lock = HAL_UNLOCKED;
292
293 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
294 /* Init the I2S Callback settings */
295 hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
296 hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
297 hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
298 hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
299 hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
300 hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
301 hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
302
303 if (hi2s->MspInitCallback == NULL)
304 {
305 hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
306 }
307
308 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
309 hi2s->MspInitCallback(hi2s);
310 #else
311 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
312 HAL_I2S_MspInit(hi2s);
313 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
314 }
315
316 hi2s->State = HAL_I2S_STATE_BUSY;
317
318 /* Disable the selected I2S peripheral */
319 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE)
320 {
321 /* Disable I2S peripheral */
322 __HAL_I2S_DISABLE(hi2s);
323 }
324
325 /* Clear I2S configuration register */
326 CLEAR_REG(hi2s->Instance->I2SCFGR);
327
328 if (IS_I2S_MASTER(hi2s->Init.Mode))
329 {
330 /*------------------------- I2SDIV and ODD Calculation ---------------------*/
331 /* If the requested audio frequency is not the default, compute the prescaler */
332 if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
333 {
334 /* Check the frame length (For the Prescaler computing) ********************/
335 if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
336 {
337 /* Channel length is 32 bits */
338 packetlength = 2UL;
339 }
340 else
341 {
342 /* Channel length is 16 bits */
343 packetlength = 1UL;
344 }
345
346 /* Check if PCM standard is used */
347 if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) ||
348 (hi2s->Init.Standard == I2S_STANDARD_PCM_LONG))
349 {
350 ispcm = 1UL;
351 }
352 else
353 {
354 ispcm = 0UL;
355 }
356
357 /* Get the source clock value: based on System Clock value */
358 #if defined (SPI_SPI6I2S_SUPPORT)
359 if (hi2s->Instance == SPI6)
360 {
361 /* SPI6 source clock */
362 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6);
363 }
364 else
365 {
366 /* SPI1,SPI2 and SPI3 share the same source clock */
367 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
368 }
369 #else
370 /* SPI1,SPI2 and SPI3 share the same source clock */
371 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
372 #endif
373
374 /* Compute the Real divider depending on the MCLK output state, with a floating point */
375 if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
376 {
377 /* MCLK output is enabled */
378 tmp = (uint32_t)((((i2sclk / (256UL >> ispcm)) * 10UL) / hi2s->Init.AudioFreq) + 5UL);
379 }
380 else
381 {
382 /* MCLK output is disabled */
383 tmp = (uint32_t)((((i2sclk / ((32UL >> ispcm) * packetlength)) * 10UL) / hi2s->Init.AudioFreq) + 5UL);
384 }
385
386 /* Remove the flatting point */
387 tmp = tmp / 10UL;
388
389 /* Check the parity of the divider */
390 i2sodd = (uint32_t)(tmp & (uint32_t)1UL);
391
392 /* Compute the i2sdiv prescaler */
393 i2sdiv = (uint32_t)((tmp - i2sodd) / 2UL);
394 }
395 else
396 {
397 /* Set the default values */
398 i2sdiv = 2UL;
399 i2sodd = 0UL;
400 }
401
402 /* Test if the obtain values are forbidden or out of range */
403 if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL))
404 {
405 /* Set the error code */
406 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
407 return HAL_ERROR;
408 }
409
410 /* Force i2smod to 1 just to be sure that (2xi2sdiv + i2sodd) is always higher than 0 */
411 if (i2sdiv == 0UL)
412 {
413 i2sodd = 1UL;
414 }
415
416 MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD),
417 ((i2sdiv << SPI_I2SCFGR_I2SDIV_Pos) | (i2sodd << SPI_I2SCFGR_ODD_Pos)));
418 }
419
420 /*-------------------------- I2Sx I2SCFGR Configuration --------------------*/
421 /* Configure I2SMOD, I2SCFG, I2SSTD, PCMSYNC, DATLEN ,CHLEN ,CKPOL, WSINV, DATAFMT, I2SDIV, ODD and MCKOE bits bits */
422 /* And configure the I2S with the I2S_InitStruct values */
423 MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SCFG | \
424 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | \
425 SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | \
426 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_WSINV | \
427 SPI_I2SCFGR_DATFMT | SPI_I2SCFGR_MCKOE),
428 (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
429 hi2s->Init.Standard | hi2s->Init.DataFormat | \
430 hi2s->Init.CPOL | hi2s->Init.WSInversion | \
431 hi2s->Init.Data24BitAlignment | hi2s->Init.MCLKOutput));
432 /*Clear status register*/
433 WRITE_REG(hi2s->Instance->IFCR, 0x0FF8);
434
435 /*---------------------------- I2Sx CFG2 Configuration ----------------------*/
436
437 /* Unlock the AF configuration to configure CFG2 register*/
438 CLEAR_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK);
439
440 MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_LSBFRST, hi2s->Init.FirstBit);
441
442 /* Insure that AFCNTR is managed only by Master */
443 if (IS_I2S_MASTER(hi2s->Init.Mode))
444 {
445 /* Alternate function GPIOs control */
446 MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_AFCNTR, (hi2s->Init.MasterKeepIOState));
447 }
448
449 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
450 hi2s->State = HAL_I2S_STATE_READY;
451
452 return HAL_OK;
453 }
454
455 /**
456 * @brief DeInitializes the I2S peripheral
457 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
458 * the configuration information for I2S module
459 * @retval HAL status
460 */
461 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
462 {
463 /* Check the I2S handle allocation */
464 if (hi2s == NULL)
465 {
466 return HAL_ERROR;
467 }
468
469 /* Check the parameters */
470 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
471
472 hi2s->State = HAL_I2S_STATE_BUSY;
473
474 /* Disable the I2S Peripheral Clock */
475 __HAL_I2S_DISABLE(hi2s);
476
477 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
478 if (hi2s->MspDeInitCallback == NULL)
479 {
480 hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
481 }
482
483 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
484 hi2s->MspDeInitCallback(hi2s);
485 #else
486 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
487 HAL_I2S_MspDeInit(hi2s);
488 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
489
490 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
491 hi2s->State = HAL_I2S_STATE_RESET;
492
493 /* Release Lock */
494 __HAL_UNLOCK(hi2s);
495
496 return HAL_OK;
497 }
498
499 /**
500 * @brief I2S MSP Init
501 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
502 * the configuration information for I2S module
503 * @retval None
504 */
505 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
506 {
507 /* Prevent unused argument(s) compilation warning */
508 UNUSED(hi2s);
509
510 /* NOTE : This function Should not be modified, when the callback is needed,
511 the HAL_I2S_MspInit could be implemented in the user file
512 */
513 }
514
515 /**
516 * @brief I2S MSP DeInit
517 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
518 * the configuration information for I2S module
519 * @retval None
520 */
521 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
522 {
523 /* Prevent unused argument(s) compilation warning */
524 UNUSED(hi2s);
525
526 /* NOTE : This function Should not be modified, when the callback is needed,
527 the HAL_I2S_MspDeInit could be implemented in the user file
528 */
529 }
530
531 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
532 /**
533 * @brief Register a User I2S Callback
534 * To be used instead of the weak predefined callback
535 * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
536 * the configuration information for the specified I2S.
537 * @param CallbackID ID of the callback to be registered
538 * @param pCallback pointer to the Callback function
539 * @retval HAL status
540 */
541 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
542 {
543 HAL_StatusTypeDef status = HAL_OK;
544
545 if (pCallback == NULL)
546 {
547 /* Update the error code */
548 hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
549
550 return HAL_ERROR;
551 }
552 /* Process locked */
553 __HAL_LOCK(hi2s);
554
555 if (HAL_I2S_STATE_READY == hi2s->State)
556 {
557 switch (CallbackID)
558 {
559 case HAL_I2S_TX_COMPLETE_CB_ID :
560 hi2s->TxCpltCallback = pCallback;
561 break;
562
563 case HAL_I2S_RX_COMPLETE_CB_ID :
564 hi2s->RxCpltCallback = pCallback;
565 break;
566
567 case HAL_I2S_TX_RX_COMPLETE_CB_ID :
568 hi2s->TxRxCpltCallback = pCallback;
569 break;
570
571 case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
572 hi2s->TxHalfCpltCallback = pCallback;
573 break;
574
575 case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
576 hi2s->RxHalfCpltCallback = pCallback;
577 break;
578
579
580 case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
581 hi2s->TxRxHalfCpltCallback = pCallback;
582 break;
583
584 case HAL_I2S_ERROR_CB_ID :
585 hi2s->ErrorCallback = pCallback;
586 break;
587
588 case HAL_I2S_MSPINIT_CB_ID :
589 hi2s->MspInitCallback = pCallback;
590 break;
591
592 case HAL_I2S_MSPDEINIT_CB_ID :
593 hi2s->MspDeInitCallback = pCallback;
594 break;
595
596 default :
597 /* Update the error code */
598 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
599
600 /* Return error status */
601 status = HAL_ERROR;
602 break;
603 }
604 }
605 else if (HAL_I2S_STATE_RESET == hi2s->State)
606 {
607 switch (CallbackID)
608 {
609 case HAL_I2S_MSPINIT_CB_ID :
610 hi2s->MspInitCallback = pCallback;
611 break;
612
613 case HAL_I2S_MSPDEINIT_CB_ID :
614 hi2s->MspDeInitCallback = pCallback;
615 break;
616
617 default :
618 /* Update the error code */
619 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
620
621 /* Return error status */
622 status = HAL_ERROR;
623 break;
624 }
625 }
626 else
627 {
628 /* Update the error code */
629 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
630
631 /* Return error status */
632 status = HAL_ERROR;
633 }
634
635 /* Release Lock */
636 __HAL_UNLOCK(hi2s);
637 return status;
638 }
639
640 /**
641 * @brief Unregister an I2S Callback
642 * I2S callback is redirected to the weak predefined callback
643 * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
644 * the configuration information for the specified I2S.
645 * @param CallbackID ID of the callback to be unregistered
646 * @retval HAL status
647 */
648 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
649 {
650 HAL_StatusTypeDef status = HAL_OK;
651
652 /* Process locked */
653 __HAL_LOCK(hi2s);
654
655 if (HAL_I2S_STATE_READY == hi2s->State)
656 {
657 switch (CallbackID)
658 {
659 case HAL_I2S_TX_COMPLETE_CB_ID :
660 hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
661 break;
662
663 case HAL_I2S_RX_COMPLETE_CB_ID :
664 hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
665 break;
666
667 case HAL_I2S_TX_RX_COMPLETE_CB_ID :
668 hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
669 break;
670
671 case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
672 hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
673 break;
674
675 case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
676 hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
677 break;
678
679 case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
680 hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
681 break;
682
683 case HAL_I2S_ERROR_CB_ID :
684 hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
685 break;
686
687 case HAL_I2S_MSPINIT_CB_ID :
688 hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
689 break;
690
691 case HAL_I2S_MSPDEINIT_CB_ID :
692 hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
693 break;
694
695 default :
696 /* Update the error code */
697 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
698
699 /* Return error status */
700 status = HAL_ERROR;
701 break;
702 }
703 }
704 else if (HAL_I2S_STATE_RESET == hi2s->State)
705 {
706 switch (CallbackID)
707 {
708 case HAL_I2S_MSPINIT_CB_ID :
709 hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
710 break;
711
712 case HAL_I2S_MSPDEINIT_CB_ID :
713 hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
714 break;
715
716 default :
717 /* Update the error code */
718 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
719
720 /* Return error status */
721 status = HAL_ERROR;
722 break;
723 }
724 }
725 else
726 {
727 /* Update the error code */
728 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
729
730 /* Return error status */
731 status = HAL_ERROR;
732 }
733
734 /* Release Lock */
735 __HAL_UNLOCK(hi2s);
736 return status;
737 }
738 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
739 /**
740 * @}
741 */
742
743 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
744 * @brief Data transfers functions
745 *
746 @verbatim
747 ===============================================================================
748 ##### IO operation functions #####
749 ===============================================================================
750 [..]
751 This subsection provides a set of functions allowing to manage the I2S data
752 transfers.
753
754 (#) There are two modes of transfer:
755 (++) Blocking mode : The communication is performed in the polling mode.
756 The status of all data processing is returned by the same function
757 after finishing transfer.
758 (++) No-Blocking mode : The communication is performed using Interrupts
759 or DMA. These functions return the status of the transfer startup.
760 The end of the data processing will be indicated through the
761 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
762 using DMA mode.
763
764 (#) Blocking mode functions are :
765 (++) HAL_I2S_Transmit()
766 (++) HAL_I2S_Receive()
767 (++) HAL_I2SEx_TransmitReceive()
768
769 (#) No-Blocking mode functions with Interrupt are :
770 (++) HAL_I2S_Transmit_IT()
771 (++) HAL_I2S_Receive_IT()
772 (++) HAL_I2SEx_TransmitReceive_IT()
773
774 (#) No-Blocking mode functions with DMA are :
775 (++) HAL_I2S_Transmit_DMA()
776 (++) HAL_I2S_Receive_DMA()
777 (++) HAL_I2SEx_TransmitReceive_DMA()
778
779 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
780 (++) HAL_I2S_TxCpltCallback()
781 (++) HAL_I2S_RxCpltCallback()
782 (++) HAL_I2SEx_TxRxCpltCallback()
783 (++) HAL_I2S_ErrorCallback()
784
785 @endverbatim
786 * @{
787 */
788
789 /**
790 * @brief Transmit an amount of data in blocking mode
791 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
792 * the configuration information for I2S module
793 * @param pData a 16-bit pointer to data buffer.
794 * @param Size number of data sample to be sent:
795 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
796 * configuration phase, the Size parameter means the number of 16-bit data length
797 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
798 * the Size parameter means the number of 16-bit data length.
799 * @param Timeout Timeout duration
800 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
801 * between Master and Slave(example: audio streaming).
802 * @retval HAL status
803 */
804 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
805 {
806 #if defined (__GNUC__)
807 __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
808 #endif /* __GNUC__ */
809
810 if ((pData == NULL) || (Size == 0UL))
811 {
812 return HAL_ERROR;
813 }
814
815 /* Process Locked */
816 __HAL_LOCK(hi2s);
817
818 if (hi2s->State != HAL_I2S_STATE_READY)
819 {
820 __HAL_UNLOCK(hi2s);
821 return HAL_BUSY;
822 }
823
824 /* Set state and reset error code */
825 hi2s->State = HAL_I2S_STATE_BUSY_TX;
826 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
827 hi2s->pTxBuffPtr = pData;
828 hi2s->TxXferSize = Size;
829 hi2s->TxXferCount = Size;
830
831 /* Initialize fields not used in handle to zero */
832 hi2s->pRxBuffPtr = NULL;
833 hi2s->RxXferSize = (uint16_t) 0UL;
834 hi2s->RxXferCount = (uint16_t) 0UL;
835
836 /* Check if the I2S is already enabled */
837 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
838 {
839 /* Enable I2S peripheral */
840 __HAL_I2S_ENABLE(hi2s);
841 }
842
843 /* Start the transfer */
844 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
845
846
847 /* Wait until TXP flag is set */
848 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, Timeout) != HAL_OK)
849 {
850 /* Set the error code */
851 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
852 hi2s->State = HAL_I2S_STATE_READY;
853 __HAL_UNLOCK(hi2s);
854 return HAL_ERROR;
855 }
856
857 while (hi2s->TxXferCount > 0UL)
858 {
859 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
860 {
861 /* Transmit data in 32 Bit mode */
862 hi2s->Instance->TXDR = *((uint32_t *)hi2s->pTxBuffPtr);
863 hi2s->pTxBuffPtr += 2;
864 hi2s->TxXferCount--;
865 }
866 else
867 {
868 /* Transmit data in 16 Bit mode */
869 #if defined (__GNUC__)
870 *ptxdr_16bits = *((uint16_t *)hi2s->pTxBuffPtr);
871 #else
872 *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
873 #endif /* __GNUC__ */
874
875 hi2s->pTxBuffPtr++;
876 hi2s->TxXferCount--;
877 }
878
879 /* Wait until TXP flag is set */
880 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, Timeout) != HAL_OK)
881 {
882 /* Set the error code */
883 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
884 hi2s->State = HAL_I2S_STATE_READY;
885 __HAL_UNLOCK(hi2s);
886 return HAL_ERROR;
887 }
888
889 /* Check if an underrun occurs */
890 if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
891 {
892 /* Clear underrun flag */
893 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
894
895 /* Set the error code */
896 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
897 }
898 }
899
900 hi2s->State = HAL_I2S_STATE_READY;
901 __HAL_UNLOCK(hi2s);
902 return HAL_OK;
903 }
904
905 /**
906 * @brief Receive an amount of data in blocking mode
907 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
908 * the configuration information for I2S module
909 * @param pData a 16-bit pointer to data buffer.
910 * @param Size number of data sample to be sent:
911 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
912 * configuration phase, the Size parameter means the number of 16-bit data length
913 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
914 * the Size parameter means the number of 16-bit data length.
915 * @param Timeout Timeout duration
916 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
917 * between Master and Slave(example: audio streaming).
918 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
919 * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
920 * @retval HAL status
921 */
922 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
923 {
924 #if defined (__GNUC__)
925 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
926 #endif /* __GNUC__ */
927
928 if ((pData == NULL) || (Size == 0UL))
929 {
930 return HAL_ERROR;
931 }
932
933 /* Process Locked */
934 __HAL_LOCK(hi2s);
935
936 if (hi2s->State != HAL_I2S_STATE_READY)
937 {
938 __HAL_UNLOCK(hi2s);
939 return HAL_BUSY;
940 }
941
942 /* Set state and reset error code */
943 hi2s->State = HAL_I2S_STATE_BUSY_RX;
944 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
945 hi2s->pRxBuffPtr = pData;
946 hi2s->RxXferSize = Size;
947 hi2s->RxXferCount = Size;
948
949 /* Initialize fields not used in handle to zero */
950 hi2s->pTxBuffPtr = NULL;
951 hi2s->TxXferSize = (uint16_t) 0UL;
952 hi2s->TxXferCount = (uint16_t) 0UL;
953
954 /* Check if the I2S is already enabled */
955 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
956 {
957 /* Enable I2S peripheral */
958 __HAL_I2S_ENABLE(hi2s);
959 }
960
961 /* Start the transfer */
962 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
963
964 /* Receive data */
965 while (hi2s->RxXferCount > 0UL)
966 {
967 /* Wait until RXP flag is set */
968 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXP, SET, Timeout) != HAL_OK)
969 {
970 /* Set the error code */
971 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
972 hi2s->State = HAL_I2S_STATE_READY;
973 __HAL_UNLOCK(hi2s);
974 return HAL_ERROR;
975 }
976
977 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
978 {
979 /* Receive data in 32 Bit mode */
980 *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
981 hi2s->pRxBuffPtr += 2;
982 hi2s->RxXferCount--;
983 }
984 else
985 {
986 /* Receive data in 16 Bit mode */
987 #if defined (__GNUC__)
988 *((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits;
989 #else
990 *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
991 #endif /* __GNUC__ */
992 hi2s->pRxBuffPtr++;
993 hi2s->RxXferCount--;
994 }
995
996 /* Check if an overrun occurs */
997 if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
998 {
999 /* Clear overrun flag */
1000 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
1001
1002 /* Set the error code */
1003 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
1004 }
1005 }
1006
1007 hi2s->State = HAL_I2S_STATE_READY;
1008 __HAL_UNLOCK(hi2s);
1009 return HAL_OK;
1010 }
1011
1012 /**
1013 * @brief Full-Duplex Transmit/Receive data in blocking mode.
1014 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1015 * the configuration information for I2S module
1016 * @param pTxData a 16-bit pointer to the Transmit data buffer.
1017 * @param pRxData a 16-bit pointer to the Receive data buffer.
1018 * @param Size number of data sample to be sent:
1019 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1020 * configuration phase, the Size parameter means the number of 16-bit data length
1021 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1022 * the Size parameter means the number of 16-bit data length.
1023 * @param Timeout Timeout duration
1024 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1025 * between Master and Slave(example: audio streaming).
1026 * @retval HAL status
1027 */
1028
1029 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
1030 uint16_t Size, uint32_t Timeout)
1031 {
1032 uint32_t tmp_TxXferCount;
1033 uint32_t tmp_RxXferCount;
1034 uint32_t tickstart;
1035
1036 #if defined (__GNUC__)
1037 __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
1038 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
1039 #endif /* __GNUC__ */
1040
1041 if (hi2s->State != HAL_I2S_STATE_READY)
1042 {
1043 __HAL_UNLOCK(hi2s);
1044 return HAL_BUSY;
1045 }
1046
1047 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1048 {
1049 return HAL_ERROR;
1050 }
1051
1052 /* Process Locked */
1053 __HAL_LOCK(hi2s);
1054
1055 /* Init tickstart for timeout management*/
1056 tickstart = HAL_GetTick();
1057
1058 hi2s->TxXferSize = Size;
1059 hi2s->TxXferCount = Size;
1060 hi2s->pTxBuffPtr = pTxData;
1061 hi2s->RxXferSize = Size;
1062 hi2s->RxXferCount = Size;
1063 hi2s->pRxBuffPtr = pRxData;
1064
1065 tmp_TxXferCount = hi2s->TxXferCount;
1066 tmp_RxXferCount = hi2s->RxXferCount;
1067
1068 /* Set state and reset error code */
1069 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1070 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
1071
1072 /* Check if the I2S is already enabled */
1073 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1074 {
1075 /* Enable I2S peripheral */
1076 __HAL_I2S_ENABLE(hi2s);
1077 }
1078
1079 /* Start the transfer */
1080 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1081
1082 while ((tmp_TxXferCount > 0UL) || (tmp_RxXferCount > 0UL))
1083 {
1084 if ((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXP) == SET) && (tmp_TxXferCount != 0UL))
1085 {
1086 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
1087 {
1088 /* Transmit data in 32 Bit mode */
1089 hi2s->Instance->TXDR = *((uint32_t *)hi2s->pTxBuffPtr);
1090 hi2s->pTxBuffPtr += 2;
1091 tmp_TxXferCount--;
1092 }
1093 else
1094 {
1095 /* Transmit data in 16 Bit mode */
1096 #if defined (__GNUC__)
1097 *ptxdr_16bits = *((uint16_t *)hi2s->pTxBuffPtr);
1098 #else
1099 *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
1100 #endif /* __GNUC__ */
1101
1102 hi2s->pTxBuffPtr++;
1103 tmp_TxXferCount--;
1104 }
1105
1106 /* Check if an underrun occurs */
1107 if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
1108 {
1109 /* Clear underrun flag */
1110 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
1111
1112 /* Set the error code */
1113 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
1114 }
1115 }
1116
1117 if ((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXP) == SET) && (tmp_RxXferCount != 0UL))
1118 {
1119 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
1120 {
1121 /* Receive data in 32 Bit mode */
1122 *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
1123 hi2s->pRxBuffPtr += 2;
1124 tmp_RxXferCount--;
1125 }
1126 else
1127 {
1128 /* Receive data in 16 Bit mode */
1129 #if defined (__GNUC__)
1130 *((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits;
1131 #else
1132 *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
1133 #endif /* __GNUC__ */
1134 hi2s->pRxBuffPtr++;
1135 tmp_RxXferCount--;
1136 }
1137
1138 /* Check if an overrun occurs */
1139 if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
1140 {
1141 /* Clear overrun flag */
1142 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
1143
1144 /* Set the error code */
1145 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
1146 }
1147 }
1148
1149 /* Timeout management */
1150 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1151 {
1152 /* Set the error code */
1153 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
1154 hi2s->State = HAL_I2S_STATE_READY;
1155 __HAL_UNLOCK(hi2s);
1156 return HAL_ERROR;
1157 }
1158 }
1159
1160 hi2s->State = HAL_I2S_STATE_READY;
1161 __HAL_UNLOCK(hi2s);
1162 return HAL_OK;
1163 }
1164
1165 /**
1166 * @brief Transmit an amount of data in non-blocking mode with Interrupt
1167 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1168 * the configuration information for I2S module
1169 * @param pData a 16-bit pointer to data buffer.
1170 * @param Size number of data sample to be sent:
1171 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1172 * configuration phase, the Size parameter means the number of 16-bit data length
1173 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1174 * the Size parameter means the number of 16-bit data length.
1175 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1176 * between Master and Slave(example: audio streaming).
1177 * @retval HAL status
1178 */
1179 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
1180 {
1181 if ((pData == NULL) || (Size == 0UL))
1182 {
1183 return HAL_ERROR;
1184 }
1185
1186 /* Process Locked */
1187 __HAL_LOCK(hi2s);
1188
1189 if (hi2s->State != HAL_I2S_STATE_READY)
1190 {
1191 __HAL_UNLOCK(hi2s);
1192 return HAL_BUSY;
1193 }
1194
1195 /* Set state and reset error code */
1196 hi2s->State = HAL_I2S_STATE_BUSY_TX;
1197 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1198 hi2s->pTxBuffPtr = (uint16_t *)pData;
1199 hi2s->TxXferSize = Size;
1200 hi2s->TxXferCount = Size;
1201
1202 /* Initialize fields not used in handle to zero */
1203 hi2s->pRxBuffPtr = NULL;
1204 hi2s->RxXferSize = (uint16_t) 0UL;
1205 hi2s->RxXferCount = (uint16_t) 0UL;
1206
1207 /* Set the function for IT treatment */
1208 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
1209 {
1210 hi2s->TxISR = I2S_Transmit_32Bit_IT;
1211 }
1212 else
1213 {
1214 hi2s->TxISR = I2S_Transmit_16Bit_IT;
1215 }
1216
1217 /* Check if the I2S is already enabled */
1218 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1219 {
1220 /* Enable I2S peripheral */
1221 __HAL_I2S_ENABLE(hi2s);
1222 }
1223
1224 /* Enable TXP and UDR interrupt */
1225 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_UDR));
1226
1227 /* Enable TIFRE interrupt if the mode is Slave */
1228 if (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)
1229 {
1230 __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE);
1231 }
1232
1233 /* Start the transfer */
1234 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1235
1236 __HAL_UNLOCK(hi2s);
1237 return HAL_OK;
1238 }
1239
1240 /**
1241 * @brief Receive an amount of data in non-blocking mode with Interrupt
1242 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1243 * the configuration information for I2S module
1244 * @param pData a 16-bit pointer to the Receive data buffer.
1245 * @param Size number of data sample to be sent:
1246 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1247 * configuration phase, the Size parameter means the number of 16-bit data length
1248 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1249 * the Size parameter means the number of 16-bit data length.
1250 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1251 * between Master and Slave(example: audio streaming).
1252 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
1253 * between Master and Slave otherwise the I2S interrupt should be optimized.
1254 * @retval HAL status
1255 */
1256 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
1257 {
1258 if ((pData == NULL) || (Size == 0UL))
1259 {
1260 return HAL_ERROR;
1261 }
1262
1263 /* Process Locked */
1264 __HAL_LOCK(hi2s);
1265
1266 if (hi2s->State != HAL_I2S_STATE_READY)
1267 {
1268 __HAL_UNLOCK(hi2s);
1269 return HAL_BUSY;
1270 }
1271
1272 /* Set state and reset error code */
1273 hi2s->State = HAL_I2S_STATE_BUSY_RX;
1274 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1275 hi2s->pRxBuffPtr = pData;
1276 hi2s->RxXferSize = Size;
1277 hi2s->RxXferCount = Size;
1278
1279 /* Initialize fields not used in handle to zero */
1280 hi2s->pTxBuffPtr = NULL;
1281 hi2s->TxXferSize = (uint16_t) 0UL;
1282 hi2s->TxXferCount = (uint16_t) 0UL;
1283
1284 /* Set the function for IT treatment */
1285 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
1286 {
1287 hi2s->RxISR = I2S_Receive_32Bit_IT;
1288 }
1289 else
1290 {
1291 hi2s->RxISR = I2S_Receive_16Bit_IT;
1292 }
1293
1294 /* Check if the I2S is already enabled */
1295 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1296 {
1297 /* Enable I2S peripheral */
1298 __HAL_I2S_ENABLE(hi2s);
1299 }
1300 /* Enable RXP and ERR interrupt */
1301 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_OVR));
1302
1303 /* Enable TIFRE interrupt if the mode is Slave */
1304 if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
1305 {
1306 __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE);
1307 }
1308
1309 /* Start the transfer */
1310 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1311
1312 __HAL_UNLOCK(hi2s);
1313 return HAL_OK;
1314 }
1315
1316 /**
1317 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
1318 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1319 * the configuration information for I2S module
1320 * @param pTxData a 16-bit pointer to the Transmit data buffer.
1321 * @param pRxData a 16-bit pointer to the Receive data buffer.
1322 * @param Size number of data sample to be sent:
1323 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1324 * configuration phase, the Size parameter means the number of 16-bit data length
1325 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1326 * the Size parameter means the number of 16-bit data length.
1327 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1328 * between Master and Slave(example: audio streaming).
1329 * @retval HAL status
1330 */
1331 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
1332 uint16_t Size)
1333 {
1334 if (hi2s->State != HAL_I2S_STATE_READY)
1335 {
1336 __HAL_UNLOCK(hi2s);
1337 return HAL_BUSY;
1338 }
1339
1340 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1341 {
1342 return HAL_ERROR;
1343 }
1344
1345 /* Process Locked */
1346 __HAL_LOCK(hi2s);
1347
1348 hi2s->pTxBuffPtr = pTxData;
1349 hi2s->pRxBuffPtr = pRxData;
1350
1351 hi2s->TxXferSize = Size;
1352 hi2s->TxXferCount = Size;
1353 hi2s->RxXferSize = Size;
1354 hi2s->RxXferCount = Size;
1355
1356 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1357 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
1358
1359
1360 /* Set the function for IT treatment */
1361 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
1362 {
1363 hi2s->TxISR = I2S_Transmit_32Bit_IT;
1364 hi2s->RxISR = I2S_Receive_32Bit_IT;
1365 }
1366 else
1367 {
1368 hi2s->TxISR = I2S_Transmit_16Bit_IT;
1369 hi2s->RxISR = I2S_Receive_16Bit_IT;
1370 }
1371
1372 /* Check if the I2S is already enabled */
1373 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1374 {
1375 /* Enable I2S peripheral */
1376 __HAL_I2S_ENABLE(hi2s);
1377 }
1378
1379 /* Enable TXP, RXP, DXP, UDR, OVR interrupts */
1380 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_DXP | I2S_IT_UDR | I2S_IT_OVR));
1381
1382 /* Enable TIFRE interrupt if the mode is Slave */
1383 if (hi2s->Init.Mode == I2S_MODE_SLAVE_FULLDUPLEX)
1384 {
1385 __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE);
1386 }
1387
1388 /* Start the transfer */
1389 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1390
1391 __HAL_UNLOCK(hi2s);
1392 return HAL_OK;
1393
1394 }
1395
1396 /**
1397 * @brief Transmit an amount of data in non-blocking mode with DMA
1398 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1399 * the configuration information for I2S module
1400 * @param pData a 16-bit pointer to the Transmit data buffer.
1401 * @param Size number of data sample to be sent:
1402 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1403 * configuration phase, the Size parameter means the number of 16-bit data length
1404 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1405 * the Size parameter means the number of 16-bit data length.
1406 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1407 * between Master and Slave(example: audio streaming).
1408 * @retval HAL status
1409 */
1410 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
1411 {
1412 if ((pData == NULL) || (Size == 0UL))
1413 {
1414 return HAL_ERROR;
1415 }
1416
1417 /* Process Locked */
1418 __HAL_LOCK(hi2s);
1419
1420 if (hi2s->State != HAL_I2S_STATE_READY)
1421 {
1422 __HAL_UNLOCK(hi2s);
1423 return HAL_BUSY;
1424 }
1425
1426 /* Set state and reset error code */
1427 hi2s->State = HAL_I2S_STATE_BUSY_TX;
1428 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1429 hi2s->pTxBuffPtr = pData;
1430 hi2s->TxXferSize = Size;
1431 hi2s->TxXferCount = Size;
1432
1433 /* Init field not used in handle to zero */
1434 hi2s->pRxBuffPtr = NULL;
1435 hi2s->RxXferSize = (uint16_t)0UL;
1436 hi2s->RxXferCount = (uint16_t)0UL;
1437
1438 /* Set the I2S Tx DMA Half transfer complete callback */
1439 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
1440
1441 /* Set the I2S Tx DMA transfer complete callback */
1442 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
1443
1444 /* Set the DMA error callback */
1445 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
1446
1447 /* Enable the Tx DMA Stream/Channel */
1448 if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, hi2s->TxXferSize))
1449 {
1450 /* Update I2S error code */
1451 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1452 hi2s->State = HAL_I2S_STATE_READY;
1453
1454 __HAL_UNLOCK(hi2s);
1455 return HAL_ERROR;
1456 }
1457
1458 /* Check if the I2S Tx request is already enabled */
1459 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN))
1460 {
1461 /* Enable Tx DMA Request */
1462 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
1463 }
1464
1465 /* Check if the I2S is already enabled */
1466 if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE))
1467 {
1468 /* Enable I2S peripheral */
1469 __HAL_I2S_ENABLE(hi2s);
1470 }
1471
1472 /* Start the transfer */
1473 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1474
1475 __HAL_UNLOCK(hi2s);
1476 return HAL_OK;
1477 }
1478
1479 /**
1480 * @brief Receive an amount of data in non-blocking mode with DMA
1481 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1482 * the configuration information for I2S module
1483 * @param pData a 16-bit pointer to the Receive data buffer.
1484 * @param Size number of data sample to be sent:
1485 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1486 * configuration phase, the Size parameter means the number of 16-bit data length
1487 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1488 * the Size parameter means the number of 16-bit data length.
1489 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1490 * between Master and Slave(example: audio streaming).
1491 * @retval HAL status
1492 */
1493 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
1494 {
1495 if ((pData == NULL) || (Size == 0UL))
1496 {
1497 return HAL_ERROR;
1498 }
1499
1500 /* Process Locked */
1501 __HAL_LOCK(hi2s);
1502
1503 if (hi2s->State != HAL_I2S_STATE_READY)
1504 {
1505 __HAL_UNLOCK(hi2s);
1506 return HAL_BUSY;
1507 }
1508
1509 /* Set state and reset error code */
1510 hi2s->State = HAL_I2S_STATE_BUSY_RX;
1511 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1512 hi2s->pRxBuffPtr = pData;
1513 hi2s->RxXferSize = Size;
1514 hi2s->RxXferCount = Size;
1515
1516 /* Init field not used in handle to zero */
1517 hi2s->pTxBuffPtr = NULL;
1518 hi2s->TxXferSize = (uint16_t)0UL;
1519 hi2s->TxXferCount = (uint16_t)0UL;
1520
1521
1522 /* Set the I2S Rx DMA Half transfer complete callback */
1523 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
1524
1525 /* Set the I2S Rx DMA transfer complete callback */
1526 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
1527
1528 /* Set the DMA error callback */
1529 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
1530
1531 /* Enable the Rx DMA Stream/Channel */
1532 if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize))
1533 {
1534 /* Update I2S error code */
1535 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1536 hi2s->State = HAL_I2S_STATE_READY;
1537
1538 __HAL_UNLOCK(hi2s);
1539 return HAL_ERROR;
1540 }
1541
1542 /* Check if the I2S Rx request is already enabled */
1543 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN))
1544 {
1545 /* Enable Rx DMA Request */
1546 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
1547 }
1548
1549 /* Check if the I2S is already enabled */
1550 if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE))
1551 {
1552 /* Enable I2S peripheral */
1553 __HAL_I2S_ENABLE(hi2s);
1554 }
1555
1556 /* Start the transfer */
1557 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1558
1559 __HAL_UNLOCK(hi2s);
1560 return HAL_OK;
1561 }
1562
1563 /**
1564 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
1565 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1566 * the configuration information for I2S module
1567 * @param pTxData a 16-bit pointer to the Transmit data buffer.
1568 * @param pRxData a 16-bit pointer to the Receive data buffer.
1569 * @param Size number of data sample to be sent:
1570 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1571 * configuration phase, the Size parameter means the number of 16-bit data length
1572 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1573 * the Size parameter means the number of 16-bit data length.
1574 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1575 * between Master and Slave(example: audio streaming).
1576 * @retval HAL status
1577 */
1578 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
1579 uint16_t Size)
1580 {
1581 if (hi2s->State != HAL_I2S_STATE_READY)
1582 {
1583 __HAL_UNLOCK(hi2s);
1584 return HAL_BUSY;
1585 }
1586
1587 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1588 {
1589 return HAL_ERROR;
1590 }
1591
1592 /* Process Locked */
1593 __HAL_LOCK(hi2s);
1594
1595 hi2s->pTxBuffPtr = pTxData;
1596 hi2s->pRxBuffPtr = pRxData;
1597
1598 hi2s->TxXferSize = Size;
1599 hi2s->TxXferCount = Size;
1600 hi2s->RxXferSize = Size;
1601 hi2s->RxXferCount = Size;
1602
1603 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1604 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
1605
1606 /* Reset the Tx/Rx DMA bits */
1607 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
1608
1609 /* Set the I2S Rx DMA Half transfer complete callback */
1610 hi2s->hdmarx->XferHalfCpltCallback = I2SEx_DMATxRxHalfCplt;
1611
1612 /* Set the I2S Rx DMA transfer complete callback */
1613 hi2s->hdmarx->XferCpltCallback = I2SEx_DMATxRxCplt;
1614
1615 /* Set the I2S Rx DMA error callback */
1616 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
1617
1618 /* Enable the Tx DMA Stream/Channel */
1619 if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, hi2s->TxXferSize))
1620 {
1621 /* Update I2S error code */
1622 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1623 hi2s->State = HAL_I2S_STATE_READY;
1624
1625 __HAL_UNLOCK(hi2s);
1626 return HAL_ERROR;
1627 }
1628
1629 /* Check if the I2S Tx request is already enabled */
1630 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN))
1631 {
1632 /* Enable Tx DMA Request */
1633 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
1634 }
1635
1636 /* Enable the Rx DMA Stream/Channel */
1637 if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize))
1638 {
1639 /* Update I2S error code */
1640 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1641 hi2s->State = HAL_I2S_STATE_READY;
1642
1643 __HAL_UNLOCK(hi2s);
1644 return HAL_ERROR;
1645 }
1646
1647 /* Check if the I2S Rx request is already enabled */
1648 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN))
1649 {
1650 /* Enable Rx DMA Request */
1651 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
1652 }
1653
1654 /* Check if the I2S is already enabled */
1655 if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE))
1656 {
1657 /* Enable I2S peripheral */
1658 __HAL_I2S_ENABLE(hi2s);
1659 }
1660
1661 /* Start the transfer */
1662 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1663
1664 __HAL_UNLOCK(hi2s);
1665 return HAL_OK;
1666 }
1667
1668 /**
1669 * @brief Pauses the audio DMA Stream/Channel playing from the Media.
1670 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1671 * the configuration information for I2S module
1672 * @retval HAL status
1673 */
1674 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
1675 {
1676 /* Process Locked */
1677 __HAL_LOCK(hi2s);
1678
1679 uint32_t tickstart;
1680
1681 /* Get tick */
1682 tickstart = HAL_GetTick();
1683
1684
1685 /* Check if the I2S peripheral is in master mode */
1686 if (IS_I2S_MASTER(hi2s->Init.Mode))
1687 {
1688 /* Check if there is a transfer on-going */
1689 if (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) == 0UL)
1690 {
1691 /* Set error code to no on going transfer */
1692 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_NO_OGT);
1693 hi2s->State = HAL_I2S_STATE_READY;
1694
1695 __HAL_UNLOCK(hi2s);
1696 return HAL_ERROR;
1697 }
1698
1699 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSUSP);
1700
1701 while (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) != 0UL)
1702 {
1703 if ((((HAL_GetTick() - tickstart) >= I2S_TIMEOUT) && (I2S_TIMEOUT != HAL_MAX_DELAY)) || (I2S_TIMEOUT == 0U))
1704 {
1705 /* Set the I2S State ready */
1706 hi2s->State = HAL_I2S_STATE_READY;
1707
1708 /* Process Unlocked */
1709 __HAL_UNLOCK(hi2s);
1710
1711 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
1712 hi2s->State = HAL_I2S_STATE_READY;
1713 return HAL_TIMEOUT;
1714 }
1715 }
1716
1717 /* Disable I2S peripheral */
1718 __HAL_I2S_DISABLE(hi2s);
1719
1720 hi2s->State = HAL_I2S_STATE_READY;
1721
1722 /* Process Unlocked */
1723 __HAL_UNLOCK(hi2s);
1724
1725 return HAL_OK;
1726 }
1727 else
1728 {
1729 /* Set error code to not supported */
1730 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_NOT_SUPPORTED);
1731 hi2s->State = HAL_I2S_STATE_READY;
1732
1733 /* Process Unlocked */
1734 __HAL_UNLOCK(hi2s);
1735
1736 return HAL_ERROR;
1737 }
1738 }
1739
1740 /**
1741 * @brief Resumes the audio DMA Stream/Channel playing from the Media.
1742 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1743 * the configuration information for I2S module
1744 * @retval HAL status
1745 */
1746 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
1747 {
1748 /* Process Locked */
1749 __HAL_LOCK(hi2s);
1750
1751 if (hi2s->State != HAL_I2S_STATE_READY)
1752 {
1753 hi2s->State = HAL_I2S_STATE_READY;
1754
1755 __HAL_UNLOCK(hi2s);
1756 return HAL_ERROR;
1757 }
1758
1759 /* Set state and reset error code */
1760 hi2s->State = HAL_I2S_STATE_BUSY;
1761 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1762
1763 /* Enable I2S peripheral */
1764 __HAL_I2S_ENABLE(hi2s);
1765
1766 /* Start the transfer */
1767 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1768
1769 /* Process Unlocked */
1770 __HAL_UNLOCK(hi2s);
1771
1772 return HAL_OK;
1773 }
1774
1775 /**
1776 * @brief Stops the audio DMA Stream/Channel playing from the Media.
1777 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1778 * the configuration information for I2S module
1779 * @retval HAL status
1780 */
1781 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
1782 {
1783 HAL_StatusTypeDef errorcode = HAL_OK;
1784 /* The Lock is not implemented on this API to allow the user application
1785 to call the HAL I2S API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
1786 when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
1787 and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
1788 */
1789
1790 /* Disable the I2S Tx/Rx DMA requests */
1791 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
1792 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
1793
1794 /* Abort the I2S DMA tx Stream/Channel */
1795 if (hi2s->hdmatx != NULL)
1796 {
1797 /* Disable the I2S DMA tx Stream/Channel */
1798 if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
1799 {
1800 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1801 errorcode = HAL_ERROR;
1802 }
1803 }
1804
1805 /* Abort the I2S DMA rx Stream/Channel */
1806 if (hi2s->hdmarx != NULL)
1807 {
1808 /* Disable the I2S DMA rx Stream/Channel */
1809 if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
1810 {
1811 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1812 errorcode = HAL_ERROR;
1813 }
1814 }
1815
1816 /* Disable I2S peripheral */
1817 __HAL_I2S_DISABLE(hi2s);
1818
1819 hi2s->State = HAL_I2S_STATE_READY;
1820
1821 return errorcode;
1822 }
1823
1824 /**
1825 * @brief This function handles I2S interrupt request.
1826 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1827 * the configuration information for I2S module
1828 * @retval None
1829 */
1830 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
1831 {
1832 uint32_t i2sier = hi2s->Instance->IER;
1833 uint32_t i2ssr = hi2s->Instance->SR;
1834 uint32_t trigger = i2sier & i2ssr;
1835
1836 if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
1837 {
1838 /* I2S in mode Receiver ------------------------------------------------*/
1839 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_RXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_OVR))
1840 {
1841 hi2s->RxISR(hi2s);
1842 }
1843
1844 /* I2S Overrun error interrupt occurred -------------------------------------*/
1845 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_OVR))
1846 {
1847 /* Disable RXP and ERR interrupt */
1848 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
1849
1850 /* Clear Overrun flag */
1851 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
1852
1853 /* Set the I2S State ready */
1854 hi2s->State = HAL_I2S_STATE_READY;
1855
1856
1857 /* Set the error code and execute error callback*/
1858 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
1859 /* Call user error callback */
1860 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
1861 hi2s->ErrorCallback(hi2s);
1862 #else
1863 HAL_I2S_ErrorCallback(hi2s);
1864 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1865 }
1866 }
1867
1868 if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
1869 {
1870 /* I2S in mode Transmitter -----------------------------------------------*/
1871 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_TXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_UDR))
1872 {
1873 hi2s->TxISR(hi2s);
1874 }
1875
1876 /* I2S Underrun error interrupt occurred --------------------------------*/
1877 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_UDR))
1878 {
1879 /* Disable TXP and ERR interrupt */
1880 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
1881
1882 /* Clear Underrun flag */
1883 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
1884
1885 /* Set the I2S State ready */
1886 hi2s->State = HAL_I2S_STATE_READY;
1887
1888 /* Set the error code and execute error callback*/
1889 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
1890 /* Call user error callback */
1891 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
1892 hi2s->ErrorCallback(hi2s);
1893 #else
1894 HAL_I2S_ErrorCallback(hi2s);
1895 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1896 }
1897 }
1898 if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
1899 {
1900 /* I2S in mode Transmitter -----------------------------------------------*/
1901 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_DXP))
1902 {
1903 hi2s->TxISR(hi2s);
1904 hi2s->RxISR(hi2s);
1905 }
1906 /* I2S in mode Receiver ------------------------------------------------*/
1907 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_RXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_DXP))
1908 {
1909 hi2s->RxISR(hi2s);
1910 }
1911 /* I2S in mode Transmitter -----------------------------------------------*/
1912 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_TXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_DXP))
1913 {
1914 hi2s->TxISR(hi2s);
1915 }
1916
1917 /* I2S Underrun error interrupt occurred --------------------------------*/
1918 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_UDR))
1919 {
1920 /* Disable TXP and ERR interrupt */
1921 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
1922
1923 /* Clear Underrun flag */
1924 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
1925
1926 /* Set the I2S State ready */
1927 hi2s->State = HAL_I2S_STATE_READY;
1928
1929 /* Set the error code and execute error callback*/
1930 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
1931 /* Call user error callback */
1932 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
1933 hi2s->ErrorCallback(hi2s);
1934 #else
1935 HAL_I2S_ErrorCallback(hi2s);
1936 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1937 }
1938
1939 /* I2S Overrun error interrupt occurred -------------------------------------*/
1940 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_OVR))
1941 {
1942 /* Disable RXP and ERR interrupt */
1943 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
1944
1945 /* Clear Overrun flag */
1946 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
1947
1948 /* Set the I2S State ready */
1949 hi2s->State = HAL_I2S_STATE_READY;
1950
1951
1952 /* Set the error code and execute error callback*/
1953 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
1954
1955 /* Call user error callback */
1956 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
1957 hi2s->ErrorCallback(hi2s);
1958 #else
1959 HAL_I2S_ErrorCallback(hi2s);
1960 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1961 }
1962 }
1963 }
1964
1965 /**
1966 * @brief Tx Transfer Half completed callbacks
1967 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1968 * the configuration information for I2S module
1969 * @retval None
1970 */
1971 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
1972 {
1973 /* Prevent unused argument(s) compilation warning */
1974 UNUSED(hi2s);
1975
1976 /* NOTE : This function Should not be modified, when the callback is needed,
1977 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
1978 */
1979 }
1980
1981 /**
1982 * @brief Tx Transfer completed callbacks
1983 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1984 * the configuration information for I2S module
1985 * @retval None
1986 */
1987 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
1988 {
1989 /* Prevent unused argument(s) compilation warning */
1990 UNUSED(hi2s);
1991
1992 /* NOTE : This function Should not be modified, when the callback is needed,
1993 the HAL_I2S_TxCpltCallback could be implemented in the user file
1994 */
1995 }
1996
1997 /**
1998 * @brief Rx Transfer half completed callbacks
1999 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2000 * the configuration information for I2S module
2001 * @retval None
2002 */
2003 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
2004 {
2005 /* Prevent unused argument(s) compilation warning */
2006 UNUSED(hi2s);
2007
2008 /* NOTE : This function Should not be modified, when the callback is needed,
2009 the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
2010 */
2011 }
2012
2013 /**
2014 * @brief Rx Transfer completed callbacks
2015 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2016 * the configuration information for I2S module
2017 * @retval None
2018 */
2019 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
2020 {
2021 /* Prevent unused argument(s) compilation warning */
2022 UNUSED(hi2s);
2023
2024 /* NOTE : This function Should not be modified, when the callback is needed,
2025 the HAL_I2S_RxCpltCallback could be implemented in the user file
2026 */
2027 }
2028
2029 /**
2030 * @brief Rx Transfer half completed callbacks
2031 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2032 * the configuration information for I2S module
2033 * @retval None
2034 */
2035 __weak void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
2036 {
2037 /* Prevent unused argument(s) compilation warning */
2038 UNUSED(hi2s);
2039
2040 /* NOTE : This function Should not be modified, when the callback is needed,
2041 the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
2042 */
2043 }
2044
2045 /**
2046 * @brief Rx Transfer completed callbacks
2047 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2048 * the configuration information for I2S module
2049 * @retval None
2050 */
2051 __weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
2052 {
2053 /* Prevent unused argument(s) compilation warning */
2054 UNUSED(hi2s);
2055
2056 /* NOTE : This function Should not be modified, when the callback is needed,
2057 the HAL_I2S_RxCpltCallback could be implemented in the user file
2058 */
2059 }
2060
2061 /**
2062 * @brief I2S error callbacks
2063 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2064 * the configuration information for I2S module
2065 * @retval None
2066 */
2067 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
2068 {
2069 /* Prevent unused argument(s) compilation warning */
2070 UNUSED(hi2s);
2071
2072 /* NOTE : This function Should not be modified, when the callback is needed,
2073 the HAL_I2S_ErrorCallback could be implemented in the user file
2074 */
2075 }
2076
2077 /**
2078 * @}
2079 */
2080
2081 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
2082 * @brief Peripheral State functions
2083 *
2084 @verbatim
2085 ===============================================================================
2086 ##### Peripheral State and Errors functions #####
2087 ===============================================================================
2088 [..]
2089 This subsection permits to get in run-time the status of the peripheral
2090 and the data flow.
2091
2092 @endverbatim
2093 * @{
2094 */
2095
2096 /**
2097 * @brief Return the I2S state
2098 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2099 * the configuration information for I2S module
2100 * @retval HAL state
2101 */
2102 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
2103 {
2104 return hi2s->State;
2105 }
2106
2107 /**
2108 * @brief Return the I2S error code
2109 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2110 * the configuration information for I2S module
2111 * @retval I2S Error Code
2112 */
2113 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
2114 {
2115 return hi2s->ErrorCode;
2116 }
2117 /**
2118 * @}
2119 */
2120
2121
2122 /**
2123 * @brief DMA I2S transmit process complete callback
2124 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2125 * the configuration information for the specified DMA module.
2126 * @retval None
2127 */
2128 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
2129 {
2130 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
2131
2132 /* if DMA is configured in DMA_NORMAL Mode */
2133 if (hdma->Init.Mode == DMA_NORMAL)
2134 {
2135 /* Disable Tx DMA Request */
2136 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
2137
2138 hi2s->TxXferCount = (uint16_t) 0UL;
2139 hi2s->State = HAL_I2S_STATE_READY;
2140 }
2141 /* Call user Tx complete callback */
2142 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2143 hi2s->TxCpltCallback(hi2s);
2144 #else
2145 HAL_I2S_TxCpltCallback(hi2s);
2146 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2147 }
2148
2149 /**
2150 * @brief DMA I2S transmit process half complete callback
2151 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2152 * the configuration information for the specified DMA module.
2153 * @retval None
2154 */
2155 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
2156 {
2157 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
2158
2159 /* Call user Tx half complete callback */
2160 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2161 hi2s->TxHalfCpltCallback(hi2s);
2162 #else
2163 HAL_I2S_TxHalfCpltCallback(hi2s);
2164 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2165 }
2166
2167 /**
2168 * @brief DMA I2S receive process complete callback
2169 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2170 * the configuration information for the specified DMA module.
2171 * @retval None
2172 */
2173 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
2174 {
2175 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
2176
2177 /* if DMA is configured in DMA_NORMAL Mode */
2178 if (hdma->Init.Mode == DMA_NORMAL)
2179 {
2180 /* Disable Rx DMA Request */
2181 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
2182 hi2s->RxXferCount = (uint16_t)0UL;
2183 hi2s->State = HAL_I2S_STATE_READY;
2184 }
2185 /* Call user Rx complete callback */
2186 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2187 hi2s->RxCpltCallback(hi2s);
2188 #else
2189 HAL_I2S_RxCpltCallback(hi2s);
2190 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2191 }
2192
2193 /**
2194 * @brief DMA I2S receive process half complete callback
2195 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2196 * the configuration information for the specified DMA module.
2197 * @retval None
2198 */
2199 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
2200 {
2201 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
2202
2203 /* Call user Rx half complete callback */
2204 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2205 hi2s->RxHalfCpltCallback(hi2s);
2206 #else
2207 HAL_I2S_RxHalfCpltCallback(hi2s);
2208 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2209 }
2210
2211 /**
2212 * @brief DMA I2S transmit receive process complete callback
2213 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2214 * the configuration information for the specified DMA module.
2215 * @retval None
2216 */
2217 static void I2SEx_DMATxRxCplt(DMA_HandleTypeDef *hdma)
2218 {
2219 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2220
2221 /* Call user TxRx complete callback */
2222 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
2223 hi2s->TxRxCpltCallback(hi2s);
2224 #else
2225 HAL_I2SEx_TxRxCpltCallback(hi2s);
2226 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2227 }
2228
2229 /**
2230 * @brief DMA I2S transmit receive process half complete callback
2231 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2232 * the configuration information for the specified DMA module.
2233 * @retval None
2234 */
2235 static void I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef *hdma)
2236 {
2237 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2238
2239 /* Call user TxRx Half complete callback */
2240 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
2241 hi2s->TxRxHalfCpltCallback(hi2s);
2242 #else
2243 HAL_I2SEx_TxRxHalfCpltCallback(hi2s);
2244 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2245 }
2246
2247 /**
2248 * @brief DMA I2S communication error callback
2249 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2250 * the configuration information for the specified DMA module.
2251 * @retval None
2252 */
2253 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
2254 {
2255 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
2256
2257 /* Disable Rx and Tx DMA Request */
2258 CLEAR_BIT(hi2s->Instance->CFG1, (SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN));
2259 hi2s->TxXferCount = (uint16_t) 0UL;
2260 hi2s->RxXferCount = (uint16_t) 0UL;
2261
2262 hi2s->State = HAL_I2S_STATE_READY;
2263
2264 /* Set the error code and execute error callback*/
2265 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
2266 /* Call user error callback */
2267 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2268 hi2s->ErrorCallback(hi2s);
2269 #else
2270 HAL_I2S_ErrorCallback(hi2s);
2271 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2272 }
2273
2274 /**
2275 * @brief Manage the transmission 16-bit in Interrupt context
2276 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2277 * the configuration information for I2S module
2278 * @retval None
2279 */
2280 static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s)
2281 {
2282 /* Transmit data */
2283 #if defined (__GNUC__)
2284 __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
2285
2286 *ptxdr_16bits = *((uint16_t *)hi2s->pTxBuffPtr);
2287 #else
2288 *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
2289 #endif /* __GNUC__ */
2290 hi2s->pTxBuffPtr++;
2291 hi2s->TxXferCount--;
2292
2293 if (hi2s->TxXferCount == 0UL)
2294 {
2295 /* Disable TXP and ERR interrupt */
2296 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
2297
2298 if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) ||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
2299 {
2300 hi2s->State = HAL_I2S_STATE_READY;
2301 }
2302 /* Call user Tx complete callback */
2303 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2304 hi2s->TxCpltCallback(hi2s);
2305 #else
2306 HAL_I2S_TxCpltCallback(hi2s);
2307 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2308 }
2309 }
2310
2311 /**
2312 * @brief Manage the transmission 32-bit in Interrupt context
2313 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2314 * the configuration information for I2S module
2315 * @retval None
2316 */
2317 static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s)
2318 {
2319 /* Transmit data */
2320 hi2s->Instance->TXDR = *((uint32_t *)hi2s->pTxBuffPtr);
2321 hi2s->pTxBuffPtr += 2;
2322 hi2s->TxXferCount--;
2323
2324 if (hi2s->TxXferCount == 0UL)
2325 {
2326 /* Disable TXP and ERR interrupt */
2327 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
2328
2329 if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) ||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
2330 {
2331 hi2s->State = HAL_I2S_STATE_READY;
2332 }
2333 /* Call user Tx complete callback */
2334 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2335 hi2s->TxCpltCallback(hi2s);
2336 #else
2337 HAL_I2S_TxCpltCallback(hi2s);
2338 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2339 }
2340 }
2341
2342 /**
2343 * @brief Manage the reception 16-bit in Interrupt context
2344 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2345 * the configuration information for I2S module
2346 * @retval None
2347 */
2348 static void I2S_Receive_16Bit_IT(I2S_HandleTypeDef *hi2s)
2349 {
2350 /* Receive data */
2351 #if defined (__GNUC__)
2352 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
2353
2354 *((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits;
2355 #else
2356 *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
2357 #endif /* __GNUC__ */
2358 hi2s->pRxBuffPtr++;
2359 hi2s->RxXferCount--;
2360
2361 if (hi2s->RxXferCount == 0UL)
2362 {
2363 if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
2364 {
2365 /* Disable TXP, RXP, DXP, ERR interrupts */
2366 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_DXP | I2S_IT_ERR));
2367 }
2368 else
2369 {
2370 /* Disable RXP and ERR interrupt */
2371 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
2372 }
2373
2374 hi2s->State = HAL_I2S_STATE_READY;
2375 /* Call user Rx complete callback */
2376 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2377 if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
2378 {
2379 hi2s->TxRxCpltCallback(hi2s);
2380 }
2381 else
2382 {
2383 hi2s->RxCpltCallback(hi2s);
2384 }
2385 #else
2386 if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
2387 {
2388 HAL_I2SEx_TxRxCpltCallback(hi2s);
2389 }
2390 else
2391 {
2392 HAL_I2S_RxCpltCallback(hi2s);
2393 }
2394 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2395 }
2396 }
2397
2398 /**
2399 * @brief Manage the reception 32-bit in Interrupt context
2400 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2401 * the configuration information for I2S module
2402 * @retval None
2403 */
2404 static void I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s)
2405 {
2406 /* Receive data */
2407 *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
2408 hi2s->pRxBuffPtr += 2;
2409 hi2s->RxXferCount--;
2410
2411 if (hi2s->RxXferCount == 0UL)
2412 {
2413 if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
2414 {
2415 /* Disable TXP, RXP, DXP, ERR interrupts */
2416 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_DXP | I2S_IT_ERR));
2417 }
2418 else
2419 {
2420 /* Disable RXP and ERR interrupt */
2421 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
2422 }
2423
2424 hi2s->State = HAL_I2S_STATE_READY;
2425 /* Call user Rx complete callback */
2426 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2427 if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
2428 {
2429 hi2s->TxRxCpltCallback(hi2s);
2430 }
2431 else
2432 {
2433 hi2s->RxCpltCallback(hi2s);
2434 }
2435 #else
2436 if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
2437 {
2438 HAL_I2SEx_TxRxCpltCallback(hi2s);
2439 }
2440 else
2441 {
2442 HAL_I2S_RxCpltCallback(hi2s);
2443 }
2444 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2445 }
2446 }
2447
2448 /**
2449 * @brief This function handles I2S Communication Timeout.
2450 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2451 * the configuration information for I2S module
2452 * @param Flag Flag checked
2453 * @param State Value of the flag expected
2454 * @param Timeout Duration of the timeout
2455 * @retval HAL status
2456 */
2457 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout)
2458 {
2459 uint32_t tickstart;
2460
2461 /* Get tick */
2462 tickstart = HAL_GetTick();
2463
2464 /* Wait until flag is set to status*/
2465 while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
2466 {
2467 if (Timeout != HAL_MAX_DELAY)
2468 {
2469 if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0UL))
2470 {
2471 /* Set the I2S State ready */
2472 hi2s->State = HAL_I2S_STATE_READY;
2473
2474 /* Process Unlocked */
2475 __HAL_UNLOCK(hi2s);
2476
2477 return HAL_TIMEOUT;
2478 }
2479 }
2480 }
2481 return HAL_OK;
2482 }
2483
2484 /**
2485 * @}
2486 */
2487
2488 /**
2489 * @}
2490 */
2491
2492 /**
2493 * @}
2494 */
2495
2496 #endif /* HAL_I2S_MODULE_ENABLED */
2497
2498 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/