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[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_hal_spi.c
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1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_spi.c
4 * @author MCD Application Team
5 * @brief SPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### How to use this driver #####
16 ==============================================================================
17 [..]
18 The SPI HAL driver can be used as follows:
19
20 (#) Declare a SPI_HandleTypeDef handle structure, for example:
21 SPI_HandleTypeDef hspi;
22
23 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
24 (##) Enable the SPIx interface clock
25 (##) SPI pins configuration
26 (+++) Enable the clock for the SPI GPIOs
27 (+++) Configure these SPI pins as alternate function push-pull
28 (##) NVIC configuration if you need to use interrupt process or DMA process
29 (+++) Configure the SPIx interrupt priority
30 (+++) Enable the NVIC SPI IRQ handle
31 (##) DMA Configuration if you need to use DMA process
32 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
33 (+++) Enable the DMAx clock
34 (+++) Configure the DMA handle parameters
35 (+++) Configure the DMA Tx or Rx Stream/Channel
36 (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
38
39 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
40 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
41
42 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
43 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
44 by calling the customized HAL_SPI_MspInit() API.
45 [..]
46 Callback registration:
47
48 (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1UL
49 allows the user to configure dynamically the driver callbacks.
50 Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
51
52 Function HAL_SPI_RegisterCallback() allows to register following callbacks:
53 (+) TxCpltCallback : SPI Tx Completed callback
54 (+) RxCpltCallback : SPI Rx Completed callback
55 (+) TxRxCpltCallback : SPI TxRx Completed callback
56 (+) TxHalfCpltCallback : SPI Tx Half Completed callback
57 (+) RxHalfCpltCallback : SPI Rx Half Completed callback
58 (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
59 (+) ErrorCallback : SPI Error callback
60 (+) AbortCpltCallback : SPI Abort callback
61 (+) MspInitCallback : SPI Msp Init callback
62 (+) MspDeInitCallback : SPI Msp DeInit callback
63 This function takes as parameters the HAL peripheral handle, the Callback ID
64 and a pointer to the user callback function.
65
66
67 (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
68 weak function.
69 HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
70 and the Callback ID.
71 This function allows to reset following callbacks:
72 (+) TxCpltCallback : SPI Tx Completed callback
73 (+) RxCpltCallback : SPI Rx Completed callback
74 (+) TxRxCpltCallback : SPI TxRx Completed callback
75 (+) TxHalfCpltCallback : SPI Tx Half Completed callback
76 (+) RxHalfCpltCallback : SPI Rx Half Completed callback
77 (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
78 (+) ErrorCallback : SPI Error callback
79 (+) AbortCpltCallback : SPI Abort callback
80 (+) MspInitCallback : SPI Msp Init callback
81 (+) MspDeInitCallback : SPI Msp DeInit callback
82
83 By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
84 all callbacks are set to the corresponding weak functions:
85 examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
86 Exception done for MspInit and MspDeInit functions that are
87 reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
88 these callbacks are null (not registered beforehand).
89 If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
90 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
91
92 Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
93 Exception done MspInit/MspDeInit functions that can be registered/unregistered
94 in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
95 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
96 Then, the user first registers the MspInit/MspDeInit user callbacks
97 using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
98 or HAL_SPI_Init() function.
99
100 When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
101 not defined, the callback registering feature is not available
102 and weak (surcharged) callbacks are used.
103
104
105 [..]
106 Circular mode restriction:
107 (+) The DMA circular mode cannot be used when the SPI is configured in these modes:
108 (++) Master 2Lines RxOnly
109 (++) Master 1Line Rx
110 (+) The CRC feature is not managed when the DMA circular mode is enabled
111 (+) The functions HAL_SPI_DMAPause()/ HAL_SPI_DMAResume() are not supported. Return always
112 HAL_ERROR with ErrorCode set to HAL_SPI_ERROR_NOT_SUPPORTED.
113 Those functions are maintained for backward compatibility reasons.
114
115 @endverbatim
116 ******************************************************************************
117 * @attention
118 *
119 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
120 * All rights reserved.</center></h2>
121 *
122 * This software component is licensed by ST under BSD 3-Clause license,
123 * the "License"; You may not use this file except in compliance with the
124 * License. You may obtain a copy of the License at:
125 * opensource.org/licenses/BSD-3-Clause
126 *
127 ******************************************************************************
128 */
129
130 /* Includes ------------------------------------------------------------------*/
131 #include "stm32h7xx_hal.h"
132
133 /** @addtogroup STM32H7xx_HAL_Driver
134 * @{
135 */
136
137 /** @defgroup SPI SPI
138 * @brief SPI HAL module driver
139 * @{
140 */
141 #ifdef HAL_SPI_MODULE_ENABLED
142
143 /* Private typedef -----------------------------------------------------------*/
144 /* Private defines -----------------------------------------------------------*/
145 /** @defgroup SPI_Private_Constants SPI Private Constants
146 * @{
147 */
148 #define SPI_DEFAULT_TIMEOUT 100UL
149 /**
150 * @}
151 */
152
153 /* Private macros ------------------------------------------------------------*/
154 /* Private variables ---------------------------------------------------------*/
155 /* Private function prototypes -----------------------------------------------*/
156 /** @defgroup SPI_Private_Functions SPI Private Functions
157 * @{
158 */
159 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
160 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
161 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
162 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
163 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
164 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
165 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
166 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
167 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
168 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
169 static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus FlagStatus,
170 uint32_t Timeout, uint32_t Tickstart);
171 static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi);
172 static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi);
173 static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi);
174 static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi);
175 static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi);
176 static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi);
177 static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi);
178 static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi);
179 static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi);
180
181
182 /**
183 * @}
184 */
185
186 /* Exported functions --------------------------------------------------------*/
187 /** @defgroup SPI_Exported_Functions SPI Exported Functions
188 * @{
189 */
190
191 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
192 * @brief Initialization and Configuration functions
193 *
194 @verbatim
195 ===============================================================================
196 ##### Initialization and de-initialization functions #####
197 ===============================================================================
198 [..] This subsection provides a set of functions allowing to initialize and
199 de-initialize the SPIx peripheral:
200
201 (+) User must implement HAL_SPI_MspInit() function in which he configures
202 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
203
204 (+) Call the function HAL_SPI_Init() to configure the selected device with
205 the selected configuration:
206 (++) Mode
207 (++) Direction
208 (++) Data Size
209 (++) Clock Polarity and Phase
210 (++) NSS Management
211 (++) BaudRate Prescaler
212 (++) FirstBit
213 (++) TIMode
214 (++) CRC Calculation
215 (++) CRC Polynomial if CRC enabled
216 (++) CRC Length, used only with Data8 and Data16
217 (++) FIFO reception threshold
218 (++) FIFO transmission threshold
219
220 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
221 of the selected SPIx peripheral.
222
223 @endverbatim
224 * @{
225 */
226
227 /**
228 * @brief Initialize the SPI according to the specified parameters
229 * in the SPI_InitTypeDef and initialize the associated handle.
230 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
231 * the configuration information for SPI module.
232 * @retval HAL status
233 */
234 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
235 {
236 uint32_t crc_length = 0UL;
237 uint32_t packet_length;
238
239 /* Check the SPI handle allocation */
240 if (hspi == NULL)
241 {
242 return HAL_ERROR;
243 }
244
245 /* Check the parameters */
246 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
247 assert_param(IS_SPI_MODE(hspi->Init.Mode));
248 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
249 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
250 assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold));
251 assert_param(IS_SPI_NSS(hspi->Init.NSS));
252 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
253 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
254 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
255 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
256 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
257 {
258 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
259 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
260 }
261 #if (USE_SPI_CRC != 0UL)
262 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
263 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
264 {
265 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
266 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
267 assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.TxCRCInitializationPattern));
268 assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.RxCRCInitializationPattern));
269 }
270 #else
271 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
272 #endif /* USE_SPI_CRC */
273
274 /* Verify that the SPI instance supports Data Size higher than 16bits */
275 if ((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (hspi->Init.DataSize > SPI_DATASIZE_16BIT))
276 {
277 return HAL_ERROR;
278 }
279
280 /* Verify that the SPI instance supports requested data packing */
281 packet_length = SPI_GetPacketSize(hspi);
282 if (((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (packet_length > SPI_LOWEND_FIFO_SIZE)) ||
283 ((IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (packet_length > SPI_HIGHEND_FIFO_SIZE)))
284 {
285 return HAL_ERROR;
286 }
287
288 #if (USE_SPI_CRC != 0UL)
289 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
290 {
291 /* Verify that the SPI instance supports CRC Length higher than 16bits */
292 if ((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (hspi->Init.CRCLength > SPI_CRC_LENGTH_16BIT))
293 {
294 return HAL_ERROR;
295 }
296
297 /* Align the CRC Length on the data size */
298 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
299 {
300 crc_length = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) << SPI_CFG1_CRCSIZE_Pos;
301 }
302 else
303 {
304 crc_length = hspi->Init.CRCLength;
305 }
306
307 /* Verify that the CRC Length is higher than DataSize */
308 if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos))
309 {
310 return HAL_ERROR;
311 }
312 }
313 #endif /* USE_SPI_CRC */
314
315 if (hspi->State == HAL_SPI_STATE_RESET)
316 {
317 /* Allocate lock resource and initialize it */
318 hspi->Lock = HAL_UNLOCKED;
319
320 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
321 /* Init the SPI Callback settings */
322 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
323 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
324 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
325 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
326 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
327 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
328 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
329 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
330
331 if (hspi->MspInitCallback == NULL)
332 {
333 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
334 }
335
336 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
337 hspi->MspInitCallback(hspi);
338 #else
339 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
340 HAL_SPI_MspInit(hspi);
341 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
342 }
343
344 hspi->State = HAL_SPI_STATE_BUSY;
345
346 /* Disable the selected SPI peripheral */
347 __HAL_SPI_DISABLE(hspi);
348
349 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
350 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
351 Communication speed, First bit, CRC calculation state, CRC Length */
352
353 if ((hspi->Init.NSS == SPI_NSS_SOFT) && (hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW))
354 {
355 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI);
356 }
357
358 /* SPIx CFG1 Configuration */
359 WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_length |
360 hspi->Init.FifoThreshold | hspi->Init.DataSize));
361
362 /* SPIx CFG2 Configuration */
363 WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode | hspi->Init.NSSPolarity |
364 hspi->Init.NSS | hspi->Init.CLKPolarity | hspi->Init.CLKPhase |
365 hspi->Init.FirstBit | hspi->Init.Mode | hspi->Init.MasterInterDataIdleness |
366 hspi->Init.Direction | hspi->Init.MasterSSIdleness | hspi->Init.IOSwap));
367
368 #if (USE_SPI_CRC != 0UL)
369 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
370 /* Configure : CRC Polynomial */
371 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
372 {
373 /* Initialize TXCRC Pattern Initial Value */
374 if (hspi->Init.TxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)
375 {
376 SET_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI);
377 }
378 else
379 {
380 CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI);
381 }
382
383 /* Initialize RXCRC Pattern Initial Value */
384 if (hspi->Init.RxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)
385 {
386 SET_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI);
387 }
388 else
389 {
390 CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI);
391 }
392
393 /* Enable 33/17 bits CRC computation */
394 if (((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) ||
395 ((IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_32BIT)))
396 {
397 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
398 }
399 else
400 {
401 CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
402 }
403
404 /* Write CRC polynomial in SPI Register */
405 WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial);
406 }
407 #endif /* USE_SPI_CRC */
408
409 /* Insure that Underrun configuration is managed only by Salve */
410 if (hspi->Init.Mode == SPI_MODE_SLAVE)
411 {
412 /* Set Default Underrun configuration */
413 #if (USE_SPI_CRC != 0UL)
414 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_DISABLE)
415 #endif
416 {
417 MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, SPI_CFG1_UDRDET_0);
418 }
419 MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG_1);
420 }
421
422 #if defined(SPI_I2SCFGR_I2SMOD)
423 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
424 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
425 #endif /* SPI_I2SCFGR_I2SMOD */
426
427 /* Insure that AFCNTR is managed only by Master */
428 if ((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER)
429 {
430 /* Alternate function GPIOs control */
431 MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState));
432 }
433
434 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
435 hspi->State = HAL_SPI_STATE_READY;
436
437 return HAL_OK;
438 }
439
440 /**
441 * @brief De-Initialize the SPI peripheral.
442 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
443 * the configuration information for SPI module.
444 * @retval HAL status
445 */
446 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
447 {
448 /* Check the SPI handle allocation */
449 if (hspi == NULL)
450 {
451 return HAL_ERROR;
452 }
453
454 /* Check SPI Instance parameter */
455 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
456
457 hspi->State = HAL_SPI_STATE_BUSY;
458
459 /* Disable the SPI Peripheral Clock */
460 __HAL_SPI_DISABLE(hspi);
461
462 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
463 if (hspi->MspDeInitCallback == NULL)
464 {
465 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
466 }
467
468 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
469 hspi->MspDeInitCallback(hspi);
470 #else
471 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
472 HAL_SPI_MspDeInit(hspi);
473 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
474
475 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
476 hspi->State = HAL_SPI_STATE_RESET;
477
478 /* Release Lock */
479 __HAL_UNLOCK(hspi);
480
481 return HAL_OK;
482 }
483
484 /**
485 * @brief Initialize the SPI MSP.
486 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
487 * the configuration information for SPI module.
488 * @retval None
489 */
490 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
491 {
492 /* Prevent unused argument(s) compilation warning */
493 UNUSED(hspi);
494
495 /* NOTE : This function should not be modified, when the callback is needed,
496 the HAL_SPI_MspInit should be implemented in the user file
497 */
498 }
499
500 /**
501 * @brief De-Initialize the SPI MSP.
502 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
503 * the configuration information for SPI module.
504 * @retval None
505 */
506 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
507 {
508 /* Prevent unused argument(s) compilation warning */
509 UNUSED(hspi);
510
511 /* NOTE : This function should not be modified, when the callback is needed,
512 the HAL_SPI_MspDeInit should be implemented in the user file
513 */
514 }
515
516 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
517 /**
518 * @brief Register a User SPI Callback
519 * To be used instead of the weak predefined callback
520 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
521 * the configuration information for the specified SPI.
522 * @param CallbackID ID of the callback to be registered
523 * @param pCallback pointer to the Callback function
524 * @retval HAL status
525 */
526 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
527 {
528 HAL_StatusTypeDef status = HAL_OK;
529
530 if (pCallback == NULL)
531 {
532 /* Update the error code */
533 hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
534
535 return HAL_ERROR;
536 }
537 /* Process locked */
538 __HAL_LOCK(hspi);
539
540 if (HAL_SPI_STATE_READY == hspi->State)
541 {
542 switch (CallbackID)
543 {
544 case HAL_SPI_TX_COMPLETE_CB_ID :
545 hspi->TxCpltCallback = pCallback;
546 break;
547
548 case HAL_SPI_RX_COMPLETE_CB_ID :
549 hspi->RxCpltCallback = pCallback;
550 break;
551
552 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
553 hspi->TxRxCpltCallback = pCallback;
554 break;
555
556 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
557 hspi->TxHalfCpltCallback = pCallback;
558 break;
559
560 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
561 hspi->RxHalfCpltCallback = pCallback;
562 break;
563
564 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
565 hspi->TxRxHalfCpltCallback = pCallback;
566 break;
567
568 case HAL_SPI_ERROR_CB_ID :
569 hspi->ErrorCallback = pCallback;
570 break;
571
572 case HAL_SPI_ABORT_CB_ID :
573 hspi->AbortCpltCallback = pCallback;
574 break;
575
576 case HAL_SPI_MSPINIT_CB_ID :
577 hspi->MspInitCallback = pCallback;
578 break;
579
580 case HAL_SPI_MSPDEINIT_CB_ID :
581 hspi->MspDeInitCallback = pCallback;
582 break;
583
584 default :
585 /* Update the error code */
586 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
587
588 /* Return error status */
589 status = HAL_ERROR;
590 break;
591 }
592 }
593 else if (HAL_SPI_STATE_RESET == hspi->State)
594 {
595 switch (CallbackID)
596 {
597 case HAL_SPI_MSPINIT_CB_ID :
598 hspi->MspInitCallback = pCallback;
599 break;
600
601 case HAL_SPI_MSPDEINIT_CB_ID :
602 hspi->MspDeInitCallback = pCallback;
603 break;
604
605 default :
606 /* Update the error code */
607 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
608
609 /* Return error status */
610 status = HAL_ERROR;
611 break;
612 }
613 }
614 else
615 {
616 /* Update the error code */
617 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
618
619 /* Return error status */
620 status = HAL_ERROR;
621 }
622
623 /* Release Lock */
624 __HAL_UNLOCK(hspi);
625 return status;
626 }
627
628 /**
629 * @brief Unregister an SPI Callback
630 * SPI callback is redirected to the weak predefined callback
631 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
632 * the configuration information for the specified SPI.
633 * @param CallbackID ID of the callback to be unregistered
634 * @retval HAL status
635 */
636 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
637 {
638 HAL_StatusTypeDef status = HAL_OK;
639
640 /* Process locked */
641 __HAL_LOCK(hspi);
642
643 if (HAL_SPI_STATE_READY == hspi->State)
644 {
645 switch (CallbackID)
646 {
647 case HAL_SPI_TX_COMPLETE_CB_ID :
648 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
649 break;
650
651 case HAL_SPI_RX_COMPLETE_CB_ID :
652 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
653 break;
654
655 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
656 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
657 break;
658
659 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
660 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
661 break;
662
663 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
664 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
665 break;
666
667 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
668 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
669 break;
670
671 case HAL_SPI_ERROR_CB_ID :
672 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
673 break;
674
675 case HAL_SPI_ABORT_CB_ID :
676 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
677 break;
678
679 case HAL_SPI_MSPINIT_CB_ID :
680 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
681 break;
682
683 case HAL_SPI_MSPDEINIT_CB_ID :
684 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
685 break;
686
687 default :
688 /* Update the error code */
689 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
690
691 /* Return error status */
692 status = HAL_ERROR;
693 break;
694 }
695 }
696 else if (HAL_SPI_STATE_RESET == hspi->State)
697 {
698 switch (CallbackID)
699 {
700 case HAL_SPI_MSPINIT_CB_ID :
701 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
702 break;
703
704 case HAL_SPI_MSPDEINIT_CB_ID :
705 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
706 break;
707
708 default :
709 /* Update the error code */
710 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
711
712 /* Return error status */
713 status = HAL_ERROR;
714 break;
715 }
716 }
717 else
718 {
719 /* Update the error code */
720 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
721
722 /* Return error status */
723 status = HAL_ERROR;
724 }
725
726 /* Release Lock */
727 __HAL_UNLOCK(hspi);
728 return status;
729 }
730 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
731 /**
732 * @}
733 */
734
735 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
736 * @brief Data transfers functions
737 *
738 @verbatim
739 ==============================================================================
740 ##### IO operation functions #####
741 ===============================================================================
742 [..]
743 This subsection provides a set of functions allowing to manage the SPI
744 data transfers.
745
746 [..] The SPI supports master and slave mode :
747
748 (#) There are two modes of transfer:
749 (##) Blocking mode: The communication is performed in polling mode.
750 The HAL status of all data processing is returned by the same function
751 after finishing transfer.
752 (##) No-Blocking mode: The communication is performed using Interrupts
753 or DMA, These APIs return the HAL status.
754 The end of the data processing will be indicated through the
755 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
756 using DMA mode.
757 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
758 will be executed respectively at the end of the transmit or Receive process
759 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
760
761 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
762 exist for 1Line (simplex) and 2Lines (full duplex) modes.
763
764 @endverbatim
765 * @{
766 */
767
768 /**
769 * @brief Transmit an amount of data in blocking mode.
770 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
771 * the configuration information for SPI module.
772 * @param pData : pointer to data buffer
773 * @param Size : amount of data to be sent
774 * @param Timeout: Timeout duration
775 * @retval HAL status
776 */
777 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
778 {
779 #if defined (__GNUC__)
780 __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
781 #endif /* __GNUC__ */
782
783 uint32_t tickstart;
784 HAL_StatusTypeDef errorcode = HAL_OK;
785
786 /* Check Direction parameter */
787 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
788
789 /* Process Locked */
790 __HAL_LOCK(hspi);
791
792 /* Init tickstart for timeout management*/
793 tickstart = HAL_GetTick();
794
795 if (hspi->State != HAL_SPI_STATE_READY)
796 {
797 errorcode = HAL_BUSY;
798 __HAL_UNLOCK(hspi);
799 return errorcode;
800 }
801
802 if ((pData == NULL) || (Size == 0UL))
803 {
804 errorcode = HAL_ERROR;
805 __HAL_UNLOCK(hspi);
806 return errorcode;
807 }
808
809 /* Set the transaction information */
810 hspi->State = HAL_SPI_STATE_BUSY_TX;
811 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
812 hspi->pTxBuffPtr = (uint8_t *)pData;
813 hspi->TxXferSize = Size;
814 hspi->TxXferCount = Size;
815
816 /*Init field not used in handle to zero */
817 hspi->pRxBuffPtr = NULL;
818 hspi->RxXferSize = (uint16_t) 0UL;
819 hspi->RxXferCount = (uint16_t) 0UL;
820 hspi->TxISR = NULL;
821 hspi->RxISR = NULL;
822
823 /* Configure communication direction : 1Line */
824 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
825 {
826 SPI_1LINE_TX(hspi);
827 }
828
829 /* Set the number of data at current transfer */
830 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
831
832 /* Enable SPI peripheral */
833 __HAL_SPI_ENABLE(hspi);
834
835 if (hspi->Init.Mode == SPI_MODE_MASTER)
836 {
837 /* Master transfer start */
838 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
839 }
840
841 /* Transmit data in 32 Bit mode */
842 if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
843 {
844 /* Transmit data in 32 Bit mode */
845 while (hspi->TxXferCount > 0UL)
846 {
847 /* Wait until TXP flag is set to send data */
848 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
849 {
850 *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
851 hspi->pTxBuffPtr += sizeof(uint32_t);
852 hspi->TxXferCount--;
853 }
854 else
855 {
856 /* Timeout management */
857 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
858 {
859 /* Call standard close procedure with error check */
860 SPI_CloseTransfer(hspi);
861
862 /* Process Unlocked */
863 __HAL_UNLOCK(hspi);
864
865 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
866 hspi->State = HAL_SPI_STATE_READY;
867 return HAL_ERROR;
868 }
869 }
870 }
871 }
872 /* Transmit data in 16 Bit mode */
873 else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
874 {
875 /* Transmit data in 16 Bit mode */
876 while (hspi->TxXferCount > 0UL)
877 {
878 /* Wait until TXP flag is set to send data */
879 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
880 {
881 if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
882 {
883 *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
884 hspi->pTxBuffPtr += sizeof(uint32_t);
885 hspi->TxXferCount -= (uint16_t)2UL;
886 }
887 else
888 {
889 #if defined (__GNUC__)
890 *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
891 #else
892 *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
893 #endif /* __GNUC__ */
894 hspi->pTxBuffPtr += sizeof(uint16_t);
895 hspi->TxXferCount--;
896 }
897 }
898 else
899 {
900 /* Timeout management */
901 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
902 {
903 /* Call standard close procedure with error check */
904 SPI_CloseTransfer(hspi);
905
906 /* Process Unlocked */
907 __HAL_UNLOCK(hspi);
908
909 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
910 hspi->State = HAL_SPI_STATE_READY;
911 return HAL_ERROR;
912 }
913 }
914 }
915 }
916 /* Transmit data in 8 Bit mode */
917 else
918 {
919 while (hspi->TxXferCount > 0UL)
920 {
921 /* Wait until TXP flag is set to send data */
922 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
923 {
924 if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
925 {
926 *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
927 hspi->pTxBuffPtr += sizeof(uint32_t);
928 hspi->TxXferCount -= (uint16_t)4UL;
929 }
930 else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
931 {
932 #if defined (__GNUC__)
933 *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
934 #else
935 *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
936 #endif /* __GNUC__ */
937 hspi->pTxBuffPtr += sizeof(uint16_t);
938 hspi->TxXferCount -= (uint16_t)2UL;
939 }
940 else
941 {
942 *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
943 hspi->pTxBuffPtr += sizeof(uint8_t);
944 hspi->TxXferCount--;
945 }
946 }
947 else
948 {
949 /* Timeout management */
950 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
951 {
952 /* Call standard close procedure with error check */
953 SPI_CloseTransfer(hspi);
954
955 /* Process Unlocked */
956 __HAL_UNLOCK(hspi);
957
958 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
959 hspi->State = HAL_SPI_STATE_READY;
960 return HAL_ERROR;
961 }
962 }
963 }
964 }
965
966 /* Wait for Tx (and CRC) data to be sent */
967 if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK)
968 {
969 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
970 }
971
972 /* Call standard close procedure with error check */
973 SPI_CloseTransfer(hspi);
974
975 /* Process Unlocked */
976 __HAL_UNLOCK(hspi);
977
978 hspi->State = HAL_SPI_STATE_READY;
979
980 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
981 {
982 return HAL_ERROR;
983 }
984 return errorcode;
985 }
986
987 /**
988 * @brief Receive an amount of data in blocking mode.
989 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
990 * the configuration information for SPI module.
991 * @param pData : pointer to data buffer
992 * @param Size : amount of data to be received
993 * @param Timeout: Timeout duration
994 * @retval HAL status
995 */
996 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
997 {
998 uint32_t tickstart;
999 HAL_StatusTypeDef errorcode = HAL_OK;
1000 #if defined (__GNUC__)
1001 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
1002 #endif /* __GNUC__ */
1003
1004 /* Check Direction parameter */
1005 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
1006
1007 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
1008 {
1009 hspi->State = HAL_SPI_STATE_BUSY_RX;
1010 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1011 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
1012 }
1013
1014 /* Process Locked */
1015 __HAL_LOCK(hspi);
1016
1017 /* Init tickstart for timeout management*/
1018 tickstart = HAL_GetTick();
1019
1020 if (hspi->State != HAL_SPI_STATE_READY)
1021 {
1022 errorcode = HAL_BUSY;
1023 __HAL_UNLOCK(hspi);
1024 return errorcode;
1025 }
1026
1027 if ((pData == NULL) || (Size == 0UL))
1028 {
1029 errorcode = HAL_ERROR;
1030 __HAL_UNLOCK(hspi);
1031 return errorcode;
1032 }
1033
1034 /* Set the transaction information */
1035 hspi->State = HAL_SPI_STATE_BUSY_RX;
1036 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1037 hspi->pRxBuffPtr = (uint8_t *)pData;
1038 hspi->RxXferSize = Size;
1039 hspi->RxXferCount = Size;
1040
1041 /*Init field not used in handle to zero */
1042 hspi->pTxBuffPtr = NULL;
1043 hspi->TxXferSize = (uint16_t) 0UL;
1044 hspi->TxXferCount = (uint16_t) 0UL;
1045 hspi->RxISR = NULL;
1046 hspi->TxISR = NULL;
1047
1048 /* Configure communication direction: 1Line */
1049 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1050 {
1051 SPI_1LINE_RX(hspi);
1052 }
1053
1054 /* Set the number of data at current transfer */
1055 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
1056
1057 /* Enable SPI peripheral */
1058 __HAL_SPI_ENABLE(hspi);
1059
1060 if (hspi->Init.Mode == SPI_MODE_MASTER)
1061 {
1062 /* Master transfer start */
1063 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
1064 }
1065
1066 /* Receive data in 32 Bit mode */
1067 if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
1068 {
1069 /* Transfer loop */
1070 while (hspi->RxXferCount > 0UL)
1071 {
1072 /* Check the RXWNE/EOT flag */
1073 if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL)
1074 {
1075 *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
1076 hspi->pRxBuffPtr += sizeof(uint32_t);
1077 hspi->RxXferCount--;
1078 }
1079 else
1080 {
1081 /* Timeout management */
1082 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1083 {
1084 /* Call standard close procedure with error check */
1085 SPI_CloseTransfer(hspi);
1086
1087 /* Process Unlocked */
1088 __HAL_UNLOCK(hspi);
1089
1090 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
1091 hspi->State = HAL_SPI_STATE_READY;
1092 return HAL_ERROR;
1093 }
1094 }
1095 }
1096 }
1097 /* Receive data in 16 Bit mode */
1098 else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1099 {
1100 /* Transfer loop */
1101 while (hspi->RxXferCount > 0UL)
1102 {
1103 /* Check the RXWNE/FRLVL flag */
1104 if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL)
1105 {
1106 if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
1107 {
1108 *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
1109 hspi->pRxBuffPtr += sizeof(uint32_t);
1110 hspi->RxXferCount -= (uint16_t)2UL;
1111 }
1112 else
1113 {
1114 #if defined (__GNUC__)
1115 *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
1116 #else
1117 *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
1118 #endif /* __GNUC__ */
1119 hspi->pRxBuffPtr += sizeof(uint16_t);
1120 hspi->RxXferCount--;
1121 }
1122 }
1123 else
1124 {
1125 /* Timeout management */
1126 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1127 {
1128 /* Call standard close procedure with error check */
1129 SPI_CloseTransfer(hspi);
1130
1131 /* Process Unlocked */
1132 __HAL_UNLOCK(hspi);
1133
1134 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
1135 hspi->State = HAL_SPI_STATE_READY;
1136 return HAL_ERROR;
1137 }
1138 }
1139 }
1140 }
1141 /* Receive data in 8 Bit mode */
1142 else
1143 {
1144 /* Transfer loop */
1145 while (hspi->RxXferCount > 0UL)
1146 {
1147 /* Check the RXWNE/FRLVL flag */
1148 if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL)
1149 {
1150 if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
1151 {
1152 *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
1153 hspi->pRxBuffPtr += sizeof(uint32_t);
1154 hspi->RxXferCount -= (uint16_t)4UL;
1155 }
1156 else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_RX_FIFO_1PACKET)
1157 {
1158 #if defined (__GNUC__)
1159 *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
1160 #else
1161 *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
1162 #endif /* __GNUC__ */
1163 hspi->pRxBuffPtr += sizeof(uint16_t);
1164 hspi->RxXferCount -= (uint16_t)2UL;
1165 }
1166 else
1167 {
1168 *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
1169 hspi->pRxBuffPtr += sizeof(uint8_t);
1170 hspi->RxXferCount--;
1171 }
1172 }
1173 else
1174 {
1175 /* Timeout management */
1176 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1177 {
1178 /* Call standard close procedure with error check */
1179 SPI_CloseTransfer(hspi);
1180
1181 /* Process Unlocked */
1182 __HAL_UNLOCK(hspi);
1183
1184 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
1185 hspi->State = HAL_SPI_STATE_READY;
1186 return HAL_ERROR;
1187 }
1188 }
1189 }
1190 }
1191
1192 #if (USE_SPI_CRC != 0UL)
1193 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1194 {
1195 /* Wait for crc data to be received */
1196 if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK)
1197 {
1198 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
1199 }
1200 }
1201 #endif /* USE_SPI_CRC */
1202
1203 /* Call standard close procedure with error check */
1204 SPI_CloseTransfer(hspi);
1205
1206 /* Process Unlocked */
1207 __HAL_UNLOCK(hspi);
1208
1209 hspi->State = HAL_SPI_STATE_READY;
1210
1211 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1212 {
1213 return HAL_ERROR;
1214 }
1215 return errorcode;
1216 }
1217
1218 /**
1219 * @brief Transmit and Receive an amount of data in blocking mode.
1220 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1221 * the configuration information for SPI module.
1222 * @param pTxData: pointer to transmission data buffer
1223 * @param pRxData: pointer to reception data buffer
1224 * @param Size : amount of data to be sent and received
1225 * @param Timeout: Timeout duration
1226 * @retval HAL status
1227 */
1228 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
1229 uint32_t Timeout)
1230 {
1231 HAL_SPI_StateTypeDef tmp_state;
1232 HAL_StatusTypeDef errorcode = HAL_OK;
1233 #if defined (__GNUC__)
1234 __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
1235 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
1236 #endif /* __GNUC__ */
1237
1238 uint32_t tickstart;
1239 uint32_t tmp_mode;
1240 uint16_t initial_TxXferCount;
1241 uint16_t initial_RxXferCount;
1242
1243 /* Check Direction parameter */
1244 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1245
1246 /* Process Locked */
1247 __HAL_LOCK(hspi);
1248
1249 /* Init tickstart for timeout management*/
1250 tickstart = HAL_GetTick();
1251
1252 initial_TxXferCount = Size;
1253 initial_RxXferCount = Size;
1254 tmp_state = hspi->State;
1255 tmp_mode = hspi->Init.Mode;
1256
1257 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1258 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1259 {
1260 errorcode = HAL_BUSY;
1261 __HAL_UNLOCK(hspi);
1262 return errorcode;
1263 }
1264
1265 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
1266 {
1267 errorcode = HAL_ERROR;
1268 __HAL_UNLOCK(hspi);
1269 return errorcode;
1270 }
1271
1272 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1273 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1274 {
1275 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1276 }
1277
1278 /* Set the transaction information */
1279 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1280 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1281 hspi->RxXferCount = Size;
1282 hspi->RxXferSize = Size;
1283 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1284 hspi->TxXferCount = Size;
1285 hspi->TxXferSize = Size;
1286
1287 /*Init field not used in handle to zero */
1288 hspi->RxISR = NULL;
1289 hspi->TxISR = NULL;
1290
1291 /* Set the number of data at current transfer */
1292 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
1293
1294 __HAL_SPI_ENABLE(hspi);
1295
1296 if (hspi->Init.Mode == SPI_MODE_MASTER)
1297 {
1298 /* Master transfer start */
1299 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
1300 }
1301
1302 /* Transmit and Receive data in 32 Bit mode */
1303 if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
1304 {
1305 while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
1306 {
1307 /* Check TXP flag */
1308 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL))
1309 {
1310 *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
1311 hspi->pTxBuffPtr += sizeof(uint32_t);
1312 hspi->TxXferCount --;
1313 initial_TxXferCount = hspi->TxXferCount;
1314 }
1315
1316 /* Check RXWNE/EOT flag */
1317 if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) && (initial_RxXferCount > 0UL))
1318 {
1319 *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
1320 hspi->pRxBuffPtr += sizeof(uint32_t);
1321 hspi->RxXferCount --;
1322 initial_RxXferCount = hspi->RxXferCount;
1323 }
1324
1325 /* Timeout management */
1326 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1327 {
1328 /* Call standard close procedure with error check */
1329 SPI_CloseTransfer(hspi);
1330
1331 /* Process Unlocked */
1332 __HAL_UNLOCK(hspi);
1333
1334 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
1335 hspi->State = HAL_SPI_STATE_READY;
1336 return HAL_ERROR;
1337 }
1338 }
1339 }
1340 /* Transmit and Receive data in 16 Bit mode */
1341 else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1342 {
1343 while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
1344 {
1345 /* Check TXP flag */
1346 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP) && (initial_TxXferCount > 0UL))
1347 {
1348 if ((initial_TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
1349 {
1350 *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
1351 hspi->pTxBuffPtr += sizeof(uint32_t);
1352 hspi->TxXferCount -= (uint16_t)2UL;
1353 initial_TxXferCount = hspi->TxXferCount;
1354 }
1355 else
1356 {
1357 #if defined (__GNUC__)
1358 *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
1359 #else
1360 *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
1361 #endif /* __GNUC__ */
1362 hspi->pTxBuffPtr += sizeof(uint16_t);
1363 hspi->TxXferCount--;
1364 initial_TxXferCount = hspi->TxXferCount;
1365 }
1366 }
1367
1368 /* Check RXWNE/FRLVL flag */
1369 if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) && (initial_RxXferCount > 0UL))
1370 {
1371 if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
1372 {
1373 *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
1374 hspi->pRxBuffPtr += sizeof(uint32_t);
1375 hspi->RxXferCount -= (uint16_t)2UL;
1376 initial_RxXferCount = hspi->RxXferCount;
1377 }
1378 else
1379 {
1380 #if defined (__GNUC__)
1381 *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
1382 #else
1383 *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
1384 #endif /* __GNUC__ */
1385 hspi->pRxBuffPtr += sizeof(uint16_t);
1386 hspi->RxXferCount--;
1387 initial_RxXferCount = hspi->RxXferCount;
1388 }
1389 }
1390
1391 /* Timeout management */
1392 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1393 {
1394 /* Call standard close procedure with error check */
1395 SPI_CloseTransfer(hspi);
1396
1397 /* Process Unlocked */
1398 __HAL_UNLOCK(hspi);
1399
1400 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
1401 hspi->State = HAL_SPI_STATE_READY;
1402 return HAL_ERROR;
1403 }
1404 }
1405 }
1406 /* Transmit and Receive data in 8 Bit mode */
1407 else
1408 {
1409 while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
1410 {
1411 /* check TXP flag */
1412 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL))
1413 {
1414 if ((initial_TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
1415 {
1416 *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
1417 hspi->pTxBuffPtr += sizeof(uint32_t);
1418 hspi->TxXferCount -= (uint16_t)4UL;
1419 initial_TxXferCount = hspi->TxXferCount;
1420 }
1421 else if ((initial_TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
1422 {
1423 #if defined (__GNUC__)
1424 *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
1425 #else
1426 *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
1427 #endif /* __GNUC__ */
1428 hspi->pTxBuffPtr += sizeof(uint16_t);
1429 hspi->TxXferCount -= (uint16_t)2UL;
1430 initial_TxXferCount = hspi->TxXferCount;
1431 }
1432 else
1433 {
1434 *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
1435 hspi->pTxBuffPtr += sizeof(uint8_t);
1436 hspi->TxXferCount--;
1437 initial_TxXferCount = hspi->TxXferCount;
1438 }
1439 }
1440
1441 /* Wait until RXWNE/FRLVL flag is reset */
1442 if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) && (initial_RxXferCount > 0UL))
1443 {
1444 if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
1445 {
1446 *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
1447 hspi->pRxBuffPtr += sizeof(uint32_t);
1448 hspi->RxXferCount -= (uint16_t)4UL;
1449 initial_RxXferCount = hspi->RxXferCount;
1450 }
1451 else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_RX_FIFO_1PACKET)
1452 {
1453 #if defined (__GNUC__)
1454 *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
1455 #else
1456 *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
1457 #endif /* __GNUC__ */
1458 hspi->pRxBuffPtr += sizeof(uint16_t);
1459 hspi->RxXferCount -= (uint16_t)2UL;
1460 initial_RxXferCount = hspi->RxXferCount;
1461 }
1462 else
1463 {
1464 *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
1465 hspi->pRxBuffPtr += sizeof(uint8_t);
1466 hspi->RxXferCount--;
1467 initial_RxXferCount = hspi->RxXferCount;
1468 }
1469 }
1470
1471 /* Timeout management */
1472 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1473 {
1474 /* Call standard close procedure with error check */
1475 SPI_CloseTransfer(hspi);
1476
1477 /* Process Unlocked */
1478 __HAL_UNLOCK(hspi);
1479
1480 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
1481 hspi->State = HAL_SPI_STATE_READY;
1482 return HAL_ERROR;
1483 }
1484 }
1485 }
1486
1487 /* Wait for Tx/Rx (and CRC) data to be sent/received */
1488 if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK)
1489 {
1490 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
1491 }
1492
1493 /* Call standard close procedure with error check */
1494 SPI_CloseTransfer(hspi);
1495
1496 /* Process Unlocked */
1497 __HAL_UNLOCK(hspi);
1498
1499 hspi->State = HAL_SPI_STATE_READY;
1500
1501 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1502 {
1503 return HAL_ERROR;
1504 }
1505 return errorcode;
1506 }
1507
1508 /**
1509 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
1510 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1511 * the configuration information for SPI module.
1512 * @param pData: pointer to data buffer
1513 * @param Size : amount of data to be sent
1514 * @retval HAL status
1515 */
1516 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1517 {
1518 HAL_StatusTypeDef errorcode = HAL_OK;
1519
1520 /* Check Direction parameter */
1521 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
1522
1523 /* Process Locked */
1524 __HAL_LOCK(hspi);
1525
1526 if ((pData == NULL) || (Size == 0UL))
1527 {
1528 errorcode = HAL_ERROR;
1529 __HAL_UNLOCK(hspi);
1530 return errorcode;
1531 }
1532
1533 if (hspi->State != HAL_SPI_STATE_READY)
1534 {
1535 errorcode = HAL_BUSY;
1536 __HAL_UNLOCK(hspi);
1537 return errorcode;
1538 }
1539
1540 /* Set the transaction information */
1541 hspi->State = HAL_SPI_STATE_BUSY_TX;
1542 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1543 hspi->pTxBuffPtr = (uint8_t *)pData;
1544 hspi->TxXferSize = Size;
1545 hspi->TxXferCount = Size;
1546
1547 /* Init field not used in handle to zero */
1548 hspi->pRxBuffPtr = NULL;
1549 hspi->RxXferSize = (uint16_t) 0UL;
1550 hspi->RxXferCount = (uint16_t) 0UL;
1551 hspi->RxISR = NULL;
1552
1553 /* Set the function for IT treatment */
1554 if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
1555 {
1556 hspi->TxISR = SPI_TxISR_32BIT;
1557 }
1558 else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1559 {
1560 hspi->TxISR = SPI_TxISR_16BIT;
1561 }
1562 else
1563 {
1564 hspi->TxISR = SPI_TxISR_8BIT;
1565 }
1566
1567 /* Configure communication direction : 1Line */
1568 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1569 {
1570 SPI_1LINE_TX(hspi);
1571 }
1572
1573 /* Set the number of data at current transfer */
1574 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
1575
1576 /* Enable SPI peripheral */
1577 __HAL_SPI_ENABLE(hspi);
1578
1579 /* Enable EOT, TXP, FRE, MODF, UDR and TSERF interrupts */
1580 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
1581
1582 if (hspi->Init.Mode == SPI_MODE_MASTER)
1583 {
1584 /* Master transfer start */
1585 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
1586 }
1587
1588 __HAL_UNLOCK(hspi);
1589 return errorcode;
1590 }
1591
1592 /**
1593 * @brief Receive an amount of data in non-blocking mode with Interrupt.
1594 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1595 * the configuration information for SPI module.
1596 * @param pData: pointer to data buffer
1597 * @param Size : amount of data to be sent
1598 * @retval HAL status
1599 */
1600 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1601 {
1602 HAL_StatusTypeDef errorcode = HAL_OK;
1603
1604 /* Check Direction parameter */
1605 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
1606
1607 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1608 {
1609 hspi->State = HAL_SPI_STATE_BUSY_RX;
1610 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1611 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1612 }
1613
1614 /* Process Locked */
1615 __HAL_LOCK(hspi);
1616
1617 if (hspi->State != HAL_SPI_STATE_READY)
1618 {
1619 errorcode = HAL_BUSY;
1620 __HAL_UNLOCK(hspi);
1621 return errorcode;
1622 }
1623
1624 if ((pData == NULL) || (Size == 0UL))
1625 {
1626 errorcode = HAL_ERROR;
1627 __HAL_UNLOCK(hspi);
1628 return errorcode;
1629 }
1630
1631 /* Set the transaction information */
1632 hspi->State = HAL_SPI_STATE_BUSY_RX;
1633 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1634 hspi->pRxBuffPtr = (uint8_t *)pData;
1635 hspi->RxXferSize = Size;
1636 hspi->RxXferCount = Size;
1637
1638 /* Init field not used in handle to zero */
1639 hspi->pTxBuffPtr = NULL;
1640 hspi->TxXferSize = (uint16_t) 0UL;
1641 hspi->TxXferCount = (uint16_t) 0UL;
1642 hspi->TxISR = NULL;
1643
1644 /* Set the function for IT treatment */
1645 if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
1646 {
1647 hspi->RxISR = SPI_RxISR_32BIT;
1648 }
1649 else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1650 {
1651 hspi->RxISR = SPI_RxISR_16BIT;
1652 }
1653 else
1654 {
1655 hspi->RxISR = SPI_RxISR_8BIT;
1656 }
1657
1658 /* Configure communication direction : 1Line */
1659 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1660 {
1661 SPI_1LINE_RX(hspi);
1662 }
1663
1664 /* Note : The SPI must be enabled after unlocking current process
1665 to avoid the risk of SPI interrupt handle execution before current
1666 process unlock */
1667
1668 /* Set the number of data at current transfer */
1669 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
1670
1671 /* Enable SPI peripheral */
1672 __HAL_SPI_ENABLE(hspi);
1673
1674 /* Enable EOT, RXP, OVR, FRE, MODF and TSERF interrupts */
1675 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
1676
1677 if (hspi->Init.Mode == SPI_MODE_MASTER)
1678 {
1679 /* Master transfer start */
1680 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
1681 }
1682
1683 /* Process Unlocked */
1684 __HAL_UNLOCK(hspi);
1685 return errorcode;
1686 }
1687
1688 /**
1689 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1690 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1691 * the configuration information for SPI module.
1692 * @param pTxData: pointer to transmission data buffer
1693 * @param pRxData: pointer to reception data buffer
1694 * @param Size : amount of data to be sent and received
1695 * @retval HAL status
1696 */
1697 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1698 {
1699 HAL_SPI_StateTypeDef tmp_state;
1700 HAL_StatusTypeDef errorcode = HAL_OK;
1701
1702 uint32_t tmp_mode;
1703
1704 /* Check Direction parameter */
1705 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1706
1707 /* Process locked */
1708 __HAL_LOCK(hspi);
1709
1710 /* Init temporary variables */
1711 tmp_state = hspi->State;
1712 tmp_mode = hspi->Init.Mode;
1713
1714 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1715 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1716 {
1717 errorcode = HAL_BUSY;
1718 __HAL_UNLOCK(hspi);
1719 return errorcode;
1720 }
1721
1722 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
1723 {
1724 errorcode = HAL_ERROR;
1725 __HAL_UNLOCK(hspi);
1726 return errorcode;
1727 }
1728
1729 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1730 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1731 {
1732 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1733 }
1734
1735 /* Set the transaction information */
1736 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1737 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1738 hspi->TxXferSize = Size;
1739 hspi->TxXferCount = Size;
1740 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1741 hspi->RxXferSize = Size;
1742 hspi->RxXferCount = Size;
1743
1744 /* Set the function for IT treatment */
1745 if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
1746 {
1747 hspi->TxISR = SPI_TxISR_32BIT;
1748 hspi->RxISR = SPI_RxISR_32BIT;
1749 }
1750 else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1751 {
1752 hspi->RxISR = SPI_RxISR_16BIT;
1753 hspi->TxISR = SPI_TxISR_16BIT;
1754 }
1755 else
1756 {
1757 hspi->RxISR = SPI_RxISR_8BIT;
1758 hspi->TxISR = SPI_TxISR_8BIT;
1759 }
1760
1761 /* Set the number of data at current transfer */
1762 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
1763
1764 /* Enable SPI peripheral */
1765 __HAL_SPI_ENABLE(hspi);
1766
1767 /* Enable EOT, RXP, TXP, DXP, UDR, OVR, FRE, MODF and TSERF interrupts */
1768 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
1769
1770 if (hspi->Init.Mode == SPI_MODE_MASTER)
1771 {
1772 /* Master transfer start */
1773 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
1774 }
1775
1776 /* Process Unlocked */
1777 __HAL_UNLOCK(hspi);
1778 return errorcode;
1779 }
1780
1781 #if defined(USE_SPI_RELOAD_TRANSFER)
1782 /**
1783 * @brief Transmit an additional amount of data in blocking mode.
1784 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1785 * the configuration information for SPI module.
1786 * @param pData: pointer to data buffer
1787 * @param Size : amount of data to be sent
1788 * @retval HAL status
1789 */
1790 HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1791 {
1792 HAL_StatusTypeDef errorcode = HAL_OK;
1793 HAL_SPI_StateTypeDef tmp_state;
1794
1795 /* Lock the process */
1796 __HAL_LOCK(hspi);
1797
1798 if ((pData == NULL) || (Size == 0UL))
1799 {
1800 errorcode = HAL_ERROR;
1801 __HAL_UNLOCK(hspi);
1802 return errorcode;
1803 }
1804
1805 if (hspi->State == HAL_SPI_STATE_BUSY_TX)
1806 {
1807 /* check if there is already a request to reload */
1808 if (hspi->Reload.Requested == 1UL)
1809 {
1810 errorcode = HAL_ERROR;
1811 __HAL_UNLOCK(hspi);
1812 return errorcode;
1813 }
1814
1815 /* Insert the new number of data to be sent just after the current one */
1816 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, (Size & 0xFFFFFFFFUL) << 16UL);
1817
1818 /* Set the transaction information */
1819 hspi->Reload.Requested = 1UL;
1820 hspi->Reload.pTxBuffPtr = (uint8_t *)pData;
1821 hspi->Reload.TxXferSize = Size;
1822
1823 tmp_state = hspi->State;
1824
1825 /* Check if the current transmit is already completed */
1826 if (((hspi->Instance->CR2 & SPI_CR2_TSER) != 0UL) && (tmp_state == HAL_SPI_STATE_READY))
1827 {
1828 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TSERF);
1829 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, 0UL);
1830 hspi->Reload.Requested = 0UL;
1831 errorcode = HAL_ERROR;
1832 __HAL_UNLOCK(hspi);
1833 return errorcode;
1834 }
1835 }
1836 else
1837 {
1838 errorcode = HAL_ERROR;
1839 return errorcode;
1840 }
1841
1842 __HAL_UNLOCK(hspi);
1843 return errorcode;
1844 }
1845 #endif /* USE_HSPI_RELOAD_TRANSFER */
1846
1847 #if defined(USE_SPI_RELOAD_TRANSFER)
1848 /**
1849 * @brief Receive an additional amount of data in blocking mode.
1850 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1851 * the configuration information for SPI module.
1852 * @param pData: pointer to data buffer
1853 * @param Size : amount of data to be sent
1854 * @retval HAL status
1855 */
1856 HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1857 {
1858 HAL_StatusTypeDef errorcode = HAL_OK;
1859 HAL_SPI_StateTypeDef tmp_state;
1860
1861 /* Lock the process */
1862 __HAL_LOCK(hspi);
1863
1864 if ((pData == NULL) || (Size == 0UL))
1865 {
1866 errorcode = HAL_ERROR;
1867 __HAL_UNLOCK(hspi);
1868 return errorcode;
1869 }
1870
1871 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
1872 {
1873 /* check if there is already a request to reload */
1874 if (hspi->Reload.Requested == 1UL)
1875 {
1876 errorcode = HAL_ERROR;
1877 __HAL_UNLOCK(hspi);
1878 return errorcode;
1879 }
1880
1881 /* Insert the new number of data that will be received just after the current one */
1882 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, (Size & 0xFFFFFFFFUL) << 16UL);
1883
1884 /* Set the transaction information */
1885 hspi->Reload.Requested = 1UL;
1886 hspi->Reload.pRxBuffPtr = (uint8_t *)pData;
1887 hspi->Reload.RxXferSize = Size;
1888
1889 tmp_state = hspi->State;
1890
1891 /* Check if the current reception is already completed */
1892 if (((hspi->Instance->CR2 & SPI_CR2_TSER) != 0UL) && (tmp_state == HAL_SPI_STATE_READY))
1893 {
1894 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TSERF);
1895 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, 0UL);
1896 hspi->Reload.Requested = 0UL;
1897 errorcode = HAL_ERROR;
1898 __HAL_UNLOCK(hspi);
1899 return errorcode;
1900 }
1901 }
1902 else
1903 {
1904 errorcode = HAL_ERROR;
1905 return errorcode;
1906 }
1907
1908 __HAL_UNLOCK(hspi);
1909 return errorcode;
1910 }
1911 #endif /* USE_HSPI_RELOAD_TRANSFER */
1912
1913 #if defined(USE_SPI_RELOAD_TRANSFER)
1914 /**
1915 * @brief Transmit and receive an additional amount of data in blocking mode.
1916 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1917 * the configuration information for SPI module.
1918 * @param pTxData: pointer to transmission data buffer
1919 * @param pRxData: pointer to reception data buffer
1920 * @param Size : amount of data to be sent and received
1921 * @retval HAL status
1922 */
1923 HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1924 {
1925 HAL_StatusTypeDef errorcode = HAL_OK;
1926 HAL_SPI_StateTypeDef tmp_state;
1927
1928 /* Lock the process */
1929 __HAL_LOCK(hspi);
1930
1931 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
1932 {
1933 errorcode = HAL_ERROR;
1934 __HAL_UNLOCK(hspi);
1935 return errorcode;
1936 }
1937
1938 if (hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
1939 {
1940 /* check if there is already a request to reload */
1941 if (hspi->Reload.Requested == 1UL)
1942 {
1943 errorcode = HAL_ERROR;
1944 __HAL_UNLOCK(hspi);
1945 return errorcode;
1946 }
1947
1948 /* Insert the new number of data that will be sent and received just after the current one */
1949 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, (Size & 0xFFFFFFFFUL) << 16UL);
1950
1951 /* Set the transaction information */
1952 hspi->Reload.Requested = 1UL;
1953 hspi->Reload.pTxBuffPtr = (uint8_t *)pTxData;
1954 hspi->Reload.TxXferSize = Size;
1955 hspi->Reload.pRxBuffPtr = (uint8_t *)pRxData;
1956 hspi->Reload.RxXferSize = Size;
1957
1958 tmp_state = hspi->State;
1959
1960 /* Check if the current transmit is already completed */
1961 if (((hspi->Instance->CR2 & SPI_CR2_TSER) != 0UL) && (tmp_state == HAL_SPI_STATE_READY))
1962 {
1963 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TSERF);
1964 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, 0UL);
1965 hspi->Reload.Requested = 0UL;
1966 errorcode = HAL_ERROR;
1967 __HAL_UNLOCK(hspi);
1968 return errorcode;
1969 }
1970 }
1971 else
1972 {
1973 errorcode = HAL_ERROR;
1974 return errorcode;
1975 }
1976
1977 __HAL_UNLOCK(hspi);
1978 return errorcode;
1979 }
1980 #endif /* USE_HSPI_RELOAD_TRANSFER */
1981
1982 /**
1983 * @brief Transmit an amount of data in non-blocking mode with DMA.
1984 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1985 * the configuration information for SPI module.
1986 * @param pData: pointer to data buffer
1987 * @param Size : amount of data to be sent
1988 * @retval HAL status
1989 */
1990 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1991 {
1992 HAL_StatusTypeDef errorcode = HAL_OK;
1993
1994 /* Check Direction parameter */
1995 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
1996
1997 /* Process Locked */
1998 __HAL_LOCK(hspi);
1999
2000 if (hspi->State != HAL_SPI_STATE_READY)
2001 {
2002 errorcode = HAL_BUSY;
2003 __HAL_UNLOCK(hspi);
2004 return errorcode;
2005 }
2006
2007 if ((pData == NULL) || (Size == 0UL))
2008 {
2009 errorcode = HAL_ERROR;
2010 __HAL_UNLOCK(hspi);
2011 return errorcode;
2012 }
2013
2014 /* Set the transaction information */
2015 hspi->State = HAL_SPI_STATE_BUSY_TX;
2016 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2017 hspi->pTxBuffPtr = (uint8_t *)pData;
2018 hspi->TxXferSize = Size;
2019 hspi->TxXferCount = Size;
2020
2021 /* Init field not used in handle to zero */
2022 hspi->pRxBuffPtr = NULL;
2023 hspi->TxISR = NULL;
2024 hspi->RxISR = NULL;
2025 hspi->RxXferSize = (uint16_t)0UL;
2026 hspi->RxXferCount = (uint16_t)0UL;
2027
2028 /* Configure communication direction : 1Line */
2029 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
2030 {
2031 SPI_1LINE_TX(hspi);
2032 }
2033
2034 /* Packing mode management is enabled by the DMA settings */
2035 if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \
2036 ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
2037 (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
2038 {
2039 /* Restriction the DMA data received is not allowed in this mode */
2040 errorcode = HAL_ERROR;
2041 __HAL_UNLOCK(hspi);
2042 return errorcode;
2043 }
2044
2045 /* Adjust XferCount according to DMA alignment / Data size */
2046 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
2047 {
2048 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2049 {
2050 hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
2051 }
2052 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
2053 {
2054 hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL;
2055 }
2056 }
2057 else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
2058 {
2059 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
2060 {
2061 hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
2062 }
2063 }
2064 else
2065 {
2066 /* Adjustment done */
2067 }
2068
2069 /* Set the SPI TxDMA Half transfer complete callback */
2070 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
2071
2072 /* Set the SPI TxDMA transfer complete callback */
2073 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
2074
2075 /* Set the DMA error callback */
2076 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
2077
2078 /* Set the DMA AbortCpltCallback */
2079 hspi->hdmatx->XferAbortCallback = NULL;
2080
2081 /* Clear TXDMAEN bit*/
2082 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
2083
2084 /* Enable the Tx DMA Stream/Channel */
2085 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, hspi->TxXferCount))
2086 {
2087 /* Update SPI error code */
2088 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2089 errorcode = HAL_ERROR;
2090 hspi->State = HAL_SPI_STATE_READY;
2091 return errorcode;
2092 }
2093
2094 /* Set the number of data at current transfer */
2095 if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
2096 {
2097 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL);
2098 }
2099 else
2100 {
2101 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
2102 }
2103
2104 /* Enable Tx DMA Request */
2105 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
2106
2107 /* Enable the SPI Error Interrupt Bit */
2108 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
2109
2110 /* Enable SPI peripheral */
2111 __HAL_SPI_ENABLE(hspi);
2112
2113 if (hspi->Init.Mode == SPI_MODE_MASTER)
2114 {
2115 /* Master transfer start */
2116 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
2117 }
2118
2119 /* Process Unlocked */
2120 __HAL_UNLOCK(hspi);
2121 return errorcode;
2122 }
2123
2124 /**
2125 * @brief Receive an amount of data in non-blocking mode with DMA.
2126 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2127 * the configuration information for SPI module.
2128 * @param pData: pointer to data buffer
2129 * @param Size : amount of data to be sent
2130 * @note When the CRC feature is enabled the pData Length must be Size + 1.
2131 * @retval HAL status
2132 */
2133 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
2134 {
2135 HAL_StatusTypeDef errorcode = HAL_OK;
2136
2137 /* Check Direction parameter */
2138 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
2139
2140 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
2141 {
2142 hspi->State = HAL_SPI_STATE_BUSY_RX;
2143 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
2144 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
2145 }
2146
2147 /* Process Locked */
2148 __HAL_LOCK(hspi);
2149
2150 if (hspi->State != HAL_SPI_STATE_READY)
2151 {
2152 errorcode = HAL_BUSY;
2153 __HAL_UNLOCK(hspi);
2154 return errorcode;
2155 }
2156
2157 if ((pData == NULL) || (Size == 0UL))
2158 {
2159 errorcode = HAL_ERROR;
2160 __HAL_UNLOCK(hspi);
2161 return errorcode;
2162 }
2163
2164 /* Set the transaction information */
2165 hspi->State = HAL_SPI_STATE_BUSY_RX;
2166 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2167 hspi->pRxBuffPtr = (uint8_t *)pData;
2168 hspi->RxXferSize = Size;
2169 hspi->RxXferCount = Size;
2170
2171 /*Init field not used in handle to zero */
2172 hspi->RxISR = NULL;
2173 hspi->TxISR = NULL;
2174 hspi->TxXferSize = (uint16_t) 0UL;
2175 hspi->TxXferCount = (uint16_t) 0UL;
2176
2177 /* Configure communication direction : 1Line */
2178 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
2179 {
2180 SPI_1LINE_RX(hspi);
2181 }
2182
2183 /* Packing mode management is enabled by the DMA settings */
2184 if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \
2185 ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
2186 (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
2187 {
2188 /* Restriction the DMA data received is not allowed in this mode */
2189 errorcode = HAL_ERROR;
2190 __HAL_UNLOCK(hspi);
2191 return errorcode;
2192 }
2193
2194 /* Clear RXDMAEN bit */
2195 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
2196
2197 /* Adjust XferCount according to DMA alignment / Data size */
2198 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
2199 {
2200 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2201 {
2202 hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
2203 }
2204 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
2205 {
2206 hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL;
2207 }
2208 }
2209 else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
2210 {
2211 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
2212 {
2213 hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
2214 }
2215 }
2216 else
2217 {
2218 /* Adjustment done */
2219 }
2220
2221 /* Set the SPI RxDMA Half transfer complete callback */
2222 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2223
2224 /* Set the SPI Rx DMA transfer complete callback */
2225 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2226
2227 /* Set the DMA error callback */
2228 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2229
2230 /* Set the DMA AbortCpltCallback */
2231 hspi->hdmarx->XferAbortCallback = NULL;
2232
2233 /* Enable the Rx DMA Stream/Channel */
2234 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
2235 {
2236 /* Update SPI error code */
2237 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2238 errorcode = HAL_ERROR;
2239 hspi->State = HAL_SPI_STATE_READY;
2240 return errorcode;
2241 }
2242
2243 /* Set the number of data at current transfer */
2244 if (hspi->hdmarx->Init.Mode == DMA_CIRCULAR)
2245 {
2246 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL);
2247 }
2248 else
2249 {
2250 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
2251 }
2252
2253 /* Enable Rx DMA Request */
2254 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
2255
2256 /* Enable the SPI Error Interrupt Bit */
2257 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
2258
2259 /* Enable SPI peripheral */
2260 __HAL_SPI_ENABLE(hspi);
2261
2262 if (hspi->Init.Mode == SPI_MODE_MASTER)
2263 {
2264 /* Master transfer start */
2265 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
2266 }
2267
2268 /* Process Unlocked */
2269 __HAL_UNLOCK(hspi);
2270 return errorcode;
2271 }
2272
2273 /**
2274 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
2275 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2276 * the configuration information for SPI module.
2277 * @param pTxData: pointer to transmission data buffer
2278 * @param pRxData: pointer to reception data buffer
2279 * @param Size : amount of data to be sent
2280 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
2281 * @retval HAL status
2282 */
2283 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
2284 uint16_t Size)
2285 {
2286 HAL_SPI_StateTypeDef tmp_state;
2287 HAL_StatusTypeDef errorcode = HAL_OK;
2288
2289 uint32_t tmp_mode;
2290
2291 /* Check Direction parameter */
2292 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
2293
2294 /* Process locked */
2295 __HAL_LOCK(hspi);
2296
2297 /* Init temporary variables */
2298 tmp_state = hspi->State;
2299 tmp_mode = hspi->Init.Mode;
2300
2301 if (!(((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)) || (tmp_state == HAL_SPI_STATE_READY)))
2302 {
2303 errorcode = HAL_BUSY;
2304 __HAL_UNLOCK(hspi);
2305 return errorcode;
2306 }
2307
2308 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
2309 {
2310 errorcode = HAL_ERROR;
2311 __HAL_UNLOCK(hspi);
2312 return errorcode;
2313 }
2314
2315 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
2316 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
2317 {
2318 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
2319 }
2320
2321 /* Set the transaction information */
2322 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2323 hspi->pTxBuffPtr = (uint8_t *)pTxData;
2324 hspi->TxXferSize = Size;
2325 hspi->TxXferCount = Size;
2326 hspi->pRxBuffPtr = (uint8_t *)pRxData;
2327 hspi->RxXferSize = Size;
2328 hspi->RxXferCount = Size;
2329
2330 /* Init field not used in handle to zero */
2331 hspi->RxISR = NULL;
2332 hspi->TxISR = NULL;
2333
2334 /* Reset the Tx/Rx DMA bits */
2335 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
2336
2337 /* Packing mode management is enabled by the DMA settings */
2338 if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \
2339 ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
2340 (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
2341 {
2342 /* Restriction the DMA data received is not allowed in this mode */
2343 errorcode = HAL_ERROR;
2344 /* Process Unlocked */
2345 __HAL_UNLOCK(hspi);
2346 return errorcode;
2347 }
2348
2349 /* Adjust XferCount according to DMA alignment / Data size */
2350 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
2351 {
2352 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2353 {
2354 hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
2355 }
2356 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
2357 {
2358 hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL;
2359 }
2360 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2361 {
2362 hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
2363 }
2364 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
2365 {
2366 hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL;
2367 }
2368 }
2369 else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
2370 {
2371 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
2372 {
2373 hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
2374 }
2375 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
2376 {
2377 hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
2378 }
2379 }
2380 else
2381 {
2382 /* Adjustment done */
2383 }
2384
2385 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
2386 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
2387 {
2388 /* Set the SPI Rx DMA Half transfer complete callback */
2389 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2390 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2391 }
2392 else
2393 {
2394 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
2395 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
2396 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
2397 }
2398
2399 /* Set the DMA error callback */
2400 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2401
2402 /* Set the DMA AbortCallback */
2403 hspi->hdmarx->XferAbortCallback = NULL;
2404
2405 /* Enable the Rx DMA Stream/Channel */
2406 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
2407 {
2408 /* Update SPI error code */
2409 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2410 errorcode = HAL_ERROR;
2411 hspi->State = HAL_SPI_STATE_READY;
2412 return errorcode;
2413 }
2414
2415 /* Enable Rx DMA Request */
2416 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
2417
2418 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
2419 is performed in DMA reception complete callback */
2420 hspi->hdmatx->XferHalfCpltCallback = NULL;
2421 hspi->hdmatx->XferCpltCallback = NULL;
2422 hspi->hdmatx->XferErrorCallback = NULL;
2423 hspi->hdmatx->XferAbortCallback = NULL;
2424
2425 /* Enable the Tx DMA Stream/Channel */
2426 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, hspi->TxXferCount))
2427 {
2428 /* Update SPI error code */
2429 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2430 errorcode = HAL_ERROR;
2431 hspi->State = HAL_SPI_STATE_READY;
2432 return errorcode;
2433 }
2434
2435 if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
2436 {
2437 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL);
2438 }
2439 else
2440 {
2441 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
2442 }
2443
2444 /* Enable Tx DMA Request */
2445 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
2446
2447 /* Enable the SPI Error Interrupt Bit */
2448 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
2449
2450 /* Enable SPI peripheral */
2451 __HAL_SPI_ENABLE(hspi);
2452
2453 if (hspi->Init.Mode == SPI_MODE_MASTER)
2454 {
2455 /* Master transfer start */
2456 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
2457 }
2458
2459 /* Process Unlocked */
2460 __HAL_UNLOCK(hspi);
2461 return errorcode;
2462 }
2463
2464 /**
2465 * @brief Abort ongoing transfer (blocking mode).
2466 * @param hspi SPI handle.
2467 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2468 * started in Interrupt or DMA mode.
2469 * @note This procedure performs following operations :
2470 * + Disable SPI Interrupts (depending of transfer direction)
2471 * + Disable the DMA transfer in the peripheral register (if enabled)
2472 * + Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
2473 * + Set handle State to READY.
2474 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
2475 * @retval HAL status
2476 */
2477 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
2478 {
2479 HAL_StatusTypeDef errorcode;
2480
2481 __IO uint32_t count;
2482
2483 /* Process locked */
2484 __HAL_LOCK(hspi);
2485
2486 /* Set hspi->state to aborting to avoid any interaction */
2487 hspi->State = HAL_SPI_STATE_ABORT;
2488
2489 /* Initialized local variable */
2490 errorcode = HAL_OK;
2491 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL);
2492
2493 /* If master communication on going, make sure current frame is done before closing the connection */
2494 if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
2495 {
2496 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP);
2497 do
2498 {
2499 count--;
2500 if (count == 0UL)
2501 {
2502 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2503 break;
2504 }
2505 }
2506 while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
2507 }
2508
2509 /* Disable the SPI DMA Tx request if enabled */
2510 if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
2511 {
2512 if (hspi->hdmatx != NULL)
2513 {
2514 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
2515 hspi->hdmatx->XferAbortCallback = NULL;
2516
2517 /* Abort DMA Tx Handle linked to SPI Peripheral */
2518 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
2519 {
2520 if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
2521 {
2522 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2523 }
2524 }
2525 }
2526 }
2527
2528 /* Disable the SPI DMA Rx request if enabled */
2529 if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
2530 {
2531 if (hspi->hdmarx != NULL)
2532 {
2533 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
2534 hspi->hdmarx->XferAbortCallback = NULL;
2535
2536 /* Abort DMA Rx Handle linked to SPI Peripheral */
2537 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
2538 {
2539 if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
2540 {
2541 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2542 }
2543 }
2544 }
2545 }
2546
2547 /* Proceed with abort procedure */
2548 SPI_AbortTransfer(hspi);
2549
2550 /* Check error during Abort procedure */
2551 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2552 {
2553 /* return HAL_Error in case of error during Abort procedure */
2554 errorcode = HAL_ERROR;
2555 }
2556 else
2557 {
2558 /* Reset errorCode */
2559 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2560 }
2561
2562 /* Process Unlocked */
2563 __HAL_UNLOCK(hspi);
2564
2565 /* Restore hspi->state to ready */
2566 hspi->State = HAL_SPI_STATE_READY;
2567
2568 return errorcode;
2569 }
2570
2571 /**
2572 * @brief Abort ongoing transfer (Interrupt mode).
2573 * @param hspi SPI handle.
2574 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2575 * started in Interrupt or DMA mode.
2576 * @note This procedure performs following operations :
2577 * + Disable SPI Interrupts (depending of transfer direction)
2578 * + Disable the DMA transfer in the peripheral register (if enabled)
2579 * + Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
2580 * + Set handle State to READY
2581 * + At abort completion, call user abort complete callback.
2582 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
2583 * considered as completed only when user abort complete callback is executed (not when exiting function).
2584 * @retval HAL status
2585 */
2586 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
2587 {
2588 HAL_StatusTypeDef errorcode;
2589 __IO uint32_t count;
2590 uint32_t dma_tx_abort_done = 1UL, dma_rx_abort_done = 1UL;
2591
2592 /* Set hspi->state to aborting to avoid any interaction */
2593 hspi->State = HAL_SPI_STATE_ABORT;
2594
2595 /* Initialized local variable */
2596 errorcode = HAL_OK;
2597 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL);
2598
2599 /* If master communication on going, make sure current frame is done before closing the connection */
2600 if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
2601 {
2602 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP);
2603 do
2604 {
2605 count--;
2606 if (count == 0UL)
2607 {
2608 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2609 break;
2610 }
2611 }
2612 while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
2613 }
2614
2615 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized
2616 before any call to DMA Abort functions */
2617
2618 if(hspi->hdmatx != NULL)
2619 {
2620 if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
2621 {
2622 /* Set DMA Abort Complete callback if SPI DMA Tx request if enabled */
2623 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
2624
2625 dma_tx_abort_done = 0UL;
2626
2627 /* Abort DMA Tx Handle linked to SPI Peripheral */
2628 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2629 {
2630 if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_NO_XFER)
2631 {
2632 dma_tx_abort_done = 1UL;
2633 hspi->hdmatx->XferAbortCallback = NULL;
2634 }
2635 }
2636 }
2637 else
2638 {
2639 hspi->hdmatx->XferAbortCallback = NULL;
2640 }
2641 }
2642
2643 if(hspi->hdmarx != NULL)
2644 {
2645 if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
2646 {
2647 /* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */
2648 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2649
2650 dma_rx_abort_done = 0UL;
2651
2652 /* Abort DMA Rx Handle linked to SPI Peripheral */
2653 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
2654 {
2655 if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_NO_XFER)
2656 {
2657 dma_rx_abort_done = 1UL;
2658 hspi->hdmarx->XferAbortCallback = NULL;
2659 }
2660 }
2661 }
2662 else
2663 {
2664 hspi->hdmarx->XferAbortCallback = NULL;
2665 }
2666 }
2667
2668 /* If no running DMA transfer, finish cleanup and call callbacks */
2669 if ((dma_tx_abort_done == 1UL) && (dma_rx_abort_done == 1UL))
2670 {
2671 /* Proceed with abort procedure */
2672 SPI_AbortTransfer(hspi);
2673
2674 /* Check error during Abort procedure */
2675 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2676 {
2677 /* return HAL_Error in case of error during Abort procedure */
2678 errorcode = HAL_ERROR;
2679 }
2680 else
2681 {
2682 /* Reset errorCode */
2683 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2684 }
2685
2686 /* Restore hspi->state to ready */
2687 hspi->State = HAL_SPI_STATE_READY;
2688
2689 /* Call user Abort complete callback */
2690 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
2691 hspi->AbortCpltCallback(hspi);
2692 #else
2693 HAL_SPI_AbortCpltCallback(hspi);
2694 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2695 }
2696
2697 return errorcode;
2698 }
2699
2700 /**
2701 * @brief Pause the DMA Transfer.
2702 * This API is not supported, it is maintained for backward compatibility.
2703 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2704 * the configuration information for the specified SPI module.
2705 * @retval HAL_ERROR
2706 */
2707 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
2708 {
2709 /* Set error code to not supported */
2710 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
2711
2712 return HAL_ERROR;
2713 }
2714
2715 /**
2716 * @brief Resume the DMA Transfer.
2717 * This API is not supported, it is maintained for backward compatibility.
2718 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2719 * the configuration information for the specified SPI module.
2720 * @retval HAL_ERROR
2721 */
2722 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
2723 {
2724 /* Set error code to not supported */
2725 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
2726
2727 return HAL_ERROR;
2728 }
2729
2730 /**
2731 * @brief Stop the DMA Transfer.
2732 * This API is not supported, it is maintained for backward compatibility.
2733 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2734 * the configuration information for the specified SPI module.
2735 * @retval HAL_ERROR
2736 */
2737 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
2738 {
2739 /* Set error code to not supported */
2740 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
2741
2742 return HAL_ERROR;
2743 }
2744
2745 /**
2746 * @brief Handle SPI interrupt request.
2747 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2748 * the configuration information for the specified SPI module.
2749 * @retval None
2750 */
2751 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
2752 {
2753 uint32_t itsource = hspi->Instance->IER;
2754 uint32_t itflag = hspi->Instance->SR;
2755 uint32_t trigger = itsource & itflag;
2756 uint32_t cfg1 = hspi->Instance->CFG1;
2757 uint32_t handled = 0UL;
2758
2759 HAL_SPI_StateTypeDef State = hspi->State;
2760 #if defined (__GNUC__)
2761 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
2762 #endif /* __GNUC__ */
2763
2764
2765 /* SPI in mode Transmitter and Receiver ------------------------------------*/
2766 if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP))
2767 {
2768 hspi->TxISR(hspi);
2769 hspi->RxISR(hspi);
2770 handled = 1UL;
2771 }
2772
2773 /* SPI in mode Receiver ----------------------------------------------------*/
2774 if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
2775 {
2776 hspi->RxISR(hspi);
2777 handled = 1UL;
2778 }
2779
2780 /* SPI in mode Transmitter -------------------------------------------------*/
2781 if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
2782 {
2783 hspi->TxISR(hspi);
2784 handled = 1UL;
2785 }
2786
2787 #if defined(USE_SPI_RELOAD_TRANSFER)
2788 /* SPI Reload -------------------------------------------------*/
2789 if (HAL_IS_BIT_SET(trigger, SPI_FLAG_TSERF))
2790 {
2791 hspi->Reload.Requested = 0UL;
2792 __HAL_SPI_CLEAR_TSERFFLAG(hspi);
2793 }
2794 #endif /* USE_HSPI_RELOAD_TRANSFER */
2795
2796 if (handled != 0UL)
2797 {
2798 return;
2799 }
2800
2801 /* SPI End Of Transfer: DMA or IT based transfer */
2802 if (HAL_IS_BIT_SET(trigger, SPI_FLAG_EOT))
2803 {
2804 /* Clear EOT/TXTF/SUSP flag */
2805 __HAL_SPI_CLEAR_EOTFLAG(hspi);
2806 __HAL_SPI_CLEAR_TXTFFLAG(hspi);
2807 __HAL_SPI_CLEAR_SUSPFLAG(hspi);
2808
2809 /* Disable EOT interrupt */
2810 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
2811
2812 /* DMA Normal Mode */
2813 if (HAL_IS_BIT_CLR(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN) || // IT based transfer is done
2814 ((State != HAL_SPI_STATE_BUSY_RX) && (hspi->hdmatx->Init.Mode == DMA_NORMAL)) || // DMA is used in normal mode
2815 ((State != HAL_SPI_STATE_BUSY_TX) && (hspi->hdmarx->Init.Mode == DMA_NORMAL))) // DMA is used in normal mode
2816 {
2817 /* For the IT based receive extra polling maybe required for last packet */
2818 if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
2819 {
2820 /* Pooling remaining data */
2821 while (hspi->RxXferCount != 0UL)
2822 {
2823 /* Receive data in 32 Bit mode */
2824 if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
2825 {
2826 *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
2827 hspi->pRxBuffPtr += sizeof(uint32_t);
2828 }
2829 /* Receive data in 16 Bit mode */
2830 else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2831 {
2832 #if defined (__GNUC__)
2833 *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
2834 #else
2835 *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
2836 #endif /* __GNUC__ */
2837 hspi->pRxBuffPtr += sizeof(uint16_t);
2838 }
2839 /* Receive data in 8 Bit mode */
2840 else
2841 {
2842 *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
2843 hspi->pRxBuffPtr += sizeof(uint8_t);
2844 }
2845
2846 hspi->RxXferCount--;
2847 }
2848 }
2849
2850 /* Call SPI Standard close procedure */
2851 SPI_CloseTransfer(hspi);
2852
2853 hspi->State = HAL_SPI_STATE_READY;
2854 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2855 {
2856 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
2857 hspi->ErrorCallback(hspi);
2858 #else
2859 HAL_SPI_ErrorCallback(hspi);
2860 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2861 return;
2862 }
2863 }
2864
2865 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
2866 /* Call appropriate user callback */
2867 if (State == HAL_SPI_STATE_BUSY_TX_RX)
2868 {
2869 hspi->TxRxCpltCallback(hspi);
2870 }
2871 else if (State == HAL_SPI_STATE_BUSY_RX)
2872 {
2873 hspi->RxCpltCallback(hspi);
2874 }
2875 else if (State == HAL_SPI_STATE_BUSY_TX)
2876 {
2877 hspi->TxCpltCallback(hspi);
2878 }
2879 #else
2880 /* Call appropriate user callback */
2881 if (State == HAL_SPI_STATE_BUSY_TX_RX)
2882 {
2883 HAL_SPI_TxRxCpltCallback(hspi);
2884 }
2885 else if (State == HAL_SPI_STATE_BUSY_RX)
2886 {
2887 HAL_SPI_RxCpltCallback(hspi);
2888 }
2889 else if (State == HAL_SPI_STATE_BUSY_TX)
2890 {
2891 HAL_SPI_TxCpltCallback(hspi);
2892 }
2893 else
2894 {
2895 /* end of the appropriate call */
2896 }
2897 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2898
2899 return;
2900 }
2901
2902 if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT))
2903 {
2904 /* Abort on going, clear SUSP flag to avoid infinite looping */
2905 __HAL_SPI_CLEAR_SUSPFLAG(hspi);
2906
2907 return;
2908 }
2909
2910 /* SPI in Error Treatment --------------------------------------------------*/
2911 if ((trigger & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE | SPI_FLAG_UDR)) != 0UL)
2912 {
2913 /* SPI Overrun error interrupt occurred ----------------------------------*/
2914 if ((trigger & SPI_FLAG_OVR) != 0UL)
2915 {
2916 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
2917 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2918 }
2919
2920 /* SPI Mode Fault error interrupt occurred -------------------------------*/
2921 if ((trigger & SPI_FLAG_MODF) != 0UL)
2922 {
2923 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
2924 __HAL_SPI_CLEAR_MODFFLAG(hspi);
2925 }
2926
2927 /* SPI Frame error interrupt occurred ------------------------------------*/
2928 if ((trigger & SPI_FLAG_FRE) != 0UL)
2929 {
2930 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
2931 __HAL_SPI_CLEAR_FREFLAG(hspi);
2932 }
2933
2934 /* SPI Underrun error interrupt occurred ------------------------------------*/
2935 if ((trigger & SPI_FLAG_UDR) != 0UL)
2936 {
2937 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR);
2938 __HAL_SPI_CLEAR_UDRFLAG(hspi);
2939 }
2940
2941 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2942 {
2943 /* Disable SPI peripheral */
2944 __HAL_SPI_DISABLE(hspi);
2945
2946 /* Disable all interrupts */
2947 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_MODF | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_UDR);
2948
2949 /* Disable the SPI DMA requests if enabled */
2950 if (HAL_IS_BIT_SET(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
2951 {
2952 /* Disable the SPI DMA requests */
2953 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
2954
2955 /* Abort the SPI DMA Rx channel */
2956 if (hspi->hdmarx != NULL)
2957 {
2958 /* Set the SPI DMA Abort callback :
2959 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2960 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
2961 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
2962 {
2963 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2964 }
2965 }
2966 /* Abort the SPI DMA Tx channel */
2967 if (hspi->hdmatx != NULL)
2968 {
2969 /* Set the SPI DMA Abort callback :
2970 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2971 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
2972 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
2973 {
2974 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2975 }
2976 }
2977 }
2978 else
2979 {
2980 /* Restore hspi->State to Ready */
2981 hspi->State = HAL_SPI_STATE_READY;
2982
2983 /* Call user error callback */
2984 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
2985 hspi->ErrorCallback(hspi);
2986 #else
2987 HAL_SPI_ErrorCallback(hspi);
2988 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2989 }
2990 }
2991 return;
2992 }
2993 }
2994
2995 /**
2996 * @brief Tx Transfer completed callback.
2997 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2998 * the configuration information for SPI module.
2999 * @retval None
3000 */
3001 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
3002 {
3003 /* Prevent unused argument(s) compilation warning */
3004 UNUSED(hspi);
3005
3006 /* NOTE : This function should not be modified, when the callback is needed,
3007 the HAL_SPI_TxCpltCallback should be implemented in the user file
3008 */
3009 }
3010
3011 /**
3012 * @brief Rx Transfer completed callback.
3013 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3014 * the configuration information for SPI module.
3015 * @retval None
3016 */
3017 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
3018 {
3019 /* Prevent unused argument(s) compilation warning */
3020 UNUSED(hspi);
3021
3022 /* NOTE : This function should not be modified, when the callback is needed,
3023 the HAL_SPI_RxCpltCallback should be implemented in the user file
3024 */
3025 }
3026
3027 /**
3028 * @brief Tx and Rx Transfer completed callback.
3029 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3030 * the configuration information for SPI module.
3031 * @retval None
3032 */
3033 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
3034 {
3035 /* Prevent unused argument(s) compilation warning */
3036 UNUSED(hspi);
3037
3038 /* NOTE : This function should not be modified, when the callback is needed,
3039 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
3040 */
3041 }
3042
3043 /**
3044 * @brief Tx Half Transfer completed callback.
3045 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3046 * the configuration information for SPI module.
3047 * @retval None
3048 */
3049 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
3050 {
3051 /* Prevent unused argument(s) compilation warning */
3052 UNUSED(hspi);
3053
3054 /* NOTE : This function should not be modified, when the callback is needed,
3055 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
3056 */
3057 }
3058
3059 /**
3060 * @brief Rx Half Transfer completed callback.
3061 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3062 * the configuration information for SPI module.
3063 * @retval None
3064 */
3065 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
3066 {
3067 /* Prevent unused argument(s) compilation warning */
3068 UNUSED(hspi);
3069
3070 /* NOTE : This function should not be modified, when the callback is needed,
3071 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
3072 */
3073 }
3074
3075 /**
3076 * @brief Tx and Rx Half Transfer callback.
3077 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3078 * the configuration information for SPI module.
3079 * @retval None
3080 */
3081 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
3082 {
3083 /* Prevent unused argument(s) compilation warning */
3084 UNUSED(hspi);
3085
3086 /* NOTE : This function should not be modified, when the callback is needed,
3087 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
3088 */
3089 }
3090
3091 /**
3092 * @brief SPI error callback.
3093 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3094 * the configuration information for SPI module.
3095 * @retval None
3096 */
3097 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
3098 {
3099 /* Prevent unused argument(s) compilation warning */
3100 UNUSED(hspi);
3101
3102 /* NOTE : This function should not be modified, when the callback is needed,
3103 the HAL_SPI_ErrorCallback should be implemented in the user file
3104 */
3105 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
3106 and user can use HAL_SPI_GetError() API to check the latest error occurred
3107 */
3108 }
3109
3110 /**
3111 * @brief SPI Abort Complete callback.
3112 * @param hspi SPI handle.
3113 * @retval None
3114 */
3115 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
3116 {
3117 /* Prevent unused argument(s) compilation warning */
3118 UNUSED(hspi);
3119
3120 /* NOTE : This function should not be modified, when the callback is needed,
3121 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
3122 */
3123 }
3124
3125 /**
3126 * @}
3127 */
3128
3129 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
3130 * @brief SPI control functions
3131 *
3132 @verbatim
3133 ===============================================================================
3134 ##### Peripheral State and Errors functions #####
3135 ===============================================================================
3136 [..]
3137 This subsection provides a set of functions allowing to control the SPI.
3138 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
3139 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
3140 @endverbatim
3141 * @{
3142 */
3143
3144 /**
3145 * @brief Return the SPI handle state.
3146 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3147 * the configuration information for SPI module.
3148 * @retval SPI state
3149 */
3150 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
3151 {
3152 /* Return SPI handle state */
3153 return hspi->State;
3154 }
3155
3156 /**
3157 * @brief Return the SPI error code.
3158 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3159 * the configuration information for SPI module.
3160 * @retval SPI error code in bitmap format
3161 */
3162 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
3163 {
3164 /* Return SPI ErrorCode */
3165 return hspi->ErrorCode;
3166 }
3167
3168 /**
3169 * @}
3170 */
3171
3172 /**
3173 * @}
3174 */
3175
3176 /** @addtogroup SPI_Private_Functions
3177 * @brief Private functions
3178 * @{
3179 */
3180
3181 /**
3182 * @brief DMA SPI transmit process complete callback.
3183 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
3184 * the configuration information for the specified DMA module.
3185 * @retval None
3186 */
3187 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
3188 {
3189 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3190
3191 if (hspi->State != HAL_SPI_STATE_ABORT)
3192 {
3193 if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
3194 {
3195 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3196 hspi->TxCpltCallback(hspi);
3197 #else
3198 HAL_SPI_TxCpltCallback(hspi);
3199 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3200 }
3201 else
3202 {
3203 /* Enable EOT interrupt */
3204 __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
3205 }
3206 }
3207 }
3208
3209 /**
3210 * @brief DMA SPI receive process complete callback.
3211 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
3212 * the configuration information for the specified DMA module.
3213 * @retval None
3214 */
3215 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
3216 {
3217 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3218
3219 if (hspi->State != HAL_SPI_STATE_ABORT)
3220 {
3221 if (hspi->hdmarx->Init.Mode == DMA_CIRCULAR)
3222 {
3223 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3224 hspi->RxCpltCallback(hspi);
3225 #else
3226 HAL_SPI_RxCpltCallback(hspi);
3227 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3228 }
3229 else
3230 {
3231 /* Enable EOT interrupt */
3232 __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
3233 }
3234 }
3235 }
3236
3237 /**
3238 * @brief DMA SPI transmit receive process complete callback.
3239 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
3240 * the configuration information for the specified DMA module.
3241 * @retval None
3242 */
3243 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3244 {
3245 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3246
3247 if (hspi->State != HAL_SPI_STATE_ABORT)
3248 {
3249 if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
3250 {
3251 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3252 hspi->TxRxCpltCallback(hspi);
3253 #else
3254 HAL_SPI_TxRxCpltCallback(hspi);
3255 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3256 }
3257 else
3258 {
3259 /* Enable EOT interrupt */
3260 __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
3261 }
3262 }
3263 }
3264
3265 /**
3266 * @brief DMA SPI half transmit process complete callback.
3267 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
3268 * the configuration information for the specified DMA module.
3269 * @retval None
3270 */
3271 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
3272 {
3273 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3274
3275 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3276 hspi->TxHalfCpltCallback(hspi);
3277 #else
3278 HAL_SPI_TxHalfCpltCallback(hspi);
3279 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3280 }
3281
3282 /**
3283 * @brief DMA SPI half receive process complete callback
3284 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
3285 * the configuration information for the specified DMA module.
3286 * @retval None
3287 */
3288 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
3289 {
3290 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3291
3292 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3293 hspi->RxHalfCpltCallback(hspi);
3294 #else
3295 HAL_SPI_RxHalfCpltCallback(hspi);
3296 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3297 }
3298
3299 /**
3300 * @brief DMA SPI half transmit receive process complete callback.
3301 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
3302 * the configuration information for the specified DMA module.
3303 * @retval None
3304 */
3305 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3306 {
3307 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3308
3309 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3310 hspi->TxRxHalfCpltCallback(hspi);
3311 #else
3312 HAL_SPI_TxRxHalfCpltCallback(hspi);
3313 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3314 }
3315
3316 /**
3317 * @brief DMA SPI communication error callback.
3318 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
3319 * the configuration information for the specified DMA module.
3320 * @retval None
3321 */
3322 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
3323 {
3324 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3325
3326 /* if DMA error is FIFO error ignore it */
3327 if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
3328 {
3329 /* Call SPI standard close procedure */
3330 SPI_CloseTransfer(hspi);
3331
3332 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
3333 hspi->State = HAL_SPI_STATE_READY;
3334 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3335 hspi->ErrorCallback(hspi);
3336 #else
3337 HAL_SPI_ErrorCallback(hspi);
3338 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3339 }
3340 }
3341
3342 /**
3343 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
3344 * (To be called at end of DMA Abort procedure following error occurrence).
3345 * @param hdma DMA handle.
3346 * @retval None
3347 */
3348 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
3349 {
3350 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3351 hspi->RxXferCount = (uint16_t) 0UL;
3352 hspi->TxXferCount = (uint16_t) 0UL;
3353
3354 /* Restore hspi->State to Ready */
3355 hspi->State = HAL_SPI_STATE_READY;
3356
3357 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3358 hspi->ErrorCallback(hspi);
3359 #else
3360 HAL_SPI_ErrorCallback(hspi);
3361 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3362 }
3363
3364 /**
3365 * @brief DMA SPI Tx communication abort callback, when initiated by user
3366 * (To be called at end of DMA Tx Abort procedure following user abort request).
3367 * @note When this callback is executed, User Abort complete call back is called only if no
3368 * Abort still ongoing for Rx DMA Handle.
3369 * @param hdma DMA handle.
3370 * @retval None
3371 */
3372 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
3373 {
3374 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3375
3376 hspi->hdmatx->XferAbortCallback = NULL;
3377
3378 /* Check if an Abort process is still ongoing */
3379 if (hspi->hdmarx != NULL)
3380 {
3381 if (hspi->hdmarx->XferAbortCallback != NULL)
3382 {
3383 return;
3384 }
3385 }
3386
3387 /* Call the Abort procedure */
3388 SPI_AbortTransfer(hspi);
3389
3390 /* Restore hspi->State to Ready */
3391 hspi->State = HAL_SPI_STATE_READY;
3392
3393 /* Call user Abort complete callback */
3394 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3395 hspi->AbortCpltCallback(hspi);
3396 #else
3397 HAL_SPI_AbortCpltCallback(hspi);
3398 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3399 }
3400
3401 /**
3402 * @brief DMA SPI Rx communication abort callback, when initiated by user
3403 * (To be called at end of DMA Rx Abort procedure following user abort request).
3404 * @note When this callback is executed, User Abort complete call back is called only if no
3405 * Abort still ongoing for Tx DMA Handle.
3406 * @param hdma DMA handle.
3407 * @retval None
3408 */
3409 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
3410 {
3411 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3412
3413 hspi->hdmarx->XferAbortCallback = NULL;
3414
3415 /* Check if an Abort process is still ongoing */
3416 if (hspi->hdmatx != NULL)
3417 {
3418 if (hspi->hdmatx->XferAbortCallback != NULL)
3419 {
3420 return;
3421 }
3422 }
3423
3424 /* Call the Abort procedure */
3425 SPI_AbortTransfer(hspi);
3426
3427 /* Restore hspi->State to Ready */
3428 hspi->State = HAL_SPI_STATE_READY;
3429
3430 /* Call user Abort complete callback */
3431 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3432 hspi->AbortCpltCallback(hspi);
3433 #else
3434 HAL_SPI_AbortCpltCallback(hspi);
3435 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3436 }
3437
3438 /**
3439 * @brief Manage the receive 8-bit in Interrupt context.
3440 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3441 * the configuration information for SPI module.
3442 * @retval None
3443 */
3444 static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi)
3445 {
3446 /* Receive data in 8 Bit mode */
3447 *((uint8_t *)hspi->pRxBuffPtr) = (*(__IO uint8_t *)&hspi->Instance->RXDR);
3448 hspi->pRxBuffPtr += sizeof(uint8_t);
3449 hspi->RxXferCount--;
3450
3451 /* Disable IT if no more data excepted */
3452 if (hspi->RxXferCount == 0UL)
3453 {
3454 #if defined(USE_SPI_RELOAD_TRANSFER)
3455 /* Check if there is any request to reload */
3456 if (hspi->Reload.Requested == 1UL)
3457 {
3458 hspi->RxXferSize = hspi->Reload.RxXferSize;
3459 hspi->RxXferCount = hspi->Reload.RxXferSize;
3460 hspi->pRxBuffPtr = hspi->Reload.pRxBuffPtr;
3461 }
3462 else
3463 {
3464 /* Disable RXP interrupts */
3465 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
3466 }
3467 #else
3468 /* Disable RXP interrupts */
3469 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
3470 #endif /* USE_HSPI_RELOAD_TRANSFER */
3471 }
3472 }
3473
3474
3475 /**
3476 * @brief Manage the 16-bit receive in Interrupt context.
3477 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3478 * the configuration information for SPI module.
3479 * @retval None
3480 */
3481 static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi)
3482 {
3483 /* Receive data in 16 Bit mode */
3484 #if defined (__GNUC__)
3485 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
3486
3487 *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
3488 #else
3489 *((uint16_t *)hspi->pRxBuffPtr) = (*(__IO uint16_t *)&hspi->Instance->RXDR);
3490 #endif /* __GNUC__ */
3491 hspi->pRxBuffPtr += sizeof(uint16_t);
3492 hspi->RxXferCount--;
3493
3494 /* Disable IT if no more data excepted */
3495 if (hspi->RxXferCount == 0UL)
3496 {
3497 #if defined(USE_SPI_RELOAD_TRANSFER)
3498 /* Check if there is any request to reload */
3499 if (hspi->Reload.Requested == 1UL)
3500 {
3501 hspi->RxXferSize = hspi->Reload.RxXferSize;
3502 hspi->RxXferCount = hspi->Reload.RxXferSize;
3503 hspi->pRxBuffPtr = hspi->Reload.pRxBuffPtr;
3504 }
3505 else
3506 {
3507 /* Disable RXP interrupts */
3508 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
3509 }
3510 #else
3511 /* Disable RXP interrupts */
3512 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
3513 #endif /* USE_HSPI_RELOAD_TRANSFER */
3514 }
3515 }
3516
3517
3518 /**
3519 * @brief Manage the 32-bit receive in Interrupt context.
3520 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3521 * the configuration information for SPI module.
3522 * @retval None
3523 */
3524 static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi)
3525 {
3526 /* Receive data in 32 Bit mode */
3527 *((uint32_t *)hspi->pRxBuffPtr) = (*(__IO uint32_t *)&hspi->Instance->RXDR);
3528 hspi->pRxBuffPtr += sizeof(uint32_t);
3529 hspi->RxXferCount--;
3530
3531 /* Disable IT if no more data excepted */
3532 if (hspi->RxXferCount == 0UL)
3533 {
3534 #if defined(USE_SPI_RELOAD_TRANSFER)
3535 /* Check if there is any request to reload */
3536 if (hspi->Reload.Requested == 1UL)
3537 {
3538 hspi->RxXferSize = hspi->Reload.RxXferSize;
3539 hspi->RxXferCount = hspi->Reload.RxXferSize;
3540 hspi->pRxBuffPtr = hspi->Reload.pRxBuffPtr;
3541 }
3542 else
3543 {
3544 /* Disable RXP interrupts */
3545 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
3546 }
3547 #else
3548 /* Disable RXP interrupts */
3549 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
3550 #endif /* USE_HSPI_RELOAD_TRANSFER */
3551 }
3552 }
3553
3554
3555 /**
3556 * @brief Handle the data 8-bit transmit in Interrupt mode.
3557 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3558 * the configuration information for SPI module.
3559 * @retval None
3560 */
3561 static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi)
3562 {
3563 /* Transmit data in 8 Bit mode */
3564 *(__IO uint8_t *)&hspi->Instance->TXDR = *((uint8_t *)hspi->pTxBuffPtr);
3565 hspi->pTxBuffPtr += sizeof(uint8_t);
3566 hspi->TxXferCount--;
3567
3568 /* Disable IT if no more data excepted */
3569 if (hspi->TxXferCount == 0UL)
3570 {
3571 #if defined(USE_SPI_RELOAD_TRANSFER)
3572 /* Check if there is any request to reload */
3573 if (hspi->Reload.Requested == 1UL)
3574 {
3575 hspi->TxXferSize = hspi->Reload.TxXferSize;
3576 hspi->TxXferCount = hspi->Reload.TxXferSize;
3577 hspi->pTxBuffPtr = hspi->Reload.pTxBuffPtr;
3578 }
3579 else
3580 {
3581 /* Disable TXP interrupts */
3582 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
3583 }
3584 #else
3585 /* Disable TXP interrupts */
3586 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
3587 #endif /* USE_HSPI_RELOAD_TRANSFER */
3588 }
3589 }
3590
3591 /**
3592 * @brief Handle the data 16-bit transmit in Interrupt mode.
3593 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3594 * the configuration information for SPI module.
3595 * @retval None
3596 */
3597 static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi)
3598 {
3599 /* Transmit data in 16 Bit mode */
3600 #if defined (__GNUC__)
3601 __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
3602
3603 *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
3604 #else
3605 *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
3606 #endif /* __GNUC__ */
3607 hspi->pTxBuffPtr += sizeof(uint16_t);
3608 hspi->TxXferCount--;
3609
3610 /* Disable IT if no more data excepted */
3611 if (hspi->TxXferCount == 0UL)
3612 {
3613 #if defined(USE_SPI_RELOAD_TRANSFER)
3614 /* Check if there is any request to reload */
3615 if (hspi->Reload.Requested == 1UL)
3616 {
3617 hspi->TxXferSize = hspi->Reload.TxXferSize;
3618 hspi->TxXferCount = hspi->Reload.TxXferSize;
3619 hspi->pTxBuffPtr = hspi->Reload.pTxBuffPtr;
3620 }
3621 else
3622 {
3623 /* Disable TXP interrupts */
3624 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
3625 }
3626 #else
3627 /* Disable TXP interrupts */
3628 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
3629 #endif /* USE_HSPI_RELOAD_TRANSFER */
3630 }
3631 }
3632
3633 /**
3634 * @brief Handle the data 32-bit transmit in Interrupt mode.
3635 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3636 * the configuration information for SPI module.
3637 * @retval None
3638 */
3639 static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi)
3640 {
3641 /* Transmit data in 32 Bit mode */
3642 *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
3643 hspi->pTxBuffPtr += sizeof(uint32_t);
3644 hspi->TxXferCount--;
3645
3646 /* Disable IT if no more data excepted */
3647 if (hspi->TxXferCount == 0UL)
3648 {
3649 #if defined(USE_SPI_RELOAD_TRANSFER)
3650 /* Check if there is any request to reload */
3651 if (hspi->Reload.Requested == 1UL)
3652 {
3653 hspi->TxXferSize = hspi->Reload.TxXferSize;
3654 hspi->TxXferCount = hspi->Reload.TxXferSize;
3655 hspi->pTxBuffPtr = hspi->Reload.pTxBuffPtr;
3656 }
3657 else
3658 {
3659 /* Disable TXP interrupts */
3660 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
3661 }
3662 #else
3663 /* Disable TXP interrupts */
3664 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
3665 #endif /* USE_HSPI_RELOAD_TRANSFER */
3666 }
3667 }
3668
3669 /**
3670 * @brief Abort Transfer and clear flags.
3671 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3672 * the configuration information for SPI module.
3673 * @retval None
3674 */
3675 static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi)
3676 {
3677 /* Disable SPI peripheral */
3678 __HAL_SPI_DISABLE(hspi);
3679
3680 /* Disable ITs */
3681 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
3682
3683 /* Clear the Status flags in the SR register */
3684 __HAL_SPI_CLEAR_EOTFLAG(hspi);
3685 __HAL_SPI_CLEAR_TXTFFLAG(hspi);
3686
3687 /* Disable Tx DMA Request */
3688 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
3689
3690 /* Clear the Error flags in the SR register */
3691 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3692 __HAL_SPI_CLEAR_UDRFLAG(hspi);
3693 __HAL_SPI_CLEAR_FREFLAG(hspi);
3694 __HAL_SPI_CLEAR_MODFFLAG(hspi);
3695 __HAL_SPI_CLEAR_SUSPFLAG(hspi);
3696
3697 #if (USE_SPI_CRC != 0U)
3698 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3699 #endif /* USE_SPI_CRC */
3700
3701 hspi->TxXferCount = (uint16_t)0UL;
3702 hspi->RxXferCount = (uint16_t)0UL;
3703 }
3704
3705
3706 /**
3707 * @brief Close Transfer and clear flags.
3708 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3709 * the configuration information for SPI module.
3710 * @retval HAL_ERROR: if any error detected
3711 * HAL_OK: if nothing detected
3712 */
3713 static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi)
3714 {
3715 uint32_t itflag = hspi->Instance->SR;
3716
3717 __HAL_SPI_CLEAR_EOTFLAG(hspi);
3718 __HAL_SPI_CLEAR_TXTFFLAG(hspi);
3719
3720 /* Disable SPI peripheral */
3721 __HAL_SPI_DISABLE(hspi);
3722
3723 /* Disable ITs */
3724 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
3725
3726 /* Disable Tx DMA Request */
3727 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
3728
3729 /* Report UnderRun error for non RX Only communication */
3730 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
3731 {
3732 if ((itflag & SPI_FLAG_UDR) != 0UL)
3733 {
3734 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR);
3735 __HAL_SPI_CLEAR_UDRFLAG(hspi);
3736 }
3737 }
3738
3739 /* Report OverRun error for non TX Only communication */
3740 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
3741 {
3742 if ((itflag & SPI_FLAG_OVR) != 0UL)
3743 {
3744 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
3745 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3746 }
3747
3748 #if (USE_SPI_CRC != 0UL)
3749 /* Check if CRC error occurred */
3750 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3751 {
3752 if ((itflag & SPI_FLAG_CRCERR) != 0UL)
3753 {
3754 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3755 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3756 }
3757 }
3758 #endif /* USE_SPI_CRC */
3759 }
3760
3761 /* SPI Mode Fault error interrupt occurred -------------------------------*/
3762 if ((itflag & SPI_FLAG_MODF) != 0UL)
3763 {
3764 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
3765 __HAL_SPI_CLEAR_MODFFLAG(hspi);
3766 }
3767
3768 /* SPI Frame error interrupt occurred ------------------------------------*/
3769 if ((itflag & SPI_FLAG_FRE) != 0UL)
3770 {
3771 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
3772 __HAL_SPI_CLEAR_FREFLAG(hspi);
3773 }
3774
3775 hspi->TxXferCount = (uint16_t)0UL;
3776 hspi->RxXferCount = (uint16_t)0UL;
3777 }
3778
3779 /**
3780 * @brief Handle SPI Communication Timeout.
3781 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3782 * the configuration information for SPI module.
3783 * @param Flag: SPI flag to check
3784 * @param Status: flag state to check
3785 * @param Timeout: Timeout duration
3786 * @param Tickstart: Tick start value
3787 * @retval HAL status
3788 */
3789 static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status,
3790 uint32_t Tickstart, uint32_t Timeout)
3791 {
3792 /* Wait until flag is set */
3793 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) == Status)
3794 {
3795 /* Check for the Timeout */
3796 if ((((HAL_GetTick() - Tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
3797 {
3798 return HAL_TIMEOUT;
3799 }
3800 }
3801 return HAL_OK;
3802 }
3803
3804 /**
3805 * @brief Compute configured packet size from fifo perspective.
3806 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3807 * the configuration information for SPI module.
3808 * @retval Packet size occupied in the fifo
3809 */
3810 static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi)
3811 {
3812 uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL;
3813 uint32_t data_size = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) + 1UL;
3814
3815 /* Convert data size to Byte */
3816 data_size = (data_size + 7UL) / 8UL;
3817
3818 return data_size * fifo_threashold;
3819 }
3820
3821
3822 /**
3823 * @}
3824 */
3825
3826 #endif /* HAL_SPI_MODULE_ENABLED */
3827
3828 /**
3829 * @}
3830 */
3831
3832 /**
3833 * @}
3834 */
3835
3836 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/