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[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_ll_adc.c
blobdf018877fe271e108574068dfe46a5f54bc466ec
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32h7xx_ll_adc.h"
23 #include "stm32h7xx_ll_bus.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
36
37 /** @addtogroup ADC_LL ADC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /** @addtogroup ADC_LL_Private_Constants
45 * @{
46 */
47
48 /* Definitions of ADC hardware constraints delays */
49 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
50 /* not timeout values: */
51 /* Timeout values for ADC operations are dependent to device clock */
52 /* configuration (system clock versus ADC clock), */
53 /* and therefore must be defined in user application. */
54 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
55 /* values definition. */
56 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
57 /* of device clock setting. */
58 /* In user application, ADC timeout values should be defined with */
59 /* temporal values, in function of device clock settings. */
60 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
61 /* - ADC clock from synchronous clock with AHB prescaler 512, */
62 /* APB prescaler 16, ADC prescaler 4. */
63 /* - ADC clock from asynchronous clock (PLL) with prescaler 1, */
64 /* with highest ratio CPU clock frequency vs HSI clock frequency */
65 /* Unit: CPU cycles. */
66 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
67 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
68 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
69
70 /**
71 * @}
72 */
73
74 /* Private macros ------------------------------------------------------------*/
75
76 /** @addtogroup ADC_LL_Private_Macros
77 * @{
78 */
79
80 /* Check of parameters for configuration of ADC hierarchical scope: */
81 /* common to several ADC instances. */
82 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
83 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
84 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
85 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
86 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
87 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
93 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
94 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
97 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
98 )
99
100 /* Check of parameters for configuration of ADC hierarchical scope: */
101 /* ADC instance. */
102 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
103 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_16B) \
104 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_14B) \
105 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
106 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
107 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
108 )
109
110 #define IS_LL_ADC_LEFT_BIT_SHIFT(__LEFT_BIT_SHIFT__) \
111 ( ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_NONE) \
112 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_1) \
113 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_2) \
114 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_3) \
115 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_4) \
116 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_5) \
117 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_6) \
118 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_7) \
119 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_8) \
120 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_9) \
121 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_10) \
122 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_11) \
123 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_12) \
124 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_13) \
125 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_14) \
126 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_15) \
127 )
128
129 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
130 ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
131 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
132 )
133
134 /* Check of parameters for configuration of ADC hierarchical scope: */
135 /* ADC group regular */
136 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
137 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
144 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
145 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
146 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
147 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
148 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
149 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
150 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
151 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
152 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
153 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
154 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) \
155 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) \
156 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_OUT) \
157 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_OUT) \
158 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM3_OUT) \
159 )
160
161 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
162 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
163 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
164 )
165
166 #define IS_LL_ADC_REG_DATA_TRANSFER_MODE(__REG_DATA_TRANSFER_MODE__) \
167 ( ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DR_TRANSFER) \
168 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
169 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
170 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DFSDM_TRANSFER) \
171 )
172
173 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
174 ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
175 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
176 )
177
178 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
179 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
180 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
181 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
182 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
183 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
184 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
185 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
186 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
187 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
188 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
189 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
190 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
191 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
192 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
193 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
194 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
195 )
196
197 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
198 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
199 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
200 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
201 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
202 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
203 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
204 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
205 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
206 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
207 )
208
209 /* Check of parameters for configuration of ADC hierarchical scope: */
210 /* ADC group injected */
211 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
212 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
213 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
214 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
215 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
216 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
217 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
218 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
219 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
220 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
221 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
222 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
223 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
224 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
225 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
226 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
227 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
228 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
229 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) \
230 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) \
231 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) \
232 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) \
233 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) \
234 )
235
236 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
237 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
238 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
239 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
240 )
241
242 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
243 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
244 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
245 )
246
247 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
248 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
249 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
250 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
251 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
252 )
253
254 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
255 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
256 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
257 )
258
259 /* Check of parameters for configuration of ADC hierarchical scope: */
260 /* multimode. */
261 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
262 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
263 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
264 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
265 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
266 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
267 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
268 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
269 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
270 )
271
272 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
273 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
274 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_32_10B) \
275 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_8B) \
276 )
277 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
278 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) \
279 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) \
280 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) \
281 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) \
282 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS) \
283 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5) \
284 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS) \
285 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
286 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5) \
287 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS) \
288 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) \
289 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
290 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
291 )
292
293 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
294 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
295 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
296 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
297 )
298
299 /**
300 * @}
301 */
302
303
304 /* Private function prototypes -----------------------------------------------*/
305
306 /* Exported functions --------------------------------------------------------*/
307 /** @addtogroup ADC_LL_Exported_Functions
308 * @{
309 */
310
311 /** @addtogroup ADC_LL_EF_Init
312 * @{
313 */
314
315 /**
316 * @brief De-initialize registers of all ADC instances belonging to
317 * the same ADC common instance to their default reset values.
318 * @note This function is performing a hard reset, using high level
319 * clock source RCC ADC reset.
320 * Caution: On this STM32 serie, if several ADC instances are available
321 * on the selected device, RCC ADC reset will reset
322 * all ADC instances belonging to the common ADC instance.
323 * To de-initialize only 1 ADC instance, use
324 * function @ref LL_ADC_DeInit().
325 * @param ADCxy_COMMON ADC common instance
326 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
327 * @retval An ErrorStatus enumeration value:
328 * - SUCCESS: ADC common registers are de-initialized
329 * - ERROR: not applicable
330 */
331 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
332 {
333 /* Check the parameters */
334 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
335
336 if (ADCxy_COMMON == ADC12_COMMON)
337 {
338 /* Force reset of ADC clock (core clock) */
339 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ADC12);
340
341 /* Release reset of ADC clock (core clock) */
342 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
343 }
344 else
345 {
346 #if defined (ADC3)
347 /* Force reset of ADC clock (core clock) */
348 LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_ADC3);
349
350 /* Release reset of ADC clock (core clock) */
351 LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_ADC3);
352 #endif
353 }
354
355 return SUCCESS;
356 }
357
358 /**
359 * @brief Initialize some features of ADC common parameters
360 * (all ADC instances belonging to the same ADC common instance)
361 * and multimode (for devices with several ADC instances available).
362 * @note The setting of ADC common parameters is conditioned to
363 * ADC instances state:
364 * All ADC instances belonging to the same ADC common instance
365 * must be disabled.
366 * @param ADCxy_COMMON ADC common instance
367 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
368 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
369 * @retval An ErrorStatus enumeration value:
370 * - SUCCESS: ADC common registers are initialized
371 * - ERROR: ADC common registers are not initialized
372 */
373 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
374 {
375 ErrorStatus status = SUCCESS;
376
377 /* Check the parameters */
378 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
379 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
380
381 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
382 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
383 {
384 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
385 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
386 }
387
388 /* Note: Hardware constraint (refer to description of functions */
389 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
390 /* On this STM32 serie, setting of these features is conditioned to */
391 /* ADC state: */
392 /* All ADC instances of the ADC common group must be disabled. */
393 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
394 {
395 /* Configuration of ADC hierarchical scope: */
396 /* - common to several ADC */
397 /* (all ADC instances belonging to the same ADC common instance) */
398 /* - Set ADC clock (conversion clock) */
399 /* - multimode (if several ADC instances available on the */
400 /* selected device) */
401 /* - Set ADC multimode configuration */
402 /* - Set ADC multimode DMA transfer */
403 /* - Set ADC multimode: delay between 2 sampling phases */
404 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
405 {
406 MODIFY_REG(ADCxy_COMMON->CCR,
407 ADC_CCR_CKMODE
408 | ADC_CCR_PRESC
409 | ADC_CCR_DUAL
410 | ADC_CCR_DAMDF
411 | ADC_CCR_DELAY
412 ,
413 ADC_CommonInitStruct->CommonClock
414 | ADC_CommonInitStruct->Multimode
415 | ADC_CommonInitStruct->MultiDMATransfer
416 | ADC_CommonInitStruct->MultiTwoSamplingDelay
417 );
418 }
419 else
420 {
421 MODIFY_REG(ADCxy_COMMON->CCR,
422 ADC_CCR_CKMODE
423 | ADC_CCR_PRESC
424 | ADC_CCR_DUAL
425 | ADC_CCR_DAMDF
426 | ADC_CCR_DELAY
427 ,
428 ADC_CommonInitStruct->CommonClock
429 | LL_ADC_MULTI_INDEPENDENT
430 );
431 }
432 }
433 else
434 {
435 /* Initialization error: One or several ADC instances belonging to */
436 /* the same ADC common instance are not disabled. */
437 status = ERROR;
438 }
439
440 return status;
441 }
442
443 /**
444 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
445 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
446 * whose fields will be set to default values.
447 * @retval None
448 */
449 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
450 {
451 /* Set ADC_CommonInitStruct fields to default values */
452 /* Set fields of ADC common */
453 /* (all ADC instances belonging to the same ADC common instance) */
454 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
455
456 /* Set fields of ADC multimode */
457 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
458 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
459 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5;
460 }
461
462 /**
463 * @brief De-initialize registers of the selected ADC instance
464 * to their default reset values.
465 * @note To reset all ADC instances quickly (perform a hard reset),
466 * use function @ref LL_ADC_CommonDeInit().
467 * @note If this functions returns error status, it means that ADC instance
468 * is in an unknown state.
469 * In this case, perform a hard reset using high level
470 * clock source RCC ADC reset.
471 * Caution: On this STM32 serie, if several ADC instances are available
472 * on the selected device, RCC ADC reset will reset
473 * all ADC instances belonging to the common ADC instance.
474 * Refer to function @ref LL_ADC_CommonDeInit().
475 * @param ADCx ADC instance
476 * @retval An ErrorStatus enumeration value:
477 * - SUCCESS: ADC registers are de-initialized
478 * - ERROR: ADC registers are not de-initialized
479 */
480 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
481 {
482 ErrorStatus status = SUCCESS;
483
484 __IO uint32_t timeout_cpu_cycles = 0UL;
485
486 /* Check the parameters */
487 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
488
489 /* Disable ADC instance if not already disabled. */
490 if (LL_ADC_IsEnabled(ADCx) == 1UL)
491 {
492 /* Set ADC group regular trigger source to SW start to ensure to not */
493 /* have an external trigger event occurring during the conversion stop */
494 /* ADC disable process. */
495 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
496
497 /* Stop potential ADC conversion on going on ADC group regular. */
498 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
499 {
500 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
501 {
502 LL_ADC_REG_StopConversion(ADCx);
503 }
504 }
505
506 /* Set ADC group injected trigger source to SW start to ensure to not */
507 /* have an external trigger event occurring during the conversion stop */
508 /* ADC disable process. */
509 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
510
511 /* Stop potential ADC conversion on going on ADC group injected. */
512 if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
513 {
514 if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
515 {
516 LL_ADC_INJ_StopConversion(ADCx);
517 }
518 }
519
520 /* Wait for ADC conversions are effectively stopped */
521 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
522 while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
523 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
524 {
525 timeout_cpu_cycles--;
526 if (timeout_cpu_cycles == 0UL)
527 {
528 /* Time-out error */
529 status = ERROR;
530 break;
531 }
532 }
533
534 /* Flush group injected contexts queue (register JSQR): */
535 /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
536 /* contexts queue is maintained with the last active context). */
537 LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
538
539 /* Disable the ADC instance */
540 LL_ADC_Disable(ADCx);
541
542 /* Wait for ADC instance is effectively disabled */
543 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
544 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
545 {
546 timeout_cpu_cycles--;
547 if (timeout_cpu_cycles == 0UL)
548 {
549 /* Time-out error */
550 status = ERROR;
551 break;
552 }
553 }
554 }
555
556 /* Check whether ADC state is compliant with expected state */
557 if (READ_BIT(ADCx->CR,
558 (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
559 | ADC_CR_ADDIS | ADC_CR_ADEN)
560 )
561 == 0UL)
562 {
563 /* ========== Reset ADC registers ========== */
564 /* Reset register IER */
565 CLEAR_BIT(ADCx->IER,
566 (LL_ADC_IT_ADRDY
567 | LL_ADC_IT_EOC
568 | LL_ADC_IT_EOS
569 | LL_ADC_IT_OVR
570 | LL_ADC_IT_EOSMP
571 | LL_ADC_IT_JEOC
572 | LL_ADC_IT_JEOS
573 | LL_ADC_IT_JQOVF
574 | LL_ADC_IT_AWD1
575 | LL_ADC_IT_AWD2
576 | LL_ADC_IT_AWD3
577 )
578 );
579
580 /* Reset register ISR */
581 SET_BIT(ADCx->ISR,
582 (LL_ADC_FLAG_ADRDY
583 | LL_ADC_FLAG_EOC
584 | LL_ADC_FLAG_EOS
585 | LL_ADC_FLAG_OVR
586 | LL_ADC_FLAG_EOSMP
587 | LL_ADC_FLAG_JEOC
588 | LL_ADC_FLAG_JEOS
589 | LL_ADC_FLAG_JQOVF
590 | LL_ADC_FLAG_AWD1
591 | LL_ADC_FLAG_AWD2
592 | LL_ADC_FLAG_AWD3
593 )
594 );
595
596 /* Reset register CR */
597 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
598 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
599 /* access mode "read-set": no direct reset applicable. */
600 /* - Reset Calibration mode to default setting (single ended). */
601 /* - Disable ADC internal voltage regulator. */
602 /* - Enable ADC deep power down. */
603 /* Note: ADC internal voltage regulator disable and ADC deep power */
604 /* down enable are conditioned to ADC state disabled: */
605 /* already done above. */
606 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
607 SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
608
609 /* Reset register CFGR */
610 CLEAR_BIT(ADCx->CFGR,
611 (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
612 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
613 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
614 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
615 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_RES
616 | ADC_CFGR_DMNGT)
617 );
618
619 SET_BIT(ADCx->CFGR, ADC_CFGR_JQDIS);
620
621 /* Reset register CFGR2 */
622 CLEAR_BIT(ADCx->CFGR2,
623 (ADC_CFGR2_LSHIFT | ADC_CFGR2_OVSR | ADC_CFGR2_RSHIFT1
624 | ADC_CFGR2_RSHIFT4 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT2
625 | ADC_CFGR2_RSHIFT1 | ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS
626 | ADC_CFGR2_OVSS | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
627 );
628
629 /* Reset register SMPR1 */
630 CLEAR_BIT(ADCx->SMPR1,
631 (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
632 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
633 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
634 );
635
636 /* Reset register SMPR2 */
637 CLEAR_BIT(ADCx->SMPR2,
638 (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17
639 | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14
640 | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11
641 | ADC_SMPR2_SMP10)
642 );
643
644 /* Reset register TR1 */
645 #if defined(ADC_VER_V5_V90)
646 if (ADCx == ADC3)
647 {
648 /* Reset register TR1 */
649 MODIFY_REG(ADCx->LTR1_TR1, ADC3_TR1_AWDFILT | ADC3_TR1_HT1 | ADC3_TR1_LT1, ADC3_TR1_HT1);
650
651 /* Reset register TR2 */
652 MODIFY_REG(ADCx->HTR1_TR2, ADC3_TR2_HT2 | ADC3_TR2_LT2, ADC3_TR2_HT2);
653
654 /* Reset register TR3 */
655 MODIFY_REG(ADCx->RES1_TR3, ADC3_TR3_HT3 | ADC3_TR3_LT3, ADC3_TR3_HT3);
656 }
657 else
658 {
659 CLEAR_BIT(ADCx->LTR1_TR1, ADC_LTR_LT);
660 SET_BIT(ADCx->HTR1_TR2, ADC_HTR_HT);
661
662 CLEAR_BIT(ADCx->LTR2_DIFSEL, ADC_LTR_LT);
663 SET_BIT(ADCx->HTR2_CALFACT, ADC_HTR_HT);
664 CLEAR_BIT(ADCx->LTR3_RES10, ADC_LTR_LT);
665 SET_BIT(ADCx->HTR3_RES11, ADC_HTR_HT);
666 }
667 #else
668 CLEAR_BIT(ADCx->LTR1, ADC_LTR_LT);
669 SET_BIT(ADCx->HTR1, ADC_HTR_HT);
670
671 CLEAR_BIT(ADCx->LTR2, ADC_LTR_LT);
672 SET_BIT(ADCx->HTR2, ADC_HTR_HT);
673 CLEAR_BIT(ADCx->LTR3, ADC_LTR_LT);
674 SET_BIT(ADCx->HTR3, ADC_HTR_HT);
675 #endif
676
677 /* Reset register SQR1 */
678 CLEAR_BIT(ADCx->SQR1,
679 (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
680 | ADC_SQR1_SQ1 | ADC_SQR1_L)
681 );
682
683 /* Reset register SQR2 */
684 CLEAR_BIT(ADCx->SQR2,
685 (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
686 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
687 );
688
689 /* Reset register SQR3 */
690 CLEAR_BIT(ADCx->SQR3,
691 (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
692 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
693 );
694
695 /* Reset register SQR4 */
696 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
697
698 /* Reset register JSQR */
699 CLEAR_BIT(ADCx->JSQR,
700 (ADC_JSQR_JL
701 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
702 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
703 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1)
704 );
705
706 /* Reset register DR */
707 /* Note: bits in access mode read only, no direct reset applicable */
708
709 /* Reset register OFR1 */
710 CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_SSATE);
711 /* Reset register OFR2 */
712 CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2 | ADC_OFR2_OFFSET2_CH | ADC_OFR2_SSATE);
713 /* Reset register OFR3 */
714 CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3 | ADC_OFR3_OFFSET3_CH | ADC_OFR3_SSATE);
715 /* Reset register OFR4 */
716 CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4 | ADC_OFR4_OFFSET4_CH | ADC_OFR4_SSATE);
717
718 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
719 /* Note: bits in access mode read only, no direct reset applicable */
720
721 /* Reset register AWD2CR */
722 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
723
724 /* Reset register AWD3CR */
725 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
726
727 /* Reset register DIFSEL */
728 #if defined(ADC_VER_V5_V90)
729 if (ADCx == ADC3)
730 {
731 CLEAR_BIT(ADCx->LTR2_DIFSEL, ADC_DIFSEL_DIFSEL);
732
733 /* Reset register CALFACT */
734 CLEAR_BIT(ADCx->HTR2_CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
735 }
736 else
737 {
738 CLEAR_BIT(ADCx->DIFSEL_RES12, ADC_DIFSEL_DIFSEL);
739
740 /* Reset register CALFACT */
741 CLEAR_BIT(ADCx->CALFACT_RES13, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
742
743 /* Reset register CALFACT2 */
744 CLEAR_BIT(ADCx->CALFACT2_RES14, ADC_CALFACT2_LINCALFACT);
745 }
746 #else
747 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
748
749 /* Reset register CALFACT */
750 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
751
752 /* Reset register CALFACT2 */
753 CLEAR_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT);
754 #endif
755 }
756 else
757 {
758 /* ADC instance is in an unknown state */
759 /* Need to performing a hard reset of ADC instance, using high level */
760 /* clock source RCC ADC reset. */
761 /* Caution: On this STM32 serie, if several ADC instances are available */
762 /* on the selected device, RCC ADC reset will reset */
763 /* all ADC instances belonging to the common ADC instance. */
764 /* Caution: On this STM32 serie, if several ADC instances are available */
765 /* on the selected device, RCC ADC reset will reset */
766 /* all ADC instances belonging to the common ADC instance. */
767 status = ERROR;
768 }
769
770 return status;
771 }
772
773 /**
774 * @brief Initialize some features of ADC instance.
775 * @note These parameters have an impact on ADC scope: ADC instance.
776 * Affects both group regular and group injected (availability
777 * of ADC group injected depends on STM32 families).
778 * Refer to corresponding unitary functions into
779 * @ref ADC_LL_EF_Configuration_ADC_Instance .
780 * @note The setting of these parameters by function @ref LL_ADC_Init()
781 * is conditioned to ADC state:
782 * ADC instance must be disabled.
783 * This condition is applied to all ADC features, for efficiency
784 * and compatibility over all STM32 families. However, the different
785 * features can be set under different ADC state conditions
786 * (setting possible with ADC enabled without conversion on going,
787 * ADC enabled with conversion on going, ...)
788 * Each feature can be updated afterwards with a unitary function
789 * and potentially with ADC in a different state than disabled,
790 * refer to description of each function for setting
791 * conditioned to ADC state.
792 * @note After using this function, some other features must be configured
793 * using LL unitary functions.
794 * The minimum configuration remaining to be done is:
795 * - Set ADC group regular or group injected sequencer:
796 * map channel on the selected sequencer rank.
797 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
798 * - Set ADC channel sampling time
799 * Refer to function LL_ADC_SetChannelSamplingTime();
800 * @param ADCx ADC instance
801 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
802 * @retval An ErrorStatus enumeration value:
803 * - SUCCESS: ADC registers are initialized
804 * - ERROR: ADC registers are not initialized
805 */
806 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
807 {
808 ErrorStatus status = SUCCESS;
809
810 /* Check the parameters */
811 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
812
813 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
814 assert_param(IS_LL_ADC_LEFT_BIT_SHIFT(ADC_InitStruct->LeftBitShift));
815 assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
816
817 /* Note: Hardware constraint (refer to description of this function): */
818 /* ADC instance must be disabled. */
819 if (LL_ADC_IsEnabled(ADCx) == 0UL)
820 {
821 /* Configuration of ADC hierarchical scope: */
822 /* - ADC instance */
823 /* - Set ADC data resolution */
824 /* - Set ADC conversion data alignment */
825 /* - Set ADC low power mode */
826 MODIFY_REG(ADCx->CFGR,
827 ADC_CFGR_RES
828 | ADC_CFGR_AUTDLY
829 ,
830 ADC_InitStruct->Resolution
831 | ADC_InitStruct->LowPowerMode
832 );
833
834 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LSHIFT, ADC_InitStruct->LeftBitShift);
835 }
836 else
837 {
838 /* Initialization error: ADC instance is not disabled. */
839 status = ERROR;
840 }
841 return status;
842 }
843
844 /**
845 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
846 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
847 * whose fields will be set to default values.
848 * @retval None
849 */
850 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
851 {
852 /* Set ADC_InitStruct fields to default values */
853 /* Set fields of ADC instance */
854 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_16B;
855 ADC_InitStruct->LeftBitShift = LL_ADC_LEFT_BIT_SHIFT_NONE;
856 ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
857
858 }
859
860 /**
861 * @brief Initialize some features of ADC group regular.
862 * @note These parameters have an impact on ADC scope: ADC group regular.
863 * Refer to corresponding unitary functions into
864 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
865 * (functions with prefix "REG").
866 * @note The setting of these parameters by function @ref LL_ADC_Init()
867 * is conditioned to ADC state:
868 * ADC instance must be disabled.
869 * This condition is applied to all ADC features, for efficiency
870 * and compatibility over all STM32 families. However, the different
871 * features can be set under different ADC state conditions
872 * (setting possible with ADC enabled without conversion on going,
873 * ADC enabled with conversion on going, ...)
874 * Each feature can be updated afterwards with a unitary function
875 * and potentially with ADC in a different state than disabled,
876 * refer to description of each function for setting
877 * conditioned to ADC state.
878 * @note After using this function, other features must be configured
879 * using LL unitary functions.
880 * The minimum configuration remaining to be done is:
881 * - Set ADC group regular or group injected sequencer:
882 * map channel on the selected sequencer rank.
883 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
884 * - Set ADC channel sampling time
885 * Refer to function LL_ADC_SetChannelSamplingTime();
886 * @param ADCx ADC instance
887 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
888 * @retval An ErrorStatus enumeration value:
889 * - SUCCESS: ADC registers are initialized
890 * - ERROR: ADC registers are not initialized
891 */
892 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
893 {
894 ErrorStatus status = SUCCESS;
895
896 /* Check the parameters */
897 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
898 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
899 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
900 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
901 {
902 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
903 }
904 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
905 assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(ADC_REG_InitStruct->DataTransferMode));
906 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
907
908 /* Note: Hardware constraint (refer to description of this function): */
909 /* ADC instance must be disabled. */
910 if (LL_ADC_IsEnabled(ADCx) == 0UL)
911 {
912 /* Configuration of ADC hierarchical scope: */
913 /* - ADC group regular */
914 /* - Set ADC group regular trigger source */
915 /* - Set ADC group regular sequencer length */
916 /* - Set ADC group regular sequencer discontinuous mode */
917 /* - Set ADC group regular continuous mode */
918 /* - Set ADC group regular conversion data transfer: no transfer or */
919 /* transfer by DMA, and DMA requests mode */
920 /* - Set ADC group regular overrun behavior */
921 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
922 /* setting of trigger source to SW start. */
923 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
924 {
925 MODIFY_REG(ADCx->CFGR,
926 ADC_CFGR_EXTSEL
927 | ADC_CFGR_EXTEN
928 | ADC_CFGR_DISCEN
929 | ADC_CFGR_DISCNUM
930 | ADC_CFGR_CONT
931 | ADC_CFGR_DMNGT
932 | ADC_CFGR_OVRMOD
933 ,
934 ADC_REG_InitStruct->TriggerSource
935 | ADC_REG_InitStruct->SequencerDiscont
936 | ADC_REG_InitStruct->ContinuousMode
937 | ADC_REG_InitStruct->DataTransferMode
938 | ADC_REG_InitStruct->Overrun
939 );
940 }
941 else
942 {
943 MODIFY_REG(ADCx->CFGR,
944 ADC_CFGR_EXTSEL
945 | ADC_CFGR_EXTEN
946 | ADC_CFGR_DISCEN
947 | ADC_CFGR_DISCNUM
948 | ADC_CFGR_CONT
949 | ADC_CFGR_DMNGT
950 | ADC_CFGR_OVRMOD
951 ,
952 ADC_REG_InitStruct->TriggerSource
953 | LL_ADC_REG_SEQ_DISCONT_DISABLE
954 | ADC_REG_InitStruct->ContinuousMode
955 | ADC_REG_InitStruct->DataTransferMode
956 | ADC_REG_InitStruct->Overrun
957 );
958 }
959
960 /* Set ADC group regular sequencer length and scan direction */
961 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
962 }
963 else
964 {
965 /* Initialization error: ADC instance is not disabled. */
966 status = ERROR;
967 }
968 return status;
969 }
970
971 /**
972 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
973 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
974 * whose fields will be set to default values.
975 * @retval None
976 */
977 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
978 {
979 /* Set ADC_REG_InitStruct fields to default values */
980 /* Set fields of ADC group regular */
981 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
982 /* setting of trigger source to SW start. */
983 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
984 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
985 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
986 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
987 ADC_REG_InitStruct->DataTransferMode = LL_ADC_REG_DR_TRANSFER;
988 ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
989 }
990
991 /**
992 * @brief Initialize some features of ADC group injected.
993 * @note These parameters have an impact on ADC scope: ADC group injected.
994 * Refer to corresponding unitary functions into
995 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
996 * (functions with prefix "INJ").
997 * @note The setting of these parameters by function @ref LL_ADC_Init()
998 * is conditioned to ADC state:
999 * ADC instance must be disabled.
1000 * This condition is applied to all ADC features, for efficiency
1001 * and compatibility over all STM32 families. However, the different
1002 * features can be set under different ADC state conditions
1003 * (setting possible with ADC enabled without conversion on going,
1004 * ADC enabled with conversion on going, ...)
1005 * Each feature can be updated afterwards with a unitary function
1006 * and potentially with ADC in a different state than disabled,
1007 * refer to description of each function for setting
1008 * conditioned to ADC state.
1009 * @note After using this function, other features must be configured
1010 * using LL unitary functions.
1011 * The minimum configuration remaining to be done is:
1012 * - Set ADC group injected sequencer:
1013 * map channel on the selected sequencer rank.
1014 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
1015 * - Set ADC channel sampling time
1016 * Refer to function LL_ADC_SetChannelSamplingTime();
1017 * @param ADCx ADC instance
1018 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1019 * @retval An ErrorStatus enumeration value:
1020 * - SUCCESS: ADC registers are initialized
1021 * - ERROR: ADC registers are not initialized
1022 */
1023 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1024 {
1025 ErrorStatus status = SUCCESS;
1026
1027 /* Check the parameters */
1028 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1029 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
1030 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
1031 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
1032 {
1033 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
1034 }
1035 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
1036
1037 /* Note: Hardware constraint (refer to description of this function): */
1038 /* ADC instance must be disabled. */
1039 if (LL_ADC_IsEnabled(ADCx) == 0UL)
1040 {
1041 /* Configuration of ADC hierarchical scope: */
1042 /* - ADC group injected */
1043 /* - Set ADC group injected trigger source */
1044 /* - Set ADC group injected sequencer length */
1045 /* - Set ADC group injected sequencer discontinuous mode */
1046 /* - Set ADC group injected conversion trigger: independent or */
1047 /* from ADC group regular */
1048 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
1049 /* setting of trigger source to SW start. */
1050 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1051 {
1052 MODIFY_REG(ADCx->CFGR,
1053 ADC_CFGR_JDISCEN
1054 | ADC_CFGR_JAUTO
1055 ,
1056 ADC_INJ_InitStruct->SequencerDiscont
1057 | ADC_INJ_InitStruct->TrigAuto
1058 );
1059 }
1060 else
1061 {
1062 MODIFY_REG(ADCx->CFGR,
1063 ADC_CFGR_JDISCEN
1064 | ADC_CFGR_JAUTO
1065 ,
1066 LL_ADC_REG_SEQ_DISCONT_DISABLE
1067 | ADC_INJ_InitStruct->TrigAuto
1068 );
1069 }
1070
1071 MODIFY_REG(ADCx->JSQR,
1072 ADC_JSQR_JEXTSEL
1073 | ADC_JSQR_JEXTEN
1074 | ADC_JSQR_JL
1075 ,
1076 ADC_INJ_InitStruct->TriggerSource
1077 | ADC_INJ_InitStruct->SequencerLength
1078 );
1079 }
1080 else
1081 {
1082 /* Initialization error: ADC instance is not disabled. */
1083 status = ERROR;
1084 }
1085 return status;
1086 }
1087
1088 /**
1089 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1090 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1091 * whose fields will be set to default values.
1092 * @retval None
1093 */
1094 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1095 {
1096 /* Set ADC_INJ_InitStruct fields to default values */
1097 /* Set fields of ADC group injected */
1098 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1099 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1100 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1101 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1102 }
1103
1104 /**
1105 * @}
1106 */
1107
1108 /**
1109 * @}
1110 */
1111
1112 /**
1113 * @}
1114 */
1115
1116 #endif /* ADC1 || ADC2 || ADC3 */
1117
1118 /**
1119 * @}
1120 */
1121
1122 #endif /* USE_FULL_LL_DRIVER */
1123
1124 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/