lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32h7xx_ll_fmc.c
   4   * @author  MCD Application Team
   5   * @brief   FMC Low Layer HAL module driver.
   6   *
   7   *          This file provides firmware functions to manage the following
   8   *          functionalities of the Flexible Memory Controller (FMC) peripheral memories:
   9   *           + Initialization/de-initialization functions
  10   *           + Peripheral Control functions
  11   *           + Peripheral State functions
  12   *
  13   @verbatim
  14   ==============================================================================
  15                         ##### FMC peripheral features #####
  16   ==============================================================================
  17   [..] The Flexible memory controller (FMC) includes following memory controllers:
  18        (+) The NOR/PSRAM memory controller
  19            (+) The NAND memory controller
  20        (+) The Synchronous DRAM (SDRAM) controller
  21
  22   [..] The FMC functional block makes the interface with synchronous and asynchronous static
  23        memories and SDRAM memories. Its main purposes are:
  24        (+) to translate AHB transactions into the appropriate external device protocol
  25        (+) to meet the access time requirements of the external memory devices
  26
  27   [..] All external memories share the addresses, data and control signals with the controller.
  28        Each external device is accessed by means of a unique Chip Select. The FMC performs
  29        only one access at a time to an external device.
  30        The main features of the FMC controller are the following:
  31         (+) Interface with static-memory mapped devices including:
  32            (++) Static random access memory (SRAM)
  33            (++) Read-only memory (ROM)
  34            (++) NOR Flash memory/OneNAND Flash memory
  35            (++) PSRAM (4 memory banks)
  36            (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
  37                 data
  38         (+) Interface with synchronous DRAM (SDRAM) memories
  39         (+) Independent Chip Select control for each memory bank
  40         (+) Independent configuration for each memory bank
  41
  42   @endverbatim
  43   ******************************************************************************
  44   * @attention
  45   *
  46   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  47   * All rights reserved.</center></h2>
  48   *
  49   * This software component is licensed by ST under BSD 3-Clause license,
  50   * the "License"; You may not use this file except in compliance with the
  51   * License. You may obtain a copy of the License at:
  52   *                       opensource.org/licenses/BSD-3-Clause
  53   *
  54   ******************************************************************************
  55   */
  56
  57 /* Includes ------------------------------------------------------------------*/
  58 #include "stm32h7xx_hal.h"
  59
  60 /** @addtogroup STM32H7xx_HAL_Driver
  61   * @{
  62   */
  63 #if (((defined HAL_NOR_MODULE_ENABLED || defined HAL_SRAM_MODULE_ENABLED)) || defined HAL_NAND_MODULE_ENABLED || defined HAL_SDRAM_MODULE_ENABLED)
  64
  65 /** @defgroup FMC_LL  FMC Low Layer
  66   * @brief FMC driver modules
  67   * @{
  68   */
  69
  70 /* Private typedef -----------------------------------------------------------*/
  71 /* Private define ------------------------------------------------------------*/
  72
  73 /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
  74   * @{
  75   */
  76
  77 /* ----------------------- FMC registers bit mask --------------------------- */
  78
  79 /* --- BCR Register ---*/
  80 /* BCR register clear mask */
  81
  82 /* --- BTR Register ---*/
  83 /* BTR register clear mask */
  84 #define BTR_CLEAR_MASK    ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD  |\
  85                                       FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
  86                                       FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT  |\
  87                                       FMC_BTRx_ACCMOD))
  88
  89 /* --- BWTR Register ---*/
  90 /* BWTR register clear mask */
  91 #if defined(FMC_BWTRx_BUSTURN)
  92 #define BWTR_CLEAR_MASK   ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD  |\
  93                                       FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\
  94                                       FMC_BWTRx_ACCMOD))
  95 #else
  96 #define BWTR_CLEAR_MASK   ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD  |\
  97                                       FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD))
  98 #endif /* FMC_BWTRx_BUSTURN */
  99
 100 /* --- PCR Register ---*/
 101 /* PCR register clear mask */
 102 #define PCR_CLEAR_MASK    ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN  | \
 103                                       FMC_PCR_PWID    | FMC_PCR_ECCEN  | \
 104                                       FMC_PCR_TCLR    | FMC_PCR_TAR    | \
 105                                       FMC_PCR_ECCPS))
 106 /* --- PMEM Register ---*/
 107 /* PMEM register clear mask */
 108 #define PMEM_CLEAR_MASK   ((uint32_t)(FMC_PMEM_MEMSET  | FMC_PMEM_MEMWAIT |\
 109                                       FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ))
 110
 111 /* --- PATT Register ---*/
 112 /* PATT register clear mask */
 113 #define PATT_CLEAR_MASK   ((uint32_t)(FMC_PATT_ATTSET  | FMC_PATT_ATTWAIT |\
 114                                       FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ))
 115
 116
 117 /* --- SDCR Register ---*/
 118 /* SDCR register clear mask */
 119 #define SDCR_CLEAR_MASK   ((uint32_t)(FMC_SDCRx_NC    | FMC_SDCRx_NR     | \
 120                                       FMC_SDCRx_MWID  | FMC_SDCRx_NB     | \
 121                                       FMC_SDCRx_CAS   | FMC_SDCRx_WP     | \
 122                                       FMC_SDCRx_SDCLK | FMC_SDCRx_RBURST | \
 123                                       FMC_SDCRx_RPIPE))
 124
 125 /* --- SDTR Register ---*/
 126 /* SDTR register clear mask */
 127 #define SDTR_CLEAR_MASK   ((uint32_t)(FMC_SDTRx_TMRD  | FMC_SDTRx_TXSR   | \
 128                                       FMC_SDTRx_TRAS  | FMC_SDTRx_TRC    | \
 129                                       FMC_SDTRx_TWR   | FMC_SDTRx_TRP    | \
 130                                       FMC_SDTRx_TRCD))
 131
 132 /**
 133   * @}
 134   */
 135
 136 /* Private macro -------------------------------------------------------------*/
 137 /* Private variables ---------------------------------------------------------*/
 138 /* Private function prototypes -----------------------------------------------*/
 139 /* Exported functions --------------------------------------------------------*/
 140
 141 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
 142   * @{
 143   */
 144
 145
 146 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
 147   * @brief  NORSRAM Controller functions
 148   *
 149   @verbatim
 150   ==============================================================================
 151                    ##### How to use NORSRAM device driver #####
 152   ==============================================================================
 153
 154   [..]
 155     This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
 156     to run the NORSRAM external devices.
 157
 158     (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
 159     (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
 160     (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
 161     (+) FMC NORSRAM bank extended timing configuration using the function
 162         FMC_NORSRAM_Extended_Timing_Init()
 163     (+) FMC NORSRAM bank enable/disable write operation using the functions
 164         FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
 165
 166 @endverbatim
 167   * @{
 168   */
 169
 170 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
 171   * @brief    Initialization and Configuration functions
 172   *
 173   @verbatim
 174   ==============================================================================
 175               ##### Initialization and de_initialization functions #####
 176   ==============================================================================
 177   [..]
 178     This section provides functions allowing to:
 179     (+) Initialize and configure the FMC NORSRAM interface
 180     (+) De-initialize the FMC NORSRAM interface
 181     (+) Configure the FMC clock and associated GPIOs
 182
 183 @endverbatim
 184   * @{
 185   */
 186
 187 /**
 188   * @brief  Initialize the FMC_NORSRAM device according to the specified
 189   *         control parameters in the FMC_NORSRAM_InitTypeDef
 190   * @param  Device Pointer to NORSRAM device instance
 191   * @param  Init Pointer to NORSRAM Initialization structure
 192   * @retval HAL status
 193   */
 194 HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
 195 {
 196   uint32_t flashaccess;
 197   uint32_t btcr_reg;
 198   uint32_t mask;
 199
 200   /* Check the parameters */
 201   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 202   assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
 203   assert_param(IS_FMC_MUX(Init->DataAddressMux));
 204   assert_param(IS_FMC_MEMORY(Init->MemoryType));
 205   assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
 206   assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
 207   assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
 208   assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
 209   assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
 210   assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
 211   assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
 212   assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
 213   assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
 214   assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
 215   assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
 216   assert_param(IS_FMC_PAGESIZE(Init->PageSize));
 217
 218   /* Disable NORSRAM Device */
 219   __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
 220
 221   /* Set NORSRAM device control parameters */
 222   if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
 223   {
 224     flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
 225   }
 226   else
 227   {
 228     flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
 229   }
 230
 231   btcr_reg = (flashaccess                   | \
 232               Init->DataAddressMux          | \
 233               Init->MemoryType              | \
 234               Init->MemoryDataWidth         | \
 235               Init->BurstAccessMode         | \
 236               Init->WaitSignalPolarity      | \
 237               Init->WaitSignalActive        | \
 238               Init->WriteOperation          | \
 239               Init->WaitSignal              | \
 240               Init->ExtendedMode            | \
 241               Init->AsynchronousWait        | \
 242               Init->WriteBurst);
 243
 244   btcr_reg |= Init->ContinuousClock;
 245   btcr_reg |= Init->WriteFifo;
 246   btcr_reg |= Init->PageSize;
 247
 248   mask = (FMC_BCRx_MBKEN                |
 249           FMC_BCRx_MUXEN                |
 250           FMC_BCRx_MTYP                 |
 251           FMC_BCRx_MWID                 |
 252           FMC_BCRx_FACCEN               |
 253           FMC_BCRx_BURSTEN              |
 254           FMC_BCRx_WAITPOL              |
 255           FMC_BCRx_WAITCFG              |
 256           FMC_BCRx_WREN                 |
 257           FMC_BCRx_WAITEN               |
 258           FMC_BCRx_EXTMOD               |
 259           FMC_BCRx_ASYNCWAIT            |
 260           FMC_BCRx_CBURSTRW);
 261
 262   mask |= FMC_BCR1_CCLKEN;
 263   mask |= FMC_BCR1_WFDIS;
 264   mask |= FMC_BCRx_CPSIZE;
 265
 266   MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
 267
 268   /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
 269   if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
 270   {
 271     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
 272   }
 273
 274   if (Init->NSBank != FMC_NORSRAM_BANK1)
 275   {
 276     /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
 277     SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
 278   }
 279
 280   return HAL_OK;
 281 }
 282
 283 /**
 284   * @brief  DeInitialize the FMC_NORSRAM peripheral
 285   * @param  Device Pointer to NORSRAM device instance
 286   * @param  ExDevice Pointer to NORSRAM extended mode device instance
 287   * @param  Bank NORSRAM bank number
 288   * @retval HAL status
 289   */
 290 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
 291 {
 292   /* Check the parameters */
 293   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 294   assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
 295   assert_param(IS_FMC_NORSRAM_BANK(Bank));
 296
 297   /* Disable the FMC_NORSRAM device */
 298   __FMC_NORSRAM_DISABLE(Device, Bank);
 299
 300   /* De-initialize the FMC_NORSRAM device */
 301   /* FMC_NORSRAM_BANK1 */
 302   if (Bank == FMC_NORSRAM_BANK1)
 303   {
 304     Device->BTCR[Bank] = 0x000030DBU;
 305   }
 306   /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
 307   else
 308   {
 309     Device->BTCR[Bank] = 0x000030D2U;
 310   }
 311
 312   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
 313   ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;
 314
 315   return HAL_OK;
 316 }
 317
 318 /**
 319   * @brief  Initialize the FMC_NORSRAM Timing according to the specified
 320   *         parameters in the FMC_NORSRAM_TimingTypeDef
 321   * @param  Device Pointer to NORSRAM device instance
 322   * @param  Timing Pointer to NORSRAM Timing structure
 323   * @param  Bank NORSRAM bank number
 324   * @retval HAL status
 325   */
 326 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
 327 {
 328   uint32_t tmpr;
 329
 330   /* Check the parameters */
 331   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 332   assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
 333   assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
 334   assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
 335   assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
 336   assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
 337   assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
 338   assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
 339   assert_param(IS_FMC_NORSRAM_BANK(Bank));
 340
 341   /* Set FMC_NORSRAM device timing parameters */
 342   MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime                                  |
 343                                                       ((Timing->AddressHoldTime)        << FMC_BTRx_ADDHLD_Pos)  |
 344                                                       ((Timing->DataSetupTime)          << FMC_BTRx_DATAST_Pos)  |
 345                                                       ((Timing->BusTurnAroundDuration)  << FMC_BTRx_BUSTURN_Pos) |
 346                                                       (((Timing->CLKDivision) - 1U)     << FMC_BTRx_CLKDIV_Pos)  |
 347                                                       (((Timing->DataLatency) - 2U)     << FMC_BTRx_DATLAT_Pos)  |
 348                                                       (Timing->AccessMode)));
 349
 350   /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
 351   if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
 352   {
 353     tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0F) << FMC_BTRx_CLKDIV_Pos));
 354     tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos);
 355     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);
 356   }
 357
 358   return HAL_OK;
 359 }
 360
 361 /**
 362   * @brief  Initialize the FMC_NORSRAM Extended mode Timing according to the specified
 363   *         parameters in the FMC_NORSRAM_TimingTypeDef
 364   * @param  Device Pointer to NORSRAM device instance
 365   * @param  Timing Pointer to NORSRAM Timing structure
 366   * @param  Bank NORSRAM bank number
 367   * @param  ExtendedMode FMC Extended Mode
 368   *          This parameter can be one of the following values:
 369   *            @arg FMC_EXTENDED_MODE_DISABLE
 370   *            @arg FMC_EXTENDED_MODE_ENABLE
 371   * @retval HAL status
 372   */
 373 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
 374 {
 375   /* Check the parameters */
 376   assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
 377
 378   /* Set NORSRAM device timing register for write configuration, if extended mode is used */
 379   if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
 380   {
 381     /* Check the parameters */
 382     assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
 383     assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
 384     assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
 385     assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
 386 #if defined(FMC_BWTRx_BUSTURN)
 387     assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
 388 #endif /* FMC_BWTRx_BUSTURN */
 389     assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
 390     assert_param(IS_FMC_NORSRAM_BANK(Bank));
 391
 392     /* Set NORSRAM device timing register for write configuration, if extended mode is used */
 393     MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
 394                                                      ((Timing->AddressHoldTime)        << FMC_BWTRx_ADDHLD_Pos)  |
 395                                                      ((Timing->DataSetupTime)          << FMC_BWTRx_DATAST_Pos)  |
 396 #if defined(FMC_BWTRx_BUSTURN)
 397                                                      Timing->AccessMode                                          |
 398                                                      ((Timing->BusTurnAroundDuration)  << FMC_BWTRx_BUSTURN_Pos)));
 399 #else
 400                                                      Timing->AccessMode));
 401 #endif /* FMC_BWTRx_BUSTURN */
 402   }
 403   else
 404   {
 405     Device->BWTR[Bank] = 0x0FFFFFFFU;
 406   }
 407
 408   return HAL_OK;
 409 }
 410 /**
 411   * @}
 412   */
 413
 414 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
 415  *  @brief   management functions
 416  *
 417 @verbatim
 418   ==============================================================================
 419                       ##### FMC_NORSRAM Control functions #####
 420   ==============================================================================
 421   [..]
 422     This subsection provides a set of functions allowing to control dynamically
 423     the FMC NORSRAM interface.
 424
 425 @endverbatim
 426   * @{
 427   */
 428
 429 /**
 430   * @brief  Enables dynamically FMC_NORSRAM write operation.
 431   * @param  Device Pointer to NORSRAM device instance
 432   * @param  Bank NORSRAM bank number
 433   * @retval HAL status
 434   */
 435 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
 436 {
 437   /* Check the parameters */
 438   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 439   assert_param(IS_FMC_NORSRAM_BANK(Bank));
 440
 441   /* Enable write operation */
 442   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
 443
 444   return HAL_OK;
 445 }
 446
 447 /**
 448   * @brief  Disables dynamically FMC_NORSRAM write operation.
 449   * @param  Device Pointer to NORSRAM device instance
 450   * @param  Bank NORSRAM bank number
 451   * @retval HAL status
 452   */
 453 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
 454 {
 455   /* Check the parameters */
 456   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 457   assert_param(IS_FMC_NORSRAM_BANK(Bank));
 458
 459   /* Disable write operation */
 460   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
 461
 462   return HAL_OK;
 463 }
 464
 465 /**
 466   * @}
 467   */
 468
 469 /**
 470   * @}
 471   */
 472
 473
 474 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
 475   * @brief    NAND Controller functions
 476   *
 477   @verbatim
 478   ==============================================================================
 479                     ##### How to use NAND device driver #####
 480   ==============================================================================
 481   [..]
 482     This driver contains a set of APIs to interface with the FMC NAND banks in order
 483     to run the NAND external devices.
 484
 485     (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
 486     (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
 487     (+) FMC NAND bank common space timing configuration using the function
 488         FMC_NAND_CommonSpace_Timing_Init()
 489     (+) FMC NAND bank attribute space timing configuration using the function
 490         FMC_NAND_AttributeSpace_Timing_Init()
 491     (+) FMC NAND bank enable/disable ECC correction feature using the functions
 492         FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
 493     (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
 494
 495 @endverbatim
 496   * @{
 497   */
 498
 499 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
 500  *  @brief    Initialization and Configuration functions
 501  *
 502 @verbatim
 503   ==============================================================================
 504               ##### Initialization and de_initialization functions #####
 505   ==============================================================================
 506   [..]
 507     This section provides functions allowing to:
 508     (+) Initialize and configure the FMC NAND interface
 509     (+) De-initialize the FMC NAND interface
 510     (+) Configure the FMC clock and associated GPIOs
 511
 512 @endverbatim
 513   * @{
 514   */
 515
 516 /**
 517   * @brief  Initializes the FMC_NAND device according to the specified
 518   *         control parameters in the FMC_NAND_HandleTypeDef
 519   * @param  Device Pointer to NAND device instance
 520   * @param  Init Pointer to NAND Initialization structure
 521   * @retval HAL status
 522   */
 523 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
 524 {
 525   /* Check the parameters */
 526   assert_param(IS_FMC_NAND_DEVICE(Device));
 527   assert_param(IS_FMC_NAND_BANK(Init->NandBank));
 528   assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
 529   assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
 530   assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
 531   assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
 532   assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
 533   assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
 534
 535   /* NAND bank 3 registers configuration */
 536   MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature                            |
 537                                            FMC_PCR_MEMORY_TYPE_NAND                     |
 538                                            Init->MemoryDataWidth                        |
 539                                            Init->EccComputation                         |
 540                                            Init->ECCPageSize                            |
 541                                            ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos)  |
 542                                            ((Init->TARSetupTime)  << FMC_PCR_TAR_Pos)));
 543
 544   return HAL_OK;
 545 }
 546
 547 /**
 548   * @brief  Initializes the FMC_NAND Common space Timing according to the specified
 549   *         parameters in the FMC_NAND_PCC_TimingTypeDef
 550   * @param  Device Pointer to NAND device instance
 551   * @param  Timing Pointer to NAND timing structure
 552   * @param  Bank NAND bank number
 553   * @retval HAL status
 554   */
 555 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
 556 {
 557   /* Check the parameters */
 558   assert_param(IS_FMC_NAND_DEVICE(Device));
 559   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
 560   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
 561   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
 562   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
 563   assert_param(IS_FMC_NAND_BANK(Bank));
 564
 565   /* Prevent unused argument(s) compilation warning if no assert_param check */
 566   UNUSED(Bank);
 567
 568   /* NAND bank 3 registers configuration */
 569   MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime                                 |
 570                                              ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
 571                                              ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) |
 572                                              ((Timing->HiZSetupTime)  << FMC_PMEM_MEMHIZ_Pos)));
 573
 574   return HAL_OK;
 575 }
 576
 577 /**
 578   * @brief  Initializes the FMC_NAND Attribute space Timing according to the specified
 579   *         parameters in the FMC_NAND_PCC_TimingTypeDef
 580   * @param  Device Pointer to NAND device instance
 581   * @param  Timing Pointer to NAND timing structure
 582   * @param  Bank NAND bank number
 583   * @retval HAL status
 584   */
 585 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
 586 {
 587   /* Check the parameters */
 588   assert_param(IS_FMC_NAND_DEVICE(Device));
 589   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
 590   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
 591   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
 592   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
 593   assert_param(IS_FMC_NAND_BANK(Bank));
 594
 595   /* Prevent unused argument(s) compilation warning if no assert_param check */
 596   UNUSED(Bank);
 597
 598   /* NAND bank 3 registers configuration */
 599   MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime                                 |
 600                                              ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
 601                                              ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) |
 602                                              ((Timing->HiZSetupTime)  << FMC_PATT_ATTHIZ_Pos)));
 603
 604   return HAL_OK;
 605 }
 606
 607 /**
 608   * @brief  DeInitializes the FMC_NAND device
 609   * @param  Device Pointer to NAND device instance
 610   * @param  Bank NAND bank number
 611   * @retval HAL status
 612   */
 613 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
 614 {
 615   /* Check the parameters */
 616   assert_param(IS_FMC_NAND_DEVICE(Device));
 617   assert_param(IS_FMC_NAND_BANK(Bank));
 618
 619   /* Disable the NAND Bank */
 620   __FMC_NAND_DISABLE(Device, Bank);
 621
 622   /* De-initialize the NAND Bank */
 623   /* Prevent unused argument(s) compilation warning if no assert_param check */
 624   UNUSED(Bank);
 625
 626   /* Set the FMC_NAND_BANK3 registers to their reset values */
 627   WRITE_REG(Device->PCR,  0x00000018U);
 628   WRITE_REG(Device->SR,   0x00000040U);
 629   WRITE_REG(Device->PMEM, 0xFCFCFCFCU);
 630   WRITE_REG(Device->PATT, 0xFCFCFCFCU);
 631
 632   return HAL_OK;
 633 }
 634
 635 /**
 636   * @}
 637   */
 638
 639 /** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions
 640   *  @brief   management functions
 641   *
 642 @verbatim
 643   ==============================================================================
 644                        ##### FMC_NAND Control functions #####
 645   ==============================================================================
 646   [..]
 647     This subsection provides a set of functions allowing to control dynamically
 648     the FMC NAND interface.
 649
 650 @endverbatim
 651   * @{
 652   */
 653
 654
 655 /**
 656   * @brief  Enables dynamically FMC_NAND ECC feature.
 657   * @param  Device Pointer to NAND device instance
 658   * @param  Bank NAND bank number
 659   * @retval HAL status
 660   */
 661 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
 662 {
 663   /* Check the parameters */
 664   assert_param(IS_FMC_NAND_DEVICE(Device));
 665   assert_param(IS_FMC_NAND_BANK(Bank));
 666
 667   /* Enable ECC feature */
 668   /* Prevent unused argument(s) compilation warning if no assert_param check */
 669   UNUSED(Bank);
 670
 671   SET_BIT(Device->PCR, FMC_PCR_ECCEN);
 672
 673   return HAL_OK;
 674 }
 675
 676
 677 /**
 678   * @brief  Disables dynamically FMC_NAND ECC feature.
 679   * @param  Device Pointer to NAND device instance
 680   * @param  Bank NAND bank number
 681   * @retval HAL status
 682   */
 683 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
 684 {
 685   /* Check the parameters */
 686   assert_param(IS_FMC_NAND_DEVICE(Device));
 687   assert_param(IS_FMC_NAND_BANK(Bank));
 688
 689   /* Disable ECC feature */
 690   /* Prevent unused argument(s) compilation warning if no assert_param check */
 691   UNUSED(Bank);
 692
 693   CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
 694
 695   return HAL_OK;
 696 }
 697
 698 /**
 699   * @brief  Disables dynamically FMC_NAND ECC feature.
 700   * @param  Device Pointer to NAND device instance
 701   * @param  ECCval Pointer to ECC value
 702   * @param  Bank NAND bank number
 703   * @param  Timeout Timeout wait value
 704   * @retval HAL status
 705   */
 706 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
 707 {
 708   uint32_t tickstart;
 709
 710   /* Check the parameters */
 711   assert_param(IS_FMC_NAND_DEVICE(Device));
 712   assert_param(IS_FMC_NAND_BANK(Bank));
 713
 714   /* Get tick */
 715   tickstart = HAL_GetTick();
 716
 717   /* Wait until FIFO is empty */
 718   while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
 719   {
 720     /* Check for the Timeout */
 721     if (Timeout != HAL_MAX_DELAY)
 722     {
 723       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
 724       {
 725         return HAL_TIMEOUT;
 726       }
 727     }
 728   }
 729
 730   /* Prevent unused argument(s) compilation warning if no assert_param check */
 731   UNUSED(Bank);
 732
 733   /* Get the ECCR register value */
 734   *ECCval = (uint32_t)Device->ECCR;
 735
 736   return HAL_OK;
 737 }
 738
 739 /**
 740   * @}
 741   */
 742
 743
 744
 745 /** @defgroup FMC_LL_SDRAM
 746   * @brief    SDRAM Controller functions
 747   *
 748   @verbatim
 749   ==============================================================================
 750                      ##### How to use SDRAM device driver #####
 751   ==============================================================================
 752   [..]
 753     This driver contains a set of APIs to interface with the FMC SDRAM banks in order
 754     to run the SDRAM external devices.
 755
 756     (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
 757     (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
 758     (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
 759     (+) FMC SDRAM bank enable/disable write operation using the functions
 760         FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
 761     (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
 762
 763 @endverbatim
 764   * @{
 765   */
 766
 767 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
 768   *  @brief    Initialization and Configuration functions
 769   *
 770 @verbatim
 771   ==============================================================================
 772               ##### Initialization and de_initialization functions #####
 773   ==============================================================================
 774   [..]
 775     This section provides functions allowing to:
 776     (+) Initialize and configure the FMC SDRAM interface
 777     (+) De-initialize the FMC SDRAM interface
 778     (+) Configure the FMC clock and associated GPIOs
 779
 780 @endverbatim
 781   * @{
 782   */
 783
 784 /**
 785   * @brief  Initializes the FMC_SDRAM device according to the specified
 786   *         control parameters in the FMC_SDRAM_InitTypeDef
 787   * @param  Device Pointer to SDRAM device instance
 788   * @param  Init Pointer to SDRAM Initialization structure
 789   * @retval HAL status
 790   */
 791 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
 792 {
 793   /* Check the parameters */
 794   assert_param(IS_FMC_SDRAM_DEVICE(Device));
 795   assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
 796   assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
 797   assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
 798   assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
 799   assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
 800   assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
 801   assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
 802   assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
 803   assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
 804   assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
 805
 806   /* Set SDRAM bank configuration parameters */
 807   if (Init->SDBank == FMC_SDRAM_BANK1)
 808   {
 809     MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
 810                SDCR_CLEAR_MASK,
 811                (Init->ColumnBitsNumber   |
 812                 Init->RowBitsNumber      |
 813                 Init->MemoryDataWidth    |
 814                 Init->InternalBankNumber |
 815                 Init->CASLatency         |
 816                 Init->WriteProtection    |
 817                 Init->SDClockPeriod      |
 818                 Init->ReadBurst          |
 819                 Init->ReadPipeDelay));
 820   }
 821   else /* FMC_Bank2_SDRAM */
 822   {
 823     MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
 824                FMC_SDCRx_SDCLK           |
 825                FMC_SDCRx_RBURST          |
 826                FMC_SDCRx_RPIPE,
 827                (Init->SDClockPeriod      |
 828                 Init->ReadBurst          |
 829                 Init->ReadPipeDelay));
 830
 831     MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],
 832                SDCR_CLEAR_MASK,
 833                (Init->ColumnBitsNumber   |
 834                 Init->RowBitsNumber      |
 835                 Init->MemoryDataWidth    |
 836                 Init->InternalBankNumber |
 837                 Init->CASLatency         |
 838                 Init->WriteProtection));
 839   }
 840
 841   return HAL_OK;
 842 }
 843
 844
 845 /**
 846   * @brief  Initializes the FMC_SDRAM device timing according to the specified
 847   *         parameters in the FMC_SDRAM_TimingTypeDef
 848   * @param  Device Pointer to SDRAM device instance
 849   * @param  Timing Pointer to SDRAM Timing structure
 850   * @param  Bank SDRAM bank number
 851   * @retval HAL status
 852   */
 853 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
 854 {
 855   /* Check the parameters */
 856   assert_param(IS_FMC_SDRAM_DEVICE(Device));
 857   assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
 858   assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
 859   assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
 860   assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
 861   assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
 862   assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
 863   assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
 864   assert_param(IS_FMC_SDRAM_BANK(Bank));
 865
 866   /* Set SDRAM device timing parameters */
 867   if (Bank == FMC_SDRAM_BANK1)
 868   {
 869     MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
 870                SDTR_CLEAR_MASK,
 871                (((Timing->LoadToActiveDelay) - 1U)                                      |
 872                 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) |
 873                 (((Timing->SelfRefreshTime) - 1U)      << FMC_SDTRx_TRAS_Pos) |
 874                 (((Timing->RowCycleDelay) - 1U)        << FMC_SDTRx_TRC_Pos)  |
 875                 (((Timing->WriteRecoveryTime) - 1U)    << FMC_SDTRx_TWR_Pos)  |
 876                 (((Timing->RPDelay) - 1U)              << FMC_SDTRx_TRP_Pos)  |
 877                 (((Timing->RCDDelay) - 1U)             << FMC_SDTRx_TRCD_Pos)));
 878   }
 879   else /* FMC_Bank2_SDRAM */
 880   {
 881     MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
 882                FMC_SDTRx_TRC |
 883                FMC_SDTRx_TRP,
 884                (((Timing->RowCycleDelay) - 1U)         << FMC_SDTRx_TRC_Pos)  |
 885                (((Timing->RPDelay) - 1U)               << FMC_SDTRx_TRP_Pos));
 886
 887     MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2],
 888                SDTR_CLEAR_MASK,
 889                (((Timing->LoadToActiveDelay) - 1U)                                      |
 890                 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) |
 891                 (((Timing->SelfRefreshTime) - 1U)      << FMC_SDTRx_TRAS_Pos) |
 892                 (((Timing->WriteRecoveryTime) - 1U)    << FMC_SDTRx_TWR_Pos)  |
 893                 (((Timing->RCDDelay) - 1U)             << FMC_SDTRx_TRCD_Pos)));
 894   }
 895
 896   return HAL_OK;
 897 }
 898
 899 /**
 900   * @brief  DeInitializes the FMC_SDRAM peripheral
 901   * @param  Device Pointer to SDRAM device instance
 902   * @retval HAL status
 903   */
 904 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
 905 {
 906   /* Check the parameters */
 907   assert_param(IS_FMC_SDRAM_DEVICE(Device));
 908   assert_param(IS_FMC_SDRAM_BANK(Bank));
 909
 910   /* De-initialize the SDRAM device */
 911   Device->SDCR[Bank] = 0x000002D0U;
 912   Device->SDTR[Bank] = 0x0FFFFFFFU;
 913   Device->SDCMR      = 0x00000000U;
 914   Device->SDRTR      = 0x00000000U;
 915   Device->SDSR       = 0x00000000U;
 916
 917   return HAL_OK;
 918 }
 919
 920 /**
 921   * @}
 922   */
 923
 924 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
 925   *  @brief   management functions
 926   *
 927 @verbatim
 928   ==============================================================================
 929                       ##### FMC_SDRAM Control functions #####
 930   ==============================================================================
 931   [..]
 932     This subsection provides a set of functions allowing to control dynamically
 933     the FMC SDRAM interface.
 934
 935 @endverbatim
 936   * @{
 937   */
 938
 939 /**
 940   * @brief  Enables dynamically FMC_SDRAM write protection.
 941   * @param  Device Pointer to SDRAM device instance
 942   * @param  Bank SDRAM bank number
 943   * @retval HAL status
 944   */
 945 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
 946 {
 947   /* Check the parameters */
 948   assert_param(IS_FMC_SDRAM_DEVICE(Device));
 949   assert_param(IS_FMC_SDRAM_BANK(Bank));
 950
 951   /* Enable write protection */
 952   SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
 953
 954   return HAL_OK;
 955 }
 956
 957 /**
 958   * @brief  Disables dynamically FMC_SDRAM write protection.
 959   * @param  hsdram FMC_SDRAM handle
 960   * @retval HAL status
 961   */
 962 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
 963 {
 964   /* Check the parameters */
 965   assert_param(IS_FMC_SDRAM_DEVICE(Device));
 966   assert_param(IS_FMC_SDRAM_BANK(Bank));
 967
 968   /* Disable write protection */
 969   CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
 970
 971   return HAL_OK;
 972 }
 973
 974 /**
 975   * @brief  Send Command to the FMC SDRAM bank
 976   * @param  Device Pointer to SDRAM device instance
 977   * @param  Command Pointer to SDRAM command structure
 978   * @param  Timing Pointer to SDRAM Timing structure
 979   * @param  Timeout Timeout wait value
 980   * @retval HAL state
 981   */
 982 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
 983 {
 984   /* Check the parameters */
 985   assert_param(IS_FMC_SDRAM_DEVICE(Device));
 986   assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
 987   assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
 988   assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
 989   assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
 990
 991   /* Set command register */
 992   SET_BIT(Device->SDCMR, ((Command->CommandMode)                                                 |
 993                           (Command->CommandTarget)                                               |
 994                           (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos)   |
 995                           ((Command->ModeRegisterDefinition)   << FMC_SDCMR_MRD_Pos)));
 996   /* Prevent unused argument(s) compilation warning */
 997   UNUSED(Timeout);
 998   return HAL_OK;
 999 }
1000
1001 /**
1002   * @brief  Program the SDRAM Memory Refresh rate.
1003   * @param  Device Pointer to SDRAM device instance
1004   * @param  RefreshRate The SDRAM refresh rate value.
1005   * @retval HAL state
1006   */
1007 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
1008 {
1009   /* Check the parameters */
1010   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1011   assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
1012
1013   /* Set the refresh rate in command register */
1014   MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos));
1015
1016   return HAL_OK;
1017 }
1018
1019 /**
1020   * @brief  Set the Number of consecutive SDRAM Memory auto Refresh commands.
1021   * @param  Device Pointer to SDRAM device instance
1022   * @param  AutoRefreshNumber Specifies the auto Refresh number.
1023   * @retval None
1024   */
1025 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
1026 {
1027   /* Check the parameters */
1028   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1029   assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
1030
1031   /* Set the Auto-refresh number in command register */
1032   MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos));
1033
1034   return HAL_OK;
1035 }
1036
1037 /**
1038   * @brief  Returns the indicated FMC SDRAM bank mode status.
1039   * @param  Device Pointer to SDRAM device instance
1040   * @param  Bank Defines the FMC SDRAM bank. This parameter can be
1041   *                     FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
1042   * @retval The FMC SDRAM bank mode status, could be on of the following values:
1043   *         FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
1044   *         FMC_SDRAM_POWER_DOWN_MODE.
1045   */
1046 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1047 {
1048   uint32_t tmpreg;
1049
1050   /* Check the parameters */
1051   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1052   assert_param(IS_FMC_SDRAM_BANK(Bank));
1053
1054   /* Get the corresponding bank mode */
1055   if (Bank == FMC_SDRAM_BANK1)
1056   {
1057     tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
1058   }
1059   else
1060   {
1061     tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
1062   }
1063
1064   /* Return the mode status */
1065   return tmpreg;
1066 }
1067
1068 /**
1069   * @}
1070   */
1071
1072 /**
1073   * @}
1074   */
1075
1076
1077 /**
1078   * @}
1079   */
1080
1081 /**
1082   * @}
1083   */
1084
1085 #endif /* HAL_NOR_MODULE_ENABLED */
1086 /**
1087   * @}
1088   */
1089
1090 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/