lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lptim.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32h7xx_ll_lptim.c
   4   * @author  MCD Application Team
   5   * @brief   LPTIM LL module driver.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19 #if defined(USE_FULL_LL_DRIVER)
  20
  21 /* Includes ------------------------------------------------------------------*/
  22 #include "stm32h7xx_ll_lptim.h"
  23 #include "stm32h7xx_ll_bus.h"
  24 #include "stm32h7xx_ll_rcc.h"
  25
  26
  27 #ifdef  USE_FULL_ASSERT
  28 #include "stm32_assert.h"
  29 #else
  30 #define assert_param(expr) ((void)0U)
  31 #endif
  32
  33 /** @addtogroup STM32H7xx_LL_Driver
  34   * @{
  35   */
  36
  37 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)
  38
  39 /** @addtogroup LPTIM_LL
  40   * @{
  41   */
  42
  43 /* Private types -------------------------------------------------------------*/
  44 /* Private variables ---------------------------------------------------------*/
  45 /* Private constants ---------------------------------------------------------*/
  46 /* Private macros ------------------------------------------------------------*/
  47 /** @addtogroup LPTIM_LL_Private_Macros
  48   * @{
  49   */
  50 #define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
  51                                           || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
  52
  53 #define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1)   \
  54                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2)   \
  55                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4)   \
  56                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8)   \
  57                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16)  \
  58                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32)  \
  59                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64)  \
  60                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
  61
  62 #define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
  63                                       || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
  64
  65 #define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
  66                                              || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
  67 /**
  68   * @}
  69   */
  70
  71
  72 /* Private function prototypes -----------------------------------------------*/
  73 /* Private functions ---------------------------------------------------------*/
  74 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
  75   * @{
  76   */
  77 /**
  78   * @}
  79   */
  80 /* Exported functions --------------------------------------------------------*/
  81 /** @addtogroup LPTIM_LL_Exported_Functions
  82   * @{
  83   */
  84
  85 /** @addtogroup LPTIM_LL_EF_Init
  86   * @{
  87   */
  88
  89 /**
  90   * @brief  Set LPTIMx registers to their reset values.
  91   * @param  LPTIMx LP Timer instance
  92   * @retval An ErrorStatus enumeration value:
  93   *          - SUCCESS: LPTIMx registers are de-initialized
  94   *          - ERROR: invalid LPTIMx instance
  95   */
  96 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx)
  97 {
  98   ErrorStatus result = SUCCESS;
  99
 100   /* Check the parameters */
 101   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
 102
 103   if (LPTIMx == LPTIM1)
 104   {
 105     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1);
 106     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
 107   }
 108   else if (LPTIMx == LPTIM2)
 109   {
 110     LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM2);
 111     LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM2);
 112   }
 113 #if defined(LPTIM3)
 114   else if (LPTIMx == LPTIM3)
 115   {
 116     LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM3);
 117     LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM3);
 118   }
 119 #endif /* LPTIM3 */
 120 #if defined(LPTIM4)
 121   else if (LPTIMx == LPTIM4)
 122   {
 123     LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM4);
 124     LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM4);
 125   }
 126 #endif /* LPTIM4 */
 127 #if defined(LPTIM5)
 128   else if (LPTIMx == LPTIM5)
 129   {
 130     LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM5);
 131     LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM5);
 132   }
 133 #endif /* LPTIM5 */
 134   else
 135   {
 136     result = ERROR;
 137   }
 138
 139   return result;
 140 }
 141
 142 /**
 143   * @brief  Set each fields of the LPTIM_InitStruct structure to its default
 144   *         value.
 145   * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
 146   * @retval None
 147   */
 148 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
 149 {
 150   /* Set the default configuration */
 151   LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL;
 152   LPTIM_InitStruct->Prescaler   = LL_LPTIM_PRESCALER_DIV1;
 153   LPTIM_InitStruct->Waveform    = LL_LPTIM_OUTPUT_WAVEFORM_PWM;
 154   LPTIM_InitStruct->Polarity    = LL_LPTIM_OUTPUT_POLARITY_REGULAR;
 155 }
 156
 157 /**
 158   * @brief  Configure the LPTIMx peripheral according to the specified parameters.
 159   * @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
 160   * @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable().
 161   * @param  LPTIMx LP Timer Instance
 162   * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
 163   * @retval An ErrorStatus enumeration value:
 164   *          - SUCCESS: LPTIMx instance has been initialized
 165   *          - ERROR: LPTIMx instance hasn't been initialized
 166   */
 167 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
 168 {
 169   ErrorStatus result = SUCCESS;
 170   /* Check the parameters */
 171   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
 172   assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
 173   assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
 174   assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
 175   assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
 176
 177   /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled
 178      (ENABLE bit is reset to 0).
 179   */
 180   if (LL_LPTIM_IsEnabled(LPTIMx) == 1UL)
 181   {
 182     result = ERROR;
 183   }
 184   else
 185   {
 186     /* Set CKSEL bitfield according to ClockSource value */
 187     /* Set PRESC bitfield according to Prescaler value */
 188     /* Set WAVE bitfield according to Waveform value */
 189     /* Set WAVEPOL bitfield according to Polarity value */
 190     MODIFY_REG(LPTIMx->CFGR,
 191                (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL),
 192                LPTIM_InitStruct->ClockSource | \
 193                LPTIM_InitStruct->Prescaler | \
 194                LPTIM_InitStruct->Waveform | \
 195                LPTIM_InitStruct->Polarity);
 196   }
 197
 198   return result;
 199 }
 200
 201 /**
 202   * @brief  Disable the LPTIM instance
 203   * @rmtoll CR           ENABLE        LL_LPTIM_Disable
 204   * @param  LPTIMx Low-Power Timer instance
 205   * @note   The following sequence is required to solve LPTIM disable HW limitation.
 206   *         Please check Errata Sheet ES0335 for more details under "MCU may remain
 207   *         stuck in LPTIM interrupt when entering Stop mode" section.
 208   * @retval None
 209   */
 210 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
 211 {
 212   LL_RCC_ClocksTypeDef rcc_clock;
 213   uint32_t tmpclksource = 0;
 214   uint32_t tmpIER;
 215   uint32_t tmpCFGR;
 216   uint32_t tmpCMP;
 217   uint32_t tmpARR;
 218   uint32_t tmpCFGR2;
 219
 220   /* Check the parameters */
 221   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
 222
 223   __disable_irq();
 224
 225   /********** Save LPTIM Config *********/
 226   /* Save LPTIM source clock */
 227   switch ((uint32_t)LPTIMx)
 228   {
 229     case LPTIM1_BASE:
 230       tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
 231       break;
 232     case LPTIM2_BASE:
 233       tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
 234       break;
 235 #if defined(LPTIM3)&&defined(LPTIM4)&&defined(LPTIM5)
 236     case LPTIM3_BASE:
 237     case LPTIM4_BASE:
 238     case LPTIM5_BASE:
 239       tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE);
 240       break;
 241 #elif defined(LPTIM3)
 242     case LPTIM3_BASE:
 243       tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE);
 244       break;
 245 #endif /* LPTIM3 && LPTIM4 && LPTIM5 */
 246     default:
 247       break;
 248   }
 249
 250   /* Save LPTIM configuration registers */
 251   tmpIER = LPTIMx->IER;
 252   tmpCFGR = LPTIMx->CFGR;
 253   tmpCMP = LPTIMx->CMP;
 254   tmpARR = LPTIMx->ARR;
 255   tmpCFGR2 = LPTIMx->CFGR2;
 256
 257   /************* Reset LPTIM ************/
 258   (void)LL_LPTIM_DeInit(LPTIMx);
 259
 260   /********* Restore LPTIM Config *******/
 261   LL_RCC_GetSystemClocksFreq(&rcc_clock);
 262
 263   if ((tmpCMP != 0UL) || (tmpARR != 0UL))
 264   {
 265     /* Force LPTIM source kernel clock from APB */
 266     switch ((uint32_t)LPTIMx)
 267     {
 268       case LPTIM1_BASE:
 269         LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
 270         break;
 271       case LPTIM2_BASE:
 272         LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK4);
 273         break;
 274 #if defined(LPTIM3)&&defined(LPTIM4)&&defined(LPTIM5)
 275       case LPTIM3_BASE:
 276       case LPTIM4_BASE:
 277       case LPTIM5_BASE:
 278         LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE_PCLK4);
 279         break;
 280 #elif defined(LPTIM3)
 281       case LPTIM3_BASE:
 282         LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE_PCLK4);
 283         break;
 284 #endif /* LPTIM3 && LPTIM4 && LPTIM5*/
 285       default:
 286         break;
 287     }
 288
 289     if (tmpCMP != 0UL)
 290     {
 291       /* Restore CMP and ARR registers (LPTIM should be enabled first) */
 292       LPTIMx->CR |= LPTIM_CR_ENABLE;
 293       LPTIMx->CMP = tmpCMP;
 294
 295       /* Polling on CMP write ok status after above restore operation */
 296       do
 297       {
 298         rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
 299       }
 300       while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
 301
 302       LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
 303     }
 304
 305     if (tmpARR != 0UL)
 306     {
 307       LPTIMx->CR |= LPTIM_CR_ENABLE;
 308       LPTIMx->ARR = tmpARR;
 309
 310       LL_RCC_GetSystemClocksFreq(&rcc_clock);
 311       /* Polling on ARR write ok status after above restore operation */
 312       do
 313       {
 314         rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
 315       }
 316       while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
 317
 318       LL_LPTIM_ClearFlag_ARROK(LPTIMx);
 319     }
 320
 321
 322     /* Restore LPTIM source kernel clock */
 323     LL_RCC_SetLPTIMClockSource(tmpclksource);
 324   }
 325
 326   /* Restore configuration registers (LPTIM should be disabled first) */
 327   LPTIMx->CR &= ~(LPTIM_CR_ENABLE);
 328   LPTIMx->IER = tmpIER;
 329   LPTIMx->CFGR = tmpCFGR;
 330   LPTIMx->CFGR2 = tmpCFGR2;
 331
 332   __enable_irq();
 333 }
 334
 335 /**
 336   * @}
 337   */
 338
 339 /**
 340   * @}
 341   */
 342
 343 /**
 344   * @}
 345   */
 346
 347 #endif /* LPTIM1 || LPTIM2 ||  LPTIM3 || LPTIM4 || LPTIM5 */
 348
 349 /**
 350   * @}
 351   */
 352
 353 #endif /* USE_FULL_LL_DRIVER */
 354
 355 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/