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[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_ll_mdma.c
blob1c33f828a792052edc52d64e23866e5aa5b35356
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_mdma.c
4 * @author MCD Application Team
5 * @brief MDMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32h7xx_ll_mdma.h"
23 #include "stm32h7xx_ll_bus.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (MDMA)
35
36 /** @defgroup MDMA_LL MDMA
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup MDMA_LL_Private_Macros
45 * @{
46 */
47
48 #define IS_LL_MDMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) (((INSTANCE) == MDMA) && \
49 (((CHANNEL) == LL_MDMA_CHANNEL_0) || \
50 ((CHANNEL) == LL_MDMA_CHANNEL_1) || \
51 ((CHANNEL) == LL_MDMA_CHANNEL_2) || \
52 ((CHANNEL) == LL_MDMA_CHANNEL_3) || \
53 ((CHANNEL) == LL_MDMA_CHANNEL_4) || \
54 ((CHANNEL) == LL_MDMA_CHANNEL_5) || \
55 ((CHANNEL) == LL_MDMA_CHANNEL_6) || \
56 ((CHANNEL) == LL_MDMA_CHANNEL_7) || \
57 ((CHANNEL) == LL_MDMA_CHANNEL_8) || \
58 ((CHANNEL) == LL_MDMA_CHANNEL_9) || \
59 ((CHANNEL) == LL_MDMA_CHANNEL_10)|| \
60 ((CHANNEL) == LL_MDMA_CHANNEL_11)|| \
61 ((CHANNEL) == LL_MDMA_CHANNEL_12)|| \
62 ((CHANNEL) == LL_MDMA_CHANNEL_13)|| \
63 ((CHANNEL) == LL_MDMA_CHANNEL_14)|| \
64 ((CHANNEL) == LL_MDMA_CHANNEL_15)|| \
65 ((CHANNEL) == LL_MDMA_CHANNEL_ALL)))
66
67 #define IS_LL_MDMA_BLK_DATALENGTH(__VALUE__) ((__VALUE__) <= 0x00010000U)
68
69 #define IS_LL_MDMA_BLK_REPEATCOUNT(__VALUE__) ((__VALUE__) <= 0x00000FFFU)
70
71 #define IS_LL_MDMA_WORDENDIANESS(__VALUE__) (((__VALUE__) == LL_MDMA_WORD_ENDIANNESS_PRESERVE) || \
72 ((__VALUE__) == LL_MDMA_WORD_ENDIANNESS_EXCHANGE))
73
74 #define IS_LL_MDMA_HALFWORDENDIANESS(__VALUE__) (((__VALUE__) == LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE) || \
75 ((__VALUE__) == LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE))
76
77 #define IS_LL_MDMA_BYTEENDIANESS(__VALUE__) (((__VALUE__) == LL_MDMA_BYTE_ENDIANNESS_PRESERVE) || \
78 ((__VALUE__) == LL_MDMA_BYTE_ENDIANNESS_EXCHANGE))
79
80 #define IS_LL_MDMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_MDMA_PRIORITY_LOW) || \
81 ((__VALUE__) == LL_MDMA_PRIORITY_MEDIUM) || \
82 ((__VALUE__) == LL_MDMA_PRIORITY_HIGH) || \
83 ((__VALUE__) == LL_MDMA_PRIORITY_VERYHIGH))
84
85 #define IS_LL_MDMA_BUFFWRITEMODE(__VALUE__) (((__VALUE__) == LL_MDMA_BUFF_WRITE_DISABLE) || \
86 ((__VALUE__) == LL_MDMA_BUFF_WRITE_ENABLE))
87
88 #define IS_LL_MDMA_REQUESTMODE(__VALUE__) (((__VALUE__) == LL_MDMA_REQUEST_MODE_HW) || \
89 ((__VALUE__) == LL_MDMA_REQUEST_MODE_SW))
90
91 #define IS_LL_MDMA_TRIGGERMODE(__VALUE__) (((__VALUE__) == LL_MDMA_BUFFER_TRANSFER) || \
92 ((__VALUE__) == LL_MDMA_BLOCK_TRANSFER) || \
93 ((__VALUE__) == LL_MDMA_REPEAT_BLOCK_TRANSFER) || \
94 ((__VALUE__) == LL_MDMA_FULL_TRANSFER))
95
96 #define IS_LL_MDMA_PADDINGALIGNEMENT(__VALUE__) (((__VALUE__) == LL_MDMA_DATAALIGN_RIGHT) || \
97 ((__VALUE__) == LL_MDMA_DATAALIGN_RIGHT_SIGNED) || \
98 ((__VALUE__) == LL_MDMA_DATAALIGN_LEFT))
99
100 #define IS_LL_MDMA_PACKMODE(__VALUE__) (((__VALUE__) == LL_MDMA_PACK_DISABLE) || \
101 ((__VALUE__) == LL_MDMA_PACK_ENABLE))
102
103 #define IS_LL_MDMA_BUFFER_XFERLENGTH(__VALUE__) ((__VALUE__) <= 0x0000007FU)
104
105 #define IS_LL_MDMA_DESTBURST(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_BURST_SINGLE) || \
106 ((__VALUE__) == LL_MDMA_DEST_BURST_2BEATS) || \
107 ((__VALUE__) == LL_MDMA_DEST_BURST_4BEATS) || \
108 ((__VALUE__) == LL_MDMA_DEST_BURST_8BEATS) || \
109 ((__VALUE__) == LL_MDMA_DEST_BURST_16BEATS)|| \
110 ((__VALUE__) == LL_MDMA_DEST_BURST_32BEATS)|| \
111 ((__VALUE__) == LL_MDMA_DEST_BURST_64BEATS)|| \
112 ((__VALUE__) == LL_MDMA_DEST_BURST_128BEATS))
113
114 #define IS_LL_MDMA_SRCTBURST(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_BURST_SINGLE) || \
115 ((__VALUE__) == LL_MDMA_SRC_BURST_2BEATS) || \
116 ((__VALUE__) == LL_MDMA_SRC_BURST_4BEATS) || \
117 ((__VALUE__) == LL_MDMA_SRC_BURST_8BEATS) || \
118 ((__VALUE__) == LL_MDMA_SRC_BURST_16BEATS)|| \
119 ((__VALUE__) == LL_MDMA_SRC_BURST_32BEATS)|| \
120 ((__VALUE__) == LL_MDMA_SRC_BURST_64BEATS)|| \
121 ((__VALUE__) == LL_MDMA_SRC_BURST_128BEATS))
122
123 #define IS_LL_MDMA_DESTINCSIZE(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_BYTE) || \
124 ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_HALFWORD) || \
125 ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_WORD) || \
126 ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD))
127
128 #define IS_LL_MDMA_SRCINCSIZE(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_BYTE) || \
129 ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_HALFWORD) || \
130 ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_WORD) || \
131 ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD))
132
133 #define IS_LL_MDMA_DESTDATASIZE(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_BYTE) || \
134 ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_HALFWORD) || \
135 ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_WORD) || \
136 ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD))
137
138 #define IS_LL_MDMA_SRCDATASIZE(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_BYTE) || \
139 ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_HALFWORD) || \
140 ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_WORD) || \
141 ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD))
142
143 #define IS_LL_MDMA_DESTINCMODE(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_FIXED) || \
144 ((__VALUE__) == LL_MDMA_DEST_INCREMENT) || \
145 ((__VALUE__) == LL_MDMA_DEST_DECREMENT))
146
147 #define IS_LL_MDMA_SRCINCMODE(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_FIXED) || \
148 ((__VALUE__) == LL_MDMA_SRC_INCREMENT) || \
149 ((__VALUE__) == LL_MDMA_SRC_DECREMENT))
150
151 #define IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(__VALUE__) (((__VALUE__) == LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT) || \
152 ((__VALUE__) == LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT))
153
154
155 #define IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(__VALUE__) (((__VALUE__) == LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT) || \
156 ((__VALUE__) == LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT))
157
158 #define IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
159
160 #define IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
161
162 #define IS_LL_MDMA_DEST_BUS(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_BUS_SYSTEM_AXI) || \
163 ((__VALUE__) == LL_MDMA_DEST_BUS_AHB_TCM))
164
165 #define IS_LL_MDMA_SRC_BUS(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_BUS_SYSTEM_AXI) || \
166 ((__VALUE__) == LL_MDMA_SRC_BUS_AHB_TCM))
167 #if defined (QUADSPI) && defined (JPEG) && defined (DSI) /* STM32H747/57 devices */
168 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \
169 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \
170 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \
171 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \
172 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \
173 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \
174 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \
175 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \
176 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \
177 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \
178 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \
179 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \
180 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \
181 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \
182 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \
183 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \
184 ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT) || \
185 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_TH) || \
186 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_NF) || \
187 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_TH) || \
188 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_NE) || \
189 ((__VALUE__) == LL_MDMA_REQ_JPEG_END_CONVERSION) || \
190 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_FIFO_TH) || \
191 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_TC) || \
192 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \
193 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \
194 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \
195 ((__VALUE__) == LL_MDMA_REQ_DSI_TEARING_EFFECT) || \
196 ((__VALUE__) == LL_MDMA_REQ_DSI_END_REFRESH) || \
197 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \
198 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
199 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END))
200 #elif defined (QUADSPI) && defined (JPEG) /* STM32H743/53/45/55 devices */
201 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \
202 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \
203 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \
204 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \
205 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \
206 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \
207 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \
208 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \
209 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \
210 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \
211 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \
212 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \
213 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \
214 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \
215 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \
216 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \
217 ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT) || \
218 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_TH) || \
219 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_NF) || \
220 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_TH) || \
221 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_NE) || \
222 ((__VALUE__) == LL_MDMA_REQ_JPEG_END_CONVERSION) || \
223 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_FIFO_TH) || \
224 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_TC) || \
225 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \
226 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \
227 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \
228 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \
229 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
230 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END))
231 #elif defined (QUADSPI) /* STM32H742 devices */
232 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \
233 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \
234 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \
235 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \
236 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \
237 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \
238 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \
239 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \
240 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \
241 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \
242 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \
243 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \
244 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \
245 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \
246 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \
247 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \
248 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_FIFO_TH) || \
249 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_TC) || \
250 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \
251 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \
252 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \
253 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \
254 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
255 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END))
256
257 #elif defined (OCTOSPI1) && defined (JPEG) /* STM32H7A3/B3 devices */
258 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \
259 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \
260 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \
261 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \
262 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \
263 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \
264 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \
265 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \
266 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \
267 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \
268 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \
269 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \
270 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \
271 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \
272 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \
273 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \
274 ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT) || \
275 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_TH) || \
276 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_NF) || \
277 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_TH) || \
278 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_NE) || \
279 ((__VALUE__) == LL_MDMA_REQ_JPEG_END_CONVERSION) || \
280 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_FIFO_TH) || \
281 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_TC) || \
282 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \
283 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \
284 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \
285 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \
286 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
287 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END) || \
288 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_FIFO_TH) || \
289 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_TC))
290 #else /* STM32H723/25/33/35 devices */
291 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \
292 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \
293 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \
294 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \
295 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \
296 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \
297 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \
298 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \
299 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \
300 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \
301 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \
302 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \
303 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \
304 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \
305 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \
306 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \
307 ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT) || \
308 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_FIFO_TH) || \
309 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_TC) || \
310 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \
311 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \
312 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \
313 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \
314 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
315 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END) || \
316 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_FIFO_TH) || \
317 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_TC))
318 #endif /* QUADSPI && JPEG && DSI */
319 /**
320 * @}
321 */
322
323 /* Private function prototypes -----------------------------------------------*/
324
325 /* Exported functions --------------------------------------------------------*/
326 /** @addtogroup MDMA_LL_Exported_Functions
327 * @{
328 */
329
330 /** @addtogroup MDMA_LL_EF_Init
331 * @{
332 */
333
334 /**
335 * @brief De-initialize the MDMA registers to their default reset values.
336 * @param MDMAx MDMAx Instance
337 * @param Channel This parameter can be one of the following values:
338 * @arg @ref LL_MDMA_CHANNEL_0
339 * @arg @ref LL_MDMA_CHANNEL_1
340 * @arg @ref LL_MDMA_CHANNEL_2
341 * @arg @ref LL_MDMA_CHANNEL_3
342 * @arg @ref LL_MDMA_CHANNEL_4
343 * @arg @ref LL_MDMA_CHANNEL_5
344 * @arg @ref LL_MDMA_CHANNEL_6
345 * @arg @ref LL_MDMA_CHANNEL_7
346 * @arg @ref LL_MDMA_CHANNEL_8
347 * @arg @ref LL_MDMA_CHANNEL_9
348 * @arg @ref LL_MDMA_CHANNEL_10
349 * @arg @ref LL_MDMA_CHANNEL_11
350 * @arg @ref LL_MDMA_CHANNEL_12
351 * @arg @ref LL_MDMA_CHANNEL_13
352 * @arg @ref LL_MDMA_CHANNEL_14
353 * @arg @ref LL_MDMA_CHANNEL_15
354 * @arg @ref LL_MDMA_CHANNEL_ALL
355 * @retval An ErrorStatus enumeration value:
356 * - SUCCESS: MDMA registers are de-initialized
357 * - ERROR: Not applicable
358 */
359 uint32_t LL_MDMA_DeInit(MDMA_TypeDef *MDMAx, uint32_t Channel)
360 {
361 MDMA_Channel_TypeDef *tmp;
362 ErrorStatus status = SUCCESS;
363
364 /* Check the MDMA Instance MDMAx and Channel parameters*/
365 assert_param(IS_LL_MDMA_ALL_CHANNEL_INSTANCE(MDMAx, Channel));
366
367 if (Channel == LL_MDMA_CHANNEL_ALL)
368 {
369 LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_MDMA);
370 LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_MDMA);
371 }
372 else
373 {
374 /* Disable the selected Channel */
375 LL_MDMA_DisableChannel(MDMAx,Channel);
376
377 /* Get the MDMA Channel Instance */
378 tmp = (MDMA_Channel_TypeDef *)(LL_MDMA_GET_CHANNEL_INSTANCE(MDMAx, Channel));
379
380 /* Reset MDMAx_Channely control register */
381 LL_MDMA_WriteReg(tmp, CCR, 0U);
382
383 /* Reset MDMAx_Channely Configuration register */
384 LL_MDMA_WriteReg(tmp, CTCR, 0U);
385
386 /* Reset MDMAx_Channely block number of data register */
387 LL_MDMA_WriteReg(tmp, CBNDTR, 0U);
388
389 /* Reset MDMAx_Channely source address register */
390 LL_MDMA_WriteReg(tmp, CSAR, 0U);
391
392 /* Reset MDMAx_Channely destination address register */
393 LL_MDMA_WriteReg(tmp, CDAR, 0U);
394
395 /* Reset MDMAx_Channely Block Repeat address Update register */
396 LL_MDMA_WriteReg(tmp, CBRUR, 0U);
397
398 /* Reset MDMAx_Channely Link Address register */
399 LL_MDMA_WriteReg(tmp, CLAR, 0U);
400
401 /* Reset MDMAx_Channely Trigger and Bus selection register */
402 LL_MDMA_WriteReg(tmp, CTBR, 0U);
403
404 /* Reset MDMAx_Channely Mask address register */
405 LL_MDMA_WriteReg(tmp, CMAR, 0U);
406
407 /* Reset MDMAx_Channely Mask Data register */
408 LL_MDMA_WriteReg(tmp, CMDR, 0U);
409
410 /* Reset the Channel pending flags */
411 LL_MDMA_WriteReg(tmp, CIFCR, 0x0000001FU);
412 }
413
414 return (uint32_t)status;
415 }
416
417 /**
418 * @brief Initialize the MDMA registers according to the specified parameters in MDMA_InitStruct.
419 * @note To convert MDMAx_Channely Instance to MDMAx Instance and Channely, use helper macros :
420 * @arg @ref LL_MDMA_GET_INSTANCE
421 * @arg @ref LL_MDMA_GET_CHANNEL
422 * @param MDMAx MDMAx Instance
423 * @param Channel This parameter can be one of the following values:
424 * @arg @ref LL_MDMA_CHANNEL_0
425 * @arg @ref LL_MDMA_CHANNEL_1
426 * @arg @ref LL_MDMA_CHANNEL_2
427 * @arg @ref LL_MDMA_CHANNEL_3
428 * @arg @ref LL_MDMA_CHANNEL_4
429 * @arg @ref LL_MDMA_CHANNEL_5
430 * @arg @ref LL_MDMA_CHANNEL_6
431 * @arg @ref LL_MDMA_CHANNEL_7
432 * @arg @ref LL_MDMA_CHANNEL_8
433 * @arg @ref LL_MDMA_CHANNEL_9
434 * @arg @ref LL_MDMA_CHANNEL_10
435 * @arg @ref LL_MDMA_CHANNEL_11
436 * @arg @ref LL_MDMA_CHANNEL_12
437 * @arg @ref LL_MDMA_CHANNEL_13
438 * @arg @ref LL_MDMA_CHANNEL_14
439 * @arg @ref LL_MDMA_CHANNEL_15
440 * @param MDMA_InitStruct pointer to a @ref LL_MDMA_InitTypeDef structure.
441 * @retval An ErrorStatus enumeration value:
442 * - SUCCESS: MDMA registers are initialized
443 * - ERROR: Not applicable
444 */
445 uint32_t LL_MDMA_Init(MDMA_TypeDef *MDMAx, uint32_t Channel, LL_MDMA_InitTypeDef *MDMA_InitStruct)
446 {
447 /* Check the MDMA Instance MDMAx and Channel parameters*/
448 assert_param(IS_LL_MDMA_ALL_CHANNEL_INSTANCE(MDMAx, Channel));
449
450 /* Check the MDMA parameters from MDMA_InitStruct */
451 assert_param(IS_LL_MDMA_BLK_DATALENGTH(MDMA_InitStruct->BlockDataLength));
452 assert_param(IS_LL_MDMA_BLK_REPEATCOUNT(MDMA_InitStruct->BlockRepeatCount));
453 assert_param(IS_LL_MDMA_WORDENDIANESS(MDMA_InitStruct->WordEndianess));
454 assert_param(IS_LL_MDMA_HALFWORDENDIANESS(MDMA_InitStruct->HalfWordEndianess));
455 assert_param(IS_LL_MDMA_BYTEENDIANESS(MDMA_InitStruct->ByteEndianess));
456 assert_param(IS_LL_MDMA_PRIORITY(MDMA_InitStruct->Priority));
457 assert_param(IS_LL_MDMA_BUFFWRITEMODE(MDMA_InitStruct->BufferableWriteMode));
458 assert_param(IS_LL_MDMA_REQUESTMODE(MDMA_InitStruct->RequestMode));
459 assert_param(IS_LL_MDMA_TRIGGERMODE(MDMA_InitStruct->TriggerMode));
460 assert_param(IS_LL_MDMA_PADDINGALIGNEMENT(MDMA_InitStruct->PaddingAlignment));
461 assert_param(IS_LL_MDMA_PACKMODE(MDMA_InitStruct->PackMode));
462 assert_param(IS_LL_MDMA_BUFFER_XFERLENGTH(MDMA_InitStruct->BufferTransferLength));
463 assert_param(IS_LL_MDMA_DESTBURST(MDMA_InitStruct->DestBurst));
464 assert_param(IS_LL_MDMA_SRCTBURST(MDMA_InitStruct->SrctBurst));
465 assert_param(IS_LL_MDMA_DESTINCSIZE(MDMA_InitStruct->DestIncSize));
466 assert_param(IS_LL_MDMA_SRCINCSIZE(MDMA_InitStruct->SrcIncSize));
467 assert_param(IS_LL_MDMA_DESTDATASIZE(MDMA_InitStruct->DestDataSize));
468 assert_param(IS_LL_MDMA_SRCDATASIZE(MDMA_InitStruct->SrcDataSize));
469 assert_param(IS_LL_MDMA_DESTINCMODE(MDMA_InitStruct->DestIncMode));
470 assert_param(IS_LL_MDMA_SRCINCMODE(MDMA_InitStruct->SrcIncMode));
471 assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatDestAddrUpdateMode));
472 assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode));
473 assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatDestAddrUpdateVal));
474 assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal));
475 assert_param(IS_LL_MDMA_DEST_BUS(MDMA_InitStruct->DestBus));
476 assert_param(IS_LL_MDMA_SRC_BUS(MDMA_InitStruct->SrcBus));
477 assert_param(IS_LL_MDMA_HWTRIGGER(MDMA_InitStruct->HWTrigger));
478
479
480 /*-------------------------- MDMAx CCR Configuration --------------------------
481 * Configure the Transfer endianness na priority with parameter :
482 * - WordEndianess: MDMA_CCR_WEX[14] bit
483 * - HalfWordEndianess: MDMA_CCR_HEX[13] bit
484 * - WordEndianess: MDMA_CCR_BEX[12] bit
485 * - Priority: MDMA_CCR_BEX[7:6] bits
486 */
487 LL_MDMA_ConfigXferEndianness(MDMAx, Channel, MDMA_InitStruct->WordEndianess | \
488 MDMA_InitStruct->HalfWordEndianess | \
489 MDMA_InitStruct->ByteEndianess);
490
491 LL_MDMA_SetChannelPriorityLevel(MDMAx, Channel, MDMA_InitStruct->Priority);
492
493 /*-------------------------- MDMAx CTCR Configuration --------------------------
494 * Configure the Transfer parameter :
495 * - BufferableWriteMode: MDMA_CTCR_BWM[31] bit
496 * - RequestMode: MDMA_CTCR_SWRM[30] bit
497 * - TriggerMode: MDMA_CTCR_TRGM[29:28] bits
498 * - PaddingAlignment: MDMA_CTCR_PAM[27:26] bits
499 * - PackMode: MDMA_CTCR_PKE[25] bit
500 * - BufferTransferLength: MDMA_CTCR_TLEN[24:18] bits
501 * - DestBurst: MDMA_CTCR_DBURST[17:15] bits
502 * - SrctBurst: MDMA_CTCR_SBURST[14:12] bits
503 * - DestIncSize: MDMA_CTCR_DINCOS[11:10] bits
504 * - SrcIncSize: MDMA_CTCR_SINCOS[9:8] bits
505 * - DestDataSize: MDMA_CTCR_DSIZE[7:6] bits
506 * - SrcDataSize: MDMA_CTCR_SSIZE[5:4] bits
507 * - DestIncMode: MDMA_CTCR_DINC[3:2] bits
508 * - SrcIncMode: MDMA_CTCR_SINC[1:0] bits
509 */
510 LL_MDMA_ConfigTransfer(MDMAx, Channel, MDMA_InitStruct->BufferableWriteMode | \
511 MDMA_InitStruct->RequestMode | \
512 MDMA_InitStruct->TriggerMode | \
513 MDMA_InitStruct->PaddingAlignment | \
514 MDMA_InitStruct->PackMode | \
515 MDMA_InitStruct->DestBurst | \
516 MDMA_InitStruct->SrctBurst | \
517 MDMA_InitStruct->DestIncSize | \
518 MDMA_InitStruct->SrcIncSize | \
519 MDMA_InitStruct->DestDataSize | \
520 MDMA_InitStruct->SrcDataSize | \
521 MDMA_InitStruct->DestIncMode | \
522 MDMA_InitStruct->SrcIncMode, MDMA_InitStruct->BufferTransferLength);
523
524 /*-------------------------- MDMAx CBNDTR Configuration --------------------------
525 * Configure the Transfer Block counters and update mode with parameter :
526 * - BlockRepeatCount: MDMA_CBNDTR_BRC[31:20] bits
527 * - BlockDataLength: MDMA_CBNDTR_BNDT[16:0] bits
528 * - BlockRepeatDestAddrUpdateMode: MDMA_CBNDTR_BRDUM[19] bit
529 * - BlockRepeatDestAddrUpdateMode: MDMA_CBNDTR_BRSUM[18] bit
530 */
531 LL_MDMA_ConfigBlkCounters(MDMAx, Channel, MDMA_InitStruct->BlockRepeatCount, MDMA_InitStruct->BlockDataLength);
532
533 LL_MDMA_ConfigBlkRepeatAddrUpdate(MDMAx, Channel, MDMA_InitStruct->BlockRepeatDestAddrUpdateMode | \
534 MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode);
535
536
537
538 /*-------------------------- MDMAx CSAR Configuration --------------------------
539 * Configure the Transfer source address with parameter :
540 * - SrcAddress: MDMA_CSAR_SAR[31:0] bits
541 */
542 LL_MDMA_SetSourceAddress(MDMAx, Channel, MDMA_InitStruct->SrcAddress);
543
544 /*-------------------------- MDMAx CDAR Configuration --------------------------
545 * Configure the Transfer destination address with parameter :
546 * - DstAddress: MDMA_CDAR_DAR[31:0] bits
547 */
548 LL_MDMA_SetDestinationAddress(MDMAx, Channel, MDMA_InitStruct->DstAddress);
549
550 /*-------------------------- MDMAx CBRUR Configuration --------------------------
551 * Configure the Transfer Block repeat address update value with parameter :
552 * - BlockRepeatDestAddrUpdateVal: MDMA_CBRUR_DUV[31:16] bits
553 * - BlockRepeatSrcAddrUpdateVal: MDMA_CBRUR_SUV[15:0] bits
554 */
555 LL_MDMA_ConfigBlkRptAddrUpdateValue(MDMAx, Channel, MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal, \
556 MDMA_InitStruct->BlockRepeatDestAddrUpdateVal);
557
558 /*-------------------------- MDMAx CLAR Configuration --------------------------
559 * Configure the Transfer linked list address with parameter :
560 * - LinkAddress: MDMA_CLAR_LAR[31:0] bits
561 */
562 LL_MDMA_SetLinkAddress(MDMAx, Channel, MDMA_InitStruct->LinkAddress);
563
564 /*-------------------------- MDMAx CTBR Configuration --------------------------
565 * Configure the Transfer HW trigger and bus selection with parameter :
566 * - DestBus: MDMA_TBR_DBUS[17] bit
567 * - SrcBus: MDMA_TBR_SBUS[16] bit
568 * - HWTrigger: MDMA_TBR_TSEL[5:0] bits
569 */
570 LL_MDMA_ConfigBusSelection(MDMAx, Channel, MDMA_InitStruct->DestBus | MDMA_InitStruct->SrcBus);
571
572 LL_MDMA_SetHWTrigger(MDMAx, Channel, MDMA_InitStruct->HWTrigger);
573
574 /*-------------------------- MDMAx CMAR Configuration --------------------------
575 * Configure the mask address with parameter :
576 * - MaskAddress: MDMA_CMAR_MAR[31:0] bits
577 */
578 LL_MDMA_SetMaskAddress(MDMAx, Channel, MDMA_InitStruct->MaskAddress);
579
580 /*-------------------------- MDMAx CMDR Configuration --------------------------
581 * Configure the mask data with parameter :
582 * - MaskData: MDMA_CMDR_MDR[31:0] bits
583 */
584 LL_MDMA_SetMaskData(MDMAx, Channel, MDMA_InitStruct->MaskData);
585
586 return (uint32_t)SUCCESS;
587 }
588
589 /**
590 * @brief Set each @ref LL_MDMA_InitTypeDef field to default value.
591 * @param MDMA_InitStruct Pointer to a @ref LL_MDMA_InitTypeDef structure.
592 * @retval None
593 */
594 void LL_MDMA_StructInit(LL_MDMA_InitTypeDef *MDMA_InitStruct)
595 {
596 /* Set DMA_InitStruct fields to default values */
597 MDMA_InitStruct->SrcAddress = 0x00000000U;
598 MDMA_InitStruct->DstAddress = 0x00000000U;
599 MDMA_InitStruct->BlockDataLength = 0x00000000U;
600 MDMA_InitStruct->BlockRepeatCount = 0x00000000U;
601 MDMA_InitStruct->WordEndianess = LL_MDMA_WORD_ENDIANNESS_PRESERVE;
602 MDMA_InitStruct->HalfWordEndianess = LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE;
603 MDMA_InitStruct->ByteEndianess = LL_MDMA_BYTE_ENDIANNESS_PRESERVE;
604 MDMA_InitStruct->Priority = LL_MDMA_PRIORITY_LOW;
605 MDMA_InitStruct->BufferableWriteMode = LL_MDMA_BUFF_WRITE_DISABLE;
606 MDMA_InitStruct->RequestMode = LL_MDMA_REQUEST_MODE_HW;
607 MDMA_InitStruct->TriggerMode = LL_MDMA_BUFFER_TRANSFER;
608 MDMA_InitStruct->PaddingAlignment = LL_MDMA_DATAALIGN_RIGHT;
609 MDMA_InitStruct->PackMode = LL_MDMA_PACK_DISABLE;
610 MDMA_InitStruct->BufferTransferLength = 0x00000000U;
611 MDMA_InitStruct->DestBurst = LL_MDMA_DEST_BURST_SINGLE;
612 MDMA_InitStruct->SrctBurst = LL_MDMA_SRC_BURST_SINGLE;
613 MDMA_InitStruct->DestIncSize = LL_MDMA_DEST_INC_OFFSET_BYTE;
614 MDMA_InitStruct->SrcIncSize = LL_MDMA_SRC_INC_OFFSET_BYTE;
615 MDMA_InitStruct->DestDataSize = LL_MDMA_DEST_DATA_SIZE_BYTE;
616 MDMA_InitStruct->SrcDataSize = LL_MDMA_SRC_DATA_SIZE_BYTE;
617 MDMA_InitStruct->DestIncMode = LL_MDMA_DEST_FIXED;
618 MDMA_InitStruct->SrcIncMode = LL_MDMA_SRC_FIXED;
619 MDMA_InitStruct->BlockRepeatDestAddrUpdateMode = LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT;
620 MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode = LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT;
621 MDMA_InitStruct->BlockRepeatDestAddrUpdateVal = 0x00000000U;
622 MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal = 0x00000000U;
623 MDMA_InitStruct->LinkAddress = 0x00000000U;
624 MDMA_InitStruct->DestBus = LL_MDMA_DEST_BUS_SYSTEM_AXI;
625 MDMA_InitStruct->SrcBus = LL_MDMA_SRC_BUS_SYSTEM_AXI;
626 MDMA_InitStruct->HWTrigger = LL_MDMA_REQ_DMA1_STREAM0_TC;
627 MDMA_InitStruct->MaskAddress = 0x00000000U;
628 MDMA_InitStruct->MaskData = 0x00000000U;
629 }
630
631 /**
632 * @brief Initializes MDMA linked list node according to the specified
633 * parameters in the MDMA_InitStruct.
634 * @param MDMA_InitStruct Pointer to a @ref LL_MDMA_InitTypeDef structure that contains
635 * linked list node registers configurations.
636 * @param pNode Pointer to linked list node to fill according to MDMA_InitStruct parameters.
637 * @retval None
638 */
639 void LL_MDMA_CreateLinkNode(LL_MDMA_InitTypeDef *MDMA_InitStruct, LL_MDMA_LinkNodeTypeDef *pNode)
640 {
641
642 /* Check the MDMA parameters from MDMA_InitStruct */
643 assert_param(IS_LL_MDMA_BLK_DATALENGTH(MDMA_InitStruct->BlockDataLength));
644 assert_param(IS_LL_MDMA_BLK_REPEATCOUNT(MDMA_InitStruct->BlockRepeatCount));
645
646 assert_param(IS_LL_MDMA_BUFFWRITEMODE(MDMA_InitStruct->BufferableWriteMode));
647 assert_param(IS_LL_MDMA_REQUESTMODE(MDMA_InitStruct->RequestMode));
648 assert_param(IS_LL_MDMA_TRIGGERMODE(MDMA_InitStruct->TriggerMode));
649 assert_param(IS_LL_MDMA_PADDINGALIGNEMENT(MDMA_InitStruct->PaddingAlignment));
650 assert_param(IS_LL_MDMA_PACKMODE(MDMA_InitStruct->PackMode));
651 assert_param(IS_LL_MDMA_BUFFER_XFERLENGTH(MDMA_InitStruct->BufferTransferLength));
652 assert_param(IS_LL_MDMA_DESTBURST(MDMA_InitStruct->DestBurst));
653 assert_param(IS_LL_MDMA_SRCTBURST(MDMA_InitStruct->SrctBurst));
654 assert_param(IS_LL_MDMA_DESTINCSIZE(MDMA_InitStruct->DestIncSize));
655 assert_param(IS_LL_MDMA_SRCINCSIZE(MDMA_InitStruct->SrcIncSize));
656 assert_param(IS_LL_MDMA_DESTDATASIZE(MDMA_InitStruct->DestDataSize));
657 assert_param(IS_LL_MDMA_SRCDATASIZE(MDMA_InitStruct->SrcDataSize));
658 assert_param(IS_LL_MDMA_DESTINCMODE(MDMA_InitStruct->DestIncMode));
659 assert_param(IS_LL_MDMA_SRCINCMODE(MDMA_InitStruct->SrcIncMode));
660 assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatDestAddrUpdateMode));
661 assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode));
662 assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatDestAddrUpdateVal));
663 assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal));
664 assert_param(IS_LL_MDMA_DEST_BUS(MDMA_InitStruct->DestBus));
665 assert_param(IS_LL_MDMA_SRC_BUS(MDMA_InitStruct->SrcBus));
666 assert_param(IS_LL_MDMA_HWTRIGGER(MDMA_InitStruct->HWTrigger));
667
668
669 /*-------------------------- MDMAx CTCR Configuration --------------------------
670 * Configure the Transfer parameter :
671 * - BufferableWriteMode: MDMA_CTCR_BWM[31] bit
672 * - RequestMode: MDMA_CTCR_SWRM[30] bit
673 * - TriggerMode: MDMA_CTCR_TRGM[29:28] bits
674 * - PaddingAlignment: MDMA_CTCR_PAM[27:26] bits
675 * - PackMode: MDMA_CTCR_PKE[25] bit
676 * - BufferTransferLength: MDMA_CTCR_TLEN[24:18] bits
677 * - DestBurst: MDMA_CTCR_DBURST[17:15] bits
678 * - SrctBurst: MDMA_CTCR_SBURST[14:12] bits
679 * - DestIncSize: MDMA_CTCR_DINCOS[11:10] bits
680 * - SrcIncSize: MDMA_CTCR_SINCOS[9:8] bits
681 * - DestDataSize: MDMA_CTCR_DSIZE[7:6] bits
682 * - SrcDataSize: MDMA_CTCR_SSIZE[5:4] bits
683 * - DestIncMode: MDMA_CTCR_DINC[3:2] bits
684 * - SrcIncMode: MDMA_CTCR_SINC[1:0] bits
685 */
686 pNode->CTCR = MDMA_InitStruct->BufferableWriteMode | \
687 MDMA_InitStruct->RequestMode | \
688 MDMA_InitStruct->TriggerMode | \
689 MDMA_InitStruct->PaddingAlignment | \
690 MDMA_InitStruct->PackMode | \
691 MDMA_InitStruct->DestBurst | \
692 MDMA_InitStruct->SrctBurst | \
693 MDMA_InitStruct->DestIncSize | \
694 MDMA_InitStruct->SrcIncSize | \
695 MDMA_InitStruct->DestDataSize | \
696 MDMA_InitStruct->SrcDataSize | \
697 MDMA_InitStruct->DestIncMode | \
698 MDMA_InitStruct->SrcIncMode | \
699 ((MDMA_InitStruct->BufferTransferLength << MDMA_CTCR_TLEN_Pos) & MDMA_CTCR_TLEN_Msk);
700
701
702
703 /*-------------------------- MDMAx CBNDTR Configuration --------------------------
704 * Configure the Transfer Block counters and update mode with parameter :
705 * - BlockRepeatCount: MDMA_CBNDTR_BRC[31:20] bits
706 * - BlockDataLength: MDMA_CBNDTR_BNDT[16:0] bits
707 * - BlockRepeatDestAddrUpdateMode: MDMA_CBNDTR_BRDUM[19] bit
708 * - BlockRepeatDestAddrUpdateMode: MDMA_CBNDTR_BRSUM[18] bit
709 */
710 pNode->CBNDTR = ((MDMA_InitStruct->BlockRepeatCount << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC_Msk) | \
711 MDMA_InitStruct->BlockRepeatDestAddrUpdateMode | \
712 MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode | \
713 (MDMA_InitStruct->BlockDataLength & MDMA_CBNDTR_BNDT_Msk);
714
715
716 /*-------------------------- MDMAx CSAR Configuration --------------------------
717 * Configure the Transfer source address with parameter :
718 * - SrcAddress: MDMA_CSAR_SAR[31:0] bits
719 */
720 pNode->CSAR = MDMA_InitStruct->SrcAddress;
721
722
723 /*-------------------------- MDMAx CDAR Configuration --------------------------
724 * Configure the Transfer destination address with parameter :
725 * - DstAddress: MDMA_CDAR_DAR[31:0] bits
726 */
727 pNode->CDAR = MDMA_InitStruct->DstAddress;
728
729 /*-------------------------- MDMAx CBRUR Configuration --------------------------
730 * Configure the Transfer Block repeat address update value with parameter :
731 * - BlockRepeatDestAddrUpdateVal: MDMA_CBRUR_DUV[31:16] bits
732 * - BlockRepeatSrcAddrUpdateVal: MDMA_CBRUR_SUV[15:0] bits
733 */
734 pNode->CBRUR = (MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal & MDMA_CBRUR_SUV_Msk) | \
735 ((MDMA_InitStruct->BlockRepeatDestAddrUpdateVal << MDMA_CBRUR_DUV_Pos) & MDMA_CBRUR_DUV_Msk) ;
736
737 /*-------------------------- MDMAx CLAR Configuration --------------------------
738 * Configure the Transfer linked list address with parameter :
739 * - LinkAddress: MDMA_CLAR_LAR[31:0] bits
740 */
741 pNode->CLAR = MDMA_InitStruct->LinkAddress;
742
743 /*-------------------------- MDMAx CTBR Configuration --------------------------
744 * Configure the Transfer HW trigger and bus selection with parameter :
745 * - DestBus: MDMA_TBR_DBUS[17] bit
746 * - SrcBus: MDMA_TBR_SBUS[16] bit
747 * - HWTrigger: MDMA_TBR_TSEL[5:0] bits
748 */
749 pNode->CTBR = MDMA_InitStruct->DestBus | MDMA_InitStruct->SrcBus | MDMA_InitStruct->HWTrigger;
750
751 /*-------------------------- MDMAx CMAR Configuration --------------------------
752 * Configure the mask address with parameter :
753 * - MaskAddress: MDMA_CMAR_MAR[31:0] bits
754 */
755 pNode->CMAR = MDMA_InitStruct->MaskAddress;
756
757 /*-------------------------- MDMAx CMDR Configuration --------------------------
758 * Configure the mask data with parameter :
759 * - MaskData: MDMA_CMDR_MDR[31:0] bits
760 */
761 pNode->CMDR = MDMA_InitStruct->MaskData;
762
763
764 pNode->Reserved = 0;
765
766 }
767
768 /**
769 * @brief Connect Linked list Nodes.
770 * @param pPrevLinkNode Pointer to previous linked list node to be connected to new Lined list node.
771 * @param pNewLinkNode Pointer to new Linked list.
772 * @retval None
773 */
774 void LL_MDMA_ConnectLinkNode(LL_MDMA_LinkNodeTypeDef *pPrevLinkNode, LL_MDMA_LinkNodeTypeDef *pNewLinkNode)
775 {
776 pPrevLinkNode->CLAR = (uint32_t)pNewLinkNode;
777 }
778
779 /**
780 * @brief Disconnect the next linked list node.
781 * @param pLinkNode Pointer to linked list node to be disconnected from the next one.
782 * @retval None
783 */
784 void LL_MDMA_DisconnectNextLinkNode(LL_MDMA_LinkNodeTypeDef *pLinkNode)
785 {
786 pLinkNode->CLAR = 0;
787 }
788
789 /**
790 * @}
791 */
792
793 /**
794 * @}
795 */
796
797 /**
798 * @}
799 */
800
801 #endif /* MDMA */
802
803 /**
804 * @}
805 */
806
807 #endif /* USE_FULL_LL_DRIVER */
808
809 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/