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[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_ll_rcc.c
blob282b9abae73178209de2dedfb3781468f1cf050e
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32h7xx_ll_rcc.h"
23 #include "stm32h7xx_ll_bus.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34 #if defined(RCC)
35
36 /** @addtogroup RCC_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 const uint8_t LL_RCC_PrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 /** @addtogroup RCC_LL_Private_Macros
46 * @{
47 */
48 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART16_CLKSOURCE) \
49 || ((__VALUE__) == LL_RCC_USART234578_CLKSOURCE))
50
51
52 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C123_CLKSOURCE) \
53 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
54
55 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
56 || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \
57 || ((__VALUE__) == LL_RCC_LPTIM345_CLKSOURCE))
58
59 #if defined(SAI3)
60 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
61 || ((__VALUE__) == LL_RCC_SAI23_CLKSOURCE) \
62 || ((__VALUE__) == LL_RCC_SAI4A_CLKSOURCE) \
63 || ((__VALUE__) == LL_RCC_SAI4B_CLKSOURCE))
64 #elif defined(SAI4)
65 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
66 || ((__VALUE__) == LL_RCC_SAI4A_CLKSOURCE) \
67 || ((__VALUE__) == LL_RCC_SAI4B_CLKSOURCE))
68 #else
69 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
70 || ((__VALUE__) == LL_RCC_SAI2A_CLKSOURCE) \
71 || ((__VALUE__) == LL_RCC_SAI2B_CLKSOURCE))
72 #endif /* SAI3 */
73
74 #define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI123_CLKSOURCE) \
75 || ((__VALUE__) == LL_RCC_SPI45_CLKSOURCE) \
76 || ((__VALUE__) == LL_RCC_SPI6_CLKSOURCE))
77
78 /**
79 * @}
80 */
81
82 /* Private function prototypes -----------------------------------------------*/
83 /** @defgroup RCC_LL_Private_Functions RCC Private functions
84 * @{
85 */
86 uint32_t RCC_GetSystemClockFreq(void);
87 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
88 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
89 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
90 uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency);
91 uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency);
92
93 /**
94 * @}
95 */
96
97
98 /* Exported functions --------------------------------------------------------*/
99 /** @addtogroup RCC_LL_Exported_Functions
100 * @{
101 */
102
103 /** @addtogroup RCC_LL_EF_Init
104 * @{
105 */
106
107 /**
108 * @brief Resets the RCC clock configuration to the default reset state.
109 * @note The default reset state of the clock configuration is given below:
110 * - HSI ON and used as system clock source
111 * - HSE, PLL1, PLL2 and PLL3 OFF
112 * - AHB, APB Bus pre-scaler set to 1.
113 * - CSS, MCO1 and MCO2 OFF
114 * - All interrupts disabled
115 * @note This function doesn't modify the configuration of the
116 * - Peripheral clocks
117 * - LSI, LSE and RTC clocks
118 * @retval None
119 */
120 void LL_RCC_DeInit(void)
121 {
122 /* Increasing the CPU frequency */
123 if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
124 {
125 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
126 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
127 }
128
129 /* Set HSION bit */
130 SET_BIT(RCC->CR, RCC_CR_HSION);
131
132 /* Wait for HSI READY bit */
133 while(LL_RCC_HSI_IsReady() == 0U)
134 {}
135
136 /* Reset CFGR register */
137 CLEAR_REG(RCC->CFGR);
138
139 /* Reset CSION , CSIKERON, HSEON, HSI48ON, HSECSSON,HSIDIV, PLL1ON, PLL2ON, PLL3ON bits */
140 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON | RCC_CR_HSI48ON \
141 |RCC_CR_CSSHSEON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
142
143 /* Wait for PLL1 READY bit to be reset */
144 while(LL_RCC_PLL1_IsReady() != 0U)
145 {}
146
147 /* Wait for PLL2 READY bit to be reset */
148 while(LL_RCC_PLL2_IsReady() != 0U)
149 {}
150
151 /* Wait for PLL3 READY bit to be reset */
152 while(LL_RCC_PLL3_IsReady() != 0U)
153 {}
154
155 #if defined(RCC_D1CFGR_HPRE)
156 /* Reset D1CFGR register */
157 CLEAR_REG(RCC->D1CFGR);
158
159 /* Reset D2CFGR register */
160 CLEAR_REG(RCC->D2CFGR);
161
162 /* Reset D3CFGR register */
163 CLEAR_REG(RCC->D3CFGR);
164 #else
165 /* Reset CDCFGR1 register */
166 CLEAR_REG(RCC->CDCFGR1);
167
168 /* Reset CDCFGR2 register */
169 CLEAR_REG(RCC->CDCFGR2);
170
171 /* Reset SRDCFGR register */
172 CLEAR_REG(RCC->SRDCFGR);
173
174 #endif /* RCC_D1CFGR_HPRE */
175
176 /* Reset PLLCKSELR register to default value */
177 RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5;
178
179 /* Reset PLLCFGR register to default value */
180 LL_RCC_WriteReg(PLLCFGR, 0x01FF0000U);
181
182 /* Reset PLL1DIVR register to default value */
183 LL_RCC_WriteReg(PLL1DIVR, 0x01010280U);
184
185 /* Reset PLL1FRACR register */
186 CLEAR_REG(RCC->PLL1FRACR);
187
188 /* Reset PLL2DIVR register to default value */
189 LL_RCC_WriteReg(PLL2DIVR, 0x01010280U);
190
191 /* Reset PLL2FRACR register */
192 CLEAR_REG(RCC->PLL2FRACR);
193
194 /* Reset PLL3DIVR register to default value */
195 LL_RCC_WriteReg(PLL3DIVR, 0x01010280U);
196
197 /* Reset PLL3FRACR register */
198 CLEAR_REG(RCC->PLL3FRACR);
199
200 /* Reset HSEBYP bit */
201 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
202
203 /* Disable all interrupts */
204 CLEAR_REG(RCC->CIER);
205
206 /* Clear all interrupts */
207 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC
208 | RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLL2RDYC
209 | RCC_CICR_PLL3RDYC | RCC_CICR_LSECSSC | RCC_CICR_HSECSSC);
210
211 /* Clear reset source flags */
212 SET_BIT(RCC->RSR, RCC_RSR_RMVF);
213
214 /* Decreasing the number of wait states because of lower CPU frequency */
215 if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
216 {
217 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
218 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
219 }
220
221 }
222
223 /**
224 * @}
225 */
226
227 /** @addtogroup RCC_LL_EF_Get_Freq
228 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
229 * and different peripheral clocks available on the device.
230 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
231 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
232 * @note If SYSCLK source is CSI, function returns values based on CSI_VALUE(***)
233 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
234 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
235 * @note (*) HSI_VALUE is a constant defined in header file (default value
236 * 64 MHz) divider by HSIDIV, but the real value may vary depending on
237 * on the variations in voltage and temperature.
238 * @note (**) HSE_VALUE is a constant defined in header file (default value
239 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
240 * frequency of the crystal used. Otherwise, this function may
241 * have wrong result.
242 * @note (***) CSI_VALUE is a constant defined in header file (default value
243 * 4 MHz) but the real value may vary depending on the variations
244 * in voltage and temperature.
245 * @note The result of this function could be incorrect when using fractional
246 * value for HSE crystal.
247 * @note This function can be used by the user application to compute the
248 * baud-rate for the communication peripherals or configure other parameters.
249 * @{
250 */
251
252 /**
253 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
254 * @note Each time SYSCLK, HCLK, PCLK1, PCLK2, PCLK3 and/or PCLK4 clock changes, this function
255 * must be called to update structure fields. Otherwise, any
256 * configuration based on this function will be incorrect.
257 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
258 * @retval None
259 */
260 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
261 {
262 /* Get SYSCLK frequency */
263 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
264
265 /* HCLK clock frequency */
266 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
267
268 /* PCLK1 clock frequency */
269 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
270
271 /* PCLK2 clock frequency */
272 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
273
274 /* PCLK3 clock frequency */
275 RCC_Clocks->PCLK3_Frequency = RCC_GetPCLK3ClockFreq(RCC_Clocks->HCLK_Frequency);
276
277 /* PCLK4 clock frequency */
278 RCC_Clocks->PCLK4_Frequency = RCC_GetPCLK4ClockFreq(RCC_Clocks->HCLK_Frequency);
279 }
280
281 /**
282 * @brief Return PLL1 clocks frequencies
283 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
284 * @retval None
285 */
286 void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
287 {
288 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
289 uint32_t m, n, fracn = 0U;
290
291 /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
292 SYSCLK = PLL_VCO / PLLP
293 */
294 pllsource = LL_RCC_PLL_GetSource();
295
296 switch (pllsource)
297 {
298 case LL_RCC_PLLSOURCE_HSI:
299 if (LL_RCC_HSI_IsReady() != 0U)
300 {
301 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
302 }
303 break;
304
305 case LL_RCC_PLLSOURCE_CSI:
306 if (LL_RCC_CSI_IsReady() != 0U)
307 {
308 pllinputfreq = CSI_VALUE;
309 }
310 break;
311
312 case LL_RCC_PLLSOURCE_HSE:
313 if (LL_RCC_HSE_IsReady() != 0U)
314 {
315 pllinputfreq = HSE_VALUE;
316 }
317 break;
318
319 case LL_RCC_PLLSOURCE_NONE:
320 default:
321 /* PLL clock disabled */
322 break;
323 }
324
325 PLL_Clocks->PLL_P_Frequency = 0U;
326 PLL_Clocks->PLL_Q_Frequency = 0U;
327 PLL_Clocks->PLL_R_Frequency = 0U;
328
329 m = LL_RCC_PLL1_GetM();
330 n = LL_RCC_PLL1_GetN();
331 if (LL_RCC_PLL1FRACN_IsEnabled() != 0U)
332 {
333 fracn = LL_RCC_PLL1_GetFRACN();
334 }
335
336 if (m != 0U)
337 {
338 if (LL_RCC_PLL1P_IsEnabled() != 0U)
339 {
340 PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetP());
341 }
342
343 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
344 {
345 PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetQ());
346 }
347
348 if (LL_RCC_PLL1R_IsEnabled() != 0U)
349 {
350 PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetR());
351 }
352 }
353 }
354
355 /**
356 * @brief Return PLL2 clocks frequencies
357 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
358 * @retval None
359 */
360 void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
361 {
362 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
363 uint32_t m, n, fracn = 0U;
364
365 /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
366 SYSCLK = PLL_VCO / PLLP
367 */
368 pllsource = LL_RCC_PLL_GetSource();
369
370 switch (pllsource)
371 {
372 case LL_RCC_PLLSOURCE_HSI:
373 if (LL_RCC_HSI_IsReady() != 0U)
374 {
375 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
376 }
377 break;
378
379 case LL_RCC_PLLSOURCE_CSI:
380 if (LL_RCC_CSI_IsReady() != 0U)
381 {
382 pllinputfreq = CSI_VALUE;
383 }
384 break;
385
386 case LL_RCC_PLLSOURCE_HSE:
387 if (LL_RCC_HSE_IsReady() != 0U)
388 {
389 pllinputfreq = HSE_VALUE;
390 }
391 break;
392
393 case LL_RCC_PLLSOURCE_NONE:
394 default:
395 /* PLL clock disabled */
396 break;
397 }
398
399 PLL_Clocks->PLL_P_Frequency = 0U;
400 PLL_Clocks->PLL_Q_Frequency = 0U;
401 PLL_Clocks->PLL_R_Frequency = 0U;
402
403 m = LL_RCC_PLL2_GetM();
404 n = LL_RCC_PLL2_GetN();
405 if (LL_RCC_PLL2FRACN_IsEnabled() != 0U)
406 {
407 fracn = LL_RCC_PLL2_GetFRACN();
408 }
409
410 if (m != 0U)
411 {
412 if (LL_RCC_PLL2P_IsEnabled() != 0U)
413 {
414 PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetP());
415 }
416
417 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
418 {
419 PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetQ());
420 }
421
422 if (LL_RCC_PLL2R_IsEnabled() != 0U)
423 {
424 PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetR());
425 }
426 }
427 }
428
429 /**
430 * @brief Return PLL3 clocks frequencies
431 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
432 * @retval None
433 */
434 void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
435 {
436 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
437 uint32_t m, n, fracn = 0U;
438
439 /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
440 SYSCLK = PLL_VCO / PLLP
441 */
442 pllsource = LL_RCC_PLL_GetSource();
443
444 switch (pllsource)
445 {
446 case LL_RCC_PLLSOURCE_HSI:
447 if (LL_RCC_HSI_IsReady() != 0U)
448 {
449 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
450 }
451 break;
452
453 case LL_RCC_PLLSOURCE_CSI:
454 if (LL_RCC_CSI_IsReady() != 0U)
455 {
456 pllinputfreq = CSI_VALUE;
457 }
458 break;
459
460 case LL_RCC_PLLSOURCE_HSE:
461 if (LL_RCC_HSE_IsReady() != 0U)
462 {
463 pllinputfreq = HSE_VALUE;
464 }
465 break;
466
467 case LL_RCC_PLLSOURCE_NONE:
468 default:
469 /* PLL clock disabled */
470 break;
471 }
472
473 PLL_Clocks->PLL_P_Frequency = 0U;
474 PLL_Clocks->PLL_Q_Frequency = 0U;
475 PLL_Clocks->PLL_R_Frequency = 0U;
476
477 m = LL_RCC_PLL3_GetM();
478 n = LL_RCC_PLL3_GetN();
479 if (LL_RCC_PLL3FRACN_IsEnabled() != 0U)
480 {
481 fracn = LL_RCC_PLL3_GetFRACN();
482 }
483
484 if ((m != 0U) && (pllinputfreq != 0U))
485 {
486 if (LL_RCC_PLL3P_IsEnabled() != 0U)
487 {
488 PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetP());
489 }
490
491 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
492 {
493 PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetQ());
494 }
495
496 if (LL_RCC_PLL3R_IsEnabled() != 0U)
497 {
498 PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetR());
499 }
500 }
501 }
502
503 /**
504 * @brief Helper function to calculate the PLL frequency output
505 * @note ex: @ref LL_RCC_CalcPLLClockFreq (HSE_VALUE, @ref LL_RCC_PLL1_GetM (),
506 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetFRACN (), @ref LL_RCC_PLL1_GetP ());
507 * @param PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/CSI)
508 * @param M Between 1 and 63
509 * @param N Between 4 and 512
510 * @param FRACN Between 0 and 0x1FFF
511 * @param PQR VCO output divider (P, Q or R)
512 * Between 1 and 128, except for PLL1P Odd value not allowed
513 * @retval PLL1 clock frequency (in Hz)
514 */
515 uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR)
516 {
517 float_t freq;
518
519 freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN/(float_t)0x2000));
520
521 freq = freq/(float_t)PQR;
522
523 return (uint32_t)freq;
524 }
525
526 /**
527 * @brief Return USARTx clock frequency
528 * @param USARTxSource This parameter can be one of the following values:
529 * @arg @ref LL_RCC_USART16_CLKSOURCE
530 * @arg @ref LL_RCC_USART234578_CLKSOURCE
531 * @retval USART clock frequency (in Hz)
532 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
533 */
534 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
535 {
536 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
537 LL_PLL_ClocksTypeDef PLL_Clocks;
538
539 /* Check parameter */
540 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
541
542 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
543 {
544 case LL_RCC_USART16_CLKSOURCE_PCLK2:
545 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
546 break;
547
548 case LL_RCC_USART234578_CLKSOURCE_PCLK1:
549 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
550 break;
551
552 case LL_RCC_USART16_CLKSOURCE_PLL2Q:
553 case LL_RCC_USART234578_CLKSOURCE_PLL2Q:
554 if (LL_RCC_PLL2_IsReady() != 0U)
555 {
556 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
557 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
558 }
559 break;
560
561 case LL_RCC_USART16_CLKSOURCE_PLL3Q:
562 case LL_RCC_USART234578_CLKSOURCE_PLL3Q:
563 if (LL_RCC_PLL3_IsReady() != 0U)
564 {
565 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
566 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
567 }
568 break;
569
570 case LL_RCC_USART16_CLKSOURCE_HSI:
571 case LL_RCC_USART234578_CLKSOURCE_HSI:
572 if (LL_RCC_HSI_IsReady() != 0U)
573 {
574 usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
575 }
576 break;
577
578 case LL_RCC_USART16_CLKSOURCE_CSI:
579 case LL_RCC_USART234578_CLKSOURCE_CSI:
580 if (LL_RCC_CSI_IsReady() != 0U)
581 {
582 usart_frequency = CSI_VALUE;
583 }
584 break;
585
586 case LL_RCC_USART16_CLKSOURCE_LSE:
587 case LL_RCC_USART234578_CLKSOURCE_LSE:
588 if (LL_RCC_LSE_IsReady() != 0U)
589 {
590 usart_frequency = LSE_VALUE;
591 }
592 break;
593
594 default:
595 /* Kernel clock disabled */
596 break;
597 }
598
599 return usart_frequency;
600 }
601
602 /**
603 * @brief Return LPUART clock frequency
604 * @param LPUARTxSource This parameter can be one of the following values:
605 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
606 * @retval LPUART clock frequency (in Hz)
607 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
608 */
609 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
610 {
611 uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
612 LL_PLL_ClocksTypeDef PLL_Clocks;
613
614 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
615 {
616 case LL_RCC_LPUART1_CLKSOURCE_PCLK4:
617 lpuart_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
618 break;
619
620 case LL_RCC_LPUART1_CLKSOURCE_PLL2Q:
621 if (LL_RCC_PLL2_IsReady() != 0U)
622 {
623 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
624 lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
625 }
626 break;
627
628 case LL_RCC_LPUART1_CLKSOURCE_PLL3Q:
629 if (LL_RCC_PLL3_IsReady() != 0U)
630 {
631 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
632 lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
633 }
634 break;
635
636 case LL_RCC_LPUART1_CLKSOURCE_HSI:
637 if (LL_RCC_HSI_IsReady() != 0U)
638 {
639 lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
640 }
641 break;
642
643 case LL_RCC_LPUART1_CLKSOURCE_CSI:
644 if (LL_RCC_CSI_IsReady() != 0U)
645 {
646 lpuart_frequency = CSI_VALUE;
647 }
648 break;
649
650 case LL_RCC_LPUART1_CLKSOURCE_LSE:
651 if (LL_RCC_LSE_IsReady() != 0U)
652 {
653 lpuart_frequency = LSE_VALUE;
654 }
655 break;
656
657 default:
658 /* Kernel clock disabled */
659 break;
660 }
661
662 return lpuart_frequency;
663 }
664
665 /**
666 * @brief Return I2Cx clock frequency
667 * @param I2CxSource This parameter can be one of the following values:
668 * @arg @ref LL_RCC_I2C123_CLKSOURCE
669 * @arg @ref LL_RCC_I2C4_CLKSOURCE
670 * @retval I2C clock frequency (in Hz)
671 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
672 */
673 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
674 {
675 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
676 LL_PLL_ClocksTypeDef PLL_Clocks;
677
678 /* Check parameter */
679 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
680
681 switch (LL_RCC_GetI2CClockSource(I2CxSource))
682 {
683 case LL_RCC_I2C123_CLKSOURCE_PCLK1:
684 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
685 break;
686
687 case LL_RCC_I2C4_CLKSOURCE_PCLK4:
688 i2c_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
689 break;
690
691 case LL_RCC_I2C123_CLKSOURCE_PLL3R:
692 case LL_RCC_I2C4_CLKSOURCE_PLL3R:
693 if (LL_RCC_PLL3_IsReady() != 0U)
694 {
695 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
696 i2c_frequency = PLL_Clocks.PLL_R_Frequency;
697 }
698 break;
699
700 case LL_RCC_I2C123_CLKSOURCE_HSI:
701 case LL_RCC_I2C4_CLKSOURCE_HSI:
702 if (LL_RCC_HSI_IsReady() != 0U)
703 {
704 i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
705 }
706 break;
707
708 case LL_RCC_I2C123_CLKSOURCE_CSI:
709 case LL_RCC_I2C4_CLKSOURCE_CSI:
710 if (LL_RCC_CSI_IsReady() != 0U)
711 {
712 i2c_frequency = CSI_VALUE;
713 }
714 break;
715
716 default:
717 /* Nothing to do */
718 break;
719 }
720
721 return i2c_frequency;
722 }
723
724 /**
725 * @brief Return LPTIMx clock frequency
726 * @param LPTIMxSource This parameter can be one of the following values:
727 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
728 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
729 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE
730 * @retval LPTIM clock frequency (in Hz)
731 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
732 */
733 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
734 {
735 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
736 LL_PLL_ClocksTypeDef PLL_Clocks;
737
738 /* Check parameter */
739 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
740
741 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
742 {
743 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:
744 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
745 break;
746
747 case LL_RCC_LPTIM2_CLKSOURCE_PCLK4:
748 case LL_RCC_LPTIM345_CLKSOURCE_PCLK4:
749 lptim_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
750 break;
751
752 case LL_RCC_LPTIM1_CLKSOURCE_PLL2P:
753 case LL_RCC_LPTIM2_CLKSOURCE_PLL2P:
754 case LL_RCC_LPTIM345_CLKSOURCE_PLL2P:
755 if (LL_RCC_PLL2_IsReady() != 0U)
756 {
757 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
758 lptim_frequency = PLL_Clocks.PLL_P_Frequency;
759 }
760 break;
761
762 case LL_RCC_LPTIM1_CLKSOURCE_PLL3R:
763 case LL_RCC_LPTIM2_CLKSOURCE_PLL3R:
764 case LL_RCC_LPTIM345_CLKSOURCE_PLL3R:
765 if (LL_RCC_PLL3_IsReady() != 0U)
766 {
767 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
768 lptim_frequency = PLL_Clocks.PLL_R_Frequency;
769 }
770 break;
771
772 case LL_RCC_LPTIM1_CLKSOURCE_LSE:
773 case LL_RCC_LPTIM2_CLKSOURCE_LSE:
774 case LL_RCC_LPTIM345_CLKSOURCE_LSE:
775 if (LL_RCC_LSE_IsReady() != 0U)
776 {
777 lptim_frequency = LSE_VALUE;
778 }
779 break;
780
781 case LL_RCC_LPTIM1_CLKSOURCE_LSI:
782 case LL_RCC_LPTIM2_CLKSOURCE_LSI:
783 case LL_RCC_LPTIM345_CLKSOURCE_LSI:
784 if (LL_RCC_LSI_IsReady() != 0U)
785 {
786 lptim_frequency = LSI_VALUE;
787 }
788 break;
789
790 case LL_RCC_LPTIM1_CLKSOURCE_CLKP:
791 case LL_RCC_LPTIM2_CLKSOURCE_CLKP:
792 case LL_RCC_LPTIM345_CLKSOURCE_CLKP:
793 lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
794 break;
795
796 default:
797 /* Kernel clock disabled */
798 break;
799 }
800
801 return lptim_frequency;
802 }
803
804 /**
805 * @brief Return SAIx clock frequency
806 * @param SAIxSource This parameter can be one of the following values:
807 * @arg @ref LL_RCC_SAI1_CLKSOURCE
808 * @arg @ref LL_RCC_SAI23_CLKSOURCE (*)
809 * @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
810 * @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
811 * @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
812 * @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
813 * @retval SAI clock frequency (in Hz)
814 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
815 *
816 * (*) : Available on some STM32H7 lines only.
817 */
818 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
819 {
820 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
821 LL_PLL_ClocksTypeDef PLL_Clocks;
822
823 /* Check parameter */
824 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
825
826 switch (LL_RCC_GetSAIClockSource(SAIxSource))
827 {
828 case LL_RCC_SAI1_CLKSOURCE_PLL1Q:
829 #if defined(SAI3)
830 case LL_RCC_SAI23_CLKSOURCE_PLL1Q:
831 #endif /* SAI3 */
832 #if defined(SAI4)
833 case LL_RCC_SAI4A_CLKSOURCE_PLL1Q:
834 case LL_RCC_SAI4B_CLKSOURCE_PLL1Q:
835 #endif /* SAI4 */
836 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
837 case LL_RCC_SAI2A_CLKSOURCE_PLL1Q:
838 case LL_RCC_SAI2B_CLKSOURCE_PLL1Q:
839 #endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
840 if (LL_RCC_PLL1_IsReady() != 0U)
841 {
842 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
843 sai_frequency = PLL_Clocks.PLL_Q_Frequency;
844 }
845 break;
846
847 case LL_RCC_SAI1_CLKSOURCE_PLL2P:
848 #if defined(SAI3)
849 case LL_RCC_SAI23_CLKSOURCE_PLL2P:
850 #endif /* SAI3 */
851 #if defined(SAI4)
852 case LL_RCC_SAI4A_CLKSOURCE_PLL2P:
853 case LL_RCC_SAI4B_CLKSOURCE_PLL2P:
854 #endif /* SAI4 */
855 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
856 case LL_RCC_SAI2A_CLKSOURCE_PLL2P:
857 case LL_RCC_SAI2B_CLKSOURCE_PLL2P:
858 #endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
859 if (LL_RCC_PLL2_IsReady() != 0U)
860 {
861 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
862 sai_frequency = PLL_Clocks.PLL_P_Frequency;
863 }
864 break;
865
866 case LL_RCC_SAI1_CLKSOURCE_PLL3P:
867 #if defined(SAI3)
868 case LL_RCC_SAI23_CLKSOURCE_PLL3P:
869 #endif /* SAI3 */
870 #if defined(SAI4)
871 case LL_RCC_SAI4A_CLKSOURCE_PLL3P:
872 case LL_RCC_SAI4B_CLKSOURCE_PLL3P:
873 #endif /* SAI4 */
874 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
875 case LL_RCC_SAI2A_CLKSOURCE_PLL3P:
876 case LL_RCC_SAI2B_CLKSOURCE_PLL3P:
877 #endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
878 if (LL_RCC_PLL3_IsReady() != 0U)
879 {
880 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
881 sai_frequency = PLL_Clocks.PLL_P_Frequency;
882 }
883 break;
884
885 case LL_RCC_SAI1_CLKSOURCE_I2S_CKIN:
886 #if defined(SAI3)
887 case LL_RCC_SAI23_CLKSOURCE_I2S_CKIN:
888 #endif /* SAI3 */
889 #if defined(SAI4)
890 case LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN:
891 case LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN:
892 #endif /* SAI4 */
893 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
894 case LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN:
895 case LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN:
896 #endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
897 sai_frequency = EXTERNAL_CLOCK_VALUE;
898 break;
899
900 case LL_RCC_SAI1_CLKSOURCE_CLKP:
901 #if defined(SAI3)
902 case LL_RCC_SAI23_CLKSOURCE_CLKP:
903 #endif /* SAI3 */
904 #if defined(SAI4)
905 case LL_RCC_SAI4A_CLKSOURCE_CLKP:
906 case LL_RCC_SAI4B_CLKSOURCE_CLKP:
907 #endif /* SAI4 */
908 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
909 case LL_RCC_SAI2A_CLKSOURCE_CLKP:
910 case LL_RCC_SAI2B_CLKSOURCE_CLKP:
911 #endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
912 sai_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
913 break;
914
915 default:
916 /* Kernel clock disabled */
917 break;
918 }
919
920 return sai_frequency;
921 }
922
923 /**
924 * @brief Return ADC clock frequency
925 * @param ADCxSource This parameter can be one of the following values:
926 * @arg @ref LL_RCC_ADC_CLKSOURCE
927 * @retval ADC clock frequency (in Hz)
928 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
929 */
930 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
931 {
932 uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
933 LL_PLL_ClocksTypeDef PLL_Clocks;
934
935 switch (LL_RCC_GetADCClockSource(ADCxSource))
936 {
937 case LL_RCC_ADC_CLKSOURCE_PLL2P:
938 if (LL_RCC_PLL2_IsReady() != 0U)
939 {
940 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
941 adc_frequency = PLL_Clocks.PLL_P_Frequency;
942 }
943 break;
944
945 case LL_RCC_ADC_CLKSOURCE_PLL3R:
946 if (LL_RCC_PLL3_IsReady() != 0U)
947 {
948 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
949 adc_frequency = PLL_Clocks.PLL_R_Frequency;
950 }
951 break;
952
953 case LL_RCC_ADC_CLKSOURCE_CLKP:
954 adc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
955 break;
956
957 default:
958 /* Kernel clock disabled */
959 break;
960 }
961
962 return adc_frequency;
963 }
964
965 /**
966 * @brief Return SDMMC clock frequency
967 * @param SDMMCxSource This parameter can be one of the following values:
968 * @arg @ref LL_RCC_SDMMC_CLKSOURCE
969 * @retval SDMMC clock frequency (in Hz)
970 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
971 */
972 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
973 {
974 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
975 LL_PLL_ClocksTypeDef PLL_Clocks;
976
977 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
978 {
979 case LL_RCC_SDMMC_CLKSOURCE_PLL1Q:
980 if (LL_RCC_PLL1_IsReady() != 0U)
981 {
982 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
983 sdmmc_frequency = PLL_Clocks.PLL_Q_Frequency;
984 }
985 break;
986
987 case LL_RCC_SDMMC_CLKSOURCE_PLL2R:
988 if (LL_RCC_PLL2_IsReady() != 0U)
989 {
990 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
991 sdmmc_frequency = PLL_Clocks.PLL_R_Frequency;
992 }
993 break;
994
995 default:
996 /* Nothing to do */
997 break;
998 }
999
1000 return sdmmc_frequency;
1001 }
1002
1003 /**
1004 * @brief Return RNG clock frequency
1005 * @param RNGxSource This parameter can be one of the following values:
1006 * @arg @ref LL_RCC_RNG_CLKSOURCE
1007 * @retval RNG clock frequency (in Hz)
1008 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1009 */
1010 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
1011 {
1012 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1013 LL_PLL_ClocksTypeDef PLL_Clocks;
1014
1015 switch (LL_RCC_GetRNGClockSource(RNGxSource))
1016 {
1017 case LL_RCC_RNG_CLKSOURCE_PLL1Q:
1018 if (LL_RCC_PLL1_IsReady() != 0U)
1019 {
1020 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1021 rng_frequency = PLL_Clocks.PLL_Q_Frequency;
1022 }
1023 break;
1024
1025 case LL_RCC_RNG_CLKSOURCE_HSI48:
1026 if (LL_RCC_HSI48_IsReady() != 0U)
1027 {
1028 rng_frequency = 48000000U;
1029 }
1030 break;
1031
1032 case LL_RCC_RNG_CLKSOURCE_LSE:
1033 if (LL_RCC_LSE_IsReady() != 0U)
1034 {
1035 rng_frequency = LSE_VALUE;
1036 }
1037 break;
1038
1039 case LL_RCC_RNG_CLKSOURCE_LSI:
1040 if (LL_RCC_LSI_IsReady() != 0U)
1041 {
1042 rng_frequency = LSI_VALUE;
1043 }
1044 break;
1045
1046 default:
1047 /* Nothing to do */
1048 break;
1049 }
1050
1051 return rng_frequency;
1052 }
1053
1054 /**
1055 * @brief Return CEC clock frequency
1056 * @param CECxSource This parameter can be one of the following values:
1057 * @arg @ref LL_RCC_RNG_CLKSOURCE
1058 * @retval CEC clock frequency (in Hz)
1059 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1060 */
1061 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
1062 {
1063 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1064
1065 switch (LL_RCC_GetCECClockSource(CECxSource))
1066 {
1067 case LL_RCC_CEC_CLKSOURCE_LSE:
1068 if (LL_RCC_LSE_IsReady() != 0U)
1069 {
1070 cec_frequency = LSE_VALUE;
1071 }
1072 break;
1073
1074 case LL_RCC_CEC_CLKSOURCE_LSI:
1075 if (LL_RCC_LSI_IsReady() != 0U)
1076 {
1077 cec_frequency = LSI_VALUE;
1078 }
1079 break;
1080
1081 case LL_RCC_CEC_CLKSOURCE_CSI_DIV122:
1082 if (LL_RCC_CSI_IsReady() != 0U)
1083 {
1084 cec_frequency = CSI_VALUE / 122U;
1085 }
1086 break;
1087
1088 default:
1089 /* Kernel clock disabled */
1090 break;
1091 }
1092
1093 return cec_frequency;
1094 }
1095
1096 /**
1097 * @brief Return USB clock frequency
1098 * @param USBxSource This parameter can be one of the following values:
1099 * @arg @ref LL_RCC_USB_CLKSOURCE
1100 * @retval USB clock frequency (in Hz)
1101 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled
1102 */
1103 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
1104 {
1105 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1106 LL_PLL_ClocksTypeDef PLL_Clocks;
1107
1108 switch (LL_RCC_GetUSBClockSource(USBxSource))
1109 {
1110 case LL_RCC_USB_CLKSOURCE_PLL1Q:
1111 if (LL_RCC_PLL1_IsReady() != 0U)
1112 {
1113 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1114 usb_frequency = PLL_Clocks.PLL_Q_Frequency;
1115 }
1116 break;
1117
1118 case LL_RCC_USB_CLKSOURCE_PLL3Q:
1119 if (LL_RCC_PLL3_IsReady() != 0U)
1120 {
1121 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1122 usb_frequency = PLL_Clocks.PLL_Q_Frequency;
1123 }
1124 break;
1125
1126 case LL_RCC_USB_CLKSOURCE_HSI48:
1127 if (LL_RCC_HSI48_IsReady() != 0U)
1128 {
1129 usb_frequency = HSI48_VALUE;
1130 }
1131 break;
1132
1133 case LL_RCC_USB_CLKSOURCE_DISABLE:
1134 default:
1135 /* Nothing to do */
1136 break;
1137 }
1138
1139 return usb_frequency;
1140 }
1141
1142 /**
1143 * @brief Return DFSDM clock frequency
1144 * @param DFSDMxSource This parameter can be one of the following values:
1145 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
1146 * @retval DFSDM clock frequency (in Hz)
1147 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1148 */
1149 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
1150 {
1151 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1152
1153 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
1154 {
1155 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK:
1156 dfsdm_frequency = RCC_GetSystemClockFreq();
1157 break;
1158
1159 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2:
1160 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
1161 break;
1162
1163 default:
1164 /* Nothing to do */
1165 break;
1166 }
1167
1168 return dfsdm_frequency;
1169 }
1170
1171 #if defined(DFSDM2_BASE)
1172 /**
1173 * @brief Return DFSDM clock frequency
1174 * @param DFSDMxSource This parameter can be one of the following values:
1175 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE
1176 * @retval DFSDM clock frequency (in Hz)
1177 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1178 */
1179 uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource)
1180 {
1181 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1182
1183
1184 switch (LL_RCC_GetDFSDM2ClockSource(DFSDMxSource))
1185 {
1186
1187 case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK:
1188 dfsdm_frequency = RCC_GetSystemClockFreq();
1189 break;
1190
1191 case LL_RCC_DFSDM2_CLKSOURCE_PCLK4:
1192 dfsdm_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
1193 break;
1194
1195 default:
1196 /* Nothing to do */
1197 break;
1198 }
1199
1200 return dfsdm_frequency;
1201 }
1202 #endif /* DFSDM2_BASE */
1203
1204 #if defined(DSI)
1205 /**
1206 * @brief Return DSI clock frequency
1207 * @param DSIxSource This parameter can be one of the following values:
1208 * @arg @ref LL_RCC_DSI_CLKSOURCE
1209 * @retval DSI clock frequency (in Hz)
1210 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1211 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
1212 */
1213 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
1214 {
1215 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1216 LL_PLL_ClocksTypeDef PLL_Clocks;
1217
1218 switch (LL_RCC_GetDSIClockSource(DSIxSource))
1219 {
1220 case LL_RCC_DSI_CLKSOURCE_PLL2Q:
1221 if (LL_RCC_PLL2_IsReady() != 0U)
1222 {
1223 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1224 dsi_frequency = PLL_Clocks.PLL_Q_Frequency;
1225 }
1226 break;
1227
1228 case LL_RCC_DSI_CLKSOURCE_PHY:
1229 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1230 break;
1231
1232 default:
1233 /* Nothing to do */
1234 break;
1235 }
1236
1237 return dsi_frequency;
1238 }
1239 #endif /* DSI */
1240
1241 /**
1242 * @brief Return SPDIF clock frequency
1243 * @param SPDIFxSource This parameter can be one of the following values:
1244 * @arg @ref LL_RCC_SPDIF_CLKSOURCE
1245 * @retval SPDIF clock frequency (in Hz)
1246 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1247 */
1248 uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource)
1249 {
1250 uint32_t spdif_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1251 LL_PLL_ClocksTypeDef PLL_Clocks;
1252
1253 switch (LL_RCC_GetSPDIFClockSource(SPDIFxSource))
1254 {
1255 case LL_RCC_SPDIF_CLKSOURCE_PLL1Q:
1256 if (LL_RCC_PLL1_IsReady() != 0U)
1257 {
1258 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1259 spdif_frequency = PLL_Clocks.PLL_Q_Frequency;
1260 }
1261 break;
1262
1263 case LL_RCC_SPDIF_CLKSOURCE_PLL2R:
1264 if (LL_RCC_PLL2_IsReady() != 0U)
1265 {
1266 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1267 spdif_frequency = PLL_Clocks.PLL_R_Frequency;
1268 }
1269 break;
1270
1271 case LL_RCC_SPDIF_CLKSOURCE_PLL3R:
1272 if (LL_RCC_PLL3_IsReady() != 0U)
1273 {
1274 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1275 spdif_frequency = PLL_Clocks.PLL_R_Frequency;
1276 }
1277 break;
1278
1279 case LL_RCC_SPDIF_CLKSOURCE_HSI:
1280 if (LL_RCC_HSI_IsReady() != 0U)
1281 {
1282 spdif_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
1283 }
1284 break;
1285
1286 default:
1287 /* Nothing to do */
1288 break;
1289 }
1290
1291 return spdif_frequency;
1292 }
1293
1294 /**
1295 * @brief Return SPIx clock frequency
1296 * @param SPIxSource This parameter can be one of the following values:
1297 * @arg @ref LL_RCC_SPI123_CLKSOURCE
1298 * @arg @ref LL_RCC_SPI45_CLKSOURCE
1299 * @arg @ref LL_RCC_SPI6_CLKSOURCE
1300 * @retval SPI clock frequency (in Hz)
1301 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1302 */
1303 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
1304 {
1305 uint32_t spi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1306 LL_PLL_ClocksTypeDef PLL_Clocks;
1307
1308 /* Check parameter */
1309 assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource));
1310
1311 switch (LL_RCC_GetSPIClockSource(SPIxSource))
1312 {
1313 case LL_RCC_SPI123_CLKSOURCE_PLL1Q:
1314 if (LL_RCC_PLL1_IsReady() != 0U)
1315 {
1316 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1317 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1318 }
1319 break;
1320
1321 case LL_RCC_SPI123_CLKSOURCE_PLL2P:
1322 if (LL_RCC_PLL2_IsReady() != 0U)
1323 {
1324 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1325 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1326 }
1327 break;
1328
1329 case LL_RCC_SPI123_CLKSOURCE_PLL3P:
1330 if (LL_RCC_PLL3_IsReady() != 0U)
1331 {
1332 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1333 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1334 }
1335 break;
1336
1337 case LL_RCC_SPI123_CLKSOURCE_I2S_CKIN:
1338 #if defined(LL_RCC_SPI6_CLKSOURCE_I2S_CKIN)
1339 case LL_RCC_SPI6_CLKSOURCE_I2S_CKIN:
1340 #endif /* LL_RCC_SPI6_CLKSOURCE_I2S_CKIN */
1341 spi_frequency = EXTERNAL_CLOCK_VALUE;
1342 break;
1343
1344 case LL_RCC_SPI123_CLKSOURCE_CLKP:
1345 spi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1346 break;
1347
1348 case LL_RCC_SPI45_CLKSOURCE_PCLK2:
1349 spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
1350 break;
1351
1352 case LL_RCC_SPI6_CLKSOURCE_PCLK4:
1353 spi_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
1354 break;
1355
1356 case LL_RCC_SPI45_CLKSOURCE_PLL2Q:
1357 case LL_RCC_SPI6_CLKSOURCE_PLL2Q:
1358 if (LL_RCC_PLL2_IsReady() != 0U)
1359 {
1360 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1361 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1362 }
1363 break;
1364
1365 case LL_RCC_SPI45_CLKSOURCE_PLL3Q:
1366 case LL_RCC_SPI6_CLKSOURCE_PLL3Q:
1367 if (LL_RCC_PLL3_IsReady() != 0U)
1368 {
1369 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1370 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1371 }
1372 break;
1373
1374 case LL_RCC_SPI45_CLKSOURCE_HSI:
1375 case LL_RCC_SPI6_CLKSOURCE_HSI:
1376 if (LL_RCC_HSI_IsReady() != 0U)
1377 {
1378 spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
1379 }
1380 break;
1381
1382 case LL_RCC_SPI45_CLKSOURCE_CSI:
1383 case LL_RCC_SPI6_CLKSOURCE_CSI:
1384 if (LL_RCC_CSI_IsReady() != 0U)
1385 {
1386 spi_frequency = CSI_VALUE;
1387 }
1388 break;
1389
1390 case LL_RCC_SPI45_CLKSOURCE_HSE:
1391 case LL_RCC_SPI6_CLKSOURCE_HSE:
1392 if (LL_RCC_HSE_IsReady() != 0U)
1393 {
1394 spi_frequency = HSE_VALUE;
1395 }
1396 break;
1397
1398 default:
1399 /* Kernel clock disabled */
1400 break;
1401 }
1402
1403 return spi_frequency;
1404 }
1405
1406 /**
1407 * @brief Return SWP clock frequency
1408 * @param SWPxSource This parameter can be one of the following values:
1409 * @arg @ref LL_RCC_SWP_CLKSOURCE
1410 * @retval SWP clock frequency (in Hz)
1411 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1412 */
1413 uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource)
1414 {
1415 uint32_t swp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1416
1417 switch (LL_RCC_GetSWPClockSource(SWPxSource))
1418 {
1419 case LL_RCC_SWP_CLKSOURCE_PCLK1:
1420 swp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
1421 break;
1422
1423 case LL_RCC_SWP_CLKSOURCE_HSI:
1424 if (LL_RCC_HSI_IsReady() != 0U)
1425 {
1426 swp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
1427 }
1428 break;
1429
1430 default:
1431 /* Nothing to do */
1432 break;
1433 }
1434
1435 return swp_frequency;
1436 }
1437
1438 /**
1439 * @brief Return FDCAN clock frequency
1440 * @param FDCANxSource This parameter can be one of the following values:
1441 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
1442 * @retval FDCAN clock frequency (in Hz)
1443 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1444 */
1445 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
1446 {
1447 uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1448 LL_PLL_ClocksTypeDef PLL_Clocks;
1449
1450 switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
1451 {
1452 case LL_RCC_FDCAN_CLKSOURCE_HSE:
1453 if (LL_RCC_HSE_IsReady() != 0U)
1454 {
1455 fdcan_frequency = HSE_VALUE;
1456 }
1457 break;
1458
1459 case LL_RCC_FDCAN_CLKSOURCE_PLL1Q:
1460 if (LL_RCC_PLL1_IsReady() != 0U)
1461 {
1462 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1463 fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
1464 }
1465 break;
1466
1467 case LL_RCC_FDCAN_CLKSOURCE_PLL2Q:
1468 if (LL_RCC_PLL2_IsReady() != 0U)
1469 {
1470 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1471 fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
1472 }
1473 break;
1474
1475 default:
1476 /* Kernel clock disabled */
1477 break;
1478 }
1479
1480 return fdcan_frequency;
1481 }
1482
1483 /**
1484 * @brief Return FMC clock frequency
1485 * @param FMCxSource This parameter can be one of the following values:
1486 * @arg @ref LL_RCC_FMC_CLKSOURCE
1487 * @retval FMC clock frequency (in Hz)
1488 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1489 */
1490 uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource)
1491 {
1492 uint32_t fmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1493 LL_PLL_ClocksTypeDef PLL_Clocks;
1494
1495 switch (LL_RCC_GetFMCClockSource(FMCxSource))
1496 {
1497 case LL_RCC_FMC_CLKSOURCE_HCLK:
1498 fmc_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
1499 break;
1500
1501 case LL_RCC_FMC_CLKSOURCE_PLL1Q:
1502 if (LL_RCC_PLL1_IsReady() != 0U)
1503 {
1504 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1505 fmc_frequency = PLL_Clocks.PLL_Q_Frequency;
1506 }
1507 break;
1508
1509 case LL_RCC_FMC_CLKSOURCE_PLL2R:
1510 if (LL_RCC_PLL2_IsReady() != 0U)
1511 {
1512 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1513 fmc_frequency = PLL_Clocks.PLL_R_Frequency;
1514 }
1515 break;
1516
1517 case LL_RCC_FMC_CLKSOURCE_CLKP:
1518 fmc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1519 break;
1520
1521 default:
1522 /* Nothing to do */
1523 break;
1524 }
1525
1526 return fmc_frequency;
1527 }
1528
1529 #if defined(QUADSPI)
1530 /**
1531 * @brief Return QSPI clock frequency
1532 * @param QSPIxSource This parameter can be one of the following values:
1533 * @arg @ref LL_RCC_QSPI_CLKSOURCE
1534 * @retval QSPI clock frequency (in Hz)
1535 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1536 */
1537 uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource)
1538 {
1539 uint32_t qspi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1540 LL_PLL_ClocksTypeDef PLL_Clocks;
1541
1542 switch (LL_RCC_GetQSPIClockSource(QSPIxSource))
1543 {
1544 case LL_RCC_QSPI_CLKSOURCE_HCLK:
1545 qspi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
1546 break;
1547
1548 case LL_RCC_QSPI_CLKSOURCE_PLL1Q:
1549 if (LL_RCC_PLL1_IsReady() != 0U)
1550 {
1551 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1552 qspi_frequency = PLL_Clocks.PLL_Q_Frequency;
1553 }
1554 break;
1555
1556 case LL_RCC_QSPI_CLKSOURCE_PLL2R:
1557 if (LL_RCC_PLL2_IsReady() != 0U)
1558 {
1559 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1560 qspi_frequency = PLL_Clocks.PLL_R_Frequency;
1561 }
1562 break;
1563
1564 case LL_RCC_QSPI_CLKSOURCE_CLKP:
1565 qspi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1566 break;
1567
1568 default:
1569 /* Nothing to do */
1570 break;
1571 }
1572
1573 return qspi_frequency;
1574 }
1575 #endif /* QUADSPI */
1576
1577 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1578 /**
1579 * @brief Return OSPI clock frequency
1580 * @param OSPIxSource This parameter can be one of the following values:
1581 * @arg @ref LL_RCC_OSPI_CLKSOURCE
1582 * @retval OSPI clock frequency (in Hz)
1583 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1584 */
1585
1586 uint32_t LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource)
1587 {
1588 uint32_t ospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1589 LL_PLL_ClocksTypeDef PLL_Clocks;
1590
1591 switch (LL_RCC_GetOSPIClockSource(OSPIxSource))
1592 {
1593 case LL_RCC_OSPI_CLKSOURCE_HCLK:
1594 ospi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
1595 break;
1596
1597 case LL_RCC_OSPI_CLKSOURCE_PLL1Q:
1598 if (LL_RCC_PLL1_IsReady() != 0U)
1599 {
1600 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1601 ospi_frequency = PLL_Clocks.PLL_Q_Frequency;
1602 }
1603 break;
1604
1605 case LL_RCC_OSPI_CLKSOURCE_PLL2R:
1606 if (LL_RCC_PLL2_IsReady() != 0U)
1607 {
1608 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1609 ospi_frequency = PLL_Clocks.PLL_R_Frequency;
1610 }
1611 break;
1612
1613 case LL_RCC_OSPI_CLKSOURCE_CLKP:
1614 ospi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1615 break;
1616
1617 default:
1618 /* Nothing to do */
1619 break;
1620 }
1621
1622 return ospi_frequency;
1623 }
1624 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
1625
1626 /**
1627 * @brief Return CLKP clock frequency
1628 * @param CLKPxSource This parameter can be one of the following values:
1629 * @arg @ref LL_RCC_CLKP_CLKSOURCE
1630 * @retval CLKP clock frequency (in Hz)
1631 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1632 */
1633 uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)
1634 {
1635 uint32_t clkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1636
1637 switch (LL_RCC_GetCLKPClockSource(CLKPxSource))
1638 {
1639 case LL_RCC_CLKP_CLKSOURCE_HSI:
1640 if (LL_RCC_HSI_IsReady() != 0U)
1641 {
1642 clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
1643 }
1644 break;
1645
1646 case LL_RCC_CLKP_CLKSOURCE_CSI:
1647 if (LL_RCC_CSI_IsReady() != 0U)
1648 {
1649 clkp_frequency = CSI_VALUE;
1650 }
1651 break;
1652
1653 case LL_RCC_CLKP_CLKSOURCE_HSE:
1654 if (LL_RCC_HSE_IsReady() != 0U)
1655 {
1656 clkp_frequency = HSE_VALUE;
1657 }
1658 break;
1659
1660 default:
1661 /* CLKP clock disabled */
1662 break;
1663 }
1664
1665 return clkp_frequency;
1666 }
1667
1668 /**
1669 * @}
1670 */
1671
1672 /**
1673 * @}
1674 */
1675
1676 /** @addtogroup RCC_LL_Private_Functions
1677 * @{
1678 */
1679
1680 /**
1681 * @brief Return SYSTEM clock frequency
1682 * @retval SYSTEM clock frequency (in Hz)
1683 */
1684 uint32_t RCC_GetSystemClockFreq(void)
1685 {
1686 uint32_t frequency = 0U;
1687 LL_PLL_ClocksTypeDef PLL_Clocks;
1688
1689 /* Get SYSCLK source -------------------------------------------------------*/
1690 switch (LL_RCC_GetSysClkSource())
1691 {
1692 /* No check on Ready: Won't be selected by hardware if not */
1693 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
1694 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
1695 break;
1696
1697 case LL_RCC_SYS_CLKSOURCE_STATUS_CSI:
1698 frequency = CSI_VALUE;
1699 break;
1700
1701 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
1702 frequency = HSE_VALUE;
1703 break;
1704
1705 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1:
1706 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1707 frequency = PLL_Clocks.PLL_P_Frequency;
1708 break;
1709
1710 default:
1711 /* Nothing to do */
1712 break;
1713 }
1714
1715 return frequency;
1716 }
1717
1718 /**
1719 * @brief Return HCLK clock frequency
1720 * @param SYSCLK_Frequency SYSCLK clock frequency
1721 * @retval HCLK clock frequency (in Hz)
1722 */
1723 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1724 {
1725 /* HCLK clock frequency */
1726 return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1727 }
1728
1729 /**
1730 * @brief Return PCLK1 clock frequency
1731 * @param HCLK_Frequency HCLK clock frequency
1732 * @retval PCLK1 clock frequency (in Hz)
1733 */
1734 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1735 {
1736 /* PCLK1 clock frequency */
1737 return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1738 }
1739
1740 /**
1741 * @brief Return PCLK2 clock frequency
1742 * @param HCLK_Frequency HCLK clock frequency
1743 * @retval PCLK2 clock frequency (in Hz)
1744 */
1745 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1746 {
1747 /* PCLK2 clock frequency */
1748 return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1749 }
1750
1751 /**
1752 * @brief Return PCLK3 clock frequency
1753 * @param HCLK_Frequency HCLK clock frequency
1754 * @retval PCLK3 clock frequency (in Hz)
1755 */
1756 uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)
1757 {
1758 /* PCLK3 clock frequency */
1759 return LL_RCC_CALC_PCLK3_FREQ(HCLK_Frequency, LL_RCC_GetAPB3Prescaler());
1760 }
1761
1762 /**
1763 * @brief Return PCLK4 clock frequency
1764 * @param HCLK_Frequency HCLK clock frequency
1765 * @retval PCLK4 clock frequency (in Hz)
1766 */
1767 uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)
1768 {
1769 /* PCLK4 clock frequency */
1770 return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler());
1771 }
1772
1773 /**
1774 * @}
1775 */
1776
1777 /**
1778 * @}
1779 */
1780
1781 #endif /* defined(RCC) */
1782
1783 /**
1784 * @}
1785 */
1786
1787 #endif /* USE_FULL_LL_DRIVER */
1788
1789 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/