lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32h7xx_ll_tim.c
   4   * @author  MCD Application Team
   5   * @brief   TIM LL module driver.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19 #if defined(USE_FULL_LL_DRIVER)
  20
  21 /* Includes ------------------------------------------------------------------*/
  22 #include "stm32h7xx_ll_tim.h"
  23 #include "stm32h7xx_ll_bus.h"
  24
  25 /** @addtogroup STM32H7xx_LL_Driver
  26   * @{
  27   */
  28
  29 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM23) || defined (TIM24)
  30
  31 /** @addtogroup TIM_LL
  32   * @{
  33   */
  34
  35 /* Private types -------------------------------------------------------------*/
  36 /* Private variables ---------------------------------------------------------*/
  37 /* Private constants ---------------------------------------------------------*/
  38 /* Private macros ------------------------------------------------------------*/
  39 /** @addtogroup TIM_LL_Private_Macros
  40   * @{
  41   */
  42 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
  43                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
  44                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
  45                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
  46                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
  47
  48 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
  49                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
  50                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
  51
  52 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
  53                                      || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
  54                                      || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
  55                                      || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
  56                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
  57                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
  58                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
  59                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
  60                                      || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
  61                                      || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
  62                                      || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
  63                                      || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
  64                                      || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
  65                                      || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
  66
  67 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
  68                                       || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
  69
  70 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
  71                                          || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
  72
  73 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
  74                                           || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
  75
  76 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
  77                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
  78                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
  79
  80 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
  81                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
  82                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
  83                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
  84
  85 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
  86                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
  87                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
  88                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
  89                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
  90                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
  91                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
  92                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
  93                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
  94                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
  95                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
  96                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
  97                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
  98                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
  99                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
 100                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
 101
 102 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
 103                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
 104                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
 105
 106 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
 107                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
 108                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
 109
 110 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
 111                                                   || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
 112
 113 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
 114                                          || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
 115
 116 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
 117                                          || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
 118
 119 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
 120                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
 121                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
 122                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
 123
 124 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
 125                                           || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
 126
 127 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
 128                                              || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
 129
 130 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
 131                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
 132                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
 133                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
 134                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
 135                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
 136                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
 137                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
 138                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
 139                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
 140                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
 141                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
 142                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
 143                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
 144                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
 145                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
 146
 147 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
 148                                            || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
 149
 150 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
 151                                               || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
 152
 153 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
 154                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
 155                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
 156                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
 157                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
 158                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
 159                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
 160                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
 161                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
 162                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
 163                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
 164                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
 165                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
 166                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
 167                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
 168                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
 169
 170 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
 171                                                      || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
 172 /**
 173   * @}
 174   */
 175
 176
 177 /* Private function prototypes -----------------------------------------------*/
 178 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
 179   * @{
 180   */
 181 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 182 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 183 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 184 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 185 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 186 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 187 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 188 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 189 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 190 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 191 /**
 192   * @}
 193   */
 194
 195 /* Exported functions --------------------------------------------------------*/
 196 /** @addtogroup TIM_LL_Exported_Functions
 197   * @{
 198   */
 199
 200 /** @addtogroup TIM_LL_EF_Init
 201   * @{
 202   */
 203
 204 /**
 205   * @brief  Set TIMx registers to their reset values.
 206   * @param  TIMx Timer instance
 207   * @retval An ErrorStatus enumeration value:
 208   *          - SUCCESS: TIMx registers are de-initialized
 209   *          - ERROR: invalid TIMx instance
 210   */
 211 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
 212 {
 213   ErrorStatus result = SUCCESS;
 214
 215   /* Check the parameters */
 216   assert_param(IS_TIM_INSTANCE(TIMx));
 217
 218   if (TIMx == TIM1)
 219   {
 220     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
 221     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
 222   }
 223 #if defined(TIM2)
 224   else if (TIMx == TIM2)
 225   {
 226     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
 227     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
 228   }
 229 #endif
 230 #if defined(TIM3)
 231   else if (TIMx == TIM3)
 232   {
 233     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
 234     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
 235   }
 236 #endif
 237 #if defined(TIM4)
 238   else if (TIMx == TIM4)
 239   {
 240     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
 241     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
 242   }
 243 #endif
 244 #if defined(TIM5)
 245   else if (TIMx == TIM5)
 246   {
 247     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
 248     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
 249   }
 250 #endif
 251 #if defined(TIM6)
 252   else if (TIMx == TIM6)
 253   {
 254     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
 255     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
 256   }
 257 #endif
 258 #if defined (TIM7)
 259   else if (TIMx == TIM7)
 260   {
 261     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
 262     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
 263   }
 264 #endif
 265 #if defined(TIM8)
 266   else if (TIMx == TIM8)
 267   {
 268     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
 269     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
 270   }
 271 #endif
 272 #if defined(TIM12)
 273   else if (TIMx == TIM12)
 274   {
 275     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
 276     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
 277   }
 278 #endif
 279 #if defined(TIM13)
 280   else if (TIMx == TIM13)
 281   {
 282     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
 283     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
 284   }
 285 #endif
 286 #if defined(TIM14)
 287   else if (TIMx == TIM14)
 288   {
 289     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
 290     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
 291   }
 292 #endif
 293 #if defined(TIM15)
 294   else if (TIMx == TIM15)
 295   {
 296     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
 297     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
 298   }
 299 #endif
 300 #if defined(TIM16)
 301   else if (TIMx == TIM16)
 302   {
 303     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
 304     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
 305   }
 306 #endif
 307 #if defined(TIM17)
 308   else if (TIMx == TIM17)
 309   {
 310     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
 311     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
 312   }
 313 #endif
 314   else
 315   {
 316     result = ERROR;
 317   }
 318
 319   return result;
 320 }
 321
 322 /**
 323   * @brief  Set the fields of the time base unit configuration data structure
 324   *         to their default values.
 325   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
 326   * @retval None
 327   */
 328 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
 329 {
 330   /* Set the default configuration */
 331   TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
 332   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
 333   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
 334   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
 335   TIM_InitStruct->RepetitionCounter = 0x00000000U;
 336 }
 337
 338 /**
 339   * @brief  Configure the TIMx time base unit.
 340   * @param  TIMx Timer Instance
 341   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
 342   * @retval An ErrorStatus enumeration value:
 343   *          - SUCCESS: TIMx registers are de-initialized
 344   *          - ERROR: not applicable
 345   */
 346 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
 347 {
 348   uint32_t tmpcr1;
 349
 350   /* Check the parameters */
 351   assert_param(IS_TIM_INSTANCE(TIMx));
 352   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
 353   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
 354
 355   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
 356
 357   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 358   {
 359     /* Select the Counter Mode */
 360     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
 361   }
 362
 363   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 364   {
 365     /* Set the clock division */
 366     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
 367   }
 368
 369   /* Write to TIMx CR1 */
 370   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
 371
 372   /* Set the Autoreload value */
 373   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
 374
 375   /* Set the Prescaler value */
 376   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
 377
 378   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 379   {
 380     /* Set the Repetition Counter value */
 381     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
 382   }
 383
 384   /* Generate an update event to reload the Prescaler
 385      and the repetition counter value (if applicable) immediately */
 386   LL_TIM_GenerateEvent_UPDATE(TIMx);
 387
 388   return SUCCESS;
 389 }
 390
 391 /**
 392   * @brief  Set the fields of the TIMx output channel configuration data
 393   *         structure to their default values.
 394   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
 395   * @retval None
 396   */
 397 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
 398 {
 399   /* Set the default configuration */
 400   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
 401   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
 402   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
 403   TIM_OC_InitStruct->CompareValue = 0x00000000U;
 404   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
 405   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
 406   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
 407   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
 408 }
 409
 410 /**
 411   * @brief  Configure the TIMx output channel.
 412   * @param  TIMx Timer Instance
 413   * @param  Channel This parameter can be one of the following values:
 414   *         @arg @ref LL_TIM_CHANNEL_CH1
 415   *         @arg @ref LL_TIM_CHANNEL_CH2
 416   *         @arg @ref LL_TIM_CHANNEL_CH3
 417   *         @arg @ref LL_TIM_CHANNEL_CH4
 418   *         @arg @ref LL_TIM_CHANNEL_CH5
 419   *         @arg @ref LL_TIM_CHANNEL_CH6
 420   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
 421   * @retval An ErrorStatus enumeration value:
 422   *          - SUCCESS: TIMx output channel is initialized
 423   *          - ERROR: TIMx output channel is not initialized
 424   */
 425 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
 426 {
 427   ErrorStatus result = ERROR;
 428
 429   switch (Channel)
 430   {
 431     case LL_TIM_CHANNEL_CH1:
 432       result = OC1Config(TIMx, TIM_OC_InitStruct);
 433       break;
 434     case LL_TIM_CHANNEL_CH2:
 435       result = OC2Config(TIMx, TIM_OC_InitStruct);
 436       break;
 437     case LL_TIM_CHANNEL_CH3:
 438       result = OC3Config(TIMx, TIM_OC_InitStruct);
 439       break;
 440     case LL_TIM_CHANNEL_CH4:
 441       result = OC4Config(TIMx, TIM_OC_InitStruct);
 442       break;
 443     case LL_TIM_CHANNEL_CH5:
 444       result = OC5Config(TIMx, TIM_OC_InitStruct);
 445       break;
 446     case LL_TIM_CHANNEL_CH6:
 447       result = OC6Config(TIMx, TIM_OC_InitStruct);
 448       break;
 449     default:
 450       break;
 451   }
 452
 453   return result;
 454 }
 455
 456 /**
 457   * @brief  Set the fields of the TIMx input channel configuration data
 458   *         structure to their default values.
 459   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
 460   * @retval None
 461   */
 462 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
 463 {
 464   /* Set the default configuration */
 465   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
 466   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 467   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
 468   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
 469 }
 470
 471 /**
 472   * @brief  Configure the TIMx input channel.
 473   * @param  TIMx Timer Instance
 474   * @param  Channel This parameter can be one of the following values:
 475   *         @arg @ref LL_TIM_CHANNEL_CH1
 476   *         @arg @ref LL_TIM_CHANNEL_CH2
 477   *         @arg @ref LL_TIM_CHANNEL_CH3
 478   *         @arg @ref LL_TIM_CHANNEL_CH4
 479   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
 480   * @retval An ErrorStatus enumeration value:
 481   *          - SUCCESS: TIMx output channel is initialized
 482   *          - ERROR: TIMx output channel is not initialized
 483   */
 484 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
 485 {
 486   ErrorStatus result = ERROR;
 487
 488   switch (Channel)
 489   {
 490     case LL_TIM_CHANNEL_CH1:
 491       result = IC1Config(TIMx, TIM_IC_InitStruct);
 492       break;
 493     case LL_TIM_CHANNEL_CH2:
 494       result = IC2Config(TIMx, TIM_IC_InitStruct);
 495       break;
 496     case LL_TIM_CHANNEL_CH3:
 497       result = IC3Config(TIMx, TIM_IC_InitStruct);
 498       break;
 499     case LL_TIM_CHANNEL_CH4:
 500       result = IC4Config(TIMx, TIM_IC_InitStruct);
 501       break;
 502     default:
 503       break;
 504   }
 505
 506   return result;
 507 }
 508
 509 /**
 510   * @brief  Fills each TIM_EncoderInitStruct field with its default value
 511   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
 512   * @retval None
 513   */
 514 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
 515 {
 516   /* Set the default configuration */
 517   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
 518   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
 519   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 520   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
 521   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
 522   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
 523   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 524   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
 525   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
 526 }
 527
 528 /**
 529   * @brief  Configure the encoder interface of the timer instance.
 530   * @param  TIMx Timer Instance
 531   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
 532   * @retval An ErrorStatus enumeration value:
 533   *          - SUCCESS: TIMx registers are de-initialized
 534   *          - ERROR: not applicable
 535   */
 536 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
 537 {
 538   uint32_t tmpccmr1;
 539   uint32_t tmpccer;
 540
 541   /* Check the parameters */
 542   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
 543   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
 544   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
 545   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
 546   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
 547   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
 548   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
 549   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
 550   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
 551   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
 552
 553   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
 554   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
 555
 556   /* Get the TIMx CCMR1 register value */
 557   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 558
 559   /* Get the TIMx CCER register value */
 560   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 561
 562   /* Configure TI1 */
 563   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
 564   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
 565   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
 566   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
 567
 568   /* Configure TI2 */
 569   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
 570   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
 571   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
 572   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
 573
 574   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
 575   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
 576   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
 577   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
 578   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
 579
 580   /* Set encoder mode */
 581   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
 582
 583   /* Write to TIMx CCMR1 */
 584   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 585
 586   /* Write to TIMx CCER */
 587   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 588
 589   return SUCCESS;
 590 }
 591
 592 /**
 593   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
 594   *         structure to their default values.
 595   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
 596   * @retval None
 597   */
 598 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
 599 {
 600   /* Set the default configuration */
 601   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
 602   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
 603   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
 604   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
 605 }
 606
 607 /**
 608   * @brief  Configure the Hall sensor interface of the timer instance.
 609   * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
 610   *       to the TI1 input channel
 611   * @note TIMx slave mode controller is configured in reset mode.
 612           Selected internal trigger is TI1F_ED.
 613   * @note Channel 1 is configured as input, IC1 is mapped on TRC.
 614   * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
 615   *       between 2 changes on the inputs. It gives information about motor speed.
 616   * @note Channel 2 is configured in output PWM 2 mode.
 617   * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
 618   * @note OC2REF is selected as trigger output on TRGO.
 619   * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
 620   *       when TIMx operates in Hall sensor interface mode.
 621   * @param  TIMx Timer Instance
 622   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
 623   * @retval An ErrorStatus enumeration value:
 624   *          - SUCCESS: TIMx registers are de-initialized
 625   *          - ERROR: not applicable
 626   */
 627 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
 628 {
 629   uint32_t tmpcr2;
 630   uint32_t tmpccmr1;
 631   uint32_t tmpccer;
 632   uint32_t tmpsmcr;
 633
 634   /* Check the parameters */
 635   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
 636   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
 637   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
 638   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
 639
 640   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
 641   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
 642
 643   /* Get the TIMx CR2 register value */
 644   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 645
 646   /* Get the TIMx CCMR1 register value */
 647   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 648
 649   /* Get the TIMx CCER register value */
 650   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 651
 652   /* Get the TIMx SMCR register value */
 653   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
 654
 655   /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
 656   tmpcr2 |= TIM_CR2_TI1S;
 657
 658   /* OC2REF signal is used as trigger output (TRGO) */
 659   tmpcr2 |= LL_TIM_TRGO_OC2REF;
 660
 661   /* Configure the slave mode controller */
 662   tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
 663   tmpsmcr |= LL_TIM_TS_TI1F_ED;
 664   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
 665
 666   /* Configure input channel 1 */
 667   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
 668   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
 669   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
 670   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
 671
 672   /* Configure input channel 2 */
 673   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
 674   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
 675
 676   /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
 677   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
 678   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
 679   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
 680
 681   /* Write to TIMx CR2 */
 682   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 683
 684   /* Write to TIMx SMCR */
 685   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
 686
 687   /* Write to TIMx CCMR1 */
 688   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 689
 690   /* Write to TIMx CCER */
 691   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 692
 693   /* Write to TIMx CCR2 */
 694   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
 695
 696   return SUCCESS;
 697 }
 698
 699 /**
 700   * @brief  Set the fields of the Break and Dead Time configuration data structure
 701   *         to their default values.
 702   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
 703   * @retval None
 704   */
 705 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
 706 {
 707   /* Set the default configuration */
 708   TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
 709   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
 710   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
 711   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
 712   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
 713   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
 714   TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
 715   TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
 716   TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
 717   TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
 718   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
 719 }
 720
 721 /**
 722   * @brief  Configure the Break and Dead Time feature of the timer instance.
 723   * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
 724   *  and DTG[7:0] can be write-locked depending on the LOCK configuration, it
 725   *  can be necessary to configure all of them during the first write access to
 726   *  the TIMx_BDTR register.
 727   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
 728   *       a timer instance provides a break input.
 729   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
 730   *       a timer instance provides a second break input.
 731   * @param  TIMx Timer Instance
 732   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
 733   * @retval An ErrorStatus enumeration value:
 734   *          - SUCCESS: Break and Dead Time is initialized
 735   *          - ERROR: not applicable
 736   */
 737 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
 738 {
 739   uint32_t tmpbdtr = 0;
 740
 741   /* Check the parameters */
 742   assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
 743   assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
 744   assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
 745   assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
 746   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
 747   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
 748   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
 749
 750   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
 751   the OSSI State, the dead time value and the Automatic Output Enable Bit */
 752
 753   /* Set the BDTR bits */
 754   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
 755   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
 756   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
 757   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
 758   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
 759   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
 760   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
 761   MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
 762   if (IS_TIM_ADVANCED_INSTANCE(TIMx))
 763   {
 764     assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
 765     MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
 766   }
 767
 768   if (IS_TIM_BKIN2_INSTANCE(TIMx))
 769   {
 770     assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
 771     assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
 772     assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
 773
 774     /* Set the BREAK2 input related BDTR bit-fields */
 775     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
 776     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
 777     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
 778   }
 779
 780   /* Set TIMx_BDTR */
 781   LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
 782
 783   return SUCCESS;
 784 }
 785 /**
 786   * @}
 787   */
 788
 789 /**
 790   * @}
 791   */
 792
 793 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
 794   *  @brief   Private functions
 795   * @{
 796   */
 797 /**
 798   * @brief  Configure the TIMx output channel 1.
 799   * @param  TIMx Timer Instance
 800   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
 801   * @retval An ErrorStatus enumeration value:
 802   *          - SUCCESS: TIMx registers are de-initialized
 803   *          - ERROR: not applicable
 804   */
 805 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 806 {
 807   uint32_t tmpccmr1;
 808   uint32_t tmpccer;
 809   uint32_t tmpcr2;
 810
 811   /* Check the parameters */
 812   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
 813   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 814   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 815   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 816   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 817   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 818
 819   /* Disable the Channel 1: Reset the CC1E Bit */
 820   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
 821
 822   /* Get the TIMx CCER register value */
 823   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 824
 825   /* Get the TIMx CR2 register value */
 826   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 827
 828   /* Get the TIMx CCMR1 register value */
 829   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 830
 831   /* Reset Capture/Compare selection Bits */
 832   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
 833
 834   /* Set the Output Compare Mode */
 835   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
 836
 837   /* Set the Output Compare Polarity */
 838   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
 839
 840   /* Set the Output State */
 841   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
 842
 843   if (IS_TIM_BREAK_INSTANCE(TIMx))
 844   {
 845     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 846     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
 847
 848     /* Set the complementary output Polarity */
 849     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
 850
 851     /* Set the complementary output State */
 852     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
 853
 854     /* Set the Output Idle state */
 855     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
 856
 857     /* Set the complementary output Idle state */
 858     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
 859   }
 860
 861   /* Write to TIMx CR2 */
 862   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 863
 864   /* Write to TIMx CCMR1 */
 865   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 866
 867   /* Set the Capture Compare Register value */
 868   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
 869
 870   /* Write to TIMx CCER */
 871   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 872
 873   return SUCCESS;
 874 }
 875
 876 /**
 877   * @brief  Configure the TIMx output channel 2.
 878   * @param  TIMx Timer Instance
 879   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
 880   * @retval An ErrorStatus enumeration value:
 881   *          - SUCCESS: TIMx registers are de-initialized
 882   *          - ERROR: not applicable
 883   */
 884 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 885 {
 886   uint32_t tmpccmr1;
 887   uint32_t tmpccer;
 888   uint32_t tmpcr2;
 889
 890   /* Check the parameters */
 891   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
 892   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 893   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 894   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 895   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 896   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 897
 898   /* Disable the Channel 2: Reset the CC2E Bit */
 899   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
 900
 901   /* Get the TIMx CCER register value */
 902   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
 903
 904   /* Get the TIMx CR2 register value */
 905   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 906
 907   /* Get the TIMx CCMR1 register value */
 908   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 909
 910   /* Reset Capture/Compare selection Bits */
 911   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
 912
 913   /* Select the Output Compare Mode */
 914   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
 915
 916   /* Set the Output Compare Polarity */
 917   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
 918
 919   /* Set the Output State */
 920   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
 921
 922   if (IS_TIM_BREAK_INSTANCE(TIMx))
 923   {
 924     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 925     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
 926
 927     /* Set the complementary output Polarity */
 928     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
 929
 930     /* Set the complementary output State */
 931     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
 932
 933     /* Set the Output Idle state */
 934     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
 935
 936     /* Set the complementary output Idle state */
 937     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
 938   }
 939
 940   /* Write to TIMx CR2 */
 941   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 942
 943   /* Write to TIMx CCMR1 */
 944   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 945
 946   /* Set the Capture Compare Register value */
 947   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
 948
 949   /* Write to TIMx CCER */
 950   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 951
 952   return SUCCESS;
 953 }
 954
 955 /**
 956   * @brief  Configure the TIMx output channel 3.
 957   * @param  TIMx Timer Instance
 958   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
 959   * @retval An ErrorStatus enumeration value:
 960   *          - SUCCESS: TIMx registers are de-initialized
 961   *          - ERROR: not applicable
 962   */
 963 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 964 {
 965   uint32_t tmpccmr2;
 966   uint32_t tmpccer;
 967   uint32_t tmpcr2;
 968
 969   /* Check the parameters */
 970   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
 971   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 972   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 973   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 974   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 975   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 976
 977   /* Disable the Channel 3: Reset the CC3E Bit */
 978   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
 979
 980   /* Get the TIMx CCER register value */
 981   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
 982
 983   /* Get the TIMx CR2 register value */
 984   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 985
 986   /* Get the TIMx CCMR2 register value */
 987   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
 988
 989   /* Reset Capture/Compare selection Bits */
 990   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
 991
 992   /* Select the Output Compare Mode */
 993   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
 994
 995   /* Set the Output Compare Polarity */
 996   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
 997
 998   /* Set the Output State */
 999   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
1000
1001   if (IS_TIM_BREAK_INSTANCE(TIMx))
1002   {
1003     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1004     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1005
1006     /* Set the complementary output Polarity */
1007     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1008
1009     /* Set the complementary output State */
1010     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1011
1012     /* Set the Output Idle state */
1013     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1014
1015     /* Set the complementary output Idle state */
1016     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1017   }
1018
1019   /* Write to TIMx CR2 */
1020   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1021
1022   /* Write to TIMx CCMR2 */
1023   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1024
1025   /* Set the Capture Compare Register value */
1026   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1027
1028   /* Write to TIMx CCER */
1029   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1030
1031   return SUCCESS;
1032 }
1033
1034 /**
1035   * @brief  Configure the TIMx output channel 4.
1036   * @param  TIMx Timer Instance
1037   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1038   * @retval An ErrorStatus enumeration value:
1039   *          - SUCCESS: TIMx registers are de-initialized
1040   *          - ERROR: not applicable
1041   */
1042 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1043 {
1044   uint32_t tmpccmr2;
1045   uint32_t tmpccer;
1046   uint32_t tmpcr2;
1047
1048   /* Check the parameters */
1049   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1050   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1051   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1052   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1053   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1054   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1055
1056   /* Disable the Channel 4: Reset the CC4E Bit */
1057   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1058
1059   /* Get the TIMx CCER register value */
1060   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1061
1062   /* Get the TIMx CR2 register value */
1063   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
1064
1065   /* Get the TIMx CCMR2 register value */
1066   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1067
1068   /* Reset Capture/Compare selection Bits */
1069   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1070
1071   /* Select the Output Compare Mode */
1072   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1073
1074   /* Set the Output Compare Polarity */
1075   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1076
1077   /* Set the Output State */
1078   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1079
1080   if (IS_TIM_BREAK_INSTANCE(TIMx))
1081   {
1082     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1083     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1084
1085     /* Set the Output Idle state */
1086     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1087   }
1088
1089   /* Write to TIMx CR2 */
1090   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1091
1092   /* Write to TIMx CCMR2 */
1093   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1094
1095   /* Set the Capture Compare Register value */
1096   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1097
1098   /* Write to TIMx CCER */
1099   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1100
1101   return SUCCESS;
1102 }
1103
1104 /**
1105   * @brief  Configure the TIMx output channel 5.
1106   * @param  TIMx Timer Instance
1107   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1108   * @retval An ErrorStatus enumeration value:
1109   *          - SUCCESS: TIMx registers are de-initialized
1110   *          - ERROR: not applicable
1111   */
1112 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1113 {
1114   uint32_t tmpccmr3;
1115   uint32_t tmpccer;
1116
1117   /* Check the parameters */
1118   assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1119   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1120   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1121   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1122   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1123   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1124
1125   /* Disable the Channel 5: Reset the CC5E Bit */
1126   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1127
1128   /* Get the TIMx CCER register value */
1129   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1130
1131   /* Get the TIMx CCMR3 register value */
1132   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1133
1134   /* Select the Output Compare Mode */
1135   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1136
1137   /* Set the Output Compare Polarity */
1138   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1139
1140   /* Set the Output State */
1141   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1142
1143   if (IS_TIM_BREAK_INSTANCE(TIMx))
1144   {
1145     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1146     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1147
1148     /* Set the Output Idle state */
1149     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1150
1151   }
1152
1153   /* Write to TIMx CCMR3 */
1154   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1155
1156   /* Set the Capture Compare Register value */
1157   LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1158
1159   /* Write to TIMx CCER */
1160   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1161
1162   return SUCCESS;
1163 }
1164
1165 /**
1166   * @brief  Configure the TIMx output channel 6.
1167   * @param  TIMx Timer Instance
1168   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1169   * @retval An ErrorStatus enumeration value:
1170   *          - SUCCESS: TIMx registers are de-initialized
1171   *          - ERROR: not applicable
1172   */
1173 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1174 {
1175   uint32_t tmpccmr3;
1176   uint32_t tmpccer;
1177
1178   /* Check the parameters */
1179   assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1180   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1181   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1182   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1183   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1184   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1185
1186   /* Disable the Channel 5: Reset the CC6E Bit */
1187   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1188
1189   /* Get the TIMx CCER register value */
1190   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1191
1192   /* Get the TIMx CCMR3 register value */
1193   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1194
1195   /* Select the Output Compare Mode */
1196   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1197
1198   /* Set the Output Compare Polarity */
1199   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1200
1201   /* Set the Output State */
1202   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1203
1204   if (IS_TIM_BREAK_INSTANCE(TIMx))
1205   {
1206     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1207     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1208
1209     /* Set the Output Idle state */
1210     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1211   }
1212
1213   /* Write to TIMx CCMR3 */
1214   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1215
1216   /* Set the Capture Compare Register value */
1217   LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1218
1219   /* Write to TIMx CCER */
1220   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1221
1222   return SUCCESS;
1223 }
1224
1225 /**
1226   * @brief  Configure the TIMx input channel 1.
1227   * @param  TIMx Timer Instance
1228   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1229   * @retval An ErrorStatus enumeration value:
1230   *          - SUCCESS: TIMx registers are de-initialized
1231   *          - ERROR: not applicable
1232   */
1233 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1234 {
1235   /* Check the parameters */
1236   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1237   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1238   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1239   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1240   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1241
1242   /* Disable the Channel 1: Reset the CC1E Bit */
1243   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1244
1245   /* Select the Input and set the filter and the prescaler value */
1246   MODIFY_REG(TIMx->CCMR1,
1247              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1248              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1249
1250   /* Select the Polarity and set the CC1E Bit */
1251   MODIFY_REG(TIMx->CCER,
1252              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1253              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1254
1255   return SUCCESS;
1256 }
1257
1258 /**
1259   * @brief  Configure the TIMx input channel 2.
1260   * @param  TIMx Timer Instance
1261   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1262   * @retval An ErrorStatus enumeration value:
1263   *          - SUCCESS: TIMx registers are de-initialized
1264   *          - ERROR: not applicable
1265   */
1266 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1267 {
1268   /* Check the parameters */
1269   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1270   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1271   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1272   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1273   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1274
1275   /* Disable the Channel 2: Reset the CC2E Bit */
1276   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1277
1278   /* Select the Input and set the filter and the prescaler value */
1279   MODIFY_REG(TIMx->CCMR1,
1280              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1281              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1282
1283   /* Select the Polarity and set the CC2E Bit */
1284   MODIFY_REG(TIMx->CCER,
1285              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1286              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1287
1288   return SUCCESS;
1289 }
1290
1291 /**
1292   * @brief  Configure the TIMx input channel 3.
1293   * @param  TIMx Timer Instance
1294   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1295   * @retval An ErrorStatus enumeration value:
1296   *          - SUCCESS: TIMx registers are de-initialized
1297   *          - ERROR: not applicable
1298   */
1299 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1300 {
1301   /* Check the parameters */
1302   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1303   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1304   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1305   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1306   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1307
1308   /* Disable the Channel 3: Reset the CC3E Bit */
1309   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1310
1311   /* Select the Input and set the filter and the prescaler value */
1312   MODIFY_REG(TIMx->CCMR2,
1313              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1314              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1315
1316   /* Select the Polarity and set the CC3E Bit */
1317   MODIFY_REG(TIMx->CCER,
1318              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1319              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1320
1321   return SUCCESS;
1322 }
1323
1324 /**
1325   * @brief  Configure the TIMx input channel 4.
1326   * @param  TIMx Timer Instance
1327   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1328   * @retval An ErrorStatus enumeration value:
1329   *          - SUCCESS: TIMx registers are de-initialized
1330   *          - ERROR: not applicable
1331   */
1332 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1333 {
1334   /* Check the parameters */
1335   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1336   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1337   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1338   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1339   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1340
1341   /* Disable the Channel 4: Reset the CC4E Bit */
1342   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1343
1344   /* Select the Input and set the filter and the prescaler value */
1345   MODIFY_REG(TIMx->CCMR2,
1346              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1347              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1348
1349   /* Select the Polarity and set the CC2E Bit */
1350   MODIFY_REG(TIMx->CCER,
1351              (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1352              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1353
1354   return SUCCESS;
1355 }
1356
1357
1358 /**
1359   * @}
1360   */
1361
1362 /**
1363   * @}
1364   */
1365
1366 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17  || TIM23  || TIM24 */
1367
1368 /**
1369   * @}
1370   */
1371
1372 #endif /* USE_FULL_LL_DRIVER */
1373
1374 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/