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[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_ll_usb.c
blob726f4f181f693761f677fb5a09aef6324ce9f97e
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_usb.c
4 * @author MCD Application Team
5 * @brief USB Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the USB Peripheral Controller:
9 * + Initialization/de-initialization functions
10 * + I/O operation functions
11 * + Peripheral Control functions
12 * + Peripheral State functions
13 *
14 @verbatim
15 ==============================================================================
16 ##### How to use this driver #####
17 ==============================================================================
18 [..]
19 (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
20
21 (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
22
23 (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
24
25 @endverbatim
26 ******************************************************************************
27 * @attention
28 *
29 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
30 * All rights reserved.</center></h2>
31 *
32 * This software component is licensed by ST under BSD 3-Clause license,
33 * the "License"; You may not use this file except in compliance with the
34 * License. You may obtain a copy of the License at:
35 * opensource.org/licenses/BSD-3-Clause
36 *
37 ******************************************************************************
38 */
39
40 /* Includes ------------------------------------------------------------------*/
41 #include "stm32h7xx_hal.h"
42
43 /** @addtogroup STM32H7xx_LL_USB_DRIVER
44 * @{
45 */
46
47 #if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
48 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
49 /* Private typedef -----------------------------------------------------------*/
50 /* Private define ------------------------------------------------------------*/
51 /* Private macro -------------------------------------------------------------*/
52
53 /** @defgroup USB_OTG_GRSTCTL_AHBIDL_TIMEOUT_MS AHB master idle timeout
54 * @{
55 */
56 #define USB_OTG_GRSTCTL_AHBIDL_TIMEOUT_MS ((uint32_t)50U)
57
58 /** @defgroup USB_OTG_GRSTCTL_CSRST_TIMEOUT_MS Core soft reset timeout
59 * @{
60 */
61 #define USB_OTG_GRSTCTL_CSRST_TIMEOUT_MS ((uint32_t)10U)
62
63 /** @defgroup USB_OTG_GRSTCTL_TXFFLSH_TIMEOUT_MS Tx FIFO flush timeout
64 * @{
65 */
66 #define USB_OTG_GRSTCTL_TXFFLSH_TIMEOUT_MS ((uint32_t)5U)
67
68 /** @defgroup USB_OTG_GRSTCTL_RXFFLSH_TIMEOUT_MS Rx FIFO flush timeout
69 * @{
70 */
71 #define USB_OTG_GRSTCTL_RXFFLSH_TIMEOUT_MS ((uint32_t)5U)
72
73 /* Private variables ---------------------------------------------------------*/
74 /* Private function prototypes -----------------------------------------------*/
75 /* Private functions ---------------------------------------------------------*/
76 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
77 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
78
79 /* Exported functions --------------------------------------------------------*/
80 /** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions
81 * @{
82 */
83
84 /** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions
85 * @brief Initialization and Configuration functions
86 *
87 @verbatim
88 ===============================================================================
89 ##### Initialization/de-initialization functions #####
90 ===============================================================================
91
92 @endverbatim
93 * @{
94 */
95
96 /**
97 * @brief Initializes the USB Core
98 * @param USBx USB Instance
99 * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
100 * the configuration information for the specified USBx peripheral.
101 * @retval HAL status
102 */
103 HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
104 {
105 HAL_StatusTypeDef ret;
106
107 if (cfg.phy_itface == USB_OTG_ULPI_PHY)
108 {
109 USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
110
111 /* Init The ULPI Interface */
112 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
113
114 /* Select vbus source */
115 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
116 if (cfg.use_external_vbus == 1U)
117 {
118 USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
119 }
120 /* Reset after a PHY select */
121 ret = USB_CoreReset(USBx);
122 }
123 else /* FS interface (embedded Phy) */
124 {
125 /* Select FS Embedded PHY */
126 USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
127
128 /* Reset after a PHY select and set Host mode */
129 ret = USB_CoreReset(USBx);
130
131 if (cfg.battery_charging_enable == 0U)
132 {
133 /* Activate the USB Transceiver */
134 USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
135 }
136 else
137 {
138 /* Deactivate the USB Transceiver */
139 USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
140 }
141 }
142
143 if (cfg.dma_enable == 1U)
144 {
145 USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
146 USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
147 }
148
149 return ret;
150 }
151
152
153 /**
154 * @brief Set the USB turnaround time
155 * @param USBx USB Instance
156 * @param hclk: AHB clock frequency
157 * @retval USB turnaround time In PHY Clocks number
158 */
159 HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
160 uint32_t hclk, uint8_t speed)
161 {
162 uint32_t UsbTrd;
163
164 /* The USBTRD is configured according to the tables below, depending on AHB frequency
165 used by application. In the low AHB frequency range it is used to stretch enough the USB response
166 time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
167 latency to the Data FIFO */
168 if (speed == USBD_FS_SPEED)
169 {
170 if ((hclk >= 14200000U) && (hclk < 15000000U))
171 {
172 /* hclk Clock Range between 14.2-15 MHz */
173 UsbTrd = 0xFU;
174 }
175 else if ((hclk >= 15000000U) && (hclk < 16000000U))
176 {
177 /* hclk Clock Range between 15-16 MHz */
178 UsbTrd = 0xEU;
179 }
180 else if ((hclk >= 16000000U) && (hclk < 17200000U))
181 {
182 /* hclk Clock Range between 16-17.2 MHz */
183 UsbTrd = 0xDU;
184 }
185 else if ((hclk >= 17200000U) && (hclk < 18500000U))
186 {
187 /* hclk Clock Range between 17.2-18.5 MHz */
188 UsbTrd = 0xCU;
189 }
190 else if ((hclk >= 18500000U) && (hclk < 20000000U))
191 {
192 /* hclk Clock Range between 18.5-20 MHz */
193 UsbTrd = 0xBU;
194 }
195 else if ((hclk >= 20000000U) && (hclk < 21800000U))
196 {
197 /* hclk Clock Range between 20-21.8 MHz */
198 UsbTrd = 0xAU;
199 }
200 else if ((hclk >= 21800000U) && (hclk < 24000000U))
201 {
202 /* hclk Clock Range between 21.8-24 MHz */
203 UsbTrd = 0x9U;
204 }
205 else if ((hclk >= 24000000U) && (hclk < 27700000U))
206 {
207 /* hclk Clock Range between 24-27.7 MHz */
208 UsbTrd = 0x8U;
209 }
210 else if ((hclk >= 27700000U) && (hclk < 32000000U))
211 {
212 /* hclk Clock Range between 27.7-32 MHz */
213 UsbTrd = 0x7U;
214 }
215 else /* if(hclk >= 32000000) */
216 {
217 /* hclk Clock Range between 32-200 MHz */
218 UsbTrd = 0x6U;
219 }
220 }
221 else if (speed == USBD_HS_SPEED)
222 {
223 UsbTrd = USBD_HS_TRDT_VALUE;
224 }
225 else
226 {
227 UsbTrd = USBD_DEFAULT_TRDT_VALUE;
228 }
229
230 USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
231 USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
232
233 return HAL_OK;
234 }
235
236 /**
237 * @brief USB_EnableGlobalInt
238 * Enables the controller's Global Int in the AHB Config reg
239 * @param USBx Selected device
240 * @retval HAL status
241 */
242 HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
243 {
244 USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
245 return HAL_OK;
246 }
247
248 /**
249 * @brief USB_DisableGlobalInt
250 * Disable the controller's Global Int in the AHB Config reg
251 * @param USBx Selected device
252 * @retval HAL status
253 */
254 HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
255 {
256 USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
257 return HAL_OK;
258 }
259
260 /**
261 * @brief USB_SetCurrentMode : Set functional mode
262 * @param USBx Selected device
263 * @param mode current core mode
264 * This parameter can be one of these values:
265 * @arg USB_DEVICE_MODE: Peripheral mode
266 * @arg USB_HOST_MODE: Host mode
267 * @arg USB_DRD_MODE: Dual Role Device mode
268 * @retval HAL status
269 */
270 HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
271 {
272 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
273
274 if (mode == USB_HOST_MODE)
275 {
276 USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
277 }
278 else if (mode == USB_DEVICE_MODE)
279 {
280 USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
281 }
282 else
283 {
284 return HAL_ERROR;
285 }
286 HAL_Delay(50U);
287
288 return HAL_OK;
289 }
290
291 /**
292 * @brief USB_DevInit : Initializes the USB_OTG controller registers
293 * for device mode
294 * @param USBx Selected device
295 * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
296 * the configuration information for the specified USBx peripheral.
297 * @retval HAL status
298 */
299 HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
300 {
301 HAL_StatusTypeDef ret = HAL_OK;
302 uint32_t USBx_BASE = (uint32_t)USBx;
303 uint32_t i;
304
305 for (i = 0U; i < 15U; i++)
306 {
307 USBx->DIEPTXF[i] = 0U;
308 }
309
310 /* VBUS Sensing setup */
311 if (cfg.vbus_sensing_enable == 0U)
312 {
313 USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
314
315 /* Deactivate VBUS Sensing B */
316 USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
317
318 /* B-peripheral session valid override enable */
319 USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
320 USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
321 }
322 else
323 {
324 /* Enable HW VBUS sensing */
325 USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
326 }
327
328 /* Restart the Phy Clock */
329 USBx_PCGCCTL = 0U;
330
331 /* Device mode configuration */
332 USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
333
334 if (cfg.phy_itface == USB_OTG_ULPI_PHY)
335 {
336 if (cfg.speed == USBD_HS_SPEED)
337 {
338 /* Set Core speed to High speed mode */
339 (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
340 }
341 else
342 {
343 /* Set Core speed to Full speed mode */
344 (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
345 }
346 }
347 else
348 {
349 /* Set Core speed to Full speed mode */
350 (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
351 }
352
353 /* Flush the FIFOs */
354 if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
355 {
356 ret = HAL_ERROR;
357 }
358
359 if (USB_FlushRxFifo(USBx) != HAL_OK)
360 {
361 ret = HAL_ERROR;
362 }
363
364 /* Clear all pending Device Interrupts */
365 USBx_DEVICE->DIEPMSK = 0U;
366 USBx_DEVICE->DOEPMSK = 0U;
367 USBx_DEVICE->DAINTMSK = 0U;
368
369 for (i = 0U; i < cfg.dev_endpoints; i++)
370 {
371 if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
372 {
373 if (i == 0U)
374 {
375 USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
376 }
377 else
378 {
379 USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
380 }
381 }
382 else
383 {
384 USBx_INEP(i)->DIEPCTL = 0U;
385 }
386
387 USBx_INEP(i)->DIEPTSIZ = 0U;
388 USBx_INEP(i)->DIEPINT = 0xFB7FU;
389 }
390
391 for (i = 0U; i < cfg.dev_endpoints; i++)
392 {
393 if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
394 {
395 if (i == 0U)
396 {
397 USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
398 }
399 else
400 {
401 USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
402 }
403 }
404 else
405 {
406 USBx_OUTEP(i)->DOEPCTL = 0U;
407 }
408
409 USBx_OUTEP(i)->DOEPTSIZ = 0U;
410 USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
411 }
412
413 USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
414
415 /* Disable all interrupts. */
416 USBx->GINTMSK = 0U;
417
418 /* Clear any pending interrupts */
419 USBx->GINTSTS = 0xBFFFFFFFU;
420
421 /* Enable the common interrupts */
422 if (cfg.dma_enable == 0U)
423 {
424 USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
425 }
426
427 /* Enable interrupts matching to the Device mode ONLY */
428 USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
429 USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
430 USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
431 USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
432
433 if (cfg.Sof_enable != 0U)
434 {
435 USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
436 }
437
438 if (cfg.vbus_sensing_enable == 1U)
439 {
440 USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
441 }
442
443 return ret;
444 }
445
446 /**
447 * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
448 * @param USBx Selected device
449 * @param num FIFO number
450 * This parameter can be a value from 1 to 15
451 15 means Flush all Tx FIFOs
452 * @retval HAL status
453 */
454 HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
455 {
456 uint32_t tickstart;
457
458 USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
459
460 /* Get tick */
461 tickstart = HAL_GetTick();
462
463 /* Wait for AHB master IDLE state. */
464 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH)
465 {
466 if ((HAL_GetTick() - tickstart) > USB_OTG_GRSTCTL_TXFFLSH_TIMEOUT_MS)
467 {
468 return HAL_TIMEOUT;
469 }
470 }
471
472 return HAL_OK;
473 }
474
475 /**
476 * @brief USB_FlushRxFifo : Flush Rx FIFO
477 * @param USBx Selected device
478 * @retval HAL status
479 */
480 HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
481 {
482 uint32_t tickstart;
483
484 USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
485
486 /* Get tick */
487 tickstart = HAL_GetTick();
488
489 /* Wait for AHB master IDLE state. */
490 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH)
491 {
492 if ((HAL_GetTick() - tickstart) > USB_OTG_GRSTCTL_RXFFLSH_TIMEOUT_MS)
493 {
494 return HAL_TIMEOUT;
495 }
496 }
497
498 return HAL_OK;
499 }
500
501 /**
502 * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register
503 * depending the PHY type and the enumeration speed of the device.
504 * @param USBx Selected device
505 * @param speed device speed
506 * This parameter can be one of these values:
507 * @arg USB_OTG_SPEED_HIGH: High speed mode
508 * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
509 * @arg USB_OTG_SPEED_FULL: Full speed mode
510 * @retval Hal status
511 */
512 HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
513 {
514 uint32_t USBx_BASE = (uint32_t)USBx;
515
516 USBx_DEVICE->DCFG |= speed;
517 return HAL_OK;
518 }
519
520 /**
521 * @brief USB_GetDevSpeed Return the Dev Speed
522 * @param USBx Selected device
523 * @retval speed device speed
524 * This parameter can be one of these values:
525 * @arg PCD_SPEED_HIGH: High speed mode
526 * @arg PCD_SPEED_FULL: Full speed mode
527 */
528 uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
529 {
530 uint32_t USBx_BASE = (uint32_t)USBx;
531 uint8_t speed;
532 uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
533
534 if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
535 {
536 speed = USBD_HS_SPEED;
537 }
538 else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
539 (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
540 {
541 speed = USBD_FS_SPEED;
542 }
543 else
544 {
545 speed = 0xFU;
546 }
547
548 return speed;
549 }
550
551 /**
552 * @brief Activate and configure an endpoint
553 * @param USBx Selected device
554 * @param ep pointer to endpoint structure
555 * @retval HAL status
556 */
557 HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
558 {
559 uint32_t USBx_BASE = (uint32_t)USBx;
560 uint32_t epnum = (uint32_t)ep->num;
561
562 if (ep->is_in == 1U)
563 {
564 USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
565
566 if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
567 {
568 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
569 ((uint32_t)ep->type << 18) | (epnum << 22) |
570 USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
571 USB_OTG_DIEPCTL_USBAEP;
572 }
573 }
574 else
575 {
576 USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
577
578 if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
579 {
580 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
581 ((uint32_t)ep->type << 18) |
582 USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
583 USB_OTG_DOEPCTL_USBAEP;
584 }
585 }
586 return HAL_OK;
587 }
588
589 /**
590 * @brief Activate and configure a dedicated endpoint
591 * @param USBx Selected device
592 * @param ep pointer to endpoint structure
593 * @retval HAL status
594 */
595 HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
596 {
597 uint32_t USBx_BASE = (uint32_t)USBx;
598 uint32_t epnum = (uint32_t)ep->num;
599
600 /* Read DEPCTLn register */
601 if (ep->is_in == 1U)
602 {
603 if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
604 {
605 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
606 ((uint32_t)ep->type << 18) | (epnum << 22) |
607 USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
608 USB_OTG_DIEPCTL_USBAEP;
609 }
610
611 USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
612 }
613 else
614 {
615 if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
616 {
617 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
618 ((uint32_t)ep->type << 18) | (epnum << 22) |
619 USB_OTG_DOEPCTL_USBAEP;
620 }
621
622 USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
623 }
624
625 return HAL_OK;
626 }
627
628 /**
629 * @brief De-activate and de-initialize an endpoint
630 * @param USBx Selected device
631 * @param ep pointer to endpoint structure
632 * @retval HAL status
633 */
634 HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
635 {
636 uint32_t USBx_BASE = (uint32_t)USBx;
637 uint32_t epnum = (uint32_t)ep->num;
638
639 /* Read DEPCTLn register */
640 if (ep->is_in == 1U)
641 {
642 if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
643 {
644 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
645 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
646 }
647
648 USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
649 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
650 USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
651 USB_OTG_DIEPCTL_MPSIZ |
652 USB_OTG_DIEPCTL_TXFNUM |
653 USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
654 USB_OTG_DIEPCTL_EPTYP);
655 }
656 else
657 {
658 if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
659 {
660 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
661 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
662 }
663
664 USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
665 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
666 USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
667 USB_OTG_DOEPCTL_MPSIZ |
668 USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
669 USB_OTG_DOEPCTL_EPTYP);
670 }
671
672 return HAL_OK;
673 }
674
675 /**
676 * @brief De-activate and de-initialize a dedicated endpoint
677 * @param USBx Selected device
678 * @param ep pointer to endpoint structure
679 * @retval HAL status
680 */
681 HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
682 {
683 uint32_t USBx_BASE = (uint32_t)USBx;
684 uint32_t epnum = (uint32_t)ep->num;
685
686 /* Read DEPCTLn register */
687 if (ep->is_in == 1U)
688 {
689 if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
690 {
691 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
692 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
693 }
694
695 USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
696 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
697 }
698 else
699 {
700 if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
701 {
702 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
703 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
704 }
705
706 USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
707 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
708 }
709
710 return HAL_OK;
711 }
712
713 /**
714 * @brief USB_EPStartXfer : setup and starts a transfer over an EP
715 * @param USBx Selected device
716 * @param ep pointer to endpoint structure
717 * @param dma USB dma enabled or disabled
718 * This parameter can be one of these values:
719 * 0 : DMA feature not used
720 * 1 : DMA feature used
721 * @retval HAL status
722 */
723 HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
724 {
725 uint32_t USBx_BASE = (uint32_t)USBx;
726 uint32_t epnum = (uint32_t)ep->num;
727 uint16_t pktcnt;
728
729 /* IN endpoint */
730 if (ep->is_in == 1U)
731 {
732 /* Zero Length Packet? */
733 if (ep->xfer_len == 0U)
734 {
735 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
736 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
737 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
738 }
739 else
740 {
741 /* Program the transfer size and packet count
742 * as follows: xfersize = N * maxpacket +
743 * short_packet pktcnt = N + (short_packet
744 * exist ? 1 : 0)
745 */
746 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
747 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
748 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
749 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
750
751 if (ep->type == EP_TYPE_ISOC)
752 {
753 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
754 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));
755 }
756 }
757
758 if (dma == 1U)
759 {
760 if ((uint32_t)ep->dma_addr != 0U)
761 {
762 USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
763 }
764
765 if (ep->type == EP_TYPE_ISOC)
766 {
767 if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
768 {
769 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
770 }
771 else
772 {
773 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
774 }
775 }
776
777 /* EP enable, IN data in FIFO */
778 USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
779 }
780 else
781 {
782 /* EP enable, IN data in FIFO */
783 USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
784
785 if (ep->type != EP_TYPE_ISOC)
786 {
787 /* Enable the Tx FIFO Empty Interrupt for this EP */
788 if (ep->xfer_len > 0U)
789 {
790 USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
791 }
792 }
793 else
794 {
795 if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
796 {
797 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
798 }
799 else
800 {
801 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
802 }
803
804 (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
805 }
806 }
807 }
808 else /* OUT endpoint */
809 {
810 /* Program the transfer size and packet count as follows:
811 * pktcnt = N
812 * xfersize = N * maxpacket
813 */
814 USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
815 USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
816
817 if (ep->xfer_len == 0U)
818 {
819 USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
820 USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
821 }
822 else
823 {
824 pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
825 USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
826 USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt);
827 }
828
829 if (dma == 1U)
830 {
831 if ((uint32_t)ep->xfer_buff != 0U)
832 {
833 USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
834 }
835 }
836
837 if (ep->type == EP_TYPE_ISOC)
838 {
839 if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
840 {
841 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
842 }
843 else
844 {
845 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
846 }
847 }
848 /* EP enable */
849 USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
850 }
851
852 return HAL_OK;
853 }
854
855 /**
856 * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0
857 * @param USBx Selected device
858 * @param ep pointer to endpoint structure
859 * @param dma USB dma enabled or disabled
860 * This parameter can be one of these values:
861 * 0 : DMA feature not used
862 * 1 : DMA feature used
863 * @retval HAL status
864 */
865 HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
866 {
867 uint32_t USBx_BASE = (uint32_t)USBx;
868 uint32_t epnum = (uint32_t)ep->num;
869
870 /* IN endpoint */
871 if (ep->is_in == 1U)
872 {
873 /* Zero Length Packet? */
874 if (ep->xfer_len == 0U)
875 {
876 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
877 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
878 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
879 }
880 else
881 {
882 /* Program the transfer size and packet count
883 * as follows: xfersize = N * maxpacket +
884 * short_packet pktcnt = N + (short_packet
885 * exist ? 1 : 0)
886 */
887 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
888 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
889
890 if (ep->xfer_len > ep->maxpacket)
891 {
892 ep->xfer_len = ep->maxpacket;
893 }
894 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
895 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
896 }
897
898 if (dma == 1U)
899 {
900 if ((uint32_t)ep->dma_addr != 0U)
901 {
902 USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
903 }
904
905 /* EP enable, IN data in FIFO */
906 USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
907 }
908 else
909 {
910 /* EP enable, IN data in FIFO */
911 USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
912
913 /* Enable the Tx FIFO Empty Interrupt for this EP */
914 if (ep->xfer_len > 0U)
915 {
916 USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
917 }
918 }
919 }
920 else /* OUT endpoint */
921 {
922 /* Program the transfer size and packet count as follows:
923 * pktcnt = N
924 * xfersize = N * maxpacket
925 */
926 USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
927 USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
928
929 if (ep->xfer_len > 0U)
930 {
931 ep->xfer_len = ep->maxpacket;
932 }
933
934 USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
935 USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
936
937 if (dma == 1U)
938 {
939 if ((uint32_t)ep->xfer_buff != 0U)
940 {
941 USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
942 }
943 }
944
945 /* EP enable */
946 USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
947 }
948
949 return HAL_OK;
950 }
951
952 /**
953 * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
954 * with the EP/channel
955 * @param USBx Selected device
956 * @param src pointer to source buffer
957 * @param ch_ep_num endpoint or host channel number
958 * @param len Number of bytes to write
959 * @param dma USB dma enabled or disabled
960 * This parameter can be one of these values:
961 * 0 : DMA feature not used
962 * 1 : DMA feature used
963 * @retval HAL status
964 */
965 HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
966 {
967 uint32_t USBx_BASE = (uint32_t)USBx;
968 uint32_t *pSrc = (uint32_t *)src;
969 uint32_t count32b, i;
970
971 if (dma == 0U)
972 {
973 count32b = ((uint32_t)len + 3U) / 4U;
974 for (i = 0U; i < count32b; i++)
975 {
976 USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
977 pSrc++;
978 }
979 }
980
981 return HAL_OK;
982 }
983
984 /**
985 * @brief USB_ReadPacket : read a packet from the RX FIFO
986 * @param USBx Selected device
987 * @param dest source pointer
988 * @param len Number of bytes to read
989 * @retval pointer to destination buffer
990 */
991 void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
992 {
993 uint32_t USBx_BASE = (uint32_t)USBx;
994 uint32_t *pDest = (uint32_t *)dest;
995 uint32_t i;
996 uint32_t count32b = ((uint32_t)len + 3U) / 4U;
997
998 for (i = 0U; i < count32b; i++)
999 {
1000 __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
1001 pDest++;
1002 }
1003
1004 return ((void *)pDest);
1005 }
1006
1007 /**
1008 * @brief USB_EPSetStall : set a stall condition over an EP
1009 * @param USBx Selected device
1010 * @param ep pointer to endpoint structure
1011 * @retval HAL status
1012 */
1013 HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
1014 {
1015 uint32_t USBx_BASE = (uint32_t)USBx;
1016 uint32_t epnum = (uint32_t)ep->num;
1017
1018 if (ep->is_in == 1U)
1019 {
1020 if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
1021 {
1022 USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
1023 }
1024 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
1025 }
1026 else
1027 {
1028 if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
1029 {
1030 USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
1031 }
1032 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
1033 }
1034
1035 return HAL_OK;
1036 }
1037
1038 /**
1039 * @brief USB_EPClearStall : Clear a stall condition over an EP
1040 * @param USBx Selected device
1041 * @param ep pointer to endpoint structure
1042 * @retval HAL status
1043 */
1044 HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
1045 {
1046 uint32_t USBx_BASE = (uint32_t)USBx;
1047 uint32_t epnum = (uint32_t)ep->num;
1048
1049 if (ep->is_in == 1U)
1050 {
1051 USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
1052 if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
1053 {
1054 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
1055 }
1056 }
1057 else
1058 {
1059 USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
1060 if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
1061 {
1062 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
1063 }
1064 }
1065 return HAL_OK;
1066 }
1067
1068 /**
1069 * @brief USB_StopDevice : Stop the usb device mode
1070 * @param USBx Selected device
1071 * @retval HAL status
1072 */
1073 HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
1074 {
1075 HAL_StatusTypeDef ret;
1076 uint32_t USBx_BASE = (uint32_t)USBx;
1077 uint32_t i;
1078
1079 /* Clear Pending interrupt */
1080 for (i = 0U; i < 15U; i++)
1081 {
1082 USBx_INEP(i)->DIEPINT = 0xFB7FU;
1083 USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
1084 }
1085
1086 /* Clear interrupt masks */
1087 USBx_DEVICE->DIEPMSK = 0U;
1088 USBx_DEVICE->DOEPMSK = 0U;
1089 USBx_DEVICE->DAINTMSK = 0U;
1090
1091 /* Flush the FIFO */
1092 ret = USB_FlushRxFifo(USBx);
1093 if (ret != HAL_OK)
1094 {
1095 return ret;
1096 }
1097
1098 ret = USB_FlushTxFifo(USBx, 0x10U);
1099 if (ret != HAL_OK)
1100 {
1101 return ret;
1102 }
1103
1104 return ret;
1105 }
1106
1107 /**
1108 * @brief USB_SetDevAddress : Stop the usb device mode
1109 * @param USBx Selected device
1110 * @param address new device address to be assigned
1111 * This parameter can be a value from 0 to 255
1112 * @retval HAL status
1113 */
1114 HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)
1115 {
1116 uint32_t USBx_BASE = (uint32_t)USBx;
1117
1118 USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
1119 USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
1120
1121 return HAL_OK;
1122 }
1123
1124 /**
1125 * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
1126 * @param USBx Selected device
1127 * @retval HAL status
1128 */
1129 HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
1130 {
1131 uint32_t USBx_BASE = (uint32_t)USBx;
1132
1133 USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
1134 HAL_Delay(3U);
1135
1136 return HAL_OK;
1137 }
1138
1139 /**
1140 * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
1141 * @param USBx Selected device
1142 * @retval HAL status
1143 */
1144 HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
1145 {
1146 uint32_t USBx_BASE = (uint32_t)USBx;
1147
1148 USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
1149 HAL_Delay(3U);
1150
1151 return HAL_OK;
1152 }
1153
1154 /**
1155 * @brief USB_ReadInterrupts: return the global USB interrupt status
1156 * @param USBx Selected device
1157 * @retval HAL status
1158 */
1159 uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)
1160 {
1161 uint32_t tmpreg;
1162
1163 tmpreg = USBx->GINTSTS;
1164 tmpreg &= USBx->GINTMSK;
1165
1166 return tmpreg;
1167 }
1168
1169 /**
1170 * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
1171 * @param USBx Selected device
1172 * @retval HAL status
1173 */
1174 uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
1175 {
1176 uint32_t USBx_BASE = (uint32_t)USBx;
1177 uint32_t tmpreg;
1178
1179 tmpreg = USBx_DEVICE->DAINT;
1180 tmpreg &= USBx_DEVICE->DAINTMSK;
1181
1182 return ((tmpreg & 0xffff0000U) >> 16);
1183 }
1184
1185 /**
1186 * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
1187 * @param USBx Selected device
1188 * @retval HAL status
1189 */
1190 uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
1191 {
1192 uint32_t USBx_BASE = (uint32_t)USBx;
1193 uint32_t tmpreg;
1194
1195 tmpreg = USBx_DEVICE->DAINT;
1196 tmpreg &= USBx_DEVICE->DAINTMSK;
1197
1198 return ((tmpreg & 0xFFFFU));
1199 }
1200
1201 /**
1202 * @brief Returns Device OUT EP Interrupt register
1203 * @param USBx Selected device
1204 * @param epnum endpoint number
1205 * This parameter can be a value from 0 to 15
1206 * @retval Device OUT EP Interrupt register
1207 */
1208 uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
1209 {
1210 uint32_t USBx_BASE = (uint32_t)USBx;
1211 uint32_t tmpreg;
1212
1213 tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
1214 tmpreg &= USBx_DEVICE->DOEPMSK;
1215
1216 return tmpreg;
1217 }
1218
1219 /**
1220 * @brief Returns Device IN EP Interrupt register
1221 * @param USBx Selected device
1222 * @param epnum endpoint number
1223 * This parameter can be a value from 0 to 15
1224 * @retval Device IN EP Interrupt register
1225 */
1226 uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
1227 {
1228 uint32_t USBx_BASE = (uint32_t)USBx;
1229 uint32_t tmpreg, msk, emp;
1230
1231 msk = USBx_DEVICE->DIEPMSK;
1232 emp = USBx_DEVICE->DIEPEMPMSK;
1233 msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
1234 tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
1235
1236 return tmpreg;
1237 }
1238
1239 /**
1240 * @brief USB_ClearInterrupts: clear a USB interrupt
1241 * @param USBx Selected device
1242 * @param interrupt interrupt flag
1243 * @retval None
1244 */
1245 void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
1246 {
1247 USBx->GINTSTS |= interrupt;
1248 }
1249
1250 /**
1251 * @brief Returns USB core mode
1252 * @param USBx Selected device
1253 * @retval return core mode : Host or Device
1254 * This parameter can be one of these values:
1255 * 0 : Host
1256 * 1 : Device
1257 */
1258 uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
1259 {
1260 return ((USBx->GINTSTS) & 0x1U);
1261 }
1262
1263 /**
1264 * @brief Activate EP0 for Setup transactions
1265 * @param USBx Selected device
1266 * @retval HAL status
1267 */
1268 HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
1269 {
1270 uint32_t USBx_BASE = (uint32_t)USBx;
1271
1272 /* Set the MPS of the IN EP0 to 64 bytes */
1273 USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
1274
1275 USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
1276
1277 return HAL_OK;
1278 }
1279
1280 /**
1281 * @brief Prepare the EP0 to start the first control setup
1282 * @param USBx Selected device
1283 * @param dma USB dma enabled or disabled
1284 * This parameter can be one of these values:
1285 * 0 : DMA feature not used
1286 * 1 : DMA feature used
1287 * @param psetup pointer to setup packet
1288 * @retval HAL status
1289 */
1290 HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
1291 {
1292 uint32_t USBx_BASE = (uint32_t)USBx;
1293 uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
1294
1295 if (gSNPSiD > USB_OTG_CORE_ID_300A)
1296 {
1297 if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
1298 {
1299 return HAL_OK;
1300 }
1301 }
1302
1303 USBx_OUTEP(0U)->DOEPTSIZ = 0U;
1304 USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
1305 USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
1306 USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
1307
1308 if (dma == 1U)
1309 {
1310 USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
1311 /* EP enable */
1312 USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;
1313 }
1314
1315 return HAL_OK;
1316 }
1317
1318 /**
1319 * @brief Reset the USB Core (needed after USB clock settings change)
1320 * @param USBx Selected device
1321 * @retval HAL status
1322 */
1323 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
1324 {
1325 uint32_t tickstart;
1326
1327 /* Get tick */
1328 tickstart = HAL_GetTick();
1329
1330 /* Wait for AHB master IDLE state. */
1331 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U)
1332 {
1333 if ((HAL_GetTick() - tickstart) > USB_OTG_GRSTCTL_AHBIDL_TIMEOUT_MS)
1334 {
1335 return HAL_TIMEOUT;
1336 }
1337 }
1338
1339 /* Core Soft Reset */
1340 USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
1341
1342 /* Get tick */
1343 tickstart = HAL_GetTick();
1344
1345 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST)
1346 {
1347 if ((HAL_GetTick() - tickstart) > USB_OTG_GRSTCTL_CSRST_TIMEOUT_MS)
1348 {
1349 return HAL_TIMEOUT;
1350 }
1351 }
1352
1353 return HAL_OK;
1354 }
1355
1356 /**
1357 * @brief USB_HostInit : Initializes the USB OTG controller registers
1358 * for Host mode
1359 * @param USBx Selected device
1360 * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
1361 * the configuration information for the specified USBx peripheral.
1362 * @retval HAL status
1363 */
1364 HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
1365 {
1366 uint32_t USBx_BASE = (uint32_t)USBx;
1367 uint32_t i;
1368
1369 /* Restart the Phy Clock */
1370 USBx_PCGCCTL = 0U;
1371
1372 /* Disable VBUS sensing */
1373 USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN);
1374
1375 /* Disable Battery chargin detector */
1376 USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
1377
1378
1379 if ((USBx->CID & (0x1U << 8)) != 0U)
1380 {
1381 if (cfg.speed == USBH_FSLS_SPEED)
1382 {
1383 /* Force Device Enumeration to FS/LS mode only */
1384 USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
1385 }
1386 else
1387 {
1388 /* Set default Max speed support */
1389 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
1390 }
1391 }
1392 else
1393 {
1394 /* Set default Max speed support */
1395 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
1396 }
1397
1398 /* Make sure the FIFOs are flushed. */
1399 (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
1400 (void)USB_FlushRxFifo(USBx);
1401
1402 /* Clear all pending HC Interrupts */
1403 for (i = 0U; i < cfg.Host_channels; i++)
1404 {
1405 USBx_HC(i)->HCINT = 0xFFFFFFFFU;
1406 USBx_HC(i)->HCINTMSK = 0U;
1407 }
1408
1409 /* Enable VBUS driving */
1410 (void)USB_DriveVbus(USBx, 1U);
1411
1412 HAL_Delay(200U);
1413
1414 /* Disable all interrupts. */
1415 USBx->GINTMSK = 0U;
1416
1417 /* Clear any pending interrupts */
1418 USBx->GINTSTS = 0xFFFFFFFFU;
1419
1420 if ((USBx->CID & (0x1U << 8)) != 0U)
1421 {
1422 /* set Rx FIFO size */
1423 USBx->GRXFSIZ = 0x200U;
1424 USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
1425 USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
1426 }
1427 else
1428 {
1429 /* set Rx FIFO size */
1430 USBx->GRXFSIZ = 0x80U;
1431 USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);
1432 USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
1433 }
1434
1435 /* Enable the common interrupts */
1436 if (cfg.dma_enable == 0U)
1437 {
1438 USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
1439 }
1440
1441 /* Enable interrupts matching to the Host mode ONLY */
1442 USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \
1443 USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \
1444 USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
1445
1446 return HAL_OK;
1447 }
1448
1449 /**
1450 * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
1451 * HCFG register on the PHY type and set the right frame interval
1452 * @param USBx Selected device
1453 * @param freq clock frequency
1454 * This parameter can be one of these values:
1455 * HCFG_48_MHZ : Full Speed 48 MHz Clock
1456 * HCFG_6_MHZ : Low Speed 6 MHz Clock
1457 * @retval HAL status
1458 */
1459 HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
1460 {
1461 uint32_t USBx_BASE = (uint32_t)USBx;
1462
1463 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
1464 USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;
1465
1466 if (freq == HCFG_48_MHZ)
1467 {
1468 USBx_HOST->HFIR = 48000U;
1469 }
1470 else if (freq == HCFG_6_MHZ)
1471 {
1472 USBx_HOST->HFIR = 6000U;
1473 }
1474 else
1475 {
1476 /* ... */
1477 }
1478
1479 return HAL_OK;
1480 }
1481
1482 /**
1483 * @brief USB_OTG_ResetPort : Reset Host Port
1484 * @param USBx Selected device
1485 * @retval HAL status
1486 * @note (1)The application must wait at least 10 ms
1487 * before clearing the reset bit.
1488 */
1489 HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
1490 {
1491 uint32_t USBx_BASE = (uint32_t)USBx;
1492
1493 __IO uint32_t hprt0 = 0U;
1494
1495 hprt0 = USBx_HPRT0;
1496
1497 hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
1498 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
1499
1500 USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
1501 HAL_Delay(100U); /* See Note #1 */
1502 USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
1503 HAL_Delay(10U);
1504
1505 return HAL_OK;
1506 }
1507
1508 /**
1509 * @brief USB_DriveVbus : activate or de-activate vbus
1510 * @param state VBUS state
1511 * This parameter can be one of these values:
1512 * 0 : VBUS Active
1513 * 1 : VBUS Inactive
1514 * @retval HAL status
1515 */
1516 HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
1517 {
1518 uint32_t USBx_BASE = (uint32_t)USBx;
1519 __IO uint32_t hprt0 = 0U;
1520
1521 hprt0 = USBx_HPRT0;
1522
1523 hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
1524 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
1525
1526 if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))
1527 {
1528 USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
1529 }
1530 if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))
1531 {
1532 USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
1533 }
1534 return HAL_OK;
1535 }
1536
1537 /**
1538 * @brief Return Host Core speed
1539 * @param USBx Selected device
1540 * @retval speed : Host speed
1541 * This parameter can be one of these values:
1542 * @arg HCD_SPEED_HIGH: High speed mode
1543 * @arg HCD_SPEED_FULL: Full speed mode
1544 * @arg HCD_SPEED_LOW: Low speed mode
1545 */
1546 uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)
1547 {
1548 uint32_t USBx_BASE = (uint32_t)USBx;
1549 __IO uint32_t hprt0 = 0U;
1550
1551 hprt0 = USBx_HPRT0;
1552 return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
1553 }
1554
1555 /**
1556 * @brief Return Host Current Frame number
1557 * @param USBx Selected device
1558 * @retval current frame number
1559 */
1560 uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)
1561 {
1562 uint32_t USBx_BASE = (uint32_t)USBx;
1563
1564 return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
1565 }
1566
1567 /**
1568 * @brief Initialize a host channel
1569 * @param USBx Selected device
1570 * @param ch_num Channel number
1571 * This parameter can be a value from 1 to 15
1572 * @param epnum Endpoint number
1573 * This parameter can be a value from 1 to 15
1574 * @param dev_address Current device address
1575 * This parameter can be a value from 0 to 255
1576 * @param speed Current device speed
1577 * This parameter can be one of these values:
1578 * @arg USB_OTG_SPEED_HIGH: High speed mode
1579 * @arg USB_OTG_SPEED_FULL: Full speed mode
1580 * @arg USB_OTG_SPEED_LOW: Low speed mode
1581 * @param ep_type Endpoint Type
1582 * This parameter can be one of these values:
1583 * @arg EP_TYPE_CTRL: Control type
1584 * @arg EP_TYPE_ISOC: Isochronous type
1585 * @arg EP_TYPE_BULK: Bulk type
1586 * @arg EP_TYPE_INTR: Interrupt type
1587 * @param mps Max Packet Size
1588 * This parameter can be a value from 0 to32K
1589 * @retval HAL state
1590 */
1591 HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
1592 uint8_t ch_num,
1593 uint8_t epnum,
1594 uint8_t dev_address,
1595 uint8_t speed,
1596 uint8_t ep_type,
1597 uint16_t mps)
1598 {
1599 HAL_StatusTypeDef ret = HAL_OK;
1600 uint32_t USBx_BASE = (uint32_t)USBx;
1601 uint32_t HCcharEpDir, HCcharLowSpeed;
1602
1603 /* Clear old interrupt conditions for this host channel. */
1604 USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;
1605
1606 /* Enable channel interrupts required for this transfer. */
1607 switch (ep_type)
1608 {
1609 case EP_TYPE_CTRL:
1610 case EP_TYPE_BULK:
1611 USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
1612 USB_OTG_HCINTMSK_STALLM |
1613 USB_OTG_HCINTMSK_TXERRM |
1614 USB_OTG_HCINTMSK_DTERRM |
1615 USB_OTG_HCINTMSK_AHBERR |
1616 USB_OTG_HCINTMSK_NAKM;
1617
1618 if ((epnum & 0x80U) == 0x80U)
1619 {
1620 USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
1621 }
1622 else
1623 {
1624 if ((USBx->CID & (0x1U << 8)) != 0U)
1625 {
1626 USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
1627 }
1628 }
1629 break;
1630
1631 case EP_TYPE_INTR:
1632 USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
1633 USB_OTG_HCINTMSK_STALLM |
1634 USB_OTG_HCINTMSK_TXERRM |
1635 USB_OTG_HCINTMSK_DTERRM |
1636 USB_OTG_HCINTMSK_NAKM |
1637 USB_OTG_HCINTMSK_AHBERR |
1638 USB_OTG_HCINTMSK_FRMORM;
1639
1640 if ((epnum & 0x80U) == 0x80U)
1641 {
1642 USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
1643 }
1644
1645 break;
1646
1647 case EP_TYPE_ISOC:
1648 USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
1649 USB_OTG_HCINTMSK_ACKM |
1650 USB_OTG_HCINTMSK_AHBERR |
1651 USB_OTG_HCINTMSK_FRMORM;
1652
1653 if ((epnum & 0x80U) == 0x80U)
1654 {
1655 USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
1656 }
1657 break;
1658
1659 default:
1660 ret = HAL_ERROR;
1661 break;
1662 }
1663
1664 /* Enable the top level host channel interrupt. */
1665 USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);
1666
1667 /* Make sure host channel interrupts are enabled. */
1668 USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
1669
1670 /* Program the HCCHAR register */
1671 if ((epnum & 0x80U) == 0x80U)
1672 {
1673 HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;
1674 }
1675 else
1676 {
1677 HCcharEpDir = 0U;
1678 }
1679
1680 if (speed == HPRT0_PRTSPD_LOW_SPEED)
1681 {
1682 HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;
1683 }
1684 else
1685 {
1686 HCcharLowSpeed = 0U;
1687 }
1688
1689 USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |
1690 ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |
1691 (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |
1692 ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;
1693
1694 if (ep_type == EP_TYPE_INTR)
1695 {
1696 USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
1697 }
1698
1699 return ret;
1700 }
1701
1702 /**
1703 * @brief Start a transfer over a host channel
1704 * @param USBx Selected device
1705 * @param hc pointer to host channel structure
1706 * @param dma USB dma enabled or disabled
1707 * This parameter can be one of these values:
1708 * 0 : DMA feature not used
1709 * 1 : DMA feature used
1710 * @retval HAL state
1711 */
1712 HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
1713 {
1714 uint32_t USBx_BASE = (uint32_t)USBx;
1715 uint32_t ch_num = (uint32_t)hc->ch_num;
1716 static __IO uint32_t tmpreg = 0U;
1717 uint8_t is_oddframe;
1718 uint16_t len_words;
1719 uint16_t num_packets;
1720 uint16_t max_hc_pkt_count = 256U;
1721
1722 if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED))
1723 {
1724 if ((dma == 0U) && (hc->do_ping == 1U))
1725 {
1726 (void)USB_DoPing(USBx, hc->ch_num);
1727 return HAL_OK;
1728 }
1729 else if (dma == 1U)
1730 {
1731 USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
1732 hc->do_ping = 0U;
1733 }
1734 else
1735 {
1736 /* ... */
1737 }
1738 }
1739
1740 /* Compute the expected number of packets associated to the transfer */
1741 if (hc->xfer_len > 0U)
1742 {
1743 num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);
1744
1745 if (num_packets > max_hc_pkt_count)
1746 {
1747 num_packets = max_hc_pkt_count;
1748 hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
1749 }
1750 }
1751 else
1752 {
1753 num_packets = 1U;
1754 }
1755 if (hc->ep_is_in != 0U)
1756 {
1757 hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
1758 }
1759
1760 /* Initialize the HCTSIZn register */
1761 USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) |
1762 (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
1763 (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);
1764
1765 if (dma != 0U)
1766 {
1767 /* xfer_buff MUST be 32-bits aligned */
1768 USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
1769 }
1770
1771 is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;
1772 USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
1773 USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;
1774
1775 /* Set host channel enable */
1776 tmpreg = USBx_HC(ch_num)->HCCHAR;
1777 tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
1778
1779 /* make sure to set the correct ep direction */
1780 if (hc->ep_is_in != 0U)
1781 {
1782 tmpreg |= USB_OTG_HCCHAR_EPDIR;
1783 }
1784 else
1785 {
1786 tmpreg &= ~USB_OTG_HCCHAR_EPDIR;
1787 }
1788 tmpreg |= USB_OTG_HCCHAR_CHENA;
1789 USBx_HC(ch_num)->HCCHAR = tmpreg;
1790
1791 if (dma == 0U) /* Slave mode */
1792 {
1793 if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
1794 {
1795 switch (hc->ep_type)
1796 {
1797 /* Non periodic transfer */
1798 case EP_TYPE_CTRL:
1799 case EP_TYPE_BULK:
1800
1801 len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
1802
1803 /* check if there is enough space in FIFO space */
1804 if (len_words > (USBx->HNPTXSTS & 0xFFFFU))
1805 {
1806 /* need to process data in nptxfempty interrupt */
1807 USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
1808 }
1809 break;
1810
1811 /* Periodic transfer */
1812 case EP_TYPE_INTR:
1813 case EP_TYPE_ISOC:
1814 len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
1815 /* check if there is enough space in FIFO space */
1816 if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
1817 {
1818 /* need to process data in ptxfempty interrupt */
1819 USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
1820 }
1821 break;
1822
1823 default:
1824 break;
1825 }
1826
1827 /* Write packet into the Tx FIFO. */
1828 (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0);
1829 }
1830 }
1831
1832 return HAL_OK;
1833 }
1834
1835 /**
1836 * @brief Read all host channel interrupts status
1837 * @param USBx Selected device
1838 * @retval HAL state
1839 */
1840 uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
1841 {
1842 uint32_t USBx_BASE = (uint32_t)USBx;
1843
1844 return ((USBx_HOST->HAINT) & 0xFFFFU);
1845 }
1846
1847 /**
1848 * @brief Halt a host channel
1849 * @param USBx Selected device
1850 * @param hc_num Host Channel number
1851 * This parameter can be a value from 1 to 15
1852 * @retval HAL state
1853 */
1854 HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
1855 {
1856 uint32_t USBx_BASE = (uint32_t)USBx;
1857 uint32_t hcnum = (uint32_t)hc_num;
1858 uint32_t count = 0U;
1859 uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
1860
1861 /* Check for space in the request queue to issue the halt. */
1862 if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))
1863 {
1864 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
1865
1866 if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
1867 {
1868 USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
1869 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1870 USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
1871 do
1872 {
1873 if (++count > 1000U)
1874 {
1875 break;
1876 }
1877 }
1878 while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
1879 }
1880 else
1881 {
1882 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1883 }
1884 }
1885 else
1886 {
1887 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
1888
1889 if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)
1890 {
1891 USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
1892 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1893 USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
1894 do
1895 {
1896 if (++count > 1000U)
1897 {
1898 break;
1899 }
1900 }
1901 while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
1902 }
1903 else
1904 {
1905 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1906 }
1907 }
1908
1909 return HAL_OK;
1910 }
1911
1912 /**
1913 * @brief Initiate Do Ping protocol
1914 * @param USBx Selected device
1915 * @param hc_num Host Channel number
1916 * This parameter can be a value from 1 to 15
1917 * @retval HAL state
1918 */
1919 HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
1920 {
1921 uint32_t USBx_BASE = (uint32_t)USBx;
1922 uint32_t chnum = (uint32_t)ch_num;
1923 uint32_t num_packets = 1U;
1924 uint32_t tmpreg;
1925
1926 USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
1927 USB_OTG_HCTSIZ_DOPING;
1928
1929 /* Set host channel enable */
1930 tmpreg = USBx_HC(chnum)->HCCHAR;
1931 tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
1932 tmpreg |= USB_OTG_HCCHAR_CHENA;
1933 USBx_HC(chnum)->HCCHAR = tmpreg;
1934
1935 return HAL_OK;
1936 }
1937
1938 /**
1939 * @brief Stop Host Core
1940 * @param USBx Selected device
1941 * @retval HAL state
1942 */
1943 HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
1944 {
1945 uint32_t USBx_BASE = (uint32_t)USBx;
1946 uint32_t count = 0U;
1947 uint32_t value;
1948 uint32_t i;
1949
1950 (void)USB_DisableGlobalInt(USBx);
1951
1952 /* Flush FIFO */
1953 (void)USB_FlushTxFifo(USBx, 0x10U);
1954 (void)USB_FlushRxFifo(USBx);
1955
1956 /* Flush out any leftover queued requests. */
1957 for (i = 0U; i <= 15U; i++)
1958 {
1959 value = USBx_HC(i)->HCCHAR;
1960 value |= USB_OTG_HCCHAR_CHDIS;
1961 value &= ~USB_OTG_HCCHAR_CHENA;
1962 value &= ~USB_OTG_HCCHAR_EPDIR;
1963 USBx_HC(i)->HCCHAR = value;
1964 }
1965
1966 /* Halt all channels to put them into a known state. */
1967 for (i = 0U; i <= 15U; i++)
1968 {
1969 value = USBx_HC(i)->HCCHAR;
1970 value |= USB_OTG_HCCHAR_CHDIS;
1971 value |= USB_OTG_HCCHAR_CHENA;
1972 value &= ~USB_OTG_HCCHAR_EPDIR;
1973 USBx_HC(i)->HCCHAR = value;
1974
1975 do
1976 {
1977 if (++count > 1000U)
1978 {
1979 break;
1980 }
1981 }
1982 while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
1983 }
1984
1985 /* Clear any pending Host interrupts */
1986 USBx_HOST->HAINT = 0xFFFFFFFFU;
1987 USBx->GINTSTS = 0xFFFFFFFFU;
1988
1989 (void)USB_EnableGlobalInt(USBx);
1990
1991 return HAL_OK;
1992 }
1993
1994 /**
1995 * @brief USB_ActivateRemoteWakeup active remote wakeup signalling
1996 * @param USBx Selected device
1997 * @retval HAL status
1998 */
1999 HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
2000 {
2001 uint32_t USBx_BASE = (uint32_t)USBx;
2002
2003 if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
2004 {
2005 /* active Remote wakeup signalling */
2006 USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
2007 }
2008
2009 return HAL_OK;
2010 }
2011
2012 /**
2013 * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling
2014 * @param USBx Selected device
2015 * @retval HAL status
2016 */
2017 HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
2018 {
2019 uint32_t USBx_BASE = (uint32_t)USBx;
2020
2021 /* active Remote wakeup signalling */
2022 USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
2023
2024 return HAL_OK;
2025 }
2026 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
2027
2028
2029 /**
2030 * @}
2031 */
2032
2033 /**
2034 * @}
2035 */
2036 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
2037 #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
2038
2039 /**
2040 * @}
2041 */
2042
2043 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/