src/main/startup/system_stm32f30x.c

   1 /**
   2   ******************************************************************************
   3   * @file    system_stm32f30x.c
   4   * @author  MCD Application Team
   5   * @version V1.1.1
   6   * @date    28-March-2014
   7   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   8   *          This file contains the system clock configuration for STM32F30x devices,
   9   *          and is generated by the clock configuration tool
  10   *          stm32f30x_Clock_Configuration_V1.0.0.xls
  11   *
  12   * 1.  This file provides two functions and one global variable to be called from
  13   *     user application:
  14   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
  15   *                      and Divider factors, AHB/APBx prescalers and Flash settings),
  16   *                      depending on the configuration made in the clock xls tool.
  17   *                      This function is called at startup just after reset and
  18   *                      before branch to main program. This call is made inside
  19   *                      the "startup_stm32f30x.s" file.
  20   *
  21   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  22   *                                  by the user application to setup the SysTick
  23   *                                  timer or configure other parameters.
  24   *
  25   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  26   *                                 be called whenever the core clock is changed
  27   *                                 during program execution.
  28   *
  29   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
  30   *    Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
  31   *    configure the system clock before to branch to main program.
  32   *
  33   * 3. If the system clock source selected by user fails to startup, the SystemInit()
  34   *    function will do nothing and HSI still used as system clock source. User can
  35   *    add some code to deal with this issue inside the SetSysClock() function.
  36   *
  37   * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
  38   *    in "stm32f30x.h" file. When HSE is used as system clock source, directly or
  39   *    through PLL, and you are using different crystal you have to adapt the HSE
  40   *    value to your own configuration.
  41   *
  42   * 5. This file configures the system clock as follows:
  43   *=============================================================================
  44   *                         Supported STM32F30x device
  45   *-----------------------------------------------------------------------------
  46   *        System Clock source                    | PLL (HSE)
  47   *-----------------------------------------------------------------------------
  48   *        SYSCLK(Hz)                             | 72000000
  49   *-----------------------------------------------------------------------------
  50   *        HCLK(Hz)                               | 72000000
  51   *-----------------------------------------------------------------------------
  52   *        AHB Prescaler                          | 1
  53   *-----------------------------------------------------------------------------
  54   *        APB2 Prescaler                         | 2
  55   *-----------------------------------------------------------------------------
  56   *        APB1 Prescaler                         | 2
  57   *-----------------------------------------------------------------------------
  58   *        HSE Frequency(Hz)                      | 8000000
  59   *----------------------------------------------------------------------------
  60   *        PLLMUL                                 | 9
  61   *-----------------------------------------------------------------------------
  62   *        PREDIV                                 | 1
  63   *-----------------------------------------------------------------------------
  64   *        USB Clock                              | ENABLE
  65   *-----------------------------------------------------------------------------
  66   *        Flash Latency(WS)                      | 2
  67   *-----------------------------------------------------------------------------
  68   *        Prefetch Buffer                        | ON
  69   *-----------------------------------------------------------------------------
  70   *=============================================================================
  71   ******************************************************************************
  72   * @attention
  73   *
  74   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
  75   *
  76   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  77   * You may not use this file except in compliance with the License.
  78   * You may obtain a copy of the License at:
  79   *
  80   *        http://www.st.com/software_license_agreement_liberty_v2
  81   *
  82   * Unless required by applicable law or agreed to in writing, software
  83   * distributed under the License is distributed on an "AS IS" BASIS,
  84   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  85   * See the License for the specific language governing permissions and
  86   * limitations under the License.
  87   *
  88   ******************************************************************************
  89   */
  90 /** @addtogroup CMSIS
  91   * @{
  92   */
  93
  94 /** @addtogroup stm32f30x_system
  95   * @{
  96   */
  97
  98 /** @addtogroup STM32F30x_System_Private_Includes
  99   * @{
 100   */
 101
 102 #include "platform.h"
 103
 104 #include "stm32f30x.h"
 105 #include "drivers/system.h"
 106
 107 uint32_t hse_value = HSE_VALUE;
 108
 109 /**
 110   * @}
 111   */
 112
 113 /* Private typedef -----------------------------------------------------------*/
 114
 115 /** @addtogroup STM32F30x_System_Private_Defines
 116   * @{
 117   */
 118 /*!< Uncomment the following line if you need to relocate your vector Table in
 119      Internal SRAM. */
 120 /* #define VECT_TAB_SRAM */
 121 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
 122                                   This value must be a multiple of 0x200. */
 123 /**
 124   * @}
 125   */
 126
 127 /* Private macro -------------------------------------------------------------*/
 128
 129 /** @addtogroup STM32F30x_System_Private_Variables
 130   * @{
 131   */
 132
 133   uint32_t SystemCoreClock = 72000000;
 134
 135   __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 136
 137 /**
 138   * @}
 139   */
 140
 141 /** @addtogroup STM32F30x_System_Private_FunctionPrototypes
 142   * @{
 143   */
 144
 145 void SetSysClock(void);
 146
 147 /**
 148   * @}
 149   */
 150
 151 /** @addtogroup STM32F30x_System_Private_Functions
 152   * @{
 153   */
 154
 155 /**
 156   * @brief  Setup the microcontroller system
 157   *         Initialize the Embedded Flash Interface, the PLL and update the
 158   *         SystemFrequency variable.
 159   * @param  None
 160   * @retval None
 161   */
 162 void SystemInit(void)
 163 {
 164   initialiseMemorySections();
 165
 166   /* FPU settings ------------------------------------------------------------*/
 167   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
 168     SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
 169   #endif
 170
 171   /* Reset the RCC clock configuration to the default reset state ------------*/
 172   /* Set HSION bit */
 173   RCC->CR |= (uint32_t)0x00000001;
 174
 175   /* Reset CFGR register */
 176   RCC->CFGR &= 0xF87FC00C;
 177
 178   /* Reset HSEON, CSSON and PLLON bits */
 179   RCC->CR &= (uint32_t)0xFEF6FFFF;
 180
 181   /* Reset HSEBYP bit */
 182   RCC->CR &= (uint32_t)0xFFFBFFFF;
 183
 184   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
 185   RCC->CFGR &= (uint32_t)0xFF80FFFF;
 186
 187   /* Reset PREDIV1[3:0] bits */
 188   RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
 189
 190   /* Reset USARTSW[1:0], I2CSW and TIMs bits */
 191   RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
 192
 193   /* Disable all interrupts */
 194   RCC->CIR = 0x00000000;
 195
 196   /* Configure the System clock source, PLL Multiplier and Divider factors,
 197      AHB/APBx prescalers and Flash settings ----------------------------------*/
 198   //SetSysClock(); // called from main()
 199
 200 #ifdef VECT_TAB_SRAM
 201   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
 202 #else
 203   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
 204 #endif
 205
 206 #ifdef USE_HAL_DRIVER
 207     HAL_Init();
 208 #endif
 209 }
 210
 211 /**
 212    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 213   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 214   *         be used by the user application to setup the SysTick timer or configure
 215   *         other parameters.
 216   *
 217   * @note   Each time the core clock (HCLK) changes, this function must be called
 218   *         to update SystemCoreClock variable value. Otherwise, any configuration
 219   *         based on this variable will be incorrect.
 220   *
 221   * @note   - The system frequency computed by this function is not the real
 222   *           frequency in the chip. It is calculated based on the predefined
 223   *           constant and the selected clock source:
 224   *
 225   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 226   *
 227   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 228   *
 229   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 230   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 231   *
 232   *         (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
 233   *             8 MHz) but the real value may vary depending on the variations
 234   *             in voltage and temperature.
 235   *
 236   *         (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
 237   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
 238   *              frequency of the crystal used. Otherwise, this function may
 239   *              have wrong result.
 240   *
 241   *         - The result of this function could be not correct when using fractional
 242   *           value for HSE crystal.
 243   *
 244   * @param  None
 245   * @retval None
 246   */
 247 void SystemCoreClockUpdate (void)
 248 {
 249   uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
 250
 251   /* Get SYSCLK source -------------------------------------------------------*/
 252   tmp = RCC->CFGR & RCC_CFGR_SWS;
 253
 254   switch (tmp)
 255   {
 256     case 0x00:  /* HSI used as system clock */
 257       SystemCoreClock = HSI_VALUE;
 258       break;
 259     case 0x04:  /* HSE used as system clock */
 260       SystemCoreClock = HSE_VALUE;
 261       break;
 262     case 0x08:  /* PLL used as system clock */
 263       /* Get PLL clock source and multiplication factor ----------------------*/
 264       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
 265       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 266       pllmull = ( pllmull >> 18) + 2;
 267
 268       if (pllsource == 0x00)
 269       {
 270         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
 271         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
 272       }
 273       else
 274       {
 275         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
 276         /* HSE oscillator clock selected as PREDIV1 clock entry */
 277         SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
 278       }
 279       break;
 280     default: /* HSI used as system clock */
 281       SystemCoreClock = HSI_VALUE;
 282       break;
 283   }
 284   /* Compute HCLK clock frequency ----------------*/
 285   /* Get HCLK prescaler */
 286   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 287   /* HCLK clock frequency */
 288   SystemCoreClock >>= tmp;
 289 }
 290
 291 /**
 292   * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
 293   *               AHB/APBx prescalers and Flash settings
 294   * @note   This function should be called only once the RCC clock configuration
 295   *         is reset to the default reset state (done in SystemInit() function).
 296   * @param  None
 297   * @retval None
 298   */
 299 void SetSysClock(void)
 300 {
 301   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
 302
 303 /******************************************************************************/
 304 /*            PLL (clocked by HSE) used as System clock source                */
 305 /******************************************************************************/
 306
 307   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
 308   /* Enable HSE */
 309   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
 310
 311   /* Wait till HSE is ready and if Time out is reached exit */
 312   do
 313   {
 314     HSEStatus = RCC->CR & RCC_CR_HSERDY;
 315     StartUpCounter++;
 316   } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 317
 318   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
 319   {
 320     HSEStatus = (uint32_t)0x01;
 321   }
 322   else
 323   {
 324     HSEStatus = (uint32_t)0x00;
 325   }
 326
 327   if (HSEStatus == (uint32_t)0x01)
 328   {
 329     /* Enable Prefetch Buffer and set Flash Latency */
 330     FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
 331
 332      /* HCLK = SYSCLK / 1 */
 333      RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
 334
 335      /* PCLK2 = HCLK / 1 */
 336      RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
 337
 338      /* PCLK1 = HCLK / 2 */
 339      RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
 340
 341     /* PLL configuration */
 342     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
 343
 344     if (HSE_VALUE == 12000000) {
 345         RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);
 346     }
 347     else {
 348         RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
 349     }
 350
 351     /* Enable PLL */
 352     RCC->CR |= RCC_CR_PLLON;
 353
 354     /* Wait till PLL is ready */
 355     while ((RCC->CR & RCC_CR_PLLRDY) == 0)
 356     {
 357     }
 358
 359     /* Select PLL as system clock source */
 360     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
 361     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
 362
 363     /* Wait till PLL is used as system clock source */
 364     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
 365     {
 366     }
 367   }
 368   else
 369   { /* If HSE fails to start-up, the application will have wrong clock
 370          configuration. User can add here some code to deal with this error */
 371   }
 372 }
 373
 374 /**
 375   * @}
 376   */
 377
 378 /**
 379   * @}
 380   */
 381
 382 /**
 383   * @}
 384   */
 385
 386 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/