| blob | f92a619ad396860f91efc2aeea0df8d17371c10f |
1 /*
2 * This file is part of Betaflight.
3 *
4 * Betaflight is free software. You can redistribute this software
5 * and/or modify this software under the terms of the GNU General
6 * Public License as published by the Free Software Foundation,
7 * either version 3 of the License, or (at your option) any later
8 * version.
9 *
10 * Betaflight is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 * See the GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public
17 * License along with this software.
18 *
19 * If not, see <http://www.gnu.org/licenses/>.
20 */
22 #pragma once
27 #define USED_TIMERS ( BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(20) )
28 #define TIMUP_TIMERS ( BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(8) | BIT(20) )
29 #define FULL_TIMER_CHANNEL_COUNT 109
30 #define HARDWARE_TIMER_DEFINITION_COUNT 15
32 // allow conditional definition of DMA related members
33 #if defined(USE_TIMER_DMA)
34 # define DEF_TIM_DMA_COND(...) __VA_ARGS__
35 #else
36 # define DEF_TIM_DMA_COND(...)
37 #endif
39 #if defined(USE_TIMER_MGMT)
40 #define TIMER_GET_IO_TAG(pin) DEFIO_TAG_E(pin)
41 #else
42 #define TIMER_GET_IO_TAG(pin) DEFIO_TAG(pin)
43 #endif
45 // map to base channel (strip N from channel); works only when channel N exists
46 #define DEF_TIM_TCH2BTCH(timch) CONCAT(B, timch)
47 #define BTCH_TMR1_CH1N BTCH_TMR1_CH1
48 #define BTCH_TMR1_CH2N BTCH_TMR1_CH2
49 #define BTCH_TMR1_CH3N BTCH_TMR1_CH3
51 #define BTCH_TMR8_CH1N BTCH_TMR8_CH1
52 #define BTCH_TMR8_CH2N BTCH_TMR8_CH2
53 #define BTCH_TMR8_CH3N BTCH_TMR8_CH3
55 #define BTCH_TMR11_CH1N BTCH_TMR11_CH1
57 #define BTCH_TMR20_CH1N BTCH_TMR20_CH1
58 #define BTCH_TMR20_CH2N BTCH_TMR20_CH2
59 #define BTCH_TMR20_CH3N BTCH_TMR20_CH3
61 // channel table D(chan_n, n_type)
62 #define DEF_TIM_CH_GET(ch) CONCAT2(DEF_TIM_CH__, ch)
63 #define DEF_TIM_CH__CH_CH1 D(1, 0)
64 #define DEF_TIM_CH__CH_CH2 D(2, 0)
65 #define DEF_TIM_CH__CH_CH3 D(3, 0)
66 #define DEF_TIM_CH__CH_CH4 D(4, 0)
67 #define DEF_TIM_CH__CH_CH1N D(1, 1)
68 #define DEF_TIM_CH__CH_CH2N D(2, 1)
69 #define DEF_TIM_CH__CH_CH3N D(3, 1)
71 // timer table D(tim_n)
72 #define DEF_TIM_TIM_GET(tim) CONCAT2(DEF_TIM_TIM__, tim)
73 #define DEF_TIM_TIM__TIM_TMR1 D(1)
74 #define DEF_TIM_TIM__TIM_TMR2 D(2)
75 #define DEF_TIM_TIM__TIM_TMR3 D(3)
76 #define DEF_TIM_TIM__TIM_TMR4 D(4)
77 #define DEF_TIM_TIM__TIM_TMR5 D(5)
78 #define DEF_TIM_TIM__TIM_TMR6 D(6)
79 #define DEF_TIM_TIM__TIM_TMR7 D(7)
80 #define DEF_TIM_TIM__TIM_TMR8 D(8)
81 #define DEF_TIM_TIM__TIM_TMR9 D(9)
82 #define DEF_TIM_TIM__TIM_TMR10 D(10)
83 #define DEF_TIM_TIM__TIM_TMR11 D(11)
84 #define DEF_TIM_TIM__TIM_TMR12 D(12)
85 #define DEF_TIM_TIM__TIM_TMR13 D(13)
86 #define DEF_TIM_TIM__TIM_TMR14 D(14)
87 #define DEF_TIM_TIM__TIM_TMR15 D(15)
88 #define DEF_TIM_TIM__TIM_TMR16 D(16)
89 #define DEF_TIM_TIM__TIM_TMR17 D(17)
90 #define DEF_TIM_TIM__TIM_TMR18 D(18)
91 #define DEF_TIM_TIM__TIM_TMR19 D(19)
92 #define DEF_TIM_TIM__TIM_TMR20 D(20)
93 #define DEF_TIM_TIM__TIM_TMR21 D(21)
94 #define DEF_TIM_TIM__TIM_TMR22 D(22)
96 // Create accessor macro and call it with entry from table
97 // DMA_VARIANT_MISSING are used to satisfy variable arguments (-Wpedantic) and to get better error message (undefined symbol instead of preprocessor error)
98 #define DEF_TIM_DMA_GET(variant, timch) PP_CALL(CONCAT(DEF_TIM_DMA_GET_VARIANT__, variant), CONCAT(DEF_TIM_DMA__, DEF_TIM_TCH2BTCH(timch)), DMA_VARIANT_MISSING, DMA_VARIANT_MISSING, ERROR)
100 #define DEF_TIM_DMA_GET_VARIANT__0(_0, ...) _0
101 #define DEF_TIM_DMA_GET_VARIANT__1(_0, _1, ...) _1
102 #define DEF_TIM_DMA_GET_VARIANT__2(_0, _1, _2, ...) _2
103 #define DEF_TIM_DMA_GET_VARIANT__3(_0, _1, _2, _3, ...) _3
104 #define DEF_TIM_DMA_GET_VARIANT__4(_0, _1, _2, _3, _4, ...) _4
105 #define DEF_TIM_DMA_GET_VARIANT__5(_0, _1, _2, _3, _4, _5, ...) _5
106 #define DEF_TIM_DMA_GET_VARIANT__6(_0, _1, _2, _3, _4, _5, _6, ...) _6
107 #define DEF_TIM_DMA_GET_VARIANT__7(_0, _1, _2, _3, _4, _5, _6, _7, ...) _7
108 #define DEF_TIM_DMA_GET_VARIANT__8(_0, _1, _2, _3, _4, _5, _6, _7, _8, ...) _8
109 #define DEF_TIM_DMA_GET_VARIANT__9(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, ...) _9
110 #define DEF_TIM_DMA_GET_VARIANT__10(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, ...) _10
111 #define DEF_TIM_DMA_GET_VARIANT__11(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, ...) _11
112 #define DEF_TIM_DMA_GET_VARIANT__12(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, ...) _12
113 #define DEF_TIM_DMA_GET_VARIANT__13(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, ...) _13
114 #define DEF_TIM_DMA_GET_VARIANT__14(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, ...) _14
115 #define DEF_TIM_DMA_GET_VARIANT__15(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, ...) _15
117 // symbolic names for DMA variants
118 #define DMA_VAR0 0
119 #define DMA_VAR1 1
120 #define DMA_VAR2 2
122 // get record from AF table
123 // Parameters in D(...) are target-specific
124 #define DEF_TIM_AF_GET(timch, pin) CONCAT4(DEF_TIM_AF__, pin, __, timch)
126 //AF
127 #define DEF_TIM_AF(timch, pin) CONCAT(DEF_TIM_AF__, DEF_TIM_AF_GET(timch, pin))
130 // define output type (N-channel)
131 #define DEF_TIM_OUTPUT(ch) CONCAT(DEF_TIM_OUTPUT__, DEF_TIM_CH_GET(ch))
132 #define DEF_TIM_OUTPUT__D(chan_n, n_channel) PP_IIF(n_channel, TIMER_OUTPUT_N_CHANNEL, TIMER_OUTPUT_NONE)
134 /*
135 DEF_TIM(tim, chan, pin, flags, out, dmaopt, upopt)
136 @tim,
137 @chan tmr & channel
138 @pin output pin
139 @out 0 for normal 1 for N_Channel
140 @dmaopt dma channel index used for timer channel data transmit
141 @upopt USE_DSHOT_DMAR timeup dma channel index
142 */
143 #define DEF_TIM(tim, chan, pin, out, dmaopt, upopt) { \
144 tim, \
145 TIMER_GET_IO_TAG(pin), \
146 DEF_TIM_CHANNEL(CH_ ## chan), \
147 (DEF_TIM_OUTPUT(CH_ ## chan) | out), \
148 DEF_TIM_AF(TCH_## tim ## _ ## chan, pin) \
150 DEF_TIM_DMA_CHANNEL(dmaopt, TCH_## tim ## _ ## chan), \
151 DEF_TIM_DMA_REQUEST(TCH_## tim ## _ ## chan) \
152 ) \
154 DEF_TIM_DMA_CHANNEL(upopt, TCH_## tim ## _UP), \
155 DEF_TIM_DMA_REQUEST(TCH_## tim ## _UP), \
156 DEF_TIM_DMA_HANDLER(upopt, TCH_## tim ## _UP) \
157 ) \
158 }
159 /**/
161 //Channel
162 #define DEF_TIM_CHANNEL(ch) CONCAT(DEF_TIM_CHANNEL__, DEF_TIM_CH_GET(ch))
163 #define DEF_TIM_CHANNEL__D(chan_n, n_channel) chan_n
166 #define DEF_TIM_DMA_CHANNEL(variant, timch) \
167 CONCAT(DEF_TIM_DMA_CHANNEL__, DEF_TIM_DMA_GET(variant, timch))
168 #define DEF_TIM_DMA_CHANNEL__D(dma_n, channel_n) (dmaResource_t *)DMA ## dma_n ## _CHANNEL ## channel_n
169 #define DEF_TIM_DMA_CHANNEL__NONE NULL
171 #define DEF_TIM_DMA_REQUEST(timch) \
172 CONCAT(DEF_TIM_DMA_REQ__, DEF_TIM_TCH2BTCH(timch))
174 #define DEF_TIM_DMA_HANDLER(variant, timch) \
175 CONCAT(DEF_TIM_DMA_HANDLER__, DEF_TIM_DMA_GET(variant, timch))
176 #define DEF_TIM_DMA_HANDLER__D(dma_n, channel_n) DMA ## dma_n ## _CH ## channel_n ## _HANDLER
177 #define DEF_TIM_DMA_HANDLER__NONE 0
180 /* DMA Channel Mappings */
181 // D(DMAx, Stream)
182 // at32f43x has DMAMUX that allow arbitrary assignment of peripherals to streams.
183 #define DEF_TIM_DMA_FULL \
184 D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), \
185 D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7)
187 #define DEF_TIM_DMA__BTCH_TMR1_CH1 DEF_TIM_DMA_FULL
188 #define DEF_TIM_DMA__BTCH_TMR1_CH2 DEF_TIM_DMA_FULL
189 #define DEF_TIM_DMA__BTCH_TMR1_CH3 DEF_TIM_DMA_FULL
190 #define DEF_TIM_DMA__BTCH_TMR1_CH4 DEF_TIM_DMA_FULL
192 #define DEF_TIM_DMA__BTCH_TMR2_CH1 DEF_TIM_DMA_FULL
193 #define DEF_TIM_DMA__BTCH_TMR2_CH2 DEF_TIM_DMA_FULL
194 #define DEF_TIM_DMA__BTCH_TMR2_CH3 DEF_TIM_DMA_FULL
195 #define DEF_TIM_DMA__BTCH_TMR2_CH4 DEF_TIM_DMA_FULL
197 #define DEF_TIM_DMA__BTCH_TMR3_CH1 DEF_TIM_DMA_FULL
198 #define DEF_TIM_DMA__BTCH_TMR3_CH2 DEF_TIM_DMA_FULL
199 #define DEF_TIM_DMA__BTCH_TMR3_CH3 DEF_TIM_DMA_FULL
200 #define DEF_TIM_DMA__BTCH_TMR3_CH4 DEF_TIM_DMA_FULL
202 #define DEF_TIM_DMA__BTCH_TMR4_CH1 DEF_TIM_DMA_FULL
203 #define DEF_TIM_DMA__BTCH_TMR4_CH2 DEF_TIM_DMA_FULL
204 #define DEF_TIM_DMA__BTCH_TMR4_CH3 DEF_TIM_DMA_FULL
205 #define DEF_TIM_DMA__BTCH_TMR4_CH4 DEF_TIM_DMA_FULL
207 #define DEF_TIM_DMA__BTCH_TMR5_CH1 DEF_TIM_DMA_FULL
208 #define DEF_TIM_DMA__BTCH_TMR5_CH2 DEF_TIM_DMA_FULL
209 #define DEF_TIM_DMA__BTCH_TMR5_CH3 DEF_TIM_DMA_FULL
210 #define DEF_TIM_DMA__BTCH_TMR5_CH4 DEF_TIM_DMA_FULL
212 #define DEF_TIM_DMA__BTCH_TMR8_CH1 DEF_TIM_DMA_FULL
213 #define DEF_TIM_DMA__BTCH_TMR8_CH2 DEF_TIM_DMA_FULL
214 #define DEF_TIM_DMA__BTCH_TMR8_CH3 DEF_TIM_DMA_FULL
215 #define DEF_TIM_DMA__BTCH_TMR8_CH4 DEF_TIM_DMA_FULL
217 #define DEF_TIM_DMA__BTCH_TMR9_CH1 NONE
218 #define DEF_TIM_DMA__BTCH_TMR9_CH2 NONE
220 #define DEF_TIM_DMA__BTCH_TMR10_CH1 NONE
222 #define DEF_TIM_DMA__BTCH_TMR11_CH1 NONE
223 #define DEF_TIM_DMA__BTCH_TMR12_CH1 NONE
224 #define DEF_TIM_DMA__BTCH_TMR12_CH2 NONE
226 #define DEF_TIM_DMA__BTCH_TMR13_CH1 NONE
227 #define DEF_TIM_DMA__BTCH_TMR14_CH1 NONE
229 #define DEF_TIM_DMA__BTCH_TMR15_CH1 NONE
230 #define DEF_TIM_DMA__BTCH_TMR15_CH2 NONE
232 #define DEF_TIM_DMA__BTCH_TMR16_CH1 NONE
233 #define DEF_TIM_DMA__BTCH_TMR17_CH1 NONE
235 #define DEF_TIM_DMA__BTCH_TMR20_CH1 DEF_TIM_DMA_FULL
236 #define DEF_TIM_DMA__BTCH_TMR20_CH2 DEF_TIM_DMA_FULL
237 #define DEF_TIM_DMA__BTCH_TMR20_CH3 DEF_TIM_DMA_FULL
238 #define DEF_TIM_DMA__BTCH_TMR20_CH4 DEF_TIM_DMA_FULL
240 // TIM_UP table
241 #define DEF_TIM_DMA__BTCH_TMR1_UP DEF_TIM_DMA_FULL
242 #define DEF_TIM_DMA__BTCH_TMR2_UP DEF_TIM_DMA_FULL
243 #define DEF_TIM_DMA__BTCH_TMR3_UP DEF_TIM_DMA_FULL
244 #define DEF_TIM_DMA__BTCH_TMR4_UP DEF_TIM_DMA_FULL
245 #define DEF_TIM_DMA__BTCH_TMR5_UP DEF_TIM_DMA_FULL
246 #define DEF_TIM_DMA__BTCH_TMR6_UP DEF_TIM_DMA_FULL
247 #define DEF_TIM_DMA__BTCH_TMR7_UP DEF_TIM_DMA_FULL
248 #define DEF_TIM_DMA__BTCH_TMR8_UP DEF_TIM_DMA_FULL
249 #define DEF_TIM_DMA__BTCH_TMR9_UP NONE
250 #define DEF_TIM_DMA__BTCH_TMR10_UP NONE
251 #define DEF_TIM_DMA__BTCH_TMR11_UP NONE
252 #define DEF_TIM_DMA__BTCH_TMR12_UP NONE
253 #define DEF_TIM_DMA__BTCH_TMR13_UP NONE
254 #define DEF_TIM_DMA__BTCH_TMR14_UP NONE
255 #define DEF_TIM_DMA__BTCH_TMR15_UP NONE
256 #define DEF_TIM_DMA__BTCH_TMR16_UP NONE
257 #define DEF_TIM_DMA__BTCH_TMR17_UP NONE
258 #define DEF_TIM_DMA__BTCH_TMR20_UP DEF_TIM_DMA_FULL
260 // TIMx_CHy request table
262 #define DMA_REQUEST_NONE 255
264 #define DEF_TIM_DMA_REQ__BTCH_TMR1_CH1 DMAMUX_DMAREQ_ID_TMR1_CH1
265 #define DEF_TIM_DMA_REQ__BTCH_TMR1_CH2 DMAMUX_DMAREQ_ID_TMR1_CH2
266 #define DEF_TIM_DMA_REQ__BTCH_TMR1_CH3 DMAMUX_DMAREQ_ID_TMR1_CH3
267 #define DEF_TIM_DMA_REQ__BTCH_TMR1_CH4 DMAMUX_DMAREQ_ID_TMR1_CH4
269 #define DEF_TIM_DMA_REQ__BTCH_TMR2_CH1 DMAMUX_DMAREQ_ID_TMR2_CH1
270 #define DEF_TIM_DMA_REQ__BTCH_TMR2_CH2 DMAMUX_DMAREQ_ID_TMR2_CH2
271 #define DEF_TIM_DMA_REQ__BTCH_TMR2_CH3 DMAMUX_DMAREQ_ID_TMR2_CH3
272 #define DEF_TIM_DMA_REQ__BTCH_TMR2_CH4 DMAMUX_DMAREQ_ID_TMR2_CH4
274 #define DEF_TIM_DMA_REQ__BTCH_TMR3_CH1 DMAMUX_DMAREQ_ID_TMR3_CH1
275 #define DEF_TIM_DMA_REQ__BTCH_TMR3_CH2 DMAMUX_DMAREQ_ID_TMR3_CH2
276 #define DEF_TIM_DMA_REQ__BTCH_TMR3_CH3 DMAMUX_DMAREQ_ID_TMR3_CH3
277 #define DEF_TIM_DMA_REQ__BTCH_TMR3_CH4 DMAMUX_DMAREQ_ID_TMR3_CH4
279 #define DEF_TIM_DMA_REQ__BTCH_TMR4_CH1 DMAMUX_DMAREQ_ID_TMR4_CH1
280 #define DEF_TIM_DMA_REQ__BTCH_TMR4_CH2 DMAMUX_DMAREQ_ID_TMR4_CH2
281 #define DEF_TIM_DMA_REQ__BTCH_TMR4_CH3 DMAMUX_DMAREQ_ID_TMR4_CH3
282 #define DEF_TIM_DMA_REQ__BTCH_TMR4_CH4 DMAMUX_DMAREQ_ID_TMR4_CH4
284 #define DEF_TIM_DMA_REQ__BTCH_TMR5_CH1 DMAMUX_DMAREQ_ID_TMR5_CH1
285 #define DEF_TIM_DMA_REQ__BTCH_TMR5_CH2 DMAMUX_DMAREQ_ID_TMR5_CH2
286 #define DEF_TIM_DMA_REQ__BTCH_TMR5_CH3 DMAMUX_DMAREQ_ID_TMR5_CH3
287 #define DEF_TIM_DMA_REQ__BTCH_TMR5_CH4 DMAMUX_DMAREQ_ID_TMR5_CH4
289 #define DEF_TIM_DMA_REQ__BTCH_TMR8_CH1 DMAMUX_DMAREQ_ID_TMR8_CH1
290 #define DEF_TIM_DMA_REQ__BTCH_TMR8_CH2 DMAMUX_DMAREQ_ID_TMR8_CH2
291 #define DEF_TIM_DMA_REQ__BTCH_TMR8_CH3 DMAMUX_DMAREQ_ID_TMR8_CH3
292 #define DEF_TIM_DMA_REQ__BTCH_TMR8_CH4 DMAMUX_DMAREQ_ID_TMR8_CH4
294 #define DEF_TIM_DMA_REQ__BTCH_TMR9_CH1 DMA_REQUEST_NONE
295 #define DEF_TIM_DMA_REQ__BTCH_TMR9_CH2 DMA_REQUEST_NONE
296 #define DEF_TIM_DMA_REQ__BTCH_TMR10_CH1 DMA_REQUEST_NONE
297 #define DEF_TIM_DMA_REQ__BTCH_TMR11_CH1 DMA_REQUEST_NONE
299 #define DEF_TIM_DMA_REQ__BTCH_TMR12_CH1 DMA_REQUEST_NONE
300 #define DEF_TIM_DMA_REQ__BTCH_TMR12_CH2 DMA_REQUEST_NONE
302 #define DEF_TIM_DMA_REQ__BTCH_TMR13_CH1 DMA_REQUEST_NONE
303 #define DEF_TIM_DMA_REQ__BTCH_TMR14_CH1 DMA_REQUEST_NONE
305 #define DEF_TIM_DMA_REQ__BTCH_TMR20_CH1 DMAMUX_DMAREQ_ID_TMR20_CH1
306 #define DEF_TIM_DMA_REQ__BTCH_TMR20_CH2 DMAMUX_DMAREQ_ID_TMR20_CH2
307 #define DEF_TIM_DMA_REQ__BTCH_TMR20_CH3 DMAMUX_DMAREQ_ID_TMR20_CH3
308 #define DEF_TIM_DMA_REQ__BTCH_TMR20_CH4 DMAMUX_DMAREQ_ID_TMR20_CH4
310 // TIM_UP request table
311 #define DEF_TIM_DMA_REQ__BTCH_TMR1_UP DMAMUX_DMAREQ_ID_TMR1_OVERFLOW
312 #define DEF_TIM_DMA_REQ__BTCH_TMR2_UP DMAMUX_DMAREQ_ID_TMR2_OVERFLOW
313 #define DEF_TIM_DMA_REQ__BTCH_TMR3_UP DMAMUX_DMAREQ_ID_TMR3_OVERFLOW
314 #define DEF_TIM_DMA_REQ__BTCH_TMR4_UP DMAMUX_DMAREQ_ID_TMR4_OVERFLOW
315 #define DEF_TIM_DMA_REQ__BTCH_TMR5_UP DMAMUX_DMAREQ_ID_TMR5_OVERFLOW
316 #define DEF_TIM_DMA_REQ__BTCH_TMR8_UP DMAMUX_DMAREQ_ID_TMR8_OVERFLOW
317 #define DEF_TIM_DMA_REQ__BTCH_TMR9_UP DMA_REQUEST_NONE
318 #define DEF_TIM_DMA_REQ__BTCH_TMR10_UP DMA_REQUEST_NONE
319 #define DEF_TIM_DMA_REQ__BTCH_TMR11_UP DMA_REQUEST_NONE
320 #define DEF_TIM_DMA_REQ__BTCH_TMR12_UP DMA_REQUEST_NONE
321 #define DEF_TIM_DMA_REQ__BTCH_TMR13_UP DMA_REQUEST_NONE
322 #define DEF_TIM_DMA_REQ__BTCH_TMR14_UP DMA_REQUEST_NONE
323 #define DEF_TIM_DMA_REQ__BTCH_TMR20_UP DMAMUX_DMAREQ_ID_TMR20_OVERFLOW
325 // AF table for timer ,default is GPIO_MUX_1 should be check after debug
327 //NONE d(mux_id, timerid)
328 #define DEF_TIM_AF__NONE__TCH_TMR1_CH1 D(1, 1)
329 #define DEF_TIM_AF__NONE__TCH_TMR1_CH2 D(1, 1)
330 #define DEF_TIM_AF__NONE__TCH_TMR1_CH3 D(1, 1)
331 #define DEF_TIM_AF__NONE__TCH_TMR1_CH4 D(1, 1)
332 #define DEF_TIM_AF__NONE__TCH_TMR8_CH1 D(1, 8)
333 #define DEF_TIM_AF__NONE__TCH_TMR8_CH2 D(1, 8)
334 #define DEF_TIM_AF__NONE__TCH_TMR8_CH3 D(1, 8)
335 #define DEF_TIM_AF__NONE__TCH_TMR8_CH4 D(1, 8)
337 //PORTA MUX 1
338 #define DEF_TIM_AF__PA0__TCH_TMR2_CH1 D(1, 2)
339 #define DEF_TIM_AF__PA1__TCH_TMR2_CH2 D(1, 2)
340 #define DEF_TIM_AF__PA2__TCH_TMR2_CH3 D(1, 2)
341 #define DEF_TIM_AF__PA3__TCH_TMR2_CH4 D(1, 2)
342 #define DEF_TIM_AF__PA5__TCH_TMR2_CH1 D(1, 2)
343 #define DEF_TIM_AF__PA7__TCH_TMR1_CH1N D(1, 1)
344 #define DEF_TIM_AF__PA8__TCH_TMR1_CH1 D(1, 1)
345 #define DEF_TIM_AF__PA9__TCH_TMR1_CH2 D(1, 1)
346 #define DEF_TIM_AF__PA10__TCH_TMR1_CH3 D(1, 1)
347 #define DEF_TIM_AF__PA11__TCH_TMR1_CH4 D(1, 1)
348 #define DEF_TIM_AF__PA15__TCH_TMR2_CH1 D(1, 2)
350 //PORTA MUX 2
351 #define DEF_TIM_AF__PA0__TCH_TMR5_CH1 D(2, 5)
352 #define DEF_TIM_AF__PA1__TCH_TMR5_CH2 D(2, 5)
353 #define DEF_TIM_AF__PA2__TCH_TMR5_CH3 D(2, 5)
354 #define DEF_TIM_AF__PA3__TCH_TMR5_CH4 D(2, 5)
355 #define DEF_TIM_AF__PA6__TCH_TMR3_CH1 D(2, 3)
356 #define DEF_TIM_AF__PA7__TCH_TMR3_CH2 D(2, 3)
358 // PORTA MUX 3
359 #define DEF_TIM_AF__PA0__TCH_TMR8_EXT D(1, 8)
360 #define DEF_TIM_AF__PA2__TCH_TMR9_CH1 D(3, 9)
361 #define DEF_TIM_AF__PA3__TCH_TMR9_CH2 D(3, 9)
362 #define DEF_TIM_AF__PA5__TCH_TMR8_CH1N D(3, 8)
363 #define DEF_TIM_AF__PA7__TCH_TMR8_CH1N D(3, 8)
365 // PORTA MUX 9
366 #define DEF_TIM_AF__PA6__TCH_TMR13_CH1 D(9, 13)
367 #define DEF_TIM_AF__PA7__TCH_TMR14_CH1 D(9, 14)
369 // PORTB MUX 1
370 #define DEF_TIM_AF__PB0__TCH_TMR1_CH2N D(1, 1)
371 #define DEF_TIM_AF__PB1__TCH_TMR1_CH3N D(1, 1)
372 #define DEF_TIM_AF__PB2__TCH_TMR2_CH4 D(1, 2)
373 #define DEF_TIM_AF__PB3__TCH_TMR2_CH2 D(1, 2)
374 #define DEF_TIM_AF__PB8__TCH_TMR2_CH1 D(1, 2)
375 #define DEF_TIM_AF__PB9__TCH_TMR2_CH2 D(1, 2)
376 #define DEF_TIM_AF__PB10__TCH_TMR2_CH3 D(1, 2)
377 #define DEF_TIM_AF__PB11__TCH_TMR2_CH4 D(1, 2)
378 #define DEF_TIM_AF__PB13__TCH_TMR1_CH1N D(1, 1)
379 #define DEF_TIM_AF__PB14__TCH_TMR1_CH2N D(1, 1)
380 #define DEF_TIM_AF__PB15__TCH_TMR1_CH3N D(1, 1)
382 // PORTB MUX 2
383 #define DEF_TIM_AF__PB0__TCH_TMR3_CH3 D(2, 3)
384 #define DEF_TIM_AF__PB1__TCH_TMR3_CH4 D(2, 3)
385 #define DEF_TIM_AF__PB2__TCH_TMR20_CH1 D(2, 20)
386 #define DEF_TIM_AF__PB4__TCH_TMR3_CH1 D(2, 3)
387 #define DEF_TIM_AF__PB5__TCH_TMR3_CH2 D(2, 3)
388 #define DEF_TIM_AF__PB6__TCH_TMR4_CH1 D(2, 4)
389 #define DEF_TIM_AF__PB7__TCH_TMR4_CH2 D(2, 4)
390 #define DEF_TIM_AF__PB8__TCH_TMR4_CH3 D(2, 4)
391 #define DEF_TIM_AF__PB9__TCH_TMR4_CH4 D(2, 4)
392 #define DEF_TIM_AF__PB11__TCH_TMR5_CH4 D(2, 5)
393 #define DEF_TIM_AF__PB12__TCH_TMR5_CH1 D(2, 5)
395 // PORTB MUX 3
396 #define DEF_TIM_AF__PB0__TCH_TMR8_CH2N D(3, 8)
397 #define DEF_TIM_AF__PB1__TCH_TMR8_CH3N D(3, 8)
398 #define DEF_TIM_AF__PB8__TCH_TMR10_CH1 D(3, 10)
399 #define DEF_TIM_AF__PB9__TCH_TMR11_CH1 D(3, 11)
400 #define DEF_TIM_AF__PB14__TCH_TMR8_CH2N D(3, 8)
401 #define DEF_TIM_AF__PB15__TCH_TMR8_CH3N D(3, 8)
403 // PORTB MUX 9
404 #define DEF_TIM_AF__PB14__TCH_TMR12_CH1 D(9, 12)
405 #define DEF_TIM_AF__PB15__TCH_TMR12_CH2 D(9, 12)
407 // PORTC MUX 2
408 #define DEF_TIM_AF__PC2__TCH_TMR20_CH2 D(2, 20)
409 #define DEF_TIM_AF__PC6__TCH_TMR3_CH1 D(2, 3)
410 #define DEF_TIM_AF__PC7__TCH_TMR3_CH2 D(2, 3)
411 #define DEF_TIM_AF__PC8__TCH_TMR3_CH3 D(2, 3)
412 #define DEF_TIM_AF__PC9__TCH_TMR3_CH4 D(2, 3)
413 #define DEF_TIM_AF__PC10__TCH_TMR5_CH2 D(2, 5)
414 #define DEF_TIM_AF__PC11__TCH_TMR5_CH3 D(2, 5)
416 // PORTC MUX 3
417 #define DEF_TIM_AF__PC4__TCH_TMR9_CH1 D(3, 9)
418 #define DEF_TIM_AF__PC5__TCH_TMR9_CH2 D(3, 9)
419 #define DEF_TIM_AF__PC6__TCH_TMR8_CH1 D(3, 8)
420 #define DEF_TIM_AF__PC7__TCH_TMR8_CH2 D(3, 8)
421 #define DEF_TIM_AF__PC8__TCH_TMR8_CH3 D(3, 8)
422 #define DEF_TIM_AF__PC9__TCH_TMR8_CH4 D(3, 8)
423 #define DEF_TIM_AF__PC12__TCH_TMR11_CH1N D(3, 11)
425 // PORTD MUX 2
426 #define DEF_TIM_AF__PD12__TCH_TMR4_CH1 D(2, 4)
427 #define DEF_TIM_AF__PD13__TCH_TMR4_CH2 D(2, 4)
428 #define DEF_TIM_AF__PD14__TCH_TMR4_CH3 D(2, 4)
429 #define DEF_TIM_AF__PD15__TCH_TMR4_CH4 D(2, 4)
431 // PORTE MUX 1
432 #define DEF_TIM_AF__PE1__TCH_TMR1_CH2N D(1, 1)
433 #define DEF_TIM_AF__PE7__TCH_TMR1_EXT D(1, 1)
434 #define DEF_TIM_AF__PE8__TCH_TMR1_CH1N D(1, 1)
435 #define DEF_TIM_AF__PE9__TCH_TMR1_CH1 D(1, 1)
436 #define DEF_TIM_AF__PE10__TCH_TMR1_CH2N D(1, 1)
437 #define DEF_TIM_AF__PE11__TCH_TMR1_CH2 D(1, 1)
438 #define DEF_TIM_AF__PE12__TCH_TMR1_CH3N D(1, 1)
439 #define DEF_TIM_AF__PE13__TCH_TMR1_CH3 D(1, 1)
440 #define DEF_TIM_AF__PE14__TCH_TMR1_CH4 D(1, 1)
441 #define DEF_TIM_AF__PE15__TCH_TMR1_BRK D(1, 1)
443 // PORTE MUX 2
444 #define DEF_TIM_AF__PE0__TCH_TMR4_EXT D(2, 4)
445 #define DEF_TIM_AF__PE2__TCH_TMR3_EXT D(2, 3)
446 #define DEF_TIM_AF__PE3__TCH_TMR3_CH1 D(2, 3)
447 #define DEF_TIM_AF__PE4__TCH_TMR3_CH2 D(2, 3)
448 #define DEF_TIM_AF__PE5__TCH_TMR3_CH3 D(2, 3)
449 #define DEF_TIM_AF__PE6__TCH_TMR3_CH4 D(2, 3)
451 // PORTE MUX 3
452 #define DEF_TIM_AF__PE5__TCH_TMR9_CH1 D(2, 9)
453 #define DEF_TIM_AF__PE6__TCH_TMR9_CH2 D(2, 9)
455 // PORTE MUX 6
456 #define DEF_TIM_AF__PE0__TCH_TMR20_EXT D(6, 20)
457 #define DEF_TIM_AF__PE1__TCH_TMR20_CH4 D(6, 20)
458 #define DEF_TIM_AF__PE2__TCH_TMR20_CH1 D(6, 20)
459 #define DEF_TIM_AF__PE3__TCH_TMR20_CH2 D(6, 20)
460 #define DEF_TIM_AF__PE4__TCH_TMR20_CH1N D(6, 20)
461 #define DEF_TIM_AF__PE5__TCH_TMR20_CH2N D(6, 20)
462 #define DEF_TIM_AF__PE6__TCH_TMR20_CH3N D(6, 20)
464 // PORTF MUX 1
465 #define DEF_TIM_AF__PF10__TCH_TMR1_EXT D(2, 1)
467 // PORTF MUX 2
468 #define DEF_TIM_AF__PF2__TCH_TMR20_CH3 D(2, 20)
469 #define DEF_TIM_AF__PF3__TCH_TMR20_CH4 D(2, 20)
470 #define DEF_TIM_AF__PF4__TCH_TMR20_CH1N D(2, 20)
471 #define DEF_TIM_AF__PF5__TCH_TMR20_CH2N D(2, 20)
472 #define DEF_TIM_AF__PF6__TCH_TMR20_CH4 D(2, 20)
473 #define DEF_TIM_AF__PF7__TCH_TMR20_BRK D(2, 20)
474 #define DEF_TIM_AF__PF9__TCH_TMR20_BRK D(2, 20)
475 #define DEF_TIM_AF__PF11__TCH_TMR20_EST D(2, 20)
476 #define DEF_TIM_AF__PF12__TCH_TMR20_CH1 D(2, 20)
477 #define DEF_TIM_AF__PF13__TCH_TMR20_CH2 D(2, 20)
478 #define DEF_TIM_AF__PF14__TCH_TMR20_CH3 D(2, 20)
479 #define DEF_TIM_AF__PF15__TCH_TMR20_CH4 D(2, 20)
481 // PORTF MUX 3
482 #define DEF_TIM_AF__PF6__TCH_TMR10_CH1 D(3, 10)
483 #define DEF_TIM_AF__PF7__TCH_TMR11_CH1 D(3, 11)
484 #define DEF_TIM_AF__PF11__TCH_TMR8_EST D(3, 8)
485 #define DEF_TIM_AF__PF12__TCH_TMR8_BRK D(3, 8)
487 // PORTF MUX 9
488 #define DEF_TIM_AF__PF8__TCH_TMR13_CH1 D(9, 13)
489 #define DEF_TIM_AF__PF9__TCH_TMR14_CH1 D(9, 14)
491 // PORTG MUX 2
492 #define DEF_TIM_AF__PG0__TCH_TMR20_CH1N D(2, 20)
493 #define DEF_TIM_AF__PG1__TCH_TMR20_CH2N D(2, 20)
494 #define DEF_TIM_AF__PG2__TCH_TMR20_CH3N D(2, 20)
495 #define DEF_TIM_AF__PG3__TCH_TMR20_BRK D(2, 20)
496 #define DEF_TIM_AF__PG5__TCH_TMR20_EXT D(2, 20)
498 // PORTH MUX 2
499 #define DEF_TIM_AF__PH2__TCH_TMR5_CH1 D(2, 5)
500 #define DEF_TIM_AF__PH3__TCH_TMR5_CH2 D(2, 5)