?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Increment eeprom version
[betaflight.git] / lib / main / STM32F1 / Drivers / STM32F1xx_HAL_Driver / Inc / stm32f1xx_hal_cec.h
blob46dc53bdda873339b76e426d0351722529a8a7c5
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_cec.h
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 12-May-2017
7 * @brief Header file of CEC HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F1xx_HAL_CEC_H
40 #define __STM32F1xx_HAL_CEC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 #if defined(STM32F100xB) || defined(STM32F100xE)
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32f1xx_hal_def.h"
49
50 /** @addtogroup STM32F1xx_HAL_Driver
51 * @{
52 */
53
54 /** @addtogroup CEC
55 * @{
56 */
57
58 /* Exported types ------------------------------------------------------------*/
59 /** @defgroup CEC_Exported_Types CEC Exported Types
60 * @{
61 */
62 /**
63 * @brief CEC Init Structure definition
64 */
65 typedef struct
66 {
67 uint32_t TimingErrorFree; /*!< Configures the CEC Bit Timing Error Mode.
68 This parameter can be a value of @ref CEC_BitTimingErrorMode */
69 uint32_t PeriodErrorFree; /*!< Configures the CEC Bit Period Error Mode.
70 This parameter can be a value of @ref CEC_BitPeriodErrorMode */
71 uint16_t OwnAddress; /*!< Own addresses configuration
72 This parameter can be a value of @ref CEC_OWN_ADDRESS */
73 uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
74 }CEC_InitTypeDef;
75
76 /**
77 * @brief HAL CEC State structures definition
78 * @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
79 * - gState contains CEC state information related to global Handle management
80 * and also information related to Tx operations.
81 * gState value coding follow below described bitmap :
82 * b7 (not used)
83 * x : Should be set to 0
84 * b6 Error information
85 * 0 : No Error
86 * 1 : Error
87 * b5 IP initilisation status
88 * 0 : Reset (IP not initialized)
89 * 1 : Init done (IP initialized. HAL CEC Init function already called)
90 * b4-b3 (not used)
91 * xx : Should be set to 00
92 * b2 Intrinsic process state
93 * 0 : Ready
94 * 1 : Busy (IP busy with some configuration or internal operations)
95 * b1 (not used)
96 * x : Should be set to 0
97 * b0 Tx state
98 * 0 : Ready (no Tx operation ongoing)
99 * 1 : Busy (Tx operation ongoing)
100 * - RxState contains information related to Rx operations.
101 * RxState value coding follow below described bitmap :
102 * b7-b6 (not used)
103 * xx : Should be set to 00
104 * b5 IP initilisation status
105 * 0 : Reset (IP not initialized)
106 * 1 : Init done (IP initialized)
107 * b4-b2 (not used)
108 * xxx : Should be set to 000
109 * b1 Rx state
110 * 0 : Ready (no Rx operation ongoing)
111 * 1 : Busy (Rx operation ongoing)
112 * b0 (not used)
113 * x : Should be set to 0.
114 */
115 typedef enum
116 {
117 HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
118 Value is allowed for gState and RxState */
119 HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
120 Value is allowed for gState and RxState */
121 HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
122 Value is allowed for gState only */
123 HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
124 Value is allowed for RxState only */
125 HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
126 Value is allowed for gState only */
127 HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
128 Value is allowed for gState only */
129 HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
130 }HAL_CEC_StateTypeDef;
131
132 /**
133 * @brief CEC handle Structure definition
134 */
135 typedef struct
136 {
137 CEC_TypeDef *Instance; /*!< CEC registers base address */
138
139 CEC_InitTypeDef Init; /*!< CEC communication parameters */
140
141 uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
142
143 uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
144
145 uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
146
147 HAL_LockTypeDef Lock; /*!< Locking object */
148
149 HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
150 and also related to Tx operations.
151 This parameter can be a value of @ref HAL_CEC_StateTypeDef */
152
153 HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
154 This parameter can be a value of @ref HAL_CEC_StateTypeDef */
155
156 uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
157 in case error is reported */
158 }CEC_HandleTypeDef;
159 /**
160 * @}
161 */
162
163 /* Exported constants --------------------------------------------------------*/
164 /** @defgroup CEC_Exported_Constants CEC Exported Constants
165 * @{
166 */
167
168 /** @defgroup CEC_Error_Code CEC Error Code
169 * @{
170 */
171 #define HAL_CEC_ERROR_NONE 0x00000000U /*!< no error */
172 #define HAL_CEC_ERROR_BTE CEC_ESR_BTE /*!< Bit Timing Error */
173 #define HAL_CEC_ERROR_BPE CEC_ESR_BPE /*!< Bit Period Error */
174 #define HAL_CEC_ERROR_RBTFE CEC_ESR_RBTFE /*!< Rx Block Transfer Finished Error */
175 #define HAL_CEC_ERROR_SBE CEC_ESR_SBE /*!< Start Bit Error */
176 #define HAL_CEC_ERROR_ACKE CEC_ESR_ACKE /*!< Block Acknowledge Error */
177 #define HAL_CEC_ERROR_LINE CEC_ESR_LINE /*!< Line Error */
178 #define HAL_CEC_ERROR_TBTFE CEC_ESR_TBTFE /*!< Tx Block Transfer Finished Error */
179 /**
180 * @}
181 */
182
183 /** @defgroup CEC_BitTimingErrorMode Bit Timing Error Mode
184 * @{
185 */
186 #define CEC_BIT_TIMING_ERROR_MODE_STANDARD 0x00000000U /*!< Bit timing error Standard Mode */
187 #define CEC_BIT_TIMING_ERROR_MODE_ERRORFREE CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
188 /**
189 * @}
190 */
191
192 /** @defgroup CEC_BitPeriodErrorMode Bit Period Error Mode
193 * @{
194 */
195 #define CEC_BIT_PERIOD_ERROR_MODE_STANDARD 0x00000000U /*!< Bit period error Standard Mode */
196 #define CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
197 /**
198 * @}
199 */
200
201 /** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
202 * @{
203 */
204 #define CEC_INITIATOR_LSB_POS 4U
205 /**
206 * @}
207 */
208
209 /** @defgroup CEC_OWN_ADDRESS CEC Own Address
210 * @{
211 */
212 #define CEC_OWN_ADDRESS_NONE CEC_OWN_ADDRESS_0 /* Reset value */
213 #define CEC_OWN_ADDRESS_0 ((uint16_t)0x0000U) /* Logical Address 0 */
214 #define CEC_OWN_ADDRESS_1 ((uint16_t)0x0001U) /* Logical Address 1 */
215 #define CEC_OWN_ADDRESS_2 ((uint16_t)0x0002U) /* Logical Address 2 */
216 #define CEC_OWN_ADDRESS_3 ((uint16_t)0x0003U) /* Logical Address 3 */
217 #define CEC_OWN_ADDRESS_4 ((uint16_t)0x0004U) /* Logical Address 4 */
218 #define CEC_OWN_ADDRESS_5 ((uint16_t)0x0005U) /* Logical Address 5 */
219 #define CEC_OWN_ADDRESS_6 ((uint16_t)0x0006U) /* Logical Address 6 */
220 #define CEC_OWN_ADDRESS_7 ((uint16_t)0x0007U) /* Logical Address 7 */
221 #define CEC_OWN_ADDRESS_8 ((uint16_t)0x0008U) /* Logical Address 8 */
222 #define CEC_OWN_ADDRESS_9 ((uint16_t)0x0009U) /* Logical Address 9 */
223 #define CEC_OWN_ADDRESS_10 ((uint16_t)0x000AU) /* Logical Address 10 */
224 #define CEC_OWN_ADDRESS_11 ((uint16_t)0x000BU) /* Logical Address 11 */
225 #define CEC_OWN_ADDRESS_12 ((uint16_t)0x000CU) /* Logical Address 12 */
226 #define CEC_OWN_ADDRESS_13 ((uint16_t)0x000DU) /* Logical Address 13 */
227 #define CEC_OWN_ADDRESS_14 ((uint16_t)0x000EU) /* Logical Address 14 */
228 #define CEC_OWN_ADDRESS_15 ((uint16_t)0x000FU) /* Logical Address 15 */
229 /**
230 * @}
231 */
232
233 /** @defgroup CEC_Interrupts_Definitions Interrupts definition
234 * @{
235 */
236 #define CEC_IT_IE CEC_CFGR_IE
237 /**
238 * @}
239 */
240
241 /** @defgroup CEC_Flags_Definitions Flags definition
242 * @{
243 */
244 #define CEC_FLAG_TSOM CEC_CSR_TSOM
245 #define CEC_FLAG_TEOM CEC_CSR_TEOM
246 #define CEC_FLAG_TERR CEC_CSR_TERR
247 #define CEC_FLAG_TBTRF CEC_CSR_TBTRF
248 #define CEC_FLAG_RSOM CEC_CSR_RSOM
249 #define CEC_FLAG_REOM CEC_CSR_REOM
250 #define CEC_FLAG_RERR CEC_CSR_RERR
251 #define CEC_FLAG_RBTF CEC_CSR_RBTF
252 /**
253 * @}
254 */
255
256 /**
257 * @}
258 */
259
260 /* Exported macros -----------------------------------------------------------*/
261 /** @defgroup CEC_Exported_Macros CEC Exported Macros
262 * @{
263 */
264
265 /** @brief Reset CEC handle gstate & RxState
266 * @param __HANDLE__: CEC handle.
267 * @retval None
268 */
269 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
270 (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
271 (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
272 } while(0U)
273
274 /** @brief Checks whether or not the specified CEC interrupt flag is set.
275 * @param __HANDLE__: specifies the CEC Handle.
276 * @param __FLAG__: specifies the flag to check.
277 * @arg CEC_FLAG_TERR: Tx Error
278 * @arg CEC_FLAG_TBTRF:Tx Block Transfer Finished
279 * @arg CEC_FLAG_RERR: Rx Error
280 * @arg CEC_FLAG_RBTF: Rx Block Transfer Finished
281 * @retval ITStatus
282 */
283 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) READ_BIT((__HANDLE__)->Instance->CSR,(__FLAG__))
284
285 /** @brief Clears the CEC's pending flags.
286 * @param __HANDLE__: specifies the CEC Handle.
287 * @param __FLAG__: specifies the flag to clear.
288 * This parameter can be any combination of the following values:
289 * @arg CEC_CSR_TERR: Tx Error
290 * @arg CEC_FLAG_TBTRF: Tx Block Transfer Finished
291 * @arg CEC_CSR_RERR: Rx Error
292 * @arg CEC_CSR_RBTF: Rx Block Transfer Finished
293 * @retval none
294 */
295 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
296 do { \
297 uint32_t tmp = 0x0U; \
298 tmp = (__HANDLE__)->Instance->CSR & 0x00000002U; \
299 (__HANDLE__)->Instance->CSR &= (uint32_t)(((~(uint32_t)(__FLAG__)) & 0xFFFFFFFCU) | tmp);\
300 } while(0U)
301
302 /** @brief Enables the specified CEC interrupt.
303 * @param __HANDLE__: specifies the CEC Handle.
304 * @param __INTERRUPT__: specifies the CEC interrupt to enable.
305 * This parameter can be:
306 * @arg CEC_IT_IE : Interrupt Enable.
307 * @retval none
308 */
309 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
310
311 /** @brief Disables the specified CEC interrupt.
312 * @param __HANDLE__: specifies the CEC Handle.
313 * @param __INTERRUPT__: specifies the CEC interrupt to disable.
314 * This parameter can be:
315 * @arg CEC_IT_IE : Interrupt Enable
316 * @retval none
317 */
318 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
319
320 /** @brief Checks whether or not the specified CEC interrupt is enabled.
321 * @param __HANDLE__: specifies the CEC Handle.
322 * @param __INTERRUPT__: specifies the CEC interrupt to check.
323 * This parameter can be:
324 * @arg CEC_IT_IE : Interrupt Enable
325 * @retval FlagStatus
326 */
327 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) READ_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
328
329 /** @brief Enables the CEC device
330 * @param __HANDLE__: specifies the CEC Handle.
331 * @retval none
332 */
333 #define __HAL_CEC_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
334
335 /** @brief Disables the CEC device
336 * @param __HANDLE__: specifies the CEC Handle.
337 * @retval none
338 */
339 #define __HAL_CEC_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
340
341 /** @brief Set Transmission Start flag
342 * @param __HANDLE__: specifies the CEC Handle.
343 * @retval none
344 */
345 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
346
347 /** @brief Set Transmission End flag
348 * @param __HANDLE__: specifies the CEC Handle.
349 * @retval none
350 */
351 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
352
353 /** @brief Get Transmission Start flag
354 * @param __HANDLE__: specifies the CEC Handle.
355 * @retval FlagStatus
356 */
357 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
358
359 /** @brief Get Transmission End flag
360 * @param __HANDLE__: specifies the CEC Handle.
361 * @retval FlagStatus
362 */
363 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
364
365 /** @brief Clear OAR register
366 * @param __HANDLE__: specifies the CEC Handle.
367 * @retval none
368 */
369 #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->OAR, CEC_OAR_OA)
370
371 /** @brief Set OAR register
372 * @param __HANDLE__: specifies the CEC Handle.
373 * @param __ADDRESS__: Own Address value.
374 * @retval none
375 */
376 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) MODIFY_REG((__HANDLE__)->Instance->OAR, CEC_OAR_OA, (__ADDRESS__));
377
378 /**
379 * @}
380 */
381
382 /* Exported functions --------------------------------------------------------*/
383 /** @addtogroup CEC_Exported_Functions CEC Exported Functions
384 * @{
385 */
386
387 /** @addtogroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
388 * @brief Initialization and Configuration functions
389 * @{
390 */
391 /* Initialization and de-initialization functions ****************************/
392 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
393 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
394 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
395 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
396 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
397 /**
398 * @}
399 */
400
401 /** @addtogroup CEC_Exported_Functions_Group2 Input and Output operation functions
402 * @brief CEC Transmit/Receive functions
403 * @{
404 */
405 /* I/O operation functions ***************************************************/
406 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
407 uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
408 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
409 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
410 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
411 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
412 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
413 /**
414 * @}
415 */
416
417 /** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions
418 * @brief CEC control functions
419 * @{
420 */
421 /* Peripheral State and Error functions ***************************************/
422 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
423 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
424 /**
425 * @}
426 */
427
428 /**
429 * @}
430 */
431
432 /* Private types -------------------------------------------------------------*/
433 /** @defgroup CEC_Private_Types CEC Private Types
434 * @{
435 */
436
437 /**
438 * @}
439 */
440
441 /* Private variables ---------------------------------------------------------*/
442 /** @defgroup CEC_Private_Variables CEC Private Variables
443 * @{
444 */
445
446 /**
447 * @}
448 */
449
450 /* Private constants ---------------------------------------------------------*/
451 /** @defgroup CEC_Private_Constants CEC Private Constants
452 * @{
453 */
454
455 /**
456 * @}
457 */
458
459 /* Private macros ------------------------------------------------------------*/
460 /** @defgroup CEC_Private_Macros CEC Private Macros
461 * @{
462 */
463 #define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BIT_TIMING_ERROR_MODE_STANDARD) || \
464 ((MODE) == CEC_BIT_TIMING_ERROR_MODE_ERRORFREE))
465
466 #define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BIT_PERIOD_ERROR_MODE_STANDARD) || \
467 ((MODE) == CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE))
468
469 /** @brief Check CEC message size.
470 * The message size is the payload size: without counting the header,
471 * it varies from 0 byte (ping operation, one header only, no payload) to
472 * 15 bytes (1 opcode and up to 14 operands following the header).
473 * @param __SIZE__: CEC message size.
474 * @retval Test result (TRUE or FALSE).
475 */
476 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
477 /** @brief Check CEC device Own Address Register (OAR) setting.
478 * @param __ADDRESS__: CEC own address.
479 * @retval Test result (TRUE or FALSE).
480 */
481 #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
482
483 /** @brief Check CEC initiator or destination logical address setting.
484 * Initiator and destination addresses are coded over 4 bits.
485 * @param __ADDRESS__: CEC initiator or logical address.
486 * @retval Test result (TRUE or FALSE).
487 */
488 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
489
490
491
492 /**
493 * @}
494 */
495 /* Private functions ---------------------------------------------------------*/
496 /** @defgroup CEC_Private_Functions CEC Private Functions
497 * @{
498 */
499
500 /**
501 * @}
502 */
503
504 /**
505 * @}
506 */
507
508 /**
509 * @}
510 */
511 #endif /* defined(STM32F100xB) || defined(STM32F100xE) */
512 #ifdef __cplusplus
513 }
514 #endif
515
516 #endif /* __STM32F1xx_HAL_CEC_H */
517
518 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/