lib/main/STM32F1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f1xx_hal_dma.h
   4   * @author  MCD Application Team
   5   * @version V1.1.1
   6   * @date    12-May-2017
   7   * @brief   Header file of DMA HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F1xx_HAL_DMA_H
  40 #define __STM32F1xx_HAL_DMA_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f1xx_hal_def.h"
  48
  49 /** @addtogroup STM32F1xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup DMA
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58
  59 /** @defgroup DMA_Exported_Types DMA Exported Types
  60   * @{
  61   */
  62
  63 /**
  64   * @brief  DMA Configuration Structure definition
  65   */
  66 typedef struct
  67 {
  68   uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
  69                                            from memory to memory or from peripheral to memory.
  70                                            This parameter can be a value of @ref DMA_Data_transfer_direction */
  71
  72   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
  73                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
  74
  75   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
  76                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */
  77
  78   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
  79                                            This parameter can be a value of @ref DMA_Peripheral_data_size */
  80
  81   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
  82                                            This parameter can be a value of @ref DMA_Memory_data_size */
  83
  84   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
  85                                            This parameter can be a value of @ref DMA_mode
  86                                            @note The circular buffer mode cannot be used if the memory-to-memory
  87                                                  data transfer is configured on the selected Channel */
  88
  89   uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
  90                                            This parameter can be a value of @ref DMA_Priority_level */
  91 } DMA_InitTypeDef;
  92
  93 /**
  94   * @brief  HAL DMA State structures definition
  95   */
  96 typedef enum
  97 {
  98   HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled    */
  99   HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use      */
 100   HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing                 */
 101   HAL_DMA_STATE_TIMEOUT           = 0x03U   /*!< DMA timeout state                      */
 102 }HAL_DMA_StateTypeDef;
 103
 104 /**
 105   * @brief  HAL DMA Error Code structure definition
 106   */
 107 typedef enum
 108 {
 109   HAL_DMA_FULL_TRANSFER           = 0x00U,    /*!< Full transfer     */
 110   HAL_DMA_HALF_TRANSFER           = 0x01U     /*!< Half Transfer     */
 111 }HAL_DMA_LevelCompleteTypeDef;
 112
 113 /**
 114   * @brief  HAL DMA Callback ID structure definition
 115   */
 116 typedef enum
 117 {
 118   HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
 119   HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half transfer     */
 120   HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,    /*!< Error             */
 121   HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,    /*!< Abort             */
 122   HAL_DMA_XFER_ALL_CB_ID           = 0x04U     /*!< All               */
 123
 124 }HAL_DMA_CallbackIDTypeDef;
 125
 126 /**
 127   * @brief  DMA handle Structure definition
 128   */
 129 typedef struct __DMA_HandleTypeDef
 130 {
 131   DMA_Channel_TypeDef   *Instance;                       /*!< Register base address                  */
 132
 133   DMA_InitTypeDef       Init;                            /*!< DMA communication parameters           */
 134
 135   HAL_LockTypeDef       Lock;                            /*!< DMA locking object                     */
 136
 137   HAL_DMA_StateTypeDef  State;                           /*!< DMA transfer state                     */
 138
 139   void                  *Parent;                                                      /*!< Parent object state                    */
 140
 141   void                  (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
 142
 143   void                  (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
 144
 145   void                  (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
 146
 147   void                  (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer abort callback            */
 148
 149   __IO uint32_t         ErrorCode;                                                    /*!< DMA Error code                         */
 150
 151   DMA_TypeDef            *DmaBaseAddress;                                             /*!< DMA Channel Base Address               */
 152
 153   uint32_t               ChannelIndex;                                                /*!< DMA Channel Index                      */
 154
 155 } DMA_HandleTypeDef;
 156 /**
 157   * @}
 158   */
 159
 160 /* Exported constants --------------------------------------------------------*/
 161
 162 /** @defgroup DMA_Exported_Constants DMA Exported Constants
 163   * @{
 164   */
 165
 166 /** @defgroup DMA_Error_Code DMA Error Code
 167   * @{
 168   */
 169 #define HAL_DMA_ERROR_NONE                     0x00000000U    /*!< No error             */
 170 #define HAL_DMA_ERROR_TE                       0x00000001U    /*!< Transfer error       */
 171 #define HAL_DMA_ERROR_NO_XFER                  0x00000004U    /*!< no ongoing transfer  */
 172 #define HAL_DMA_ERROR_TIMEOUT                  0x00000020U    /*!< Timeout error        */
 173 #define HAL_DMA_ERROR_NOT_SUPPORTED            0x00000100U    /*!< Not supported mode                    */
 174 /**
 175   * @}
 176   */
 177
 178 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
 179   * @{
 180   */
 181 #define DMA_PERIPH_TO_MEMORY         0x00000000U                 /*!< Peripheral to memory direction */
 182 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)     /*!< Memory to peripheral direction */
 183 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction     */
 184
 185 /**
 186   * @}
 187   */
 188
 189 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
 190   * @{
 191   */
 192 #define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)  /*!< Peripheral increment mode Enable */
 193 #define DMA_PINC_DISABLE       0x00000000U               /*!< Peripheral increment mode Disable */
 194 /**
 195   * @}
 196   */
 197
 198 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
 199   * @{
 200   */
 201 #define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)  /*!< Memory increment mode Enable  */
 202 #define DMA_MINC_DISABLE        0x00000000U               /*!< Memory increment mode Disable */
 203 /**
 204   * @}
 205   */
 206
 207 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
 208   * @{
 209   */
 210 #define DMA_PDATAALIGN_BYTE          0x00000000U                  /*!< Peripheral data alignment: Byte     */
 211 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord */
 212 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)  /*!< Peripheral data alignment: Word     */
 213 /**
 214   * @}
 215   */
 216
 217 /** @defgroup DMA_Memory_data_size DMA Memory data size
 218   * @{
 219   */
 220 #define DMA_MDATAALIGN_BYTE          0x00000000U                  /*!< Memory data alignment: Byte     */
 221 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
 222 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)  /*!< Memory data alignment: Word     */
 223 /**
 224   * @}
 225   */
 226
 227 /** @defgroup DMA_mode DMA mode
 228   * @{
 229   */
 230 #define DMA_NORMAL         0x00000000U                  /*!< Normal mode                  */
 231 #define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)     /*!< Circular mode                */
 232 /**
 233   * @}
 234   */
 235
 236 /** @defgroup DMA_Priority_level DMA Priority level
 237   * @{
 238   */
 239 #define DMA_PRIORITY_LOW             0x00000000U               /*!< Priority level : Low       */
 240 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)  /*!< Priority level : Medium    */
 241 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)  /*!< Priority level : High      */
 242 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)    /*!< Priority level : Very_High */
 243 /**
 244   * @}
 245   */
 246
 247
 248 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
 249   * @{
 250   */
 251 #define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
 252 #define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
 253 #define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
 254 /**
 255   * @}
 256   */
 257
 258 /** @defgroup DMA_flag_definitions DMA flag definitions
 259   * @{
 260   */
 261 #define DMA_FLAG_GL1                      0x00000001U
 262 #define DMA_FLAG_TC1                      0x00000002U
 263 #define DMA_FLAG_HT1                      0x00000004U
 264 #define DMA_FLAG_TE1                      0x00000008U
 265 #define DMA_FLAG_GL2                      0x00000010U
 266 #define DMA_FLAG_TC2                      0x00000020U
 267 #define DMA_FLAG_HT2                      0x00000040U
 268 #define DMA_FLAG_TE2                      0x00000080U
 269 #define DMA_FLAG_GL3                      0x00000100U
 270 #define DMA_FLAG_TC3                      0x00000200U
 271 #define DMA_FLAG_HT3                      0x00000400U
 272 #define DMA_FLAG_TE3                      0x00000800U
 273 #define DMA_FLAG_GL4                      0x00001000U
 274 #define DMA_FLAG_TC4                      0x00002000U
 275 #define DMA_FLAG_HT4                      0x00004000U
 276 #define DMA_FLAG_TE4                      0x00008000U
 277 #define DMA_FLAG_GL5                      0x00010000U
 278 #define DMA_FLAG_TC5                      0x00020000U
 279 #define DMA_FLAG_HT5                      0x00040000U
 280 #define DMA_FLAG_TE5                      0x00080000U
 281 #define DMA_FLAG_GL6                      0x00100000U
 282 #define DMA_FLAG_TC6                      0x00200000U
 283 #define DMA_FLAG_HT6                      0x00400000U
 284 #define DMA_FLAG_TE6                      0x00800000U
 285 #define DMA_FLAG_GL7                      0x01000000U
 286 #define DMA_FLAG_TC7                      0x02000000U
 287 #define DMA_FLAG_HT7                      0x04000000U
 288 #define DMA_FLAG_TE7                      0x08000000U
 289 /**
 290   * @}
 291   */
 292
 293 /**
 294   * @}
 295   */
 296
 297
 298 /* Exported macros -----------------------------------------------------------*/
 299 /** @defgroup DMA_Exported_Macros DMA Exported Macros
 300   * @{
 301   */
 302
 303 /** @brief  Reset DMA handle state.
 304   * @param  __HANDLE__: DMA handle
 305   * @retval None
 306   */
 307 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
 308
 309 /**
 310   * @brief  Enable the specified DMA Channel.
 311   * @param  __HANDLE__: DMA handle
 312   * @retval None
 313   */
 314 #define __HAL_DMA_ENABLE(__HANDLE__)        (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
 315
 316 /**
 317   * @brief  Disable the specified DMA Channel.
 318   * @param  __HANDLE__: DMA handle
 319   * @retval None
 320   */
 321 #define __HAL_DMA_DISABLE(__HANDLE__)       (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
 322
 323
 324 /* Interrupt & Flag management */
 325
 326 /**
 327   * @brief  Enables the specified DMA Channel interrupts.
 328   * @param  __HANDLE__: DMA handle
 329   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
 330   *          This parameter can be any combination of the following values:
 331   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 332   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 333   *            @arg DMA_IT_TE:  Transfer error interrupt mask
 334   * @retval None
 335   */
 336 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
 337
 338 /**
 339   * @brief  Disable the specified DMA Channel interrupts.
 340   * @param  __HANDLE__: DMA handle
 341   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
 342   *          This parameter can be any combination of the following values:
 343   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 344   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 345   *            @arg DMA_IT_TE:  Transfer error interrupt mask
 346   * @retval None
 347   */
 348 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
 349
 350 /**
 351   * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
 352   * @param  __HANDLE__: DMA handle
 353   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
 354   *          This parameter can be one of the following values:
 355   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 356   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 357   *            @arg DMA_IT_TE:  Transfer error interrupt mask
 358   * @retval The state of DMA_IT (SET or RESET).
 359   */
 360 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 361
 362 /**
 363   * @brief  Return the number of remaining data units in the current DMA Channel transfer.
 364   * @param  __HANDLE__: DMA handle
 365   * @retval The number of remaining data units in the current DMA Channel transfer.
 366   */
 367 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
 368
 369 /**
 370   * @}
 371   */
 372
 373 /* Include DMA HAL Extension module */
 374 #include "stm32f1xx_hal_dma_ex.h"
 375
 376 /* Exported functions --------------------------------------------------------*/
 377 /** @addtogroup DMA_Exported_Functions
 378   * @{
 379   */
 380
 381 /** @addtogroup DMA_Exported_Functions_Group1
 382   * @{
 383   */
 384 /* Initialization and de-initialization functions *****************************/
 385 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
 386 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
 387 /**
 388   * @}
 389   */
 390
 391 /** @addtogroup DMA_Exported_Functions_Group2
 392   * @{
 393   */
 394 /* IO operation functions *****************************************************/
 395 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 396 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 397 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
 398 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
 399 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
 400 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
 401 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
 402 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
 403
 404 /**
 405   * @}
 406   */
 407
 408 /** @addtogroup DMA_Exported_Functions_Group3
 409   * @{
 410   */
 411 /* Peripheral State and Error functions ***************************************/
 412 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
 413 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
 414 /**
 415   * @}
 416   */
 417
 418 /**
 419   * @}
 420   */
 421
 422 /* Private macros ------------------------------------------------------------*/
 423 /** @defgroup DMA_Private_Macros DMA Private Macros
 424   * @{
 425   */
 426
 427 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
 428                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
 429                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
 430
 431 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
 432
 433 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
 434                                             ((STATE) == DMA_PINC_DISABLE))
 435
 436 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
 437                                         ((STATE) == DMA_MINC_DISABLE))
 438
 439 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
 440                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
 441                                            ((SIZE) == DMA_PDATAALIGN_WORD))
 442
 443 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
 444                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
 445                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
 446
 447 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
 448                            ((MODE) == DMA_CIRCULAR))
 449
 450 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
 451                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
 452                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
 453                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
 454
 455 /**
 456   * @}
 457   */
 458
 459 /* Private functions ---------------------------------------------------------*/
 460
 461 /**
 462   * @}
 463   */
 464
 465 /**
 466   * @}
 467   */
 468
 469 #ifdef __cplusplus
 470 }
 471 #endif
 472
 473 #endif /* __STM32F1xx_HAL_DMA_H */
 474
 475 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/