lib/main/STM32F1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_nand.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f1xx_hal_nand.h
   4   * @author  MCD Application Team
   5   * @version V1.1.1
   6   * @date    12-May-2017
   7   * @brief   Header file of NAND HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F1xx_HAL_NAND_H
  40 #define __STM32F1xx_HAL_NAND_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f1xx_ll_fsmc.h"
  48
  49 /** @addtogroup STM32F1xx_HAL_Driver
  50   * @{
  51   */
  52
  53 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
  54 /** @addtogroup NAND
  55   * @{
  56   */
  57
  58
  59 /* Exported typedef ----------------------------------------------------------*/
  60 /* Exported types ------------------------------------------------------------*/
  61 /** @defgroup NAND_Exported_Types NAND Exported Types
  62   * @{
  63   */
  64
  65 /**
  66   * @brief  HAL NAND State structures definition
  67   */
  68 typedef enum
  69 {
  70   HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
  71   HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
  72   HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
  73   HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
  74 }HAL_NAND_StateTypeDef;
  75
  76 /**
  77   * @brief  NAND Memory electronic signature Structure definition
  78   */
  79 typedef struct
  80 {
  81   /*<! NAND memory electronic signature maker and device IDs */
  82
  83   uint8_t Maker_Id;
  84
  85   uint8_t Device_Id;
  86
  87   uint8_t Third_Id;
  88
  89   uint8_t Fourth_Id;
  90 }NAND_IDTypeDef;
  91
  92 /**
  93   * @brief  NAND Memory address Structure definition
  94   */
  95 typedef struct
  96 {
  97   uint16_t Page;   /*!< NAND memory Page address    */
  98
  99   uint16_t Plane;   /*!< NAND memory Plane address  */
 100
 101   uint16_t Block;  /*!< NAND memory Block address   */
 102
 103 }NAND_AddressTypeDef;
 104
 105 /**
 106   * @brief  NAND Memory info Structure definition
 107   */
 108 typedef struct
 109 {
 110   uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes
 111                                               for 8 bits adressing or words for 16 bits addressing             */
 112
 113   uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes
 114                                               for 8 bits adressing or words for 16 bits addressing             */
 115
 116   uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */
 117
 118   uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */
 119
 120   uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */
 121
 122   uint32_t        PlaneSize;             /*!< NAND memory plane size measured in number of blocks              */
 123
 124   FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This
 125                                               parameter is mandatory for some NAND parts after the read
 126                                               command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
 127                                               Example: Toshiba THTH58BYG3S0HBAI6.
 128                                               This parameter could be ENABLE or DISABLE
 129                                               Please check the Read Mode sequnece in the NAND device datasheet */
 130 }NAND_DeviceConfigTypeDef;
 131
 132 /**
 133   * @brief  NAND handle Structure definition
 134   */
 135 typedef struct
 136 {
 137   FSMC_NAND_TypeDef              *Instance;  /*!< Register base address                                 */
 138
 139   FSMC_NAND_InitTypeDef          Init;       /*!< NAND device control configuration parameters          */
 140
 141   HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */
 142
 143   __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
 144
 145   NAND_DeviceConfigTypeDef       Config;     /*!< NAND phusical characteristic information structure    */
 146
 147 }NAND_HandleTypeDef;
 148
 149 /**
 150   * @}
 151   */
 152
 153 /* Exported constants --------------------------------------------------------*/
 154 /* Exported macros -----------------------------------------------------------*/
 155 /** @defgroup NAND_Exported_Macros NAND Exported Macros
 156   * @{
 157   */
 158
 159 /** @brief Reset NAND handle state
 160   * @param  __HANDLE__: specifies the NAND handle.
 161   * @retval None
 162   */
 163 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
 164
 165 /**
 166   * @}
 167   */
 168
 169 /* Exported functions --------------------------------------------------------*/
 170 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
 171   * @{
 172   */
 173
 174 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
 175   * @{
 176   */
 177
 178 /* Initialization/de-initialization functions  ********************************/
 179 HAL_StatusTypeDef   HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
 180 HAL_StatusTypeDef   HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
 181
 182 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
 183
 184 HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
 185
 186 void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
 187 void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
 188 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
 189 void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
 190
 191 /**
 192   * @}
 193   */
 194
 195 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
 196   * @{
 197   */
 198
 199 /* IO operation functions  ****************************************************/
 200
 201 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
 202
 203 HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
 204 HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
 205 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
 206 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
 207
 208 HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
 209 HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
 210 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
 211 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
 212
 213 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 214 uint32_t           HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 215 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 216
 217 /**
 218   * @}
 219   */
 220
 221 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
 222   * @{
 223   */
 224
 225 /* NAND Control functions  ****************************************************/
 226 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
 227 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
 228 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
 229
 230 /**
 231   * @}
 232   */
 233
 234 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
 235   * @{
 236   */
 237
 238 /* NAND State functions *******************************************************/
 239 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
 240 uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 241
 242 /**
 243   * @}
 244   */
 245
 246 /**
 247   * @}
 248   */
 249 /* Private types -------------------------------------------------------------*/
 250 /* Private variables ---------------------------------------------------------*/
 251 /* Private constants ---------------------------------------------------------*/
 252 /** @addtogroup NAND_Private_Constants
 253   * @{
 254   */
 255
 256 #define NAND_DEVICE1               FSMC_BANK2
 257 #define NAND_DEVICE2               FSMC_BANK3
 258 #define NAND_WRITE_TIMEOUT         1000U
 259
 260 #define CMD_AREA                   (1U<<16U)  /* A16 = CLE high */
 261 #define ADDR_AREA                  (1U<<17U)  /* A17 = ALE high */
 262
 263 #define NAND_CMD_AREA_A            ((uint8_t)0x00)
 264 #define NAND_CMD_AREA_B            ((uint8_t)0x01)
 265 #define NAND_CMD_AREA_C            ((uint8_t)0x50)
 266 #define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
 267
 268 #define NAND_CMD_WRITE0            ((uint8_t)0x80)
 269 #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
 270 #define NAND_CMD_ERASE0            ((uint8_t)0x60)
 271 #define NAND_CMD_ERASE1            ((uint8_t)0xD0)
 272 #define NAND_CMD_READID            ((uint8_t)0x90)
 273 #define NAND_CMD_STATUS            ((uint8_t)0x70)
 274 #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
 275 #define NAND_CMD_RESET             ((uint8_t)0xFF)
 276
 277 /* NAND memory status */
 278 #define NAND_VALID_ADDRESS         0x00000100U
 279 #define NAND_INVALID_ADDRESS       0x00000200U
 280 #define NAND_TIMEOUT_ERROR         0x00000400U
 281 #define NAND_BUSY                  0x00000000U
 282 #define NAND_ERROR                 0x00000001U
 283 #define NAND_READY                 0x00000040U
 284
 285 /**
 286   * @}
 287   */
 288
 289 /* Private macros ------------------------------------------------------------*/
 290 /** @addtogroup NAND_Private_Macros
 291   * @{
 292   */
 293
 294 /**
 295   * @brief  NAND memory address computation.
 296   * @param  __ADDRESS__: NAND memory address.
 297   * @param  __HANDLE__ : NAND handle.
 298   * @retval NAND Raw address value
 299   */
 300 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
 301                          (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
 302
 303 /**
 304   * @brief  NAND memory Column address computation.
 305   * @param  __HANDLE__: NAND handle.
 306   * @retval NAND Raw address value
 307   */
 308 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
 309
 310 /**
 311   * @brief  NAND memory address cycling.
 312   * @param  __ADDRESS__: NAND memory address.
 313   * @retval NAND address cycling value.
 314   */
 315 #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)               /* 1st addressing cycle */
 316 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8U)       /* 2nd addressing cycle */
 317 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16U)      /* 3rd addressing cycle */
 318 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24U)      /* 4th addressing cycle */
 319
 320 /**
 321   * @brief  NAND memory Columns cycling.
 322   * @param  __ADDRESS__: NAND memory address.
 323   * @retval NAND Column address cycling value.
 324   */
 325 #define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st Column addressing cycle */
 326 #define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8U)      /* 2nd Column addressing cycle */
 327
 328 /**
 329   * @}
 330   */
 331
 332 /**
 333   * @}
 334   */
 335 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
 336
 337 /**
 338   * @}
 339   */
 340
 341 #ifdef __cplusplus
 342 }
 343 #endif
 344
 345 #endif /* __STM32F1xx_HAL_NAND_H */
 346
 347 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/