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Increment eeprom version
[betaflight.git] / lib / main / STM32F1 / Drivers / STM32F1xx_HAL_Driver / Inc / stm32f1xx_hal_tim.h
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1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_tim.h
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 12-May-2017
7 * @brief Header file of TIM HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F1xx_HAL_TIM_H
40 #define __STM32F1xx_HAL_TIM_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f1xx_hal_def.h"
48
49 /** @addtogroup STM32F1xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup TIM
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup TIM_Exported_Types TIM Exported Types
59 * @{
60 */
61 /**
62 * @brief TIM Time base Configuration Structure definition
63 */
64 typedef struct
65 {
66 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
67 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
68
69 uint32_t CounterMode; /*!< Specifies the counter mode.
70 This parameter can be a value of @ref TIM_Counter_Mode */
71
72 uint32_t Period; /*!< Specifies the period value to be loaded into the active
73 Auto-Reload Register at the next update event.
74 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
75
76 uint32_t ClockDivision; /*!< Specifies the clock division.
77 This parameter can be a value of @ref TIM_ClockDivision */
78
79 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
80 reaches zero, an update event is generated and counting restarts
81 from the RCR value (N).
82 This means in PWM mode that (N+1) corresponds to:
83 - the number of PWM periods in edge-aligned mode
84 - the number of half PWM period in center-aligned mode
85 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
86 @note This parameter is valid only for TIM1 and TIM8. */
87
88 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
89 This parameter can be a value of @ref TIM_AutoReloadPreload */
90 } TIM_Base_InitTypeDef;
91
92 /**
93 * @brief TIM Output Compare Configuration Structure definition
94 */
95 typedef struct
96 {
97 uint32_t OCMode; /*!< Specifies the TIM mode.
98 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
99
100 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
101 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
102
103 uint32_t OCPolarity; /*!< Specifies the output polarity.
104 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
105
106 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
107 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
108 @note This parameter is valid only for TIM1 and TIM8. */
109
110 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
111 This parameter can be a value of @ref TIM_Output_Fast_State
112 @note This parameter is valid only in PWM1 and PWM2 mode. */
113
114
115 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
116 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
117 @note This parameter is valid only for TIM1 and TIM8. */
118
119 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
120 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
121 @note This parameter is valid only for TIM1 and TIM8. */
122 } TIM_OC_InitTypeDef;
123
124 /**
125 * @brief TIM One Pulse Mode Configuration Structure definition
126 */
127 typedef struct
128 {
129 uint32_t OCMode; /*!< Specifies the TIM mode.
130 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
131
132 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
133 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
134
135 uint32_t OCPolarity; /*!< Specifies the output polarity.
136 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
137
138 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
139 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
140 @note This parameter is valid only for TIM1 and TIM8. */
141
142 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
143 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
144 @note This parameter is valid only for TIM1 and TIM8. */
145
146 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
147 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
148 @note This parameter is valid only for TIM1 and TIM8. */
149
150 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
151 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
152
153 uint32_t ICSelection; /*!< Specifies the input.
154 This parameter can be a value of @ref TIM_Input_Capture_Selection */
155
156 uint32_t ICFilter; /*!< Specifies the input capture filter.
157 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
158 } TIM_OnePulse_InitTypeDef;
159
160
161 /**
162 * @brief TIM Input Capture Configuration Structure definition
163 */
164 typedef struct
165 {
166 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
167 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
168
169 uint32_t ICSelection; /*!< Specifies the input.
170 This parameter can be a value of @ref TIM_Input_Capture_Selection */
171
172 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
173 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
174
175 uint32_t ICFilter; /*!< Specifies the input capture filter.
176 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
177 } TIM_IC_InitTypeDef;
178
179 /**
180 * @brief TIM Encoder Configuration Structure definition
181 */
182 typedef struct
183 {
184 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
185 This parameter can be a value of @ref TIM_Encoder_Mode */
186
187 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
188 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
189
190 uint32_t IC1Selection; /*!< Specifies the input.
191 This parameter can be a value of @ref TIM_Input_Capture_Selection */
192
193 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
194 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
195
196 uint32_t IC1Filter; /*!< Specifies the input capture filter.
197 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
198
199 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
200 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
201
202 uint32_t IC2Selection; /*!< Specifies the input.
203 This parameter can be a value of @ref TIM_Input_Capture_Selection */
204
205 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
206 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
207
208 uint32_t IC2Filter; /*!< Specifies the input capture filter.
209 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
210 } TIM_Encoder_InitTypeDef;
211
212
213 /**
214 * @brief TIM Clock Configuration Handle Structure definition
215 */
216 typedef struct
217 {
218 uint32_t ClockSource; /*!< TIM clock sources
219 This parameter can be a value of @ref TIM_Clock_Source */
220 uint32_t ClockPolarity; /*!< TIM clock polarity
221 This parameter can be a value of @ref TIM_Clock_Polarity */
222 uint32_t ClockPrescaler; /*!< TIM clock prescaler
223 This parameter can be a value of @ref TIM_Clock_Prescaler */
224 uint32_t ClockFilter; /*!< TIM clock filter
225 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
226 }TIM_ClockConfigTypeDef;
227
228 /**
229 * @brief TIM Clear Input Configuration Handle Structure definition
230 */
231 typedef struct
232 {
233 uint32_t ClearInputState; /*!< TIM clear Input state
234 This parameter can be ENABLE or DISABLE */
235 uint32_t ClearInputSource; /*!< TIM clear Input sources
236 This parameter can be a value of @ref TIM_ClearInput_Source */
237 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
238 This parameter can be a value of @ref TIM_ClearInput_Polarity */
239 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
240 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
241 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
242 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
243 }TIM_ClearInputConfigTypeDef;
244
245 /**
246 * @brief TIM Slave configuration Structure definition
247 */
248 typedef struct {
249 uint32_t SlaveMode; /*!< Slave mode selection
250 This parameter can be a value of @ref TIM_Slave_Mode */
251 uint32_t InputTrigger; /*!< Input Trigger source
252 This parameter can be a value of @ref TIM_Trigger_Selection */
253 uint32_t TriggerPolarity; /*!< Input Trigger polarity
254 This parameter can be a value of @ref TIM_Trigger_Polarity */
255 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
256 This parameter can be a value of @ref TIM_Trigger_Prescaler */
257 uint32_t TriggerFilter; /*!< Input trigger filter
258 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
259
260 }TIM_SlaveConfigTypeDef;
261
262 /**
263 * @brief HAL State structures definition
264 */
265 typedef enum
266 {
267 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
268 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
269 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
270 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
271 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
272 }HAL_TIM_StateTypeDef;
273
274 /**
275 * @brief HAL Active channel structures definition
276 */
277 typedef enum
278 {
279 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
280 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
281 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
282 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
283 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
284 }HAL_TIM_ActiveChannel;
285
286 /**
287 * @brief TIM Time Base Handle Structure definition
288 */
289 typedef struct
290 {
291 TIM_TypeDef *Instance; /*!< Register base address */
292 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
293 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
294 DMA_HandleTypeDef *hdma[7U]; /*!< DMA Handlers array
295 This array is accessed by a @ref TIM_DMA_Handle_index */
296 HAL_LockTypeDef Lock; /*!< Locking object */
297 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
298 }TIM_HandleTypeDef;
299
300 /**
301 * @}
302 */
303
304 /* Exported constants --------------------------------------------------------*/
305 /** @defgroup TIM_Exported_Constants TIM Exported Constants
306 * @{
307 */
308
309 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
310 * @{
311 */
312 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
313 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
314 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
315 /**
316 * @}
317 */
318
319 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
320 * @{
321 */
322 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
323 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
324 /**
325 * @}
326 */
327
328 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
329 * @{
330 */
331 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
332 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
333 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
334 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
335 /**
336 * @}
337 */
338
339 /** @defgroup TIM_Counter_Mode TIM Counter Mode
340 * @{
341 */
342 #define TIM_COUNTERMODE_UP 0x00000000U
343 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
344 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
345 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
346 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
347 /**
348 * @}
349 */
350
351 /** @defgroup TIM_ClockDivision TIM ClockDivision
352 * @{
353 */
354 #define TIM_CLOCKDIVISION_DIV1 0x00000000U
355 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
356 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
357 /**
358 * @}
359 */
360
361 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
362 * @{
363 */
364 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x0000U /*!< TIMx_ARR register is not buffered */
365 #define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */
366 /**
367 * @}
368 */
369
370 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
371 * @{
372 */
373 #define TIM_OCMODE_TIMING 0x00000000U
374 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
375 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
376 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
377 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
378 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
379 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
380 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
381 /**
382 * @}
383 */
384
385 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
386 * @{
387 */
388 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U
389 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
390 /**
391 * @}
392 */
393
394 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
395 * @{
396 */
397 #define TIM_OCFAST_DISABLE 0x00000000U
398 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
399 /**
400 * @}
401 */
402
403 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
404 * @{
405 */
406 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U
407 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
408 /**
409 * @}
410 */
411
412 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
413 * @{
414 */
415 #define TIM_OCPOLARITY_HIGH 0x00000000U
416 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
417 /**
418 * @}
419 */
420
421 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
422 * @{
423 */
424 #define TIM_OCNPOLARITY_HIGH 0x00000000U
425 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
426 /**
427 * @}
428 */
429
430 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
431 * @{
432 */
433 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
434 #define TIM_OCIDLESTATE_RESET 0x00000000U
435 /**
436 * @}
437 */
438
439 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
440 * @{
441 */
442 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
443 #define TIM_OCNIDLESTATE_RESET 0x00000000U
444 /**
445 * @}
446 */
447
448 /** @defgroup TIM_Channel TIM Channel
449 * @{
450 */
451 #define TIM_CHANNEL_1 0x00000000U
452 #define TIM_CHANNEL_2 0x00000004U
453 #define TIM_CHANNEL_3 0x00000008U
454 #define TIM_CHANNEL_4 0x0000000CU
455 #define TIM_CHANNEL_ALL 0x00000018U
456 /**
457 * @}
458 */
459
460 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
461 * @{
462 */
463 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
464 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
465 /**
466 * @}
467 */
468
469 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
470 * @{
471 */
472 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
473 connected to IC1, IC2, IC3 or IC4, respectively */
474 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
475 connected to IC2, IC1, IC4 or IC3, respectively */
476 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
477 /**
478 * @}
479 */
480
481 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
482 * @{
483 */
484 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
485 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
486 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
487 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
488 /**
489 * @}
490 */
491
492 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
493 * @{
494 */
495 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
496 #define TIM_OPMODE_REPETITIVE 0x00000000U
497 /**
498 * @}
499 */
500
501 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
502 * @{
503 */
504 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
505 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
506 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
507 /**
508 * @}
509 */
510
511 /** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
512 * @{
513 */
514 #define TIM_IT_UPDATE (TIM_DIER_UIE)
515 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
516 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
517 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
518 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
519 #define TIM_IT_COM (TIM_DIER_COMIE)
520 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
521 #define TIM_IT_BREAK (TIM_DIER_BIE)
522 /**
523 * @}
524 */
525
526 /** @defgroup TIM_Commutation_Source TIM Commutation Source
527 * @{
528 */
529 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
530 #define TIM_COMMUTATION_SOFTWARE 0x00000000U
531
532 /**
533 * @}
534 */
535
536 /** @defgroup TIM_DMA_sources TIM DMA Sources
537 * @{
538 */
539 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
540 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
541 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
542 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
543 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
544 #define TIM_DMA_COM (TIM_DIER_COMDE)
545 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
546 /**
547 * @}
548 */
549
550 /** @defgroup TIM_Event_Source TIM Event Source
551 * @{
552 */
553 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
554 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
555 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
556 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
557 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
558 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
559 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
560 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
561 /**
562 * @}
563 */
564
565 /** @defgroup TIM_Flag_definition TIM Flag Definition
566 * @{
567 */
568 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
569 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
570 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
571 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
572 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
573 #define TIM_FLAG_COM (TIM_SR_COMIF)
574 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
575 #define TIM_FLAG_BREAK (TIM_SR_BIF)
576 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
577 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
578 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
579 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
580 /**
581 * @}
582 */
583
584 /** @defgroup TIM_Clock_Source TIM Clock Source
585 * @{
586 */
587 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
588 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
589 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
590 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
591 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
592 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
593 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
594 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
595 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
596 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
597 /**
598 * @}
599 */
600
601 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
602 * @{
603 */
604 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
605 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
606 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
607 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
608 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
609 /**
610 * @}
611 */
612
613 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
614 * @{
615 */
616 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
617 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
618 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
619 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
620 /**
621 * @}
622 */
623
624 /** @defgroup TIM_ClearInput_Source TIM ClearInput Source
625 * @{
626 */
627 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U
628 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U
629 /**
630 * @}
631 */
632
633 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
634 * @{
635 */
636 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
637 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
638 /**
639 * @}
640 */
641
642 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
643 * @{
644 */
645 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
646 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
647 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
648 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
649 /**
650 * @}
651 */
652
653 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
654 * @{
655 */
656 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
657 #define TIM_OSSR_DISABLE 0x00000000U
658 /**
659 * @}
660 */
661
662 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
663 * @{
664 */
665 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
666 #define TIM_OSSI_DISABLE 0x00000000U
667 /**
668 * @}
669 */
670
671 /** @defgroup TIM_Lock_level TIM Lock level
672 * @{
673 */
674 #define TIM_LOCKLEVEL_OFF 0x00000000U
675 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
676 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
677 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
678 /**
679 * @}
680 */
681
682 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
683 * @{
684 */
685 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
686 #define TIM_BREAK_DISABLE 0x00000000U
687 /**
688 * @}
689 */
690
691 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
692 * @{
693 */
694 #define TIM_BREAKPOLARITY_LOW 0x00000000U
695 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
696 /**
697 * @}
698 */
699 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
700 * @{
701 */
702 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
703 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
704 /**
705 * @}
706 */
707
708 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
709 * @{
710 */
711 #define TIM_TRGO_RESET 0x00000000U
712 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
713 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
714 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
715 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
716 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
717 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
718 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
719 /**
720 * @}
721 */
722
723 /** @defgroup TIM_Slave_Mode TIM Slave Mode
724 * @{
725 */
726 #define TIM_SLAVEMODE_DISABLE 0x00000000U
727 #define TIM_SLAVEMODE_RESET 0x00000004U
728 #define TIM_SLAVEMODE_GATED 0x00000005U
729 #define TIM_SLAVEMODE_TRIGGER 0x00000006U
730 #define TIM_SLAVEMODE_EXTERNAL1 0x00000007U
731 /**
732 * @}
733 */
734
735 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
736 * @{
737 */
738 #define TIM_MASTERSLAVEMODE_ENABLE 0x00000080U
739 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
740 /**
741 * @}
742 */
743
744 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
745 * @{
746 */
747 #define TIM_TS_ITR0 0x00000000U
748 #define TIM_TS_ITR1 0x00000010U
749 #define TIM_TS_ITR2 0x00000020U
750 #define TIM_TS_ITR3 0x00000030U
751 #define TIM_TS_TI1F_ED 0x00000040U
752 #define TIM_TS_TI1FP1 0x00000050U
753 #define TIM_TS_TI2FP2 0x00000060U
754 #define TIM_TS_ETRF 0x00000070U
755 #define TIM_TS_NONE 0x0000FFFFU
756 /**
757 * @}
758 */
759
760 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
761 * @{
762 */
763 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
764 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
765 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
766 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
767 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
768 /**
769 * @}
770 */
771
772 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
773 * @{
774 */
775 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
776 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
777 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
778 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
779 /**
780 * @}
781 */
782
783 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
784 * @{
785 */
786 #define TIM_TI1SELECTION_CH1 0x00000000U
787 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
788 /**
789 * @}
790 */
791
792 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
793 * @{
794 */
795 #define TIM_DMABASE_CR1 0x00000000U
796 #define TIM_DMABASE_CR2 0x00000001U
797 #define TIM_DMABASE_SMCR 0x00000002U
798 #define TIM_DMABASE_DIER 0x00000003U
799 #define TIM_DMABASE_SR 0x00000004U
800 #define TIM_DMABASE_EGR 0x00000005U
801 #define TIM_DMABASE_CCMR1 0x00000006U
802 #define TIM_DMABASE_CCMR2 0x00000007U
803 #define TIM_DMABASE_CCER 0x00000008U
804 #define TIM_DMABASE_CNT 0x00000009U
805 #define TIM_DMABASE_PSC 0x0000000AU
806 #define TIM_DMABASE_ARR 0x0000000BU
807 #define TIM_DMABASE_RCR 0x0000000CU
808 #define TIM_DMABASE_CCR1 0x0000000DU
809 #define TIM_DMABASE_CCR2 0x0000000EU
810 #define TIM_DMABASE_CCR3 0x0000000FU
811 #define TIM_DMABASE_CCR4 0x00000010U
812 #define TIM_DMABASE_BDTR 0x00000011U
813 #define TIM_DMABASE_DCR 0x00000012U
814 /**
815 * @}
816 */
817
818 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
819 * @{
820 */
821 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
822 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
823 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
824 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
825 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
826 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
827 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
828 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
829 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
830 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
831 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
832 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
833 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
834 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
835 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
836 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
837 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
838 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
839 /**
840 * @}
841 */
842
843 /** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
844 * @{
845 */
846 #define TIM_DMA_ID_UPDATE ((uint16_t)0x0) /*!< Index of the DMA handle used for Update DMA requests */
847 #define TIM_DMA_ID_CC1 ((uint16_t)0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
848 #define TIM_DMA_ID_CC2 ((uint16_t)0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
849 #define TIM_DMA_ID_CC3 ((uint16_t)0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
850 #define TIM_DMA_ID_CC4 ((uint16_t)0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
851 #define TIM_DMA_ID_COMMUTATION ((uint16_t)0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
852 #define TIM_DMA_ID_TRIGGER ((uint16_t)0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
853 /**
854 * @}
855 */
856
857 /** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
858 * @{
859 */
860 #define TIM_CCx_ENABLE 0x00000001U
861 #define TIM_CCx_DISABLE 0x00000000U
862 #define TIM_CCxN_ENABLE 0x00000004U
863 #define TIM_CCxN_DISABLE 0x00000000U
864 /**
865 * @}
866 */
867
868 /**
869 * @}
870 */
871
872 /* Private Constants -----------------------------------------------------------*/
873 /** @defgroup TIM_Private_Constants TIM Private Constants
874 * @{
875 */
876
877 /* The counter of a timer instance is disabled only if all the CCx and CCxN
878 channels have been disabled */
879 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
880 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
881
882 /**
883 * @}
884 */
885
886 /* Private Macros -----------------------------------------------------------*/
887 /** @defgroup TIM_Private_Macros TIM Private Macros
888 * @{
889 */
890
891 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
892 ((MODE) == TIM_COUNTERMODE_DOWN) || \
893 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
894 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
895 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
896
897 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
898 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
899 ((DIV) == TIM_CLOCKDIVISION_DIV4))
900
901 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
902 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
903
904 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
905 ((MODE) == TIM_OCMODE_PWM2))
906
907 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
908 ((MODE) == TIM_OCMODE_ACTIVE) || \
909 ((MODE) == TIM_OCMODE_INACTIVE) || \
910 ((MODE) == TIM_OCMODE_TOGGLE) || \
911 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
912 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
913
914 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
915 ((STATE) == TIM_OCFAST_ENABLE))
916
917 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
918 ((POLARITY) == TIM_OCPOLARITY_LOW))
919
920 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
921 ((POLARITY) == TIM_OCNPOLARITY_LOW))
922
923 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
924 ((STATE) == TIM_OCIDLESTATE_RESET))
925
926 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
927 ((STATE) == TIM_OCNIDLESTATE_RESET))
928
929 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
930 ((CHANNEL) == TIM_CHANNEL_2) || \
931 ((CHANNEL) == TIM_CHANNEL_3) || \
932 ((CHANNEL) == TIM_CHANNEL_4) || \
933 ((CHANNEL) == TIM_CHANNEL_ALL))
934
935 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
936 ((CHANNEL) == TIM_CHANNEL_2))
937
938 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
939 ((CHANNEL) == TIM_CHANNEL_2) || \
940 ((CHANNEL) == TIM_CHANNEL_3))
941
942 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
943 ((POLARITY) == TIM_ICPOLARITY_FALLING))
944
945 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
946 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
947 ((SELECTION) == TIM_ICSELECTION_TRC))
948
949 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
950 ((PRESCALER) == TIM_ICPSC_DIV2) || \
951 ((PRESCALER) == TIM_ICPSC_DIV4) || \
952 ((PRESCALER) == TIM_ICPSC_DIV8))
953
954 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
955 ((MODE) == TIM_OPMODE_REPETITIVE))
956
957 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
958 ((MODE) == TIM_ENCODERMODE_TI2) || \
959 ((MODE) == TIM_ENCODERMODE_TI12))
960
961 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
962
963 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
964
965 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
966 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
967 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
968 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
969 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
970 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
971 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
972 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
973 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
974 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
975
976 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
977 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
978 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
979 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
980 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
981
982 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
983 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
984 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
985 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
986
987 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
988
989 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \
990 ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
991
992 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
993 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
994
995 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
996 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
997 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
998 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
999
1000 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
1001
1002 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
1003 ((STATE) == TIM_OSSR_DISABLE))
1004
1005 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
1006 ((STATE) == TIM_OSSI_DISABLE))
1007
1008 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
1009 ((LEVEL) == TIM_LOCKLEVEL_1) || \
1010 ((LEVEL) == TIM_LOCKLEVEL_2) || \
1011 ((LEVEL) == TIM_LOCKLEVEL_3))
1012
1013 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
1014 ((STATE) == TIM_BREAK_DISABLE))
1015
1016 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
1017 ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
1018
1019 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
1020 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
1021
1022 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
1023 ((SOURCE) == TIM_TRGO_ENABLE) || \
1024 ((SOURCE) == TIM_TRGO_UPDATE) || \
1025 ((SOURCE) == TIM_TRGO_OC1) || \
1026 ((SOURCE) == TIM_TRGO_OC1REF) || \
1027 ((SOURCE) == TIM_TRGO_OC2REF) || \
1028 ((SOURCE) == TIM_TRGO_OC3REF) || \
1029 ((SOURCE) == TIM_TRGO_OC4REF))
1030
1031 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
1032 ((MODE) == TIM_SLAVEMODE_GATED) || \
1033 ((MODE) == TIM_SLAVEMODE_RESET) || \
1034 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
1035 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
1036
1037 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
1038 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
1039
1040 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
1041 ((SELECTION) == TIM_TS_ITR1) || \
1042 ((SELECTION) == TIM_TS_ITR2) || \
1043 ((SELECTION) == TIM_TS_ITR3) || \
1044 ((SELECTION) == TIM_TS_TI1F_ED) || \
1045 ((SELECTION) == TIM_TS_TI1FP1) || \
1046 ((SELECTION) == TIM_TS_TI2FP2) || \
1047 ((SELECTION) == TIM_TS_ETRF))
1048
1049 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
1050 ((SELECTION) == TIM_TS_ITR1) || \
1051 ((SELECTION) == TIM_TS_ITR2) || \
1052 ((SELECTION) == TIM_TS_ITR3) || \
1053 ((SELECTION) == TIM_TS_NONE))
1054
1055 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
1056 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
1057 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
1058 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
1059 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
1060
1061 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
1062 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
1063 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
1064 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
1065
1066 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
1067
1068 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
1069 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
1070
1071 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
1072 ((BASE) == TIM_DMABASE_CR2) || \
1073 ((BASE) == TIM_DMABASE_SMCR) || \
1074 ((BASE) == TIM_DMABASE_DIER) || \
1075 ((BASE) == TIM_DMABASE_SR) || \
1076 ((BASE) == TIM_DMABASE_EGR) || \
1077 ((BASE) == TIM_DMABASE_CCMR1) || \
1078 ((BASE) == TIM_DMABASE_CCMR2) || \
1079 ((BASE) == TIM_DMABASE_CCER) || \
1080 ((BASE) == TIM_DMABASE_CNT) || \
1081 ((BASE) == TIM_DMABASE_PSC) || \
1082 ((BASE) == TIM_DMABASE_ARR) || \
1083 ((BASE) == TIM_DMABASE_RCR) || \
1084 ((BASE) == TIM_DMABASE_CCR1) || \
1085 ((BASE) == TIM_DMABASE_CCR2) || \
1086 ((BASE) == TIM_DMABASE_CCR3) || \
1087 ((BASE) == TIM_DMABASE_CCR4) || \
1088 ((BASE) == TIM_DMABASE_BDTR) || \
1089 ((BASE) == TIM_DMABASE_DCR))
1090
1091 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
1092 ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
1093 ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
1094 ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
1095 ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
1096 ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
1097 ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
1098 ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
1099 ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
1100 ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
1101 ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
1102 ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
1103 ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
1104 ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
1105 ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
1106 ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
1107 ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
1108 ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
1109
1110 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
1111
1112 /** @brief Set TIM IC prescaler
1113 * @param __HANDLE__: TIM handle
1114 * @param __CHANNEL__: specifies TIM Channel
1115 * @param __ICPSC__: specifies the prescaler value.
1116 * @retval None
1117 */
1118 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
1119 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
1120 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
1121 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
1122 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
1123
1124 /** @brief Reset TIM IC prescaler
1125 * @param __HANDLE__: TIM handle
1126 * @param __CHANNEL__: specifies TIM Channel
1127 * @retval None
1128 */
1129 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
1130 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
1131 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
1132 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
1133 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
1134
1135
1136 /** @brief Set TIM IC polarity
1137 * @param __HANDLE__: TIM handle
1138 * @param __CHANNEL__: specifies TIM Channel
1139 * @param __POLARITY__: specifies TIM Channel Polarity
1140 * @retval None
1141 */
1142 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1143 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
1144 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
1145 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
1146 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
1147
1148 /** @brief Reset TIM IC polarity
1149 * @param __HANDLE__: TIM handle
1150 * @param __CHANNEL__: specifies TIM Channel
1151 * @retval None
1152 */
1153 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
1154 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
1155 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
1156 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
1157 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
1158
1159 /**
1160 * @}
1161 */
1162
1163 /* Private Functions --------------------------------------------------------*/
1164 /** @addtogroup TIM_Private_Functions
1165 * @{
1166 */
1167 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
1168 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
1169 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1170 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
1171 void TIM_DMAError(DMA_HandleTypeDef *hdma);
1172 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
1173 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
1174 /**
1175 * @}
1176 */
1177
1178 /* Exported macros -----------------------------------------------------------*/
1179 /** @defgroup TIM_Exported_Macros TIM Exported Macros
1180 * @{
1181 */
1182
1183 /** @brief Reset TIM handle state
1184 * @param __HANDLE__: TIM handle.
1185 * @retval None
1186 */
1187 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
1188
1189 /**
1190 * @brief Enable the TIM peripheral.
1191 * @param __HANDLE__: TIM handle
1192 * @retval None
1193 */
1194 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1195
1196 /**
1197 * @brief Enable the TIM main Output.
1198 * @param __HANDLE__: TIM handle
1199 * @retval None
1200 */
1201 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
1202
1203 /**
1204 * @brief Disable the TIM peripheral.
1205 * @param __HANDLE__: TIM handle
1206 * @retval None
1207 */
1208 #define __HAL_TIM_DISABLE(__HANDLE__) \
1209 do { \
1210 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
1211 { \
1212 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
1213 { \
1214 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1215 } \
1216 } \
1217 } while(0U)
1218 /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
1219 channels have been disabled */
1220 /**
1221 * @brief Disable the TIM main Output.
1222 * @param __HANDLE__: TIM handle
1223 * @retval None
1224 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
1225 */
1226 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1227 do { \
1228 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
1229 { \
1230 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
1231 { \
1232 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1233 } \
1234 } \
1235 } while(0U)
1236
1237 /**
1238 * @brief Disable the TIM main Output.
1239 * @param __HANDLE__: TIM handle
1240 * @retval None
1241 * @note The Main Output Enable of a timer instance is disabled unconditionally
1242 */
1243 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
1244
1245 /**
1246 * @brief Enables the specified TIM interrupt.
1247 * @param __HANDLE__: specifies the TIM Handle.
1248 * @param __INTERRUPT__: specifies the TIM interrupt source to enable.
1249 * This parameter can be one of the following values:
1250 * @arg TIM_IT_UPDATE: Update interrupt
1251 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1252 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1253 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1254 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1255 * @arg TIM_IT_COM: Commutation interrupt
1256 * @arg TIM_IT_TRIGGER: Trigger interrupt
1257 * @arg TIM_IT_BREAK: Break interrupt
1258 * @retval None
1259 */
1260 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1261
1262 /**
1263 * @brief Disables the specified TIM interrupt.
1264 * @param __HANDLE__: specifies the TIM Handle.
1265 * @param __INTERRUPT__: specifies the TIM interrupt source to disable.
1266 * This parameter can be one of the following values:
1267 * @arg TIM_IT_UPDATE: Update interrupt
1268 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1269 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1270 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1271 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1272 * @arg TIM_IT_COM: Commutation interrupt
1273 * @arg TIM_IT_TRIGGER: Trigger interrupt
1274 * @arg TIM_IT_BREAK: Break interrupt
1275 * @retval None
1276 */
1277 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1278
1279 /**
1280 * @brief Enables the specified DMA request.
1281 * @param __HANDLE__: specifies the TIM Handle.
1282 * @param __DMA__: specifies the TIM DMA request to enable.
1283 * This parameter can be one of the following values:
1284 * @arg TIM_DMA_UPDATE: Update DMA request
1285 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
1286 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
1287 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
1288 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
1289 * @arg TIM_DMA_COM: Commutation DMA request
1290 * @arg TIM_DMA_TRIGGER: Trigger DMA request
1291 * @retval None
1292 */
1293 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
1294
1295 /**
1296 * @brief Disables the specified DMA request.
1297 * @param __HANDLE__: specifies the TIM Handle.
1298 * @param __DMA__: specifies the TIM DMA request to disable.
1299 * This parameter can be one of the following values:
1300 * @arg TIM_DMA_UPDATE: Update DMA request
1301 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
1302 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
1303 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
1304 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
1305 * @arg TIM_DMA_COM: Commutation DMA request
1306 * @arg TIM_DMA_TRIGGER: Trigger DMA request
1307 * @retval None
1308 */
1309 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1310
1311 /**
1312 * @brief Checks whether the specified TIM interrupt flag is set or not.
1313 * @param __HANDLE__: specifies the TIM Handle.
1314 * @param __FLAG__: specifies the TIM interrupt flag to check.
1315 * This parameter can be one of the following values:
1316 * @arg TIM_FLAG_UPDATE: Update interrupt flag
1317 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1318 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1319 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1320 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1321 * @arg TIM_FLAG_COM: Commutation interrupt flag
1322 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1323 * @arg TIM_FLAG_BREAK: Break interrupt flag
1324 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1325 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1326 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1327 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1328 * @retval The new state of __FLAG__ (TRUE or FALSE).
1329 */
1330 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1331
1332 /**
1333 * @brief Clears the specified TIM interrupt flag.
1334 * @param __HANDLE__: specifies the TIM Handle.
1335 * @param __FLAG__: specifies the TIM interrupt flag to clear.
1336 * This parameter can be one of the following values:
1337 * @arg TIM_FLAG_UPDATE: Update interrupt flag
1338 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1339 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1340 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1341 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1342 * @arg TIM_FLAG_COM: Commutation interrupt flag
1343 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1344 * @arg TIM_FLAG_BREAK: Break interrupt flag
1345 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1346 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1347 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1348 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1349 * @retval The new state of __FLAG__ (TRUE or FALSE).
1350 */
1351 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1352
1353 /**
1354 * @brief Checks whether the specified TIM interrupt has occurred or not.
1355 * @param __HANDLE__: TIM handle
1356 * @param __INTERRUPT__: specifies the TIM interrupt source to check.
1357 * @retval The state of TIM_IT (SET or RESET).
1358 */
1359 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
1360
1361 /**
1362 * @brief Clear the TIM interrupt pending bits
1363 * @param __HANDLE__: TIM handle
1364 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
1365 * @retval None
1366 */
1367 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1368
1369 /**
1370 * @brief Indicates whether or not the TIM Counter is used as downcounter
1371 * @param __HANDLE__: TIM handle.
1372 * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
1373 * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
1374 mode.
1375 */
1376 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
1377
1378 /**
1379 * @brief Sets the TIM active prescaler register value on update event.
1380 * @param __HANDLE__: TIM handle.
1381 * @param __PRESC__: specifies the active prescaler register new value.
1382 * @retval None
1383 */
1384 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1385
1386 /**
1387 * @brief Sets the TIM Capture Compare Register value on runtime without
1388 * calling another time ConfigChannel function.
1389 * @param __HANDLE__: TIM handle.
1390 * @param __CHANNEL__ : TIM Channels to be configured.
1391 * This parameter can be one of the following values:
1392 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1393 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1394 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1395 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1396 * @param __COMPARE__: specifies the Capture Compare register new value.
1397 * @retval None
1398 */
1399 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1400 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
1401
1402 /**
1403 * @brief Gets the TIM Capture Compare Register value on runtime
1404 * @param __HANDLE__: TIM handle.
1405 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
1406 * This parameter can be one of the following values:
1407 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
1408 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
1409 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
1410 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
1411 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
1412 */
1413 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1414 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
1415
1416 /**
1417 * @brief Sets the TIM Counter Register value on runtime.
1418 * @param __HANDLE__: TIM handle.
1419 * @param __COUNTER__: specifies the Counter register new value.
1420 * @retval None
1421 */
1422 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1423
1424 /**
1425 * @brief Gets the TIM Counter Register value on runtime.
1426 * @param __HANDLE__: TIM handle.
1427 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
1428 */
1429 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
1430 ((__HANDLE__)->Instance->CNT)
1431
1432 /**
1433 * @brief Sets the TIM Autoreload Register value on runtime without calling
1434 * another time any Init function.
1435 * @param __HANDLE__: TIM handle.
1436 * @param __AUTORELOAD__: specifies the Counter register new value.
1437 * @retval None
1438 */
1439 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1440 do{ \
1441 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1442 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1443 } while(0U)
1444
1445 /**
1446 * @brief Gets the TIM Autoreload Register value on runtime
1447 * @param __HANDLE__: TIM handle.
1448 * @retval @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
1449 */
1450 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
1451 ((__HANDLE__)->Instance->ARR)
1452
1453 /**
1454 * @brief Sets the TIM Clock Division value on runtime without calling
1455 * another time any Init function.
1456 * @param __HANDLE__: TIM handle.
1457 * @param __CKD__: specifies the clock division value.
1458 * This parameter can be one of the following value:
1459 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1460 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1461 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1462 * @retval None
1463 */
1464 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1465 do{ \
1466 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
1467 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1468 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1469 } while(0U)
1470
1471 /**
1472 * @brief Gets the TIM Clock Division value on runtime
1473 * @param __HANDLE__: TIM handle.
1474 * @retval The clock division can be one of the following values:
1475 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1476 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1477 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1478 */
1479 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
1480 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1481
1482 /**
1483 * @brief Sets the TIM Input Capture prescaler on runtime without calling
1484 * another time HAL_TIM_IC_ConfigChannel() function.
1485 * @param __HANDLE__: TIM handle.
1486 * @param __CHANNEL__ : TIM Channels to be configured.
1487 * This parameter can be one of the following values:
1488 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1489 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1490 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1491 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1492 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
1493 * This parameter can be one of the following values:
1494 * @arg TIM_ICPSC_DIV1: no prescaler
1495 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1496 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1497 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1498 * @retval None
1499 */
1500 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1501 do{ \
1502 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1503 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1504 } while(0U)
1505
1506 /**
1507 * @brief Gets the TIM Input Capture prescaler on runtime
1508 * @param __HANDLE__: TIM handle.
1509 * @param __CHANNEL__: TIM Channels to be configured.
1510 * This parameter can be one of the following values:
1511 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1512 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1513 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1514 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1515 * @retval The input capture prescaler can be one of the following values:
1516 * @arg TIM_ICPSC_DIV1: no prescaler
1517 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1518 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1519 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1520 */
1521 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1522 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1523 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
1524 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1525 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
1526
1527 /**
1528 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
1529 * @param __HANDLE__: TIM handle.
1530 * @note When the USR bit of the TIMx_CR1 register is set, only counter
1531 * overflow/underflow generates an update interrupt or DMA request (if
1532 * enabled)
1533 * @retval None
1534 */
1535 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
1536 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
1537
1538 /**
1539 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
1540 * @param __HANDLE__: TIM handle.
1541 * @note When the USR bit of the TIMx_CR1 register is reset, any of the
1542 * following events generate an update interrupt or DMA request (if
1543 * enabled):
1544 * (+) Counter overflow/underflow
1545 * (+) Setting the UG bit
1546 * (+) Update generation through the slave mode controller
1547 * @retval None
1548 */
1549 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
1550 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
1551
1552 /**
1553 * @brief Sets the TIM Capture x input polarity on runtime.
1554 * @param __HANDLE__: TIM handle.
1555 * @param __CHANNEL__: TIM Channels to be configured.
1556 * This parameter can be one of the following values:
1557 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1558 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1559 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1560 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1561 * @param __POLARITY__: Polarity for TIx source
1562 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
1563 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
1564 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
1565 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
1566 * @retval None
1567 */
1568 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1569 do{ \
1570 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1571 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1572 }while(0U)
1573
1574 /**
1575 * @}
1576 */
1577
1578 /* Include TIM HAL Extension module */
1579 #include "stm32f1xx_hal_tim_ex.h"
1580
1581 /* Exported functions --------------------------------------------------------*/
1582 /** @addtogroup TIM_Exported_Functions
1583 * @{
1584 */
1585
1586 /** @addtogroup TIM_Exported_Functions_Group1
1587 * @{
1588 */
1589 /* Time Base functions ********************************************************/
1590 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
1591 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
1592 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
1593 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
1594 /* Blocking mode: Polling */
1595 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
1596 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
1597 /* Non-Blocking mode: Interrupt */
1598 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
1599 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
1600 /* Non-Blocking mode: DMA */
1601 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
1602 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
1603 /**
1604 * @}
1605 */
1606
1607 /** @addtogroup TIM_Exported_Functions_Group2
1608 * @{
1609 */
1610 /* Timer Output Compare functions **********************************************/
1611 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
1612 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
1613 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
1614 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
1615 /* Blocking mode: Polling */
1616 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1617 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1618 /* Non-Blocking mode: Interrupt */
1619 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1620 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1621 /* Non-Blocking mode: DMA */
1622 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1623 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1624
1625 /**
1626 * @}
1627 */
1628
1629 /** @addtogroup TIM_Exported_Functions_Group3
1630 * @{
1631 */
1632 /* Timer PWM functions *********************************************************/
1633 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
1634 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
1635 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
1636 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
1637 /* Blocking mode: Polling */
1638 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1639 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1640 /* Non-Blocking mode: Interrupt */
1641 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1642 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1643 /* Non-Blocking mode: DMA */
1644 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1645 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1646 /**
1647 * @}
1648 */
1649
1650 /** @addtogroup TIM_Exported_Functions_Group4
1651 * @{
1652 */
1653 /* Timer Input Capture functions ***********************************************/
1654 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
1655 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
1656 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
1657 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
1658 /* Blocking mode: Polling */
1659 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1660 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1661 /* Non-Blocking mode: Interrupt */
1662 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1663 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1664 /* Non-Blocking mode: DMA */
1665 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1666 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1667 /**
1668 * @}
1669 */
1670
1671 /** @addtogroup TIM_Exported_Functions_Group5
1672 * @{
1673 */
1674 /* Timer One Pulse functions ***************************************************/
1675 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
1676 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
1677 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
1678 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
1679 /* Blocking mode: Polling */
1680 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1681 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1682 /* Non-Blocking mode: Interrupt */
1683 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1684 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1685 /**
1686 * @}
1687 */
1688
1689 /** @addtogroup TIM_Exported_Functions_Group6
1690 * @{
1691 */
1692 /* Timer Encoder functions *****************************************************/
1693 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
1694 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
1695 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
1696 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
1697 /* Blocking mode: Polling */
1698 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1699 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1700 /* Non-Blocking mode: Interrupt */
1701 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1702 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1703 /* Non-Blocking mode: DMA */
1704 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
1705 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1706
1707 /**
1708 * @}
1709 */
1710
1711 /** @addtogroup TIM_Exported_Functions_Group7
1712 * @{
1713 */
1714 /* Interrupt Handler functions **********************************************/
1715 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
1716 /**
1717 * @}
1718 */
1719
1720 /** @addtogroup TIM_Exported_Functions_Group8
1721 * @{
1722 */
1723 /* Control functions *********************************************************/
1724 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1725 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1726 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
1727 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
1728 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
1729 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
1730 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
1731 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1732 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1733 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1734 uint32_t *BurstBuffer, uint32_t BurstLength);
1735 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1736 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1737 uint32_t *BurstBuffer, uint32_t BurstLength);
1738 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1739 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
1740 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
1741
1742 /**
1743 * @}
1744 */
1745
1746 /** @addtogroup TIM_Exported_Functions_Group9
1747 * @{
1748 */
1749 /* Callback in non blocking modes (Interrupt and DMA) *************************/
1750 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
1751 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
1752 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
1753 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
1754 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
1755 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
1756 /**
1757 * @}
1758 */
1759
1760 /** @addtogroup TIM_Exported_Functions_Group10
1761 * @{
1762 */
1763 /* Peripheral State functions **************************************************/
1764 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
1765 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
1766 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
1767 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
1768 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
1769 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
1770
1771 /**
1772 * @}
1773 */
1774
1775 /**
1776 * @}
1777 */
1778
1779 /**
1780 * @}
1781 */
1782
1783 /**
1784 * @}
1785 */
1786
1787 #ifdef __cplusplus
1788 }
1789 #endif
1790
1791 #endif /* __STM32F1xx_HAL_TIM_H */
1792
1793 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/