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Increment eeprom version
[betaflight.git] / lib / main / STM32F1 / Drivers / STM32F1xx_HAL_Driver / Inc / stm32f1xx_ll_bus.h
blob7b1ab0ae8e093f332bb555fcb6885c9e76c596d3
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_bus.h
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 12-May-2017
7 * @brief Header file of BUS LL module.
8
9 @verbatim
10 ##### RCC Limitations #####
11 ==============================================================================
12 [..]
13 A delay between an RCC peripheral clock enable and the effective peripheral
14 enabling should be taken into account in order to manage the peripheral read/write
15 from/to registers.
16 (+) This delay depends on the peripheral mapping.
17 (++) AHB & APB peripherals, 1 dummy read is necessary
18
19 [..]
20 Workarounds:
21 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
22 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
23
24 @endverbatim
25 ******************************************************************************
26 * @attention
27 *
28 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
29 *
30 * Redistribution and use in source and binary forms, with or without modification,
31 * are permitted provided that the following conditions are met:
32 * 1. Redistributions of source code must retain the above copyright notice,
33 * this list of conditions and the following disclaimer.
34 * 2. Redistributions in binary form must reproduce the above copyright notice,
35 * this list of conditions and the following disclaimer in the documentation
36 * and/or other materials provided with the distribution.
37 * 3. Neither the name of STMicroelectronics nor the names of its contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
40 *
41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
44 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
48 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 *
52 ******************************************************************************
53 */
54
55 /* Define to prevent recursive inclusion -------------------------------------*/
56 #ifndef __STM32F1xx_LL_BUS_H
57 #define __STM32F1xx_LL_BUS_H
58
59 #ifdef __cplusplus
60 extern "C" {
61 #endif
62
63 /* Includes ------------------------------------------------------------------*/
64 #include "stm32f1xx.h"
65
66 /** @addtogroup STM32F1xx_LL_Driver
67 * @{
68 */
69
70 #if defined(RCC)
71
72 /** @defgroup BUS_LL BUS
73 * @{
74 */
75
76 /* Private types -------------------------------------------------------------*/
77 /* Private variables ---------------------------------------------------------*/
78
79 /* Private constants ---------------------------------------------------------*/
80 #if defined(RCC_AHBRSTR_OTGFSRST) || defined(RCC_AHBRSTR_ETHMACRST)
81 #define RCC_AHBRSTR_SUPPORT
82 #endif /* RCC_AHBRSTR_OTGFSRST || RCC_AHBRSTR_ETHMACRST */
83
84 /* Private macros ------------------------------------------------------------*/
85
86 /* Exported types ------------------------------------------------------------*/
87 /* Exported constants --------------------------------------------------------*/
88 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
89 * @{
90 */
91
92 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
93 * @{
94 */
95 #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
96 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
97 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
98 #if defined(DMA2)
99 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
100 #endif /*DMA2*/
101 #if defined(ETH)
102 #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHBENR_ETHMACEN
103 #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHBENR_ETHMACRXEN
104 #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHBENR_ETHMACTXEN
105 #endif /*ETH*/
106 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
107 #if defined(FSMC_Bank1)
108 #define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN
109 #endif /*FSMC_Bank1*/
110 #if defined(USB_OTG_FS)
111 #define LL_AHB1_GRP1_PERIPH_OTGFS RCC_AHBENR_OTGFSEN
112 #endif /*USB_OTG_FS*/
113 #if defined(SDIO)
114 #define LL_AHB1_GRP1_PERIPH_SDIO RCC_AHBENR_SDIOEN
115 #endif /*SDIO*/
116 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
117 /**
118 * @}
119 */
120
121 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
122 * @{
123 */
124 #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
125 #define LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN
126 #if defined(CAN1)
127 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
128 #endif /*CAN1*/
129 #if defined(CAN2)
130 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
131 #endif /*CAN2*/
132 #if defined(CEC)
133 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
134 #endif /*CEC*/
135 #if defined(DAC)
136 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
137 #endif /*DAC*/
138 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
139 #if defined(I2C2)
140 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
141 #endif /*I2C2*/
142 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
143 #if defined(SPI2)
144 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
145 #endif /*SPI2*/
146 #if defined(SPI3)
147 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
148 #endif /*SPI3*/
149 #if defined(TIM12)
150 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
151 #endif /*TIM12*/
152 #if defined(TIM13)
153 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
154 #endif /*TIM13*/
155 #if defined(TIM14)
156 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
157 #endif /*TIM14*/
158 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
159 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
160 #if defined(TIM4)
161 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
162 #endif /*TIM4*/
163 #if defined(TIM5)
164 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
165 #endif /*TIM5*/
166 #if defined(TIM6)
167 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
168 #endif /*TIM6*/
169 #if defined(TIM7)
170 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
171 #endif /*TIM7*/
172 #if defined(UART4)
173 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
174 #endif /*UART4*/
175 #if defined(UART5)
176 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
177 #endif /*UART5*/
178 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
179 #if defined(USART3)
180 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
181 #endif /*USART3*/
182 #if defined(USB)
183 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
184 #endif /*USB*/
185 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
186 /**
187 * @}
188 */
189
190 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
191 * @{
192 */
193 #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
194 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
195 #if defined(ADC2)
196 #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
197 #endif /*ADC2*/
198 #if defined(ADC3)
199 #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
200 #endif /*ADC3*/
201 #define LL_APB2_GRP1_PERIPH_AFIO RCC_APB2ENR_AFIOEN
202 #define LL_APB2_GRP1_PERIPH_GPIOA RCC_APB2ENR_IOPAEN
203 #define LL_APB2_GRP1_PERIPH_GPIOB RCC_APB2ENR_IOPBEN
204 #define LL_APB2_GRP1_PERIPH_GPIOC RCC_APB2ENR_IOPCEN
205 #define LL_APB2_GRP1_PERIPH_GPIOD RCC_APB2ENR_IOPDEN
206 #if defined(GPIOE)
207 #define LL_APB2_GRP1_PERIPH_GPIOE RCC_APB2ENR_IOPEEN
208 #endif /*GPIOE*/
209 #if defined(GPIOF)
210 #define LL_APB2_GRP1_PERIPH_GPIOF RCC_APB2ENR_IOPFEN
211 #endif /*GPIOF*/
212 #if defined(GPIOG)
213 #define LL_APB2_GRP1_PERIPH_GPIOG RCC_APB2ENR_IOPGEN
214 #endif /*GPIOG*/
215 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
216 #if defined(TIM10)
217 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
218 #endif /*TIM10*/
219 #if defined(TIM11)
220 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
221 #endif /*TIM11*/
222 #if defined(TIM15)
223 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
224 #endif /*TIM15*/
225 #if defined(TIM16)
226 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
227 #endif /*TIM16*/
228 #if defined(TIM17)
229 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
230 #endif /*TIM17*/
231 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
232 #if defined(TIM8)
233 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
234 #endif /*TIM8*/
235 #if defined(TIM9)
236 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
237 #endif /*TIM9*/
238 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
239 /**
240 * @}
241 */
242
243 /**
244 * @}
245 */
246
247 /* Exported macro ------------------------------------------------------------*/
248
249 /* Exported functions --------------------------------------------------------*/
250 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
251 * @{
252 */
253
254 /** @defgroup BUS_LL_EF_AHB1 AHB1
255 * @{
256 */
257
258 /**
259 * @brief Enable AHB1 peripherals clock.
260 * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
261 * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
262 * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
263 * AHBENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
264 * AHBENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
265 * AHBENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
266 * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
267 * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock\n
268 * AHBENR OTGFSEN LL_AHB1_GRP1_EnableClock\n
269 * AHBENR SDIOEN LL_AHB1_GRP1_EnableClock\n
270 * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock
271 * @param Periphs This parameter can be a combination of the following values:
272 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
273 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
274 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
275 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
276 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
277 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
278 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
279 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
280 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
281 * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
282 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
283 *
284 * (*) value not defined in all devices.
285 * @retval None
286 */
287 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
288 {
289 __IO uint32_t tmpreg;
290 SET_BIT(RCC->AHBENR, Periphs);
291 /* Delay after an RCC peripheral clock enabling */
292 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
293 (void)tmpreg;
294 }
295
296 /**
297 * @brief Check if AHB1 peripheral clock is enabled or not
298 * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
299 * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
300 * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
301 * AHBENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
302 * AHBENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
303 * AHBENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
304 * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
305 * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock\n
306 * AHBENR OTGFSEN LL_AHB1_GRP1_IsEnabledClock\n
307 * AHBENR SDIOEN LL_AHB1_GRP1_IsEnabledClock\n
308 * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock
309 * @param Periphs This parameter can be a combination of the following values:
310 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
311 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
312 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
313 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
314 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
315 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
316 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
317 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
318 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
319 * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
320 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
321 *
322 * (*) value not defined in all devices.
323 * @retval State of Periphs (1 or 0).
324 */
325 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
326 {
327 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
328 }
329
330 /**
331 * @brief Disable AHB1 peripherals clock.
332 * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
333 * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
334 * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
335 * AHBENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
336 * AHBENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
337 * AHBENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
338 * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
339 * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock\n
340 * AHBENR OTGFSEN LL_AHB1_GRP1_DisableClock\n
341 * AHBENR SDIOEN LL_AHB1_GRP1_DisableClock\n
342 * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock
343 * @param Periphs This parameter can be a combination of the following values:
344 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
345 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
346 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
347 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
348 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
349 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
350 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
351 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
352 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
353 * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
354 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
355 *
356 * (*) value not defined in all devices.
357 * @retval None
358 */
359 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
360 {
361 CLEAR_BIT(RCC->AHBENR, Periphs);
362 }
363
364 #if defined(RCC_AHBRSTR_SUPPORT)
365 /**
366 * @brief Force AHB1 peripherals reset.
367 * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
368 * AHBRSTR OTGFSRST LL_AHB1_GRP1_ForceReset
369 * @param Periphs This parameter can be a combination of the following values:
370 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
371 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
372 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
373 *
374 * (*) value not defined in all devices.
375 * @retval None
376 */
377 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
378 {
379 SET_BIT(RCC->AHBRSTR, Periphs);
380 }
381
382 /**
383 * @brief Release AHB1 peripherals reset.
384 * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
385 * AHBRSTR OTGFSRST LL_AHB1_GRP1_ReleaseReset
386 * @param Periphs This parameter can be a combination of the following values:
387 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
388 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
389 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
390 *
391 * (*) value not defined in all devices.
392 * @retval None
393 */
394 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
395 {
396 CLEAR_BIT(RCC->AHBRSTR, Periphs);
397 }
398 #endif /* RCC_AHBRSTR_SUPPORT */
399
400 /**
401 * @}
402 */
403
404 /** @defgroup BUS_LL_EF_APB1 APB1
405 * @{
406 */
407
408 /**
409 * @brief Enable APB1 peripherals clock.
410 * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_EnableClock\n
411 * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
412 * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
413 * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
414 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
415 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
416 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
417 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
418 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
419 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
420 * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
421 * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
422 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
423 * APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
424 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
425 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
426 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
427 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
428 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
429 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
430 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
431 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
432 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
433 * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
434 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock
435 * @param Periphs This parameter can be a combination of the following values:
436 * @arg @ref LL_APB1_GRP1_PERIPH_BKP
437 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
438 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
439 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
440 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
441 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
442 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
443 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
444 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
445 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
446 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
447 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
448 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
449 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
450 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
451 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
452 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
453 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
454 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
455 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
456 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
457 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
458 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
459 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
460 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
461 *
462 * (*) value not defined in all devices.
463 * @retval None
464 */
465 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
466 {
467 __IO uint32_t tmpreg;
468 SET_BIT(RCC->APB1ENR, Periphs);
469 /* Delay after an RCC peripheral clock enabling */
470 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
471 (void)tmpreg;
472 }
473
474 /**
475 * @brief Check if APB1 peripheral clock is enabled or not
476 * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_IsEnabledClock\n
477 * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
478 * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
479 * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
480 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
481 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
482 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
483 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
484 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
485 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
486 * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
487 * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
488 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
489 * APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
490 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
491 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
492 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
493 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
494 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
495 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
496 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
497 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
498 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
499 * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
500 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock
501 * @param Periphs This parameter can be a combination of the following values:
502 * @arg @ref LL_APB1_GRP1_PERIPH_BKP
503 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
504 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
505 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
506 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
507 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
508 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
509 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
510 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
511 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
512 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
513 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
514 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
515 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
516 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
517 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
518 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
519 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
520 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
521 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
522 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
523 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
524 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
525 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
526 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
527 *
528 * (*) value not defined in all devices.
529 * @retval State of Periphs (1 or 0).
530 */
531 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
532 {
533 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
534 }
535
536 /**
537 * @brief Disable APB1 peripherals clock.
538 * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_DisableClock\n
539 * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
540 * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
541 * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
542 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
543 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
544 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
545 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
546 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
547 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
548 * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
549 * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
550 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
551 * APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
552 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
553 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
554 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
555 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
556 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
557 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
558 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
559 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
560 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
561 * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
562 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock
563 * @param Periphs This parameter can be a combination of the following values:
564 * @arg @ref LL_APB1_GRP1_PERIPH_BKP
565 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
566 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
567 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
568 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
569 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
570 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
571 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
572 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
573 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
574 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
575 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
576 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
577 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
578 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
579 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
580 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
581 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
582 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
583 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
584 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
585 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
586 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
587 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
588 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
589 *
590 * (*) value not defined in all devices.
591 * @retval None
592 */
593 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
594 {
595 CLEAR_BIT(RCC->APB1ENR, Periphs);
596 }
597
598 /**
599 * @brief Force APB1 peripherals reset.
600 * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ForceReset\n
601 * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
602 * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
603 * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
604 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
605 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
606 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
607 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
608 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
609 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
610 * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
611 * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
612 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
613 * APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
614 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
615 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
616 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
617 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
618 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
619 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
620 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
621 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
622 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
623 * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
624 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset
625 * @param Periphs This parameter can be a combination of the following values:
626 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
627 * @arg @ref LL_APB1_GRP1_PERIPH_BKP
628 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
629 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
630 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
631 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
632 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
633 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
634 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
635 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
636 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
637 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
638 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
639 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
640 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
641 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
642 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
643 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
644 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
645 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
646 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
647 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
648 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
649 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
650 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
651 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
652 *
653 * (*) value not defined in all devices.
654 * @retval None
655 */
656 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
657 {
658 SET_BIT(RCC->APB1RSTR, Periphs);
659 }
660
661 /**
662 * @brief Release APB1 peripherals reset.
663 * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ReleaseReset\n
664 * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
665 * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
666 * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
667 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
668 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
669 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
670 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
671 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
672 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
673 * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
674 * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
675 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
676 * APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
677 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
678 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
679 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
680 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
681 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
682 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
683 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
684 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
685 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
686 * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
687 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset
688 * @param Periphs This parameter can be a combination of the following values:
689 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
690 * @arg @ref LL_APB1_GRP1_PERIPH_BKP
691 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
692 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
693 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
694 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
695 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
696 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
697 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
698 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
699 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
700 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
701 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
702 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
703 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
704 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
705 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
706 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
707 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
708 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
709 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
710 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
711 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
712 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
713 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
714 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
715 *
716 * (*) value not defined in all devices.
717 * @retval None
718 */
719 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
720 {
721 CLEAR_BIT(RCC->APB1RSTR, Periphs);
722 }
723
724 /**
725 * @}
726 */
727
728 /** @defgroup BUS_LL_EF_APB2 APB2
729 * @{
730 */
731
732 /**
733 * @brief Enable APB2 peripherals clock.
734 * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
735 * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
736 * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
737 * APB2ENR AFIOEN LL_APB2_GRP1_EnableClock\n
738 * APB2ENR IOPAEN LL_APB2_GRP1_EnableClock\n
739 * APB2ENR IOPBEN LL_APB2_GRP1_EnableClock\n
740 * APB2ENR IOPCEN LL_APB2_GRP1_EnableClock\n
741 * APB2ENR IOPDEN LL_APB2_GRP1_EnableClock\n
742 * APB2ENR IOPEEN LL_APB2_GRP1_EnableClock\n
743 * APB2ENR IOPFEN LL_APB2_GRP1_EnableClock\n
744 * APB2ENR IOPGEN LL_APB2_GRP1_EnableClock\n
745 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
746 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
747 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
748 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
749 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
750 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
751 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
752 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
753 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
754 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock
755 * @param Periphs This parameter can be a combination of the following values:
756 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
757 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
758 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
759 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
760 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
761 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
762 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
763 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
764 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
765 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
766 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
767 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
768 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
769 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
770 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
771 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
772 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
773 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
774 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
775 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
776 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
777 *
778 * (*) value not defined in all devices.
779 * @retval None
780 */
781 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
782 {
783 __IO uint32_t tmpreg;
784 SET_BIT(RCC->APB2ENR, Periphs);
785 /* Delay after an RCC peripheral clock enabling */
786 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
787 (void)tmpreg;
788 }
789
790 /**
791 * @brief Check if APB2 peripheral clock is enabled or not
792 * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
793 * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
794 * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
795 * APB2ENR AFIOEN LL_APB2_GRP1_IsEnabledClock\n
796 * APB2ENR IOPAEN LL_APB2_GRP1_IsEnabledClock\n
797 * APB2ENR IOPBEN LL_APB2_GRP1_IsEnabledClock\n
798 * APB2ENR IOPCEN LL_APB2_GRP1_IsEnabledClock\n
799 * APB2ENR IOPDEN LL_APB2_GRP1_IsEnabledClock\n
800 * APB2ENR IOPEEN LL_APB2_GRP1_IsEnabledClock\n
801 * APB2ENR IOPFEN LL_APB2_GRP1_IsEnabledClock\n
802 * APB2ENR IOPGEN LL_APB2_GRP1_IsEnabledClock\n
803 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
804 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
805 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
806 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
807 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
808 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
809 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
810 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
811 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
812 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
813 * @param Periphs This parameter can be a combination of the following values:
814 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
815 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
816 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
817 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
818 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
819 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
820 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
821 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
822 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
823 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
824 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
825 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
826 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
827 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
828 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
829 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
830 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
831 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
832 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
833 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
834 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
835 *
836 * (*) value not defined in all devices.
837 * @retval State of Periphs (1 or 0).
838 */
839 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
840 {
841 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
842 }
843
844 /**
845 * @brief Disable APB2 peripherals clock.
846 * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
847 * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
848 * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
849 * APB2ENR AFIOEN LL_APB2_GRP1_DisableClock\n
850 * APB2ENR IOPAEN LL_APB2_GRP1_DisableClock\n
851 * APB2ENR IOPBEN LL_APB2_GRP1_DisableClock\n
852 * APB2ENR IOPCEN LL_APB2_GRP1_DisableClock\n
853 * APB2ENR IOPDEN LL_APB2_GRP1_DisableClock\n
854 * APB2ENR IOPEEN LL_APB2_GRP1_DisableClock\n
855 * APB2ENR IOPFEN LL_APB2_GRP1_DisableClock\n
856 * APB2ENR IOPGEN LL_APB2_GRP1_DisableClock\n
857 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
858 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
859 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
860 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
861 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
862 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
863 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
864 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
865 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
866 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock
867 * @param Periphs This parameter can be a combination of the following values:
868 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
869 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
870 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
871 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
872 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
873 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
874 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
875 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
876 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
877 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
878 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
879 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
880 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
881 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
882 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
883 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
884 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
885 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
886 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
887 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
888 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
889 *
890 * (*) value not defined in all devices.
891 * @retval None
892 */
893 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
894 {
895 CLEAR_BIT(RCC->APB2ENR, Periphs);
896 }
897
898 /**
899 * @brief Force APB2 peripherals reset.
900 * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
901 * APB2RSTR ADC2RST LL_APB2_GRP1_ForceReset\n
902 * APB2RSTR ADC3RST LL_APB2_GRP1_ForceReset\n
903 * APB2RSTR AFIORST LL_APB2_GRP1_ForceReset\n
904 * APB2RSTR IOPARST LL_APB2_GRP1_ForceReset\n
905 * APB2RSTR IOPBRST LL_APB2_GRP1_ForceReset\n
906 * APB2RSTR IOPCRST LL_APB2_GRP1_ForceReset\n
907 * APB2RSTR IOPDRST LL_APB2_GRP1_ForceReset\n
908 * APB2RSTR IOPERST LL_APB2_GRP1_ForceReset\n
909 * APB2RSTR IOPFRST LL_APB2_GRP1_ForceReset\n
910 * APB2RSTR IOPGRST LL_APB2_GRP1_ForceReset\n
911 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
912 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
913 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
914 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
915 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
916 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
917 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
918 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
919 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
920 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
921 * @param Periphs This parameter can be a combination of the following values:
922 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
923 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
924 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
925 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
926 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
927 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
928 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
929 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
930 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
931 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
932 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
933 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
934 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
935 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
936 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
937 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
938 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
939 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
940 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
941 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
942 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
943 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
944 *
945 * (*) value not defined in all devices.
946 * @retval None
947 */
948 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
949 {
950 SET_BIT(RCC->APB2RSTR, Periphs);
951 }
952
953 /**
954 * @brief Release APB2 peripherals reset.
955 * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
956 * APB2RSTR ADC2RST LL_APB2_GRP1_ReleaseReset\n
957 * APB2RSTR ADC3RST LL_APB2_GRP1_ReleaseReset\n
958 * APB2RSTR AFIORST LL_APB2_GRP1_ReleaseReset\n
959 * APB2RSTR IOPARST LL_APB2_GRP1_ReleaseReset\n
960 * APB2RSTR IOPBRST LL_APB2_GRP1_ReleaseReset\n
961 * APB2RSTR IOPCRST LL_APB2_GRP1_ReleaseReset\n
962 * APB2RSTR IOPDRST LL_APB2_GRP1_ReleaseReset\n
963 * APB2RSTR IOPERST LL_APB2_GRP1_ReleaseReset\n
964 * APB2RSTR IOPFRST LL_APB2_GRP1_ReleaseReset\n
965 * APB2RSTR IOPGRST LL_APB2_GRP1_ReleaseReset\n
966 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
967 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
968 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
969 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
970 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
971 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
972 * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
973 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
974 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
975 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
976 * @param Periphs This parameter can be a combination of the following values:
977 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
978 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
979 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
980 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
981 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
982 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
983 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
984 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
985 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
986 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
987 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
988 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
989 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
990 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
991 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
992 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
993 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
994 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
995 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
996 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
997 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
998 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
999 *
1000 * (*) value not defined in all devices.
1001 * @retval None
1002 */
1003 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1004 {
1005 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1006 }
1007
1008 /**
1009 * @}
1010 */
1011
1012
1013 /**
1014 * @}
1015 */
1016
1017 /**
1018 * @}
1019 */
1020
1021 #endif /* defined(RCC) */
1022
1023 /**
1024 * @}
1025 */
1026
1027 #ifdef __cplusplus
1028 }
1029 #endif
1030
1031 #endif /* __STM32F1xx_LL_BUS_H */
1032
1033 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/