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Increment eeprom version
[betaflight.git] / lib / main / STM32F1 / Drivers / STM32F1xx_HAL_Driver / Inc / stm32f1xx_ll_dac.h
blob6acb37e497ef815c6187a4d7fe27094983adec48
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_dac.h
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 12-May-2017
7 * @brief Header file of DAC LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F1xx_LL_DAC_H
40 #define __STM32F1xx_LL_DAC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f1xx.h"
48
49 /** @addtogroup STM32F1xx_LL_Driver
50 * @{
51 */
52
53 #if defined (DAC)
54
55 /** @defgroup DAC_LL DAC
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61
62 /* Private constants ---------------------------------------------------------*/
63 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
64 * @{
65 */
66
67 /* Internal masks for DAC channels definition */
68 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
69 /* - channel bits position into register CR */
70 /* - channel bits position into register SWTRIG */
71 /* - channel register offset of data holding register DHRx */
72 /* - channel register offset of data output register DORx */
73 #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
74 #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
75 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
76
77 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
78 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
79 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
80
81 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
82 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
83 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
84 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
85 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
86 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
87 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
88 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
89 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
90 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
91
92 #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
93 #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
94 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
95
96 /* DAC registers bits positions */
97 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
98 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
99 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
100
101 /* Miscellaneous data */
102 #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
103
104 /**
105 * @}
106 */
107
108
109 /* Private macros ------------------------------------------------------------*/
110 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
111 * @{
112 */
113
114 /**
115 * @brief Driver macro reserved for internal use: isolate bits with the
116 * selected mask and shift them to the register LSB
117 * (shift mask on register position bit 0).
118 * @param __BITS__ Bits in register 32 bits
119 * @param __MASK__ Mask in register 32 bits
120 * @retval Bits in register 32 bits
121 */
122 #define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
123 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
124
125 /**
126 * @brief Driver macro reserved for internal use: set a pointer to
127 * a register from a register basis from which an offset
128 * is applied.
129 * @param __REG__ Register basis from which the offset is applied.
130 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
131 * @retval Pointer to register address
132 */
133 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
134 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
135
136 /**
137 * @}
138 */
139
140
141 /* Exported types ------------------------------------------------------------*/
142 #if defined(USE_FULL_LL_DRIVER)
143 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
144 * @{
145 */
146
147 /**
148 * @brief Structure definition of some features of DAC instance.
149 */
150 typedef struct
151 {
152 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
153 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
154
155 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
156
157 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
158 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
159
160 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
161
162 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
163 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
164 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
165 @note If waveform automatic generation mode is disabled, this parameter is discarded.
166
167 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
168
169 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
170 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
171
172 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
173
174 } LL_DAC_InitTypeDef;
175
176 /**
177 * @}
178 */
179 #endif /* USE_FULL_LL_DRIVER */
180
181 /* Exported constants --------------------------------------------------------*/
182 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
183 * @{
184 */
185
186 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
187 * @brief Flags defines which can be used with LL_DAC_ReadReg function
188 * @{
189 */
190 /* DAC channel 1 flags */
191 #if defined(DAC_SR_DMAUDR1)
192 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
193 #endif /* DAC_SR_DMAUDR1 */
194
195 /* DAC channel 2 flags */
196 #if defined(DAC_SR_DMAUDR2)
197 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
198 #endif /* DAC_SR_DMAUDR2 */
199 /**
200 * @}
201 */
202
203 /** @defgroup DAC_LL_EC_IT DAC interruptions
204 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
205 * @{
206 */
207 #if defined(DAC_CR_DMAUDRIE1)
208 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
209 #endif /* DAC_CR_DMAUDRIE1 */
210 #if defined(DAC_CR_DMAUDRIE2)
211 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
212 #endif /* DAC_CR_DMAUDRIE2 */
213 /**
214 * @}
215 */
216
217 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
218 * @{
219 */
220 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
221 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
222 /**
223 * @}
224 */
225
226 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
227 * @{
228 */
229 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
230 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
231 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */
232 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
233 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
234 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
235 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
236 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
237 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
238 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
239 /**
240 * @}
241 */
242
243 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
244 * @{
245 */
246 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
247 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
248 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
249 /**
250 * @}
251 */
252
253 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
254 * @{
255 */
256 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
257 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
258 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
259 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
260 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
261 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
262 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
263 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
264 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
265 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
266 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
267 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
268 /**
269 * @}
270 */
271
272 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
273 * @{
274 */
275 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
276 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
277 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
278 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
279 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
280 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
281 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
282 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
283 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
284 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
285 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
286 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
287 /**
288 * @}
289 */
290
291 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
292 * @{
293 */
294 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
295 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
296 /**
297 * @}
298 */
299
300
301 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
302 * @{
303 */
304 #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
305 #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
306 /**
307 * @}
308 */
309
310 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
311 * @{
312 */
313 /* List of DAC registers intended to be used (most commonly) with */
314 /* DMA transfer. */
315 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
316 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
317 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
318 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
319 /**
320 * @}
321 */
322
323 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
324 * @note Only DAC IP HW delays are defined in DAC LL driver driver,
325 * not timeout values.
326 * For details on delays values, refer to descriptions in source code
327 * above each literal definition.
328 * @{
329 */
330
331 /* Delay for DAC channel voltage settling time from DAC channel startup */
332 /* (transition from disable to enable). */
333 /* Note: DAC channel startup time depends on board application environment: */
334 /* impedance connected to DAC channel output. */
335 /* The delay below is specified under conditions: */
336 /* - voltage maximum transition (lowest to highest value) */
337 /* - until voltage reaches final value +-1LSB */
338 /* - DAC channel output buffer enabled */
339 /* - load impedance of 5kOhm (min), 50pF (max) */
340 /* Literal set to maximum value (refer to device datasheet, */
341 /* parameter "tWAKEUP"). */
342 /* Unit: us */
343 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
344
345 /* Delay for DAC channel voltage settling time. */
346 /* Note: DAC channel startup time depends on board application environment: */
347 /* impedance connected to DAC channel output. */
348 /* The delay below is specified under conditions: */
349 /* - voltage maximum transition (lowest to highest value) */
350 /* - until voltage reaches final value +-1LSB */
351 /* - DAC channel output buffer enabled */
352 /* - load impedance of 5kOhm min, 50pF max */
353 /* Literal set to maximum value (refer to device datasheet, */
354 /* parameter "tSETTLING"). */
355 /* Unit: us */
356 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
357 /**
358 * @}
359 */
360
361 /**
362 * @}
363 */
364
365 /* Exported macro ------------------------------------------------------------*/
366 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
367 * @{
368 */
369
370 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
371 * @{
372 */
373
374 /**
375 * @brief Write a value in DAC register
376 * @param __INSTANCE__ DAC Instance
377 * @param __REG__ Register to be written
378 * @param __VALUE__ Value to be written in the register
379 * @retval None
380 */
381 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
382
383 /**
384 * @brief Read a value in DAC register
385 * @param __INSTANCE__ DAC Instance
386 * @param __REG__ Register to be read
387 * @retval Register value
388 */
389 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
390
391 /**
392 * @}
393 */
394
395 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
396 * @{
397 */
398
399 /**
400 * @brief Helper macro to get DAC channel number in decimal format
401 * from literals LL_DAC_CHANNEL_x.
402 * Example:
403 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
404 * will return decimal number "1".
405 * @note The input can be a value from functions where a channel
406 * number is returned.
407 * @param __CHANNEL__ This parameter can be one of the following values:
408 * @arg @ref LL_DAC_CHANNEL_1
409 * @arg @ref LL_DAC_CHANNEL_2
410 * @retval 1...2
411 */
412 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
413 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
414
415 /**
416 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
417 * from number in decimal format.
418 * Example:
419 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
420 * will return a data equivalent to "LL_DAC_CHANNEL_1".
421 * @note If the input parameter does not correspond to a DAC channel,
422 * this macro returns value '0'.
423 * @param __DECIMAL_NB__ 1...2
424 * @retval Returned value can be one of the following values:
425 * @arg @ref LL_DAC_CHANNEL_1
426 * @arg @ref LL_DAC_CHANNEL_2
427 */
428 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
429 (((__DECIMAL_NB__) == 1U) \
430 ? ( \
431 LL_DAC_CHANNEL_1 \
432 ) \
433 : \
434 (((__DECIMAL_NB__) == 2U) \
435 ? ( \
436 LL_DAC_CHANNEL_2 \
437 ) \
438 : \
439 ( \
440 0 \
441 ) \
442 ) \
443 )
444
445 /**
446 * @brief Helper macro to define the DAC conversion data full-scale digital
447 * value corresponding to the selected DAC resolution.
448 * @note DAC conversion data full-scale corresponds to voltage range
449 * determined by analog voltage references Vref+ and Vref-
450 * (refer to reference manual).
451 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
452 * @arg @ref LL_DAC_RESOLUTION_12B
453 * @arg @ref LL_DAC_RESOLUTION_8B
454 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
455 */
456 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
457 ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
458
459 /**
460 * @brief Helper macro to calculate the DAC conversion data (unit: digital
461 * value) corresponding to a voltage (unit: mVolt).
462 * @note This helper macro is intended to provide input data in voltage
463 * rather than digital value,
464 * to be used with LL DAC functions such as
465 * @ref LL_DAC_ConvertData12RightAligned().
466 * @note Analog reference voltage (Vref+) must be either known from
467 * user board environment or can be calculated using ADC measurement
468 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
469 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
470 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
471 * (unit: mVolt).
472 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
473 * @arg @ref LL_DAC_RESOLUTION_12B
474 * @arg @ref LL_DAC_RESOLUTION_8B
475 * @retval DAC conversion data (unit: digital value)
476 */
477 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
478 __DAC_VOLTAGE__,\
479 __DAC_RESOLUTION__) \
480 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
481 / (__VREFANALOG_VOLTAGE__) \
482 )
483
484 /**
485 * @}
486 */
487
488 /**
489 * @}
490 */
491
492
493 /* Exported functions --------------------------------------------------------*/
494 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
495 * @{
496 */
497 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
498 * @{
499 */
500
501 /**
502 * @brief Set the conversion trigger source for the selected DAC channel.
503 * @note For conversion trigger source to be effective, DAC trigger
504 * must be enabled using function @ref LL_DAC_EnableTrigger().
505 * @note To set conversion trigger source, DAC channel must be disabled.
506 * Otherwise, the setting is discarded.
507 * @note Availability of parameters of trigger sources from timer
508 * depends on timers availability on the selected device.
509 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
510 * CR TSEL2 LL_DAC_SetTriggerSource
511 * @param DACx DAC instance
512 * @param DAC_Channel This parameter can be one of the following values:
513 * @arg @ref LL_DAC_CHANNEL_1
514 * @arg @ref LL_DAC_CHANNEL_2
515 * @param TriggerSource This parameter can be one of the following values:
516 * @arg @ref LL_DAC_TRIG_SOFTWARE
517 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
518 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
519 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
520 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
521 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
522 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
523 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
524 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
525 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
526 * @retval None
527 */
528 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
529 {
530 MODIFY_REG(DACx->CR,
531 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
532 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
533 }
534
535 /**
536 * @brief Get the conversion trigger source for the selected DAC channel.
537 * @note For conversion trigger source to be effective, DAC trigger
538 * must be enabled using function @ref LL_DAC_EnableTrigger().
539 * @note Availability of parameters of trigger sources from timer
540 * depends on timers availability on the selected device.
541 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
542 * CR TSEL2 LL_DAC_GetTriggerSource
543 * @param DACx DAC instance
544 * @param DAC_Channel This parameter can be one of the following values:
545 * @arg @ref LL_DAC_CHANNEL_1
546 * @arg @ref LL_DAC_CHANNEL_2
547 * @retval Returned value can be one of the following values:
548 * @arg @ref LL_DAC_TRIG_SOFTWARE
549 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
550 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
551 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
552 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
553 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
554 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
555 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
556 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
557 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
558 */
559 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
560 {
561 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
562 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
563 );
564 }
565
566 /**
567 * @brief Set the waveform automatic generation mode
568 * for the selected DAC channel.
569 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
570 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
571 * @param DACx DAC instance
572 * @param DAC_Channel This parameter can be one of the following values:
573 * @arg @ref LL_DAC_CHANNEL_1
574 * @arg @ref LL_DAC_CHANNEL_2
575 * @param WaveAutoGeneration This parameter can be one of the following values:
576 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
577 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
578 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
579 * @retval None
580 */
581 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
582 {
583 MODIFY_REG(DACx->CR,
584 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
585 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
586 }
587
588 /**
589 * @brief Get the waveform automatic generation mode
590 * for the selected DAC channel.
591 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
592 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
593 * @param DACx DAC instance
594 * @param DAC_Channel This parameter can be one of the following values:
595 * @arg @ref LL_DAC_CHANNEL_1
596 * @arg @ref LL_DAC_CHANNEL_2
597 * @retval Returned value can be one of the following values:
598 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
599 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
600 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
601 */
602 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
603 {
604 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
605 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
606 );
607 }
608
609 /**
610 * @brief Set the noise waveform generation for the selected DAC channel:
611 * Noise mode and parameters LFSR (linear feedback shift register).
612 * @note For wave generation to be effective, DAC channel
613 * wave generation mode must be enabled using
614 * function @ref LL_DAC_SetWaveAutoGeneration().
615 * @note This setting can be set when the selected DAC channel is disabled
616 * (otherwise, the setting operation is ignored).
617 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
618 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
619 * @param DACx DAC instance
620 * @param DAC_Channel This parameter can be one of the following values:
621 * @arg @ref LL_DAC_CHANNEL_1
622 * @arg @ref LL_DAC_CHANNEL_2
623 * @param NoiseLFSRMask This parameter can be one of the following values:
624 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
625 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
626 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
627 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
628 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
629 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
630 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
631 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
632 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
633 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
634 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
635 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
636 * @retval None
637 */
638 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
639 {
640 MODIFY_REG(DACx->CR,
641 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
642 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
643 }
644
645 /**
646 * @brief Set the noise waveform generation for the selected DAC channel:
647 * Noise mode and parameters LFSR (linear feedback shift register).
648 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
649 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
650 * @param DACx DAC instance
651 * @param DAC_Channel This parameter can be one of the following values:
652 * @arg @ref LL_DAC_CHANNEL_1
653 * @arg @ref LL_DAC_CHANNEL_2
654 * @retval Returned value can be one of the following values:
655 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
656 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
657 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
658 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
659 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
660 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
661 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
662 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
663 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
664 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
665 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
666 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
667 */
668 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
669 {
670 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
671 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
672 );
673 }
674
675 /**
676 * @brief Set the triangle waveform generation for the selected DAC channel:
677 * triangle mode and amplitude.
678 * @note For wave generation to be effective, DAC channel
679 * wave generation mode must be enabled using
680 * function @ref LL_DAC_SetWaveAutoGeneration().
681 * @note This setting can be set when the selected DAC channel is disabled
682 * (otherwise, the setting operation is ignored).
683 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
684 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
685 * @param DACx DAC instance
686 * @param DAC_Channel This parameter can be one of the following values:
687 * @arg @ref LL_DAC_CHANNEL_1
688 * @arg @ref LL_DAC_CHANNEL_2
689 * @param TriangleAmplitude This parameter can be one of the following values:
690 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
691 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
692 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
693 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
694 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
695 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
696 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
697 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
698 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
699 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
700 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
701 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
702 * @retval None
703 */
704 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
705 {
706 MODIFY_REG(DACx->CR,
707 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
708 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
709 }
710
711 /**
712 * @brief Set the triangle waveform generation for the selected DAC channel:
713 * triangle mode and amplitude.
714 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
715 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
716 * @param DACx DAC instance
717 * @param DAC_Channel This parameter can be one of the following values:
718 * @arg @ref LL_DAC_CHANNEL_1
719 * @arg @ref LL_DAC_CHANNEL_2
720 * @retval Returned value can be one of the following values:
721 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
722 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
723 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
724 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
725 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
726 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
727 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
728 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
729 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
730 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
731 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
732 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
733 */
734 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
735 {
736 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
737 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
738 );
739 }
740
741 /**
742 * @brief Set the output buffer for the selected DAC channel.
743 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
744 * CR BOFF2 LL_DAC_SetOutputBuffer
745 * @param DACx DAC instance
746 * @param DAC_Channel This parameter can be one of the following values:
747 * @arg @ref LL_DAC_CHANNEL_1
748 * @arg @ref LL_DAC_CHANNEL_2
749 * @param OutputBuffer This parameter can be one of the following values:
750 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
751 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
752 * @retval None
753 */
754 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
755 {
756 MODIFY_REG(DACx->CR,
757 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
758 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
759 }
760
761 /**
762 * @brief Get the output buffer state for the selected DAC channel.
763 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
764 * CR BOFF2 LL_DAC_GetOutputBuffer
765 * @param DACx DAC instance
766 * @param DAC_Channel This parameter can be one of the following values:
767 * @arg @ref LL_DAC_CHANNEL_1
768 * @arg @ref LL_DAC_CHANNEL_2
769 * @retval Returned value can be one of the following values:
770 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
771 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
772 */
773 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
774 {
775 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
776 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
777 );
778 }
779
780 /**
781 * @}
782 */
783
784 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
785 * @{
786 */
787
788 /**
789 * @brief Enable DAC DMA transfer request of the selected channel.
790 * @note To configure DMA source address (peripheral address),
791 * use function @ref LL_DAC_DMA_GetRegAddr().
792 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
793 * CR DMAEN2 LL_DAC_EnableDMAReq
794 * @param DACx DAC instance
795 * @param DAC_Channel This parameter can be one of the following values:
796 * @arg @ref LL_DAC_CHANNEL_1
797 * @arg @ref LL_DAC_CHANNEL_2
798 * @retval None
799 */
800 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
801 {
802 SET_BIT(DACx->CR,
803 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
804 }
805
806 /**
807 * @brief Disable DAC DMA transfer request of the selected channel.
808 * @note To configure DMA source address (peripheral address),
809 * use function @ref LL_DAC_DMA_GetRegAddr().
810 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
811 * CR DMAEN2 LL_DAC_DisableDMAReq
812 * @param DACx DAC instance
813 * @param DAC_Channel This parameter can be one of the following values:
814 * @arg @ref LL_DAC_CHANNEL_1
815 * @arg @ref LL_DAC_CHANNEL_2
816 * @retval None
817 */
818 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
819 {
820 CLEAR_BIT(DACx->CR,
821 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
822 }
823
824 /**
825 * @brief Get DAC DMA transfer request state of the selected channel.
826 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
827 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
828 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
829 * @param DACx DAC instance
830 * @param DAC_Channel This parameter can be one of the following values:
831 * @arg @ref LL_DAC_CHANNEL_1
832 * @arg @ref LL_DAC_CHANNEL_2
833 * @retval State of bit (1 or 0).
834 */
835 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
836 {
837 return (READ_BIT(DACx->CR,
838 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
839 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
840 }
841
842 /**
843 * @brief Function to help to configure DMA transfer to DAC: retrieve the
844 * DAC register address from DAC instance and a list of DAC registers
845 * intended to be used (most commonly) with DMA transfer.
846 * @note These DAC registers are data holding registers:
847 * when DAC conversion is requested, DAC generates a DMA transfer
848 * request to have data available in DAC data holding registers.
849 * @note This macro is intended to be used with LL DMA driver, refer to
850 * function "LL_DMA_ConfigAddresses()".
851 * Example:
852 * LL_DMA_ConfigAddresses(DMA1,
853 * LL_DMA_CHANNEL_1,
854 * (uint32_t)&< array or variable >,
855 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
856 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
857 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
858 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
859 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
860 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
861 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
862 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
863 * @param DACx DAC instance
864 * @param DAC_Channel This parameter can be one of the following values:
865 * @arg @ref LL_DAC_CHANNEL_1
866 * @arg @ref LL_DAC_CHANNEL_2
867 * @param Register This parameter can be one of the following values:
868 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
869 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
870 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
871 * @retval DAC register address
872 */
873 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
874 {
875 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
876 /* DAC channel selected. */
877 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
878 }
879 /**
880 * @}
881 */
882
883 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
884 * @{
885 */
886
887 /**
888 * @brief Enable DAC selected channel.
889 * @rmtoll CR EN1 LL_DAC_Enable\n
890 * CR EN2 LL_DAC_Enable
891 * @note After enable from off state, DAC channel requires a delay
892 * for output voltage to reach accuracy +/- 1 LSB.
893 * Refer to device datasheet, parameter "tWAKEUP".
894 * @param DACx DAC instance
895 * @param DAC_Channel This parameter can be one of the following values:
896 * @arg @ref LL_DAC_CHANNEL_1
897 * @arg @ref LL_DAC_CHANNEL_2
898 * @retval None
899 */
900 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
901 {
902 SET_BIT(DACx->CR,
903 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
904 }
905
906 /**
907 * @brief Disable DAC selected channel.
908 * @rmtoll CR EN1 LL_DAC_Disable\n
909 * CR EN2 LL_DAC_Disable
910 * @param DACx DAC instance
911 * @param DAC_Channel This parameter can be one of the following values:
912 * @arg @ref LL_DAC_CHANNEL_1
913 * @arg @ref LL_DAC_CHANNEL_2
914 * @retval None
915 */
916 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
917 {
918 CLEAR_BIT(DACx->CR,
919 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
920 }
921
922 /**
923 * @brief Get DAC enable state of the selected channel.
924 * (0: DAC channel is disabled, 1: DAC channel is enabled)
925 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
926 * CR EN2 LL_DAC_IsEnabled
927 * @param DACx DAC instance
928 * @param DAC_Channel This parameter can be one of the following values:
929 * @arg @ref LL_DAC_CHANNEL_1
930 * @arg @ref LL_DAC_CHANNEL_2
931 * @retval State of bit (1 or 0).
932 */
933 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
934 {
935 return (READ_BIT(DACx->CR,
936 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
937 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
938 }
939
940 /**
941 * @brief Enable DAC trigger of the selected channel.
942 * @note - If DAC trigger is disabled, DAC conversion is performed
943 * automatically once the data holding register is updated,
944 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
945 * @ref LL_DAC_ConvertData12RightAligned(), ...
946 * - If DAC trigger is enabled, DAC conversion is performed
947 * only when a hardware of software trigger event is occurring.
948 * Select trigger source using
949 * function @ref LL_DAC_SetTriggerSource().
950 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
951 * CR TEN2 LL_DAC_EnableTrigger
952 * @param DACx DAC instance
953 * @param DAC_Channel This parameter can be one of the following values:
954 * @arg @ref LL_DAC_CHANNEL_1
955 * @arg @ref LL_DAC_CHANNEL_2
956 * @retval None
957 */
958 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
959 {
960 SET_BIT(DACx->CR,
961 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
962 }
963
964 /**
965 * @brief Disable DAC trigger of the selected channel.
966 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
967 * CR TEN2 LL_DAC_DisableTrigger
968 * @param DACx DAC instance
969 * @param DAC_Channel This parameter can be one of the following values:
970 * @arg @ref LL_DAC_CHANNEL_1
971 * @arg @ref LL_DAC_CHANNEL_2
972 * @retval None
973 */
974 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
975 {
976 CLEAR_BIT(DACx->CR,
977 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
978 }
979
980 /**
981 * @brief Get DAC trigger state of the selected channel.
982 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
983 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
984 * CR TEN2 LL_DAC_IsTriggerEnabled
985 * @param DACx DAC instance
986 * @param DAC_Channel This parameter can be one of the following values:
987 * @arg @ref LL_DAC_CHANNEL_1
988 * @arg @ref LL_DAC_CHANNEL_2
989 * @retval State of bit (1 or 0).
990 */
991 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
992 {
993 return (READ_BIT(DACx->CR,
994 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
995 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
996 }
997
998 /**
999 * @brief Trig DAC conversion by software for the selected DAC channel.
1000 * @note Preliminarily, DAC trigger must be set to software trigger
1001 * using function @ref LL_DAC_SetTriggerSource()
1002 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1003 * and DAC trigger must be enabled using
1004 * function @ref LL_DAC_EnableTrigger().
1005 * @note For devices featuring DAC with 2 channels: this function
1006 * can perform a SW start of both DAC channels simultaneously.
1007 * Two channels can be selected as parameter.
1008 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1009 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1010 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1011 * @param DACx DAC instance
1012 * @param DAC_Channel This parameter can a combination of the following values:
1013 * @arg @ref LL_DAC_CHANNEL_1
1014 * @arg @ref LL_DAC_CHANNEL_2
1015 * @retval None
1016 */
1017 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1018 {
1019 SET_BIT(DACx->SWTRIGR,
1020 (DAC_Channel & DAC_SWTR_CHX_MASK));
1021 }
1022
1023 /**
1024 * @brief Set the data to be loaded in the data holding register
1025 * in format 12 bits left alignment (LSB aligned on bit 0),
1026 * for the selected DAC channel.
1027 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1028 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1029 * @param DACx DAC instance
1030 * @param DAC_Channel This parameter can be one of the following values:
1031 * @arg @ref LL_DAC_CHANNEL_1
1032 * @arg @ref LL_DAC_CHANNEL_2
1033 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1034 * @retval None
1035 */
1036 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1037 {
1038 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
1039
1040 MODIFY_REG(*preg,
1041 DAC_DHR12R1_DACC1DHR,
1042 Data);
1043 }
1044
1045 /**
1046 * @brief Set the data to be loaded in the data holding register
1047 * in format 12 bits left alignment (MSB aligned on bit 15),
1048 * for the selected DAC channel.
1049 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1050 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1051 * @param DACx DAC instance
1052 * @param DAC_Channel This parameter can be one of the following values:
1053 * @arg @ref LL_DAC_CHANNEL_1
1054 * @arg @ref LL_DAC_CHANNEL_2
1055 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1056 * @retval None
1057 */
1058 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1059 {
1060 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
1061
1062 MODIFY_REG(*preg,
1063 DAC_DHR12L1_DACC1DHR,
1064 Data);
1065 }
1066
1067 /**
1068 * @brief Set the data to be loaded in the data holding register
1069 * in format 8 bits left alignment (LSB aligned on bit 0),
1070 * for the selected DAC channel.
1071 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1072 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1073 * @param DACx DAC instance
1074 * @param DAC_Channel This parameter can be one of the following values:
1075 * @arg @ref LL_DAC_CHANNEL_1
1076 * @arg @ref LL_DAC_CHANNEL_2
1077 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1078 * @retval None
1079 */
1080 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1081 {
1082 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
1083
1084 MODIFY_REG(*preg,
1085 DAC_DHR8R1_DACC1DHR,
1086 Data);
1087 }
1088
1089 /**
1090 * @brief Set the data to be loaded in the data holding register
1091 * in format 12 bits left alignment (LSB aligned on bit 0),
1092 * for both DAC channels.
1093 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1094 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1095 * @param DACx DAC instance
1096 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1097 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1098 * @retval None
1099 */
1100 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1101 {
1102 MODIFY_REG(DACx->DHR12RD,
1103 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1104 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1105 }
1106
1107 /**
1108 * @brief Set the data to be loaded in the data holding register
1109 * in format 12 bits left alignment (MSB aligned on bit 15),
1110 * for both DAC channels.
1111 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1112 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1113 * @param DACx DAC instance
1114 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1115 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1116 * @retval None
1117 */
1118 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1119 {
1120 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1121 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1122 /* the 4 LSB must be taken into account for the shift value. */
1123 MODIFY_REG(DACx->DHR12LD,
1124 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1125 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1126 }
1127
1128 /**
1129 * @brief Set the data to be loaded in the data holding register
1130 * in format 8 bits left alignment (LSB aligned on bit 0),
1131 * for both DAC channels.
1132 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1133 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1134 * @param DACx DAC instance
1135 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1136 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1137 * @retval None
1138 */
1139 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1140 {
1141 MODIFY_REG(DACx->DHR8RD,
1142 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1143 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1144 }
1145
1146 /**
1147 * @brief Retrieve output data currently generated for the selected DAC channel.
1148 * @note Whatever alignment and resolution settings
1149 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1150 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1151 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1152 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1153 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1154 * @param DACx DAC instance
1155 * @param DAC_Channel This parameter can be one of the following values:
1156 * @arg @ref LL_DAC_CHANNEL_1
1157 * @arg @ref LL_DAC_CHANNEL_2
1158 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1159 */
1160 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1161 {
1162 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
1163
1164 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1165 }
1166
1167 /**
1168 * @}
1169 */
1170
1171 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1172 * @{
1173 */
1174 #if defined(DAC_SR_DMAUDR1)
1175 /**
1176 * @brief Get DAC underrun flag for DAC channel 1
1177 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1178 * @param DACx DAC instance
1179 * @retval State of bit (1 or 0).
1180 */
1181 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1182 {
1183 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
1184 }
1185 #endif /* DAC_SR_DMAUDR1 */
1186
1187 #if defined(DAC_SR_DMAUDR2)
1188 /**
1189 * @brief Get DAC underrun flag for DAC channel 2
1190 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1191 * @param DACx DAC instance
1192 * @retval State of bit (1 or 0).
1193 */
1194 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1195 {
1196 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
1197 }
1198 #endif /* DAC_SR_DMAUDR2 */
1199
1200 #if defined(DAC_SR_DMAUDR1)
1201 /**
1202 * @brief Clear DAC underrun flag for DAC channel 1
1203 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1204 * @param DACx DAC instance
1205 * @retval None
1206 */
1207 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1208 {
1209 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1210 }
1211 #endif /* DAC_SR_DMAUDR1 */
1212
1213 #if defined(DAC_SR_DMAUDR2)
1214 /**
1215 * @brief Clear DAC underrun flag for DAC channel 2
1216 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1217 * @param DACx DAC instance
1218 * @retval None
1219 */
1220 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1221 {
1222 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1223 }
1224 #endif /* DAC_SR_DMAUDR2 */
1225
1226 /**
1227 * @}
1228 */
1229 /** @defgroup DAC_LL_EF_IT_Management IT management
1230 * @{
1231 */
1232
1233 #if defined(DAC_CR_DMAUDRIE1)
1234 /**
1235 * @brief Enable DMA underrun interrupt for DAC channel 1
1236 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1237 * @param DACx DAC instance
1238 * @retval None
1239 */
1240 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1241 {
1242 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1243 }
1244 #endif /* DAC_CR_DMAUDRIE1 */
1245
1246 #if defined(DAC_CR_DMAUDRIE2)
1247 /**
1248 * @brief Enable DMA underrun interrupt for DAC channel 2
1249 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1250 * @param DACx DAC instance
1251 * @retval None
1252 */
1253 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1254 {
1255 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1256 }
1257 #endif /* DAC_CR_DMAUDRIE2 */
1258
1259 #if defined(DAC_CR_DMAUDRIE1)
1260 /**
1261 * @brief Disable DMA underrun interrupt for DAC channel 1
1262 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1263 * @param DACx DAC instance
1264 * @retval None
1265 */
1266 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1267 {
1268 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1269 }
1270 #endif /* DAC_CR_DMAUDRIE1 */
1271
1272 #if defined(DAC_CR_DMAUDRIE2)
1273 /**
1274 * @brief Disable DMA underrun interrupt for DAC channel 2
1275 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1276 * @param DACx DAC instance
1277 * @retval None
1278 */
1279 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1280 {
1281 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1282 }
1283 #endif /* DAC_CR_DMAUDRIE2 */
1284
1285 #if defined(DAC_CR_DMAUDRIE1)
1286 /**
1287 * @brief Get DMA underrun interrupt for DAC channel 1
1288 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1289 * @param DACx DAC instance
1290 * @retval State of bit (1 or 0).
1291 */
1292 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1293 {
1294 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
1295 }
1296 #endif /* DAC_CR_DMAUDRIE1 */
1297
1298 #if defined(DAC_CR_DMAUDRIE2)
1299 /**
1300 * @brief Get DMA underrun interrupt for DAC channel 2
1301 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1302 * @param DACx DAC instance
1303 * @retval State of bit (1 or 0).
1304 */
1305 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1306 {
1307 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
1308 }
1309 #endif /* DAC_CR_DMAUDRIE2 */
1310
1311 /**
1312 * @}
1313 */
1314
1315 #if defined(USE_FULL_LL_DRIVER)
1316 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1317 * @{
1318 */
1319
1320 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
1321 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
1322 void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
1323
1324 /**
1325 * @}
1326 */
1327 #endif /* USE_FULL_LL_DRIVER */
1328
1329 /**
1330 * @}
1331 */
1332
1333 /**
1334 * @}
1335 */
1336
1337 #endif /* DAC */
1338
1339 /**
1340 * @}
1341 */
1342
1343 #ifdef __cplusplus
1344 }
1345 #endif
1346
1347 #endif /* __STM32F1xx_LL_DAC_H */
1348
1349 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/