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Increment eeprom version
[betaflight.git] / lib / main / STM32F1 / Drivers / STM32F1xx_HAL_Driver / Inc / stm32f1xx_ll_gpio.h
blob6a2b64fb21ba9eff124f48cecad1e8c28336d9b0
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_gpio.h
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 12-May-2017
7 * @brief Header file of GPIO LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F1xx_LL_GPIO_H
40 #define __STM32F1xx_LL_GPIO_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f1xx.h"
48
49 /** @addtogroup STM32F1xx_LL_Driver
50 * @{
51 */
52
53 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
54
55 /** @defgroup GPIO_LL GPIO
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61
62 /* Private constants ---------------------------------------------------------*/
63 /** @defgroup GPIO_LL_Private_Constants GPIO Private Constants
64 * @{
65 */
66 /**
67 * @}
68 */
69
70
71 /* Private macros ------------------------------------------------------------*/
72 #if defined(USE_FULL_LL_DRIVER)
73 /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
74 * @{
75 */
76
77 /**
78 * @}
79 */
80 #endif /*USE_FULL_LL_DRIVER*/
81
82 /* Exported types ------------------------------------------------------------*/
83 #if defined(USE_FULL_LL_DRIVER)
84 /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
85 * @{
86 */
87
88 /**
89 * @brief LL GPIO Init Structure definition
90 */
91 typedef struct
92 {
93 uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
94 This parameter can be any value of @ref GPIO_LL_EC_PIN */
95
96 uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
97 This parameter can be a value of @ref GPIO_LL_EC_MODE.
98
99 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
100
101 uint32_t Speed; /*!< Specifies the speed for the selected pins.
102 This parameter can be a value of @ref GPIO_LL_EC_SPEED.
103
104 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
105
106 uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
107 This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
108
109 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
110
111 uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
112 This parameter can be a value of @ref GPIO_LL_EC_PULL.
113
114 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
115 }LL_GPIO_InitTypeDef;
116
117 /**
118 * @}
119 */
120 #endif /* USE_FULL_LL_DRIVER */
121
122 /* Exported constants --------------------------------------------------------*/
123 /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
124 * @{
125 */
126
127 /** @defgroup GPIO_LL_EC_PIN PIN
128 * @{
129 */
130 #define LL_GPIO_PIN_0 (GPIO_BSRR_BS0 << 8) | 0x00000001U /*!< Select pin 0 */
131 #define LL_GPIO_PIN_1 (GPIO_BSRR_BS1 << 8) | 0x00000002U /*!< Select pin 1 */
132 #define LL_GPIO_PIN_2 (GPIO_BSRR_BS2 << 8) | 0x00000004U /*!< Select pin 2 */
133 #define LL_GPIO_PIN_3 (GPIO_BSRR_BS3 << 8) | 0x00000008U /*!< Select pin 3 */
134 #define LL_GPIO_PIN_4 (GPIO_BSRR_BS4 << 8) | 0x00000010U /*!< Select pin 4 */
135 #define LL_GPIO_PIN_5 (GPIO_BSRR_BS5 << 8) | 0x00000020U /*!< Select pin 5 */
136 #define LL_GPIO_PIN_6 (GPIO_BSRR_BS6 << 8) | 0x00000040U /*!< Select pin 6 */
137 #define LL_GPIO_PIN_7 (GPIO_BSRR_BS7 << 8) | 0x00000080U /*!< Select pin 7 */
138 #define LL_GPIO_PIN_8 (GPIO_BSRR_BS8 << 8) | 0x04000001U /*!< Select pin 8 */
139 #define LL_GPIO_PIN_9 (GPIO_BSRR_BS9 << 8) | 0x04000002U /*!< Select pin 9 */
140 #define LL_GPIO_PIN_10 (GPIO_BSRR_BS10 << 8) | 0x04000004U /*!< Select pin 10 */
141 #define LL_GPIO_PIN_11 (GPIO_BSRR_BS11 << 8) | 0x04000008U /*!< Select pin 11 */
142 #define LL_GPIO_PIN_12 (GPIO_BSRR_BS12 << 8) | 0x04000010U /*!< Select pin 12 */
143 #define LL_GPIO_PIN_13 (GPIO_BSRR_BS13 << 8) | 0x04000020U /*!< Select pin 13 */
144 #define LL_GPIO_PIN_14 (GPIO_BSRR_BS14 << 8) | 0x04000040U /*!< Select pin 14 */
145 #define LL_GPIO_PIN_15 (GPIO_BSRR_BS15 << 8) | 0x04000080U /*!< Select pin 15 */
146 #define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | \
147 LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | \
148 LL_GPIO_PIN_6 | LL_GPIO_PIN_7 | LL_GPIO_PIN_8 | \
149 LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \
150 LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \
151 LL_GPIO_PIN_15) /*!< Select all pins */
152 /**
153 * @}
154 */
155
156 /** @defgroup GPIO_LL_EC_MODE Mode
157 * @{
158 */
159 #define LL_GPIO_MODE_ANALOG 0x00000000U /*!< Select analog mode */
160 #define LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0 /*!< Select floating mode */
161 #define LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1 /*!< Select input mode */
162 #define LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0 /*!< Select general purpose output mode */
163 #define LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 | GPIO_CRL_MODE0_0) /*!< Select alternate function mode */
164 /**
165 * @}
166 */
167
168 /** @defgroup GPIO_LL_EC_OUTPUT Output Type
169 * @{
170 */
171 #define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U /*!< Select push-pull as output type */
172 #define LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0 /*!< Select open-drain as output type */
173 /**
174 * @}
175 */
176
177 /** @defgroup GPIO_LL_EC_SPEED Output Speed
178 * @{
179 */
180 #define LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0 /*!< Select Output mode, max speed 10 MHz */
181 #define LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1 /*!< Select Output mode, max speed 20 MHz */
182 #define LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0 /*!< Select Output mode, max speed 50 MHz */
183 /**
184 * @}
185 */
186
187 #define LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz /*!< Select I/O low output speed */
188 #define LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz /*!< Select I/O medium output speed */
189 #define LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz /*!< Select I/O high output speed */
190
191 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
192 * @{
193 */
194 #define LL_GPIO_PULL_DOWN 0x00000000U /*!< Select I/O pull down */
195 #define LL_GPIO_PULL_UP GPIO_ODR_ODR0 /*!< Select I/O pull up */
196
197 /**
198 * @}
199 */
200
201 /** @defgroup GPIO_LL_EVENTOUT_PIN EVENTOUT Pin
202 * @{
203 */
204
205 #define LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
206 #define LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
207 #define LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
208 #define LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
209 #define LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
210 #define LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
211 #define LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
212 #define LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
213 #define LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
214 #define LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
215 #define LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
216 #define LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
217 #define LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
218 #define LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
219 #define LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
220 #define LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
221
222 /**
223 * @}
224 */
225
226 /** @defgroup GPIO_LL_EVENTOUT_PORT EVENTOUT Port
227 * @{
228 */
229
230 #define LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
231 #define LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
232 #define LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
233 #define LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
234 #define LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
235
236 /**
237 * @}
238 */
239
240 /** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT
241 * @{
242 */
243 #define LL_GPIO_AF_EXTI_PORTA (uint32_t)0 /*!< EXTI PORT A */
244 #define LL_GPIO_AF_EXTI_PORTB (uint32_t)1 /*!< EXTI PORT B */
245 #define LL_GPIO_AF_EXTI_PORTC (uint32_t)2 /*!< EXTI PORT C */
246 #define LL_GPIO_AF_EXTI_PORTD (uint32_t)3 /*!< EXTI PORT D */
247 #define LL_GPIO_AF_EXTI_PORTE (uint32_t)4 /*!< EXTI PORT E */
248 #define LL_GPIO_AF_EXTI_PORTF (uint32_t)5 /*!< EXTI PORT F */
249 #define LL_GPIO_AF_EXTI_PORTG (uint32_t)6 /*!< EXTI PORT G */
250 /**
251 * @}
252 */
253
254 /** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE
255 * @{
256 */
257 #define LL_GPIO_AF_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0) /*!< EXTI_POSITION_0 | EXTICR[0] */
258 #define LL_GPIO_AF_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0) /*!< EXTI_POSITION_4 | EXTICR[0] */
259 #define LL_GPIO_AF_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0) /*!< EXTI_POSITION_8 | EXTICR[0] */
260 #define LL_GPIO_AF_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0) /*!< EXTI_POSITION_12 | EXTICR[0] */
261 #define LL_GPIO_AF_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1) /*!< EXTI_POSITION_0 | EXTICR[1] */
262 #define LL_GPIO_AF_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1) /*!< EXTI_POSITION_4 | EXTICR[1] */
263 #define LL_GPIO_AF_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1) /*!< EXTI_POSITION_8 | EXTICR[1] */
264 #define LL_GPIO_AF_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1) /*!< EXTI_POSITION_12 | EXTICR[1] */
265 #define LL_GPIO_AF_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2) /*!< EXTI_POSITION_0 | EXTICR[2] */
266 #define LL_GPIO_AF_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2) /*!< EXTI_POSITION_4 | EXTICR[2] */
267 #define LL_GPIO_AF_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2) /*!< EXTI_POSITION_8 | EXTICR[2] */
268 #define LL_GPIO_AF_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2) /*!< EXTI_POSITION_12 | EXTICR[2] */
269 #define LL_GPIO_AF_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3) /*!< EXTI_POSITION_0 | EXTICR[3] */
270 #define LL_GPIO_AF_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3) /*!< EXTI_POSITION_4 | EXTICR[3] */
271 #define LL_GPIO_AF_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3) /*!< EXTI_POSITION_8 | EXTICR[3] */
272 #define LL_GPIO_AF_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3) /*!< EXTI_POSITION_12 | EXTICR[3] */
273 /**
274 * @}
275 */
276
277 /**
278 * @}
279 */
280
281 /* Exported macro ------------------------------------------------------------*/
282 /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
283 * @{
284 */
285
286 /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
287 * @{
288 */
289
290 /**
291 * @brief Write a value in GPIO register
292 * @param __INSTANCE__ GPIO Instance
293 * @param __REG__ Register to be written
294 * @param __VALUE__ Value to be written in the register
295 * @retval None
296 */
297 #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
298
299 /**
300 * @brief Read a value in GPIO register
301 * @param __INSTANCE__ GPIO Instance
302 * @param __REG__ Register to be read
303 * @retval Register value
304 */
305 #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
306 /**
307 * @}
308 */
309
310 /**
311 * @}
312 */
313
314 /* Exported functions --------------------------------------------------------*/
315 /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
316 * @{
317 */
318
319 /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
320 * @{
321 */
322
323 /**
324 * @brief Configure gpio mode for a dedicated pin on dedicated port.
325 * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
326 * Alternate function Output.
327 * @note Warning: only one pin can be passed as parameter.
328 * @rmtoll CRL CNFy LL_GPIO_SetPinMode
329 * @rmtoll CRL MODEy LL_GPIO_SetPinMode
330 * @rmtoll CRH CNFy LL_GPIO_SetPinMode
331 * @rmtoll CRH MODEy LL_GPIO_SetPinMode
332 * @param GPIOx GPIO Port
333 * @param Pin This parameter can be one of the following values:
334 * @arg @ref LL_GPIO_PIN_0
335 * @arg @ref LL_GPIO_PIN_1
336 * @arg @ref LL_GPIO_PIN_2
337 * @arg @ref LL_GPIO_PIN_3
338 * @arg @ref LL_GPIO_PIN_4
339 * @arg @ref LL_GPIO_PIN_5
340 * @arg @ref LL_GPIO_PIN_6
341 * @arg @ref LL_GPIO_PIN_7
342 * @arg @ref LL_GPIO_PIN_8
343 * @arg @ref LL_GPIO_PIN_9
344 * @arg @ref LL_GPIO_PIN_10
345 * @arg @ref LL_GPIO_PIN_11
346 * @arg @ref LL_GPIO_PIN_12
347 * @arg @ref LL_GPIO_PIN_13
348 * @arg @ref LL_GPIO_PIN_14
349 * @arg @ref LL_GPIO_PIN_15
350 * @param Mode This parameter can be one of the following values:
351 * @arg @ref LL_GPIO_MODE_ANALOG
352 * @arg @ref LL_GPIO_MODE_FLOATING
353 * @arg @ref LL_GPIO_MODE_INPUT
354 * @arg @ref LL_GPIO_MODE_OUTPUT
355 * @arg @ref LL_GPIO_MODE_ALTERNATE
356 * @retval None
357 */
358 __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
359 {
360 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24)));
361 MODIFY_REG(*pReg, ((GPIO_CRL_CNF0|GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), (Mode << (POSITION_VAL(Pin) * 4U)));
362 }
363
364 /**
365 * @brief Return gpio mode for a dedicated pin on dedicated port.
366 * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
367 * Alternate function Output.
368 * @note Warning: only one pin can be passed as parameter.
369 * @rmtoll CRL CNFy LL_GPIO_GetPinMode
370 * @rmtoll CRL MODEy LL_GPIO_GetPinMode
371 * @rmtoll CRH CNFy LL_GPIO_GetPinMode
372 * @rmtoll CRH MODEy LL_GPIO_GetPinMode
373 * @param GPIOx GPIO Port
374 * @param Pin This parameter can be one of the following values:
375 * @arg @ref LL_GPIO_PIN_0
376 * @arg @ref LL_GPIO_PIN_1
377 * @arg @ref LL_GPIO_PIN_2
378 * @arg @ref LL_GPIO_PIN_3
379 * @arg @ref LL_GPIO_PIN_4
380 * @arg @ref LL_GPIO_PIN_5
381 * @arg @ref LL_GPIO_PIN_6
382 * @arg @ref LL_GPIO_PIN_7
383 * @arg @ref LL_GPIO_PIN_8
384 * @arg @ref LL_GPIO_PIN_9
385 * @arg @ref LL_GPIO_PIN_10
386 * @arg @ref LL_GPIO_PIN_11
387 * @arg @ref LL_GPIO_PIN_12
388 * @arg @ref LL_GPIO_PIN_13
389 * @arg @ref LL_GPIO_PIN_14
390 * @arg @ref LL_GPIO_PIN_15
391 * @retval Returned value can be one of the following values:
392 * @arg @ref LL_GPIO_MODE_ANALOG
393 * @arg @ref LL_GPIO_MODE_FLOATING
394 * @arg @ref LL_GPIO_MODE_INPUT
395 * @arg @ref LL_GPIO_MODE_OUTPUT
396 * @arg @ref LL_GPIO_MODE_ALTERNATE
397 */
398 __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
399 {
400 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24)));
401 return (uint32_t)(READ_BIT(*pReg,
402 ((GPIO_CRL_CNF0|GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
403 }
404
405 /**
406 * @brief Configure gpio speed for a dedicated pin on dedicated port.
407 * @note I/O speed can be Low, Medium or Fast speed.
408 * @note Warning: only one pin can be passed as parameter.
409 * @note Refer to datasheet for frequency specifications and the power
410 * supply and load conditions for each speed.
411 * @rmtoll CRL MODEy LL_GPIO_SetPinSpeed
412 * @rmtoll CRH MODEy LL_GPIO_SetPinSpeed
413 * @param GPIOx GPIO Port
414 * @param Pin This parameter can be one of the following values:
415 * @arg @ref LL_GPIO_PIN_0
416 * @arg @ref LL_GPIO_PIN_1
417 * @arg @ref LL_GPIO_PIN_2
418 * @arg @ref LL_GPIO_PIN_3
419 * @arg @ref LL_GPIO_PIN_4
420 * @arg @ref LL_GPIO_PIN_5
421 * @arg @ref LL_GPIO_PIN_6
422 * @arg @ref LL_GPIO_PIN_7
423 * @arg @ref LL_GPIO_PIN_8
424 * @arg @ref LL_GPIO_PIN_9
425 * @arg @ref LL_GPIO_PIN_10
426 * @arg @ref LL_GPIO_PIN_11
427 * @arg @ref LL_GPIO_PIN_12
428 * @arg @ref LL_GPIO_PIN_13
429 * @arg @ref LL_GPIO_PIN_14
430 * @arg @ref LL_GPIO_PIN_15
431 * @param Speed This parameter can be one of the following values:
432 * @arg @ref LL_GPIO_SPEED_FREQ_LOW
433 * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
434 * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
435 * @retval None
436 */
437 __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
438 {
439 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24)));
440 MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)),
441 (Speed << (POSITION_VAL(Pin) * 4U)));
442 }
443
444 /**
445 * @brief Return gpio speed for a dedicated pin on dedicated port.
446 * @note I/O speed can be Low, Medium, Fast or High speed.
447 * @note Warning: only one pin can be passed as parameter.
448 * @note Refer to datasheet for frequency specifications and the power
449 * supply and load conditions for each speed.
450 * @rmtoll CRL MODEy LL_GPIO_GetPinSpeed
451 * @rmtoll CRH MODEy LL_GPIO_GetPinSpeed
452 * @param GPIOx GPIO Port
453 * @param Pin This parameter can be one of the following values:
454 * @arg @ref LL_GPIO_PIN_0
455 * @arg @ref LL_GPIO_PIN_1
456 * @arg @ref LL_GPIO_PIN_2
457 * @arg @ref LL_GPIO_PIN_3
458 * @arg @ref LL_GPIO_PIN_4
459 * @arg @ref LL_GPIO_PIN_5
460 * @arg @ref LL_GPIO_PIN_6
461 * @arg @ref LL_GPIO_PIN_7
462 * @arg @ref LL_GPIO_PIN_8
463 * @arg @ref LL_GPIO_PIN_9
464 * @arg @ref LL_GPIO_PIN_10
465 * @arg @ref LL_GPIO_PIN_11
466 * @arg @ref LL_GPIO_PIN_12
467 * @arg @ref LL_GPIO_PIN_13
468 * @arg @ref LL_GPIO_PIN_14
469 * @arg @ref LL_GPIO_PIN_15
470 * @retval Returned value can be one of the following values:
471 * @arg @ref LL_GPIO_SPEED_FREQ_LOW
472 * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
473 * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
474 */
475 __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
476 {
477 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24)));
478 return (uint32_t)(READ_BIT(*pReg,
479 (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
480 }
481
482 /**
483 * @brief Configure gpio output type for several pins on dedicated port.
484 * @note Output type as to be set when gpio pin is in output or
485 * alternate modes. Possible type are Push-pull or Open-drain.
486 * @rmtoll CRL MODEy LL_GPIO_SetPinOutputType
487 * @rmtoll CRH MODEy LL_GPIO_SetPinOutputType
488 * @param GPIOx GPIO Port
489 * @param Pin This parameter can be a combination of the following values:
490 * @arg @ref LL_GPIO_PIN_0
491 * @arg @ref LL_GPIO_PIN_1
492 * @arg @ref LL_GPIO_PIN_2
493 * @arg @ref LL_GPIO_PIN_3
494 * @arg @ref LL_GPIO_PIN_4
495 * @arg @ref LL_GPIO_PIN_5
496 * @arg @ref LL_GPIO_PIN_6
497 * @arg @ref LL_GPIO_PIN_7
498 * @arg @ref LL_GPIO_PIN_8
499 * @arg @ref LL_GPIO_PIN_9
500 * @arg @ref LL_GPIO_PIN_10
501 * @arg @ref LL_GPIO_PIN_11
502 * @arg @ref LL_GPIO_PIN_12
503 * @arg @ref LL_GPIO_PIN_13
504 * @arg @ref LL_GPIO_PIN_14
505 * @arg @ref LL_GPIO_PIN_15
506 * @arg @ref LL_GPIO_PIN_ALL
507 * @param OutputType This parameter can be one of the following values:
508 * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
509 * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
510 * @retval None
511 */
512 __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
513 {
514 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24)));
515 MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)),
516 (OutputType << (POSITION_VAL(Pin) * 4U)));
517 }
518
519 /**
520 * @brief Return gpio output type for several pins on dedicated port.
521 * @note Output type as to be set when gpio pin is in output or
522 * alternate modes. Possible type are Push-pull or Open-drain.
523 * @note Warning: only one pin can be passed as parameter.
524 * @rmtoll CRL MODEy LL_GPIO_GetPinOutputType
525 * @rmtoll CRH MODEy LL_GPIO_GetPinOutputType
526 * @param GPIOx GPIO Port
527 * @param Pin This parameter can be one of the following values:
528 * @arg @ref LL_GPIO_PIN_0
529 * @arg @ref LL_GPIO_PIN_1
530 * @arg @ref LL_GPIO_PIN_2
531 * @arg @ref LL_GPIO_PIN_3
532 * @arg @ref LL_GPIO_PIN_4
533 * @arg @ref LL_GPIO_PIN_5
534 * @arg @ref LL_GPIO_PIN_6
535 * @arg @ref LL_GPIO_PIN_7
536 * @arg @ref LL_GPIO_PIN_8
537 * @arg @ref LL_GPIO_PIN_9
538 * @arg @ref LL_GPIO_PIN_10
539 * @arg @ref LL_GPIO_PIN_11
540 * @arg @ref LL_GPIO_PIN_12
541 * @arg @ref LL_GPIO_PIN_13
542 * @arg @ref LL_GPIO_PIN_14
543 * @arg @ref LL_GPIO_PIN_15
544 * @arg @ref LL_GPIO_PIN_ALL
545 * @retval Returned value can be one of the following values:
546 * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
547 * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
548 */
549 __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
550 {
551 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24)));
552 return (uint32_t)(READ_BIT(*pReg,
553 (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
554
555 }
556
557 /**
558 * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
559 * @note Warning: only one pin can be passed as parameter.
560 * @rmtoll ODR ODR LL_GPIO_SetPinPull
561 * @param GPIOx GPIO Port
562 * @param Pin This parameter can be one of the following values:
563 * @arg @ref LL_GPIO_PIN_0
564 * @arg @ref LL_GPIO_PIN_1
565 * @arg @ref LL_GPIO_PIN_2
566 * @arg @ref LL_GPIO_PIN_3
567 * @arg @ref LL_GPIO_PIN_4
568 * @arg @ref LL_GPIO_PIN_5
569 * @arg @ref LL_GPIO_PIN_6
570 * @arg @ref LL_GPIO_PIN_7
571 * @arg @ref LL_GPIO_PIN_8
572 * @arg @ref LL_GPIO_PIN_9
573 * @arg @ref LL_GPIO_PIN_10
574 * @arg @ref LL_GPIO_PIN_11
575 * @arg @ref LL_GPIO_PIN_12
576 * @arg @ref LL_GPIO_PIN_13
577 * @arg @ref LL_GPIO_PIN_14
578 * @arg @ref LL_GPIO_PIN_15
579 * @param Pull This parameter can be one of the following values:
580 * @arg @ref LL_GPIO_PULL_DOWN
581 * @arg @ref LL_GPIO_PULL_UP
582 * @retval None
583 */
584 __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
585 {
586 MODIFY_REG(GPIOx->ODR, (Pin>>8) , Pull << (POSITION_VAL(Pin>>8)));
587 }
588
589 /**
590 * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
591 * @note Warning: only one pin can be passed as parameter.
592 * @rmtoll ODR ODR LL_GPIO_GetPinPull
593 * @param GPIOx GPIO Port
594 * @param Pin This parameter can be one of the following values:
595 * @arg @ref LL_GPIO_PIN_0
596 * @arg @ref LL_GPIO_PIN_1
597 * @arg @ref LL_GPIO_PIN_2
598 * @arg @ref LL_GPIO_PIN_3
599 * @arg @ref LL_GPIO_PIN_4
600 * @arg @ref LL_GPIO_PIN_5
601 * @arg @ref LL_GPIO_PIN_6
602 * @arg @ref LL_GPIO_PIN_7
603 * @arg @ref LL_GPIO_PIN_8
604 * @arg @ref LL_GPIO_PIN_9
605 * @arg @ref LL_GPIO_PIN_10
606 * @arg @ref LL_GPIO_PIN_11
607 * @arg @ref LL_GPIO_PIN_12
608 * @arg @ref LL_GPIO_PIN_13
609 * @arg @ref LL_GPIO_PIN_14
610 * @arg @ref LL_GPIO_PIN_15
611 * @retval Returned value can be one of the following values:
612 * @arg @ref LL_GPIO_PULL_DOWN
613 * @arg @ref LL_GPIO_PULL_UP
614 */
615 __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
616 {
617 return (uint32_t)(READ_BIT(GPIOx->ODR,
618 (GPIO_ODR_ODR0 << (POSITION_VAL(Pin>>8)))) >> (POSITION_VAL(Pin>>8)));
619 }
620
621 /**
622 * @brief Lock configuration of several pins for a dedicated port.
623 * @note When the lock sequence has been applied on a port bit, the
624 * value of this port bit can no longer be modified until the
625 * next reset.
626 * @note Each lock bit freezes a specific configuration register
627 * (control and alternate function registers).
628 * @rmtoll LCKR LCKK LL_GPIO_LockPin
629 * @param GPIOx GPIO Port
630 * @param PinMask This parameter can be a combination of the following values:
631 * @arg @ref LL_GPIO_PIN_0
632 * @arg @ref LL_GPIO_PIN_1
633 * @arg @ref LL_GPIO_PIN_2
634 * @arg @ref LL_GPIO_PIN_3
635 * @arg @ref LL_GPIO_PIN_4
636 * @arg @ref LL_GPIO_PIN_5
637 * @arg @ref LL_GPIO_PIN_6
638 * @arg @ref LL_GPIO_PIN_7
639 * @arg @ref LL_GPIO_PIN_8
640 * @arg @ref LL_GPIO_PIN_9
641 * @arg @ref LL_GPIO_PIN_10
642 * @arg @ref LL_GPIO_PIN_11
643 * @arg @ref LL_GPIO_PIN_12
644 * @arg @ref LL_GPIO_PIN_13
645 * @arg @ref LL_GPIO_PIN_14
646 * @arg @ref LL_GPIO_PIN_15
647 * @arg @ref LL_GPIO_PIN_ALL
648 * @retval None
649 */
650 __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
651 {
652 __IO uint32_t temp;
653 WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> 8) & 0x0000FFFFU));
654 WRITE_REG(GPIOx->LCKR, ((PinMask >>8 ) & 0x0000FFFFU));
655 WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask>>8) & 0x0000FFFFU));
656 temp = READ_REG(GPIOx->LCKR);
657 (void) temp;
658 }
659
660 /**
661 * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
662 * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
663 * @param GPIOx GPIO Port
664 * @param PinMask This parameter can be a combination of the following values:
665 * @arg @ref LL_GPIO_PIN_0
666 * @arg @ref LL_GPIO_PIN_1
667 * @arg @ref LL_GPIO_PIN_2
668 * @arg @ref LL_GPIO_PIN_3
669 * @arg @ref LL_GPIO_PIN_4
670 * @arg @ref LL_GPIO_PIN_5
671 * @arg @ref LL_GPIO_PIN_6
672 * @arg @ref LL_GPIO_PIN_7
673 * @arg @ref LL_GPIO_PIN_8
674 * @arg @ref LL_GPIO_PIN_9
675 * @arg @ref LL_GPIO_PIN_10
676 * @arg @ref LL_GPIO_PIN_11
677 * @arg @ref LL_GPIO_PIN_12
678 * @arg @ref LL_GPIO_PIN_13
679 * @arg @ref LL_GPIO_PIN_14
680 * @arg @ref LL_GPIO_PIN_15
681 * @arg @ref LL_GPIO_PIN_ALL
682 * @retval State of bit (1 or 0).
683 */
684 __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
685 {
686 return (READ_BIT(GPIOx->LCKR, ((PinMask >> 8 ) & 0x0000FFFFU)) == ((PinMask >>8 ) & 0x0000FFFFU));
687 }
688
689 /**
690 * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
691 * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
692 * @param GPIOx GPIO Port
693 * @retval State of bit (1 or 0).
694 */
695 __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
696 {
697 return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
698 }
699
700 /**
701 * @}
702 */
703
704 /** @defgroup GPIO_LL_EF_Data_Access Data Access
705 * @{
706 */
707
708 /**
709 * @brief Return full input data register value for a dedicated port.
710 * @rmtoll IDR IDy LL_GPIO_ReadInputPort
711 * @param GPIOx GPIO Port
712 * @retval Input data register value of port
713 */
714 __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
715 {
716 return (uint32_t)(READ_REG(GPIOx->IDR));
717 }
718
719 /**
720 * @brief Return if input data level for several pins of dedicated port is high or low.
721 * @rmtoll IDR IDy LL_GPIO_IsInputPinSet
722 * @param GPIOx GPIO Port
723 * @param PinMask This parameter can be a combination of the following values:
724 * @arg @ref LL_GPIO_PIN_0
725 * @arg @ref LL_GPIO_PIN_1
726 * @arg @ref LL_GPIO_PIN_2
727 * @arg @ref LL_GPIO_PIN_3
728 * @arg @ref LL_GPIO_PIN_4
729 * @arg @ref LL_GPIO_PIN_5
730 * @arg @ref LL_GPIO_PIN_6
731 * @arg @ref LL_GPIO_PIN_7
732 * @arg @ref LL_GPIO_PIN_8
733 * @arg @ref LL_GPIO_PIN_9
734 * @arg @ref LL_GPIO_PIN_10
735 * @arg @ref LL_GPIO_PIN_11
736 * @arg @ref LL_GPIO_PIN_12
737 * @arg @ref LL_GPIO_PIN_13
738 * @arg @ref LL_GPIO_PIN_14
739 * @arg @ref LL_GPIO_PIN_15
740 * @arg @ref LL_GPIO_PIN_ALL
741 * @retval State of bit (1 or 0).
742 */
743 __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
744 {
745 return (READ_BIT(GPIOx->IDR, (PinMask >> 8 ) & 0x0000FFFFU) == ((PinMask >> 8 ) & 0x0000FFFFU));
746 }
747
748 /**
749 * @brief Write output data register for the port.
750 * @rmtoll ODR ODy LL_GPIO_WriteOutputPort
751 * @param GPIOx GPIO Port
752 * @param PortValue Level value for each pin of the port
753 * @retval None
754 */
755 __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
756 {
757 WRITE_REG(GPIOx->ODR, PortValue);
758 }
759
760 /**
761 * @brief Return full output data register value for a dedicated port.
762 * @rmtoll ODR ODy LL_GPIO_ReadOutputPort
763 * @param GPIOx GPIO Port
764 * @retval Output data register value of port
765 */
766 __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
767 {
768 return (uint32_t)(READ_REG(GPIOx->ODR));
769 }
770
771 /**
772 * @brief Return if input data level for several pins of dedicated port is high or low.
773 * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
774 * @param GPIOx GPIO Port
775 * @param PinMask This parameter can be a combination of the following values:
776 * @arg @ref LL_GPIO_PIN_0
777 * @arg @ref LL_GPIO_PIN_1
778 * @arg @ref LL_GPIO_PIN_2
779 * @arg @ref LL_GPIO_PIN_3
780 * @arg @ref LL_GPIO_PIN_4
781 * @arg @ref LL_GPIO_PIN_5
782 * @arg @ref LL_GPIO_PIN_6
783 * @arg @ref LL_GPIO_PIN_7
784 * @arg @ref LL_GPIO_PIN_8
785 * @arg @ref LL_GPIO_PIN_9
786 * @arg @ref LL_GPIO_PIN_10
787 * @arg @ref LL_GPIO_PIN_11
788 * @arg @ref LL_GPIO_PIN_12
789 * @arg @ref LL_GPIO_PIN_13
790 * @arg @ref LL_GPIO_PIN_14
791 * @arg @ref LL_GPIO_PIN_15
792 * @arg @ref LL_GPIO_PIN_ALL
793 * @retval State of bit (1 or 0).
794 */
795 __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
796 {
797 return (READ_BIT(GPIOx->ODR, (PinMask >> 8 ) & 0x0000FFFFU) == ((PinMask >> 8 ) & 0x0000FFFFU));
798 }
799
800 /**
801 * @brief Set several pins to high level on dedicated gpio port.
802 * @rmtoll BSRR BSy LL_GPIO_SetOutputPin
803 * @param GPIOx GPIO Port
804 * @param PinMask This parameter can be a combination of the following values:
805 * @arg @ref LL_GPIO_PIN_0
806 * @arg @ref LL_GPIO_PIN_1
807 * @arg @ref LL_GPIO_PIN_2
808 * @arg @ref LL_GPIO_PIN_3
809 * @arg @ref LL_GPIO_PIN_4
810 * @arg @ref LL_GPIO_PIN_5
811 * @arg @ref LL_GPIO_PIN_6
812 * @arg @ref LL_GPIO_PIN_7
813 * @arg @ref LL_GPIO_PIN_8
814 * @arg @ref LL_GPIO_PIN_9
815 * @arg @ref LL_GPIO_PIN_10
816 * @arg @ref LL_GPIO_PIN_11
817 * @arg @ref LL_GPIO_PIN_12
818 * @arg @ref LL_GPIO_PIN_13
819 * @arg @ref LL_GPIO_PIN_14
820 * @arg @ref LL_GPIO_PIN_15
821 * @arg @ref LL_GPIO_PIN_ALL
822 * @retval None
823 */
824 __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
825 {
826 WRITE_REG(GPIOx->BSRR, (PinMask >> 8) & 0x0000FFFFU);
827 }
828
829 /**
830 * @brief Set several pins to low level on dedicated gpio port.
831 * @rmtoll BRR BRy LL_GPIO_ResetOutputPin
832 * @param GPIOx GPIO Port
833 * @param PinMask This parameter can be a combination of the following values:
834 * @arg @ref LL_GPIO_PIN_0
835 * @arg @ref LL_GPIO_PIN_1
836 * @arg @ref LL_GPIO_PIN_2
837 * @arg @ref LL_GPIO_PIN_3
838 * @arg @ref LL_GPIO_PIN_4
839 * @arg @ref LL_GPIO_PIN_5
840 * @arg @ref LL_GPIO_PIN_6
841 * @arg @ref LL_GPIO_PIN_7
842 * @arg @ref LL_GPIO_PIN_8
843 * @arg @ref LL_GPIO_PIN_9
844 * @arg @ref LL_GPIO_PIN_10
845 * @arg @ref LL_GPIO_PIN_11
846 * @arg @ref LL_GPIO_PIN_12
847 * @arg @ref LL_GPIO_PIN_13
848 * @arg @ref LL_GPIO_PIN_14
849 * @arg @ref LL_GPIO_PIN_15
850 * @arg @ref LL_GPIO_PIN_ALL
851 * @retval None
852 */
853 __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
854 {
855 WRITE_REG(GPIOx->BRR, (PinMask >> 8 ) & 0x0000FFFFU);
856 }
857
858 /**
859 * @brief Toggle data value for several pin of dedicated port.
860 * @rmtoll ODR ODy LL_GPIO_TogglePin
861 * @param GPIOx GPIO Port
862 * @param PinMask This parameter can be a combination of the following values:
863 * @arg @ref LL_GPIO_PIN_0
864 * @arg @ref LL_GPIO_PIN_1
865 * @arg @ref LL_GPIO_PIN_2
866 * @arg @ref LL_GPIO_PIN_3
867 * @arg @ref LL_GPIO_PIN_4
868 * @arg @ref LL_GPIO_PIN_5
869 * @arg @ref LL_GPIO_PIN_6
870 * @arg @ref LL_GPIO_PIN_7
871 * @arg @ref LL_GPIO_PIN_8
872 * @arg @ref LL_GPIO_PIN_9
873 * @arg @ref LL_GPIO_PIN_10
874 * @arg @ref LL_GPIO_PIN_11
875 * @arg @ref LL_GPIO_PIN_12
876 * @arg @ref LL_GPIO_PIN_13
877 * @arg @ref LL_GPIO_PIN_14
878 * @arg @ref LL_GPIO_PIN_15
879 * @arg @ref LL_GPIO_PIN_ALL
880 * @retval None
881 */
882 __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
883 {
884 WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ ((PinMask >> 8 ) & 0x0000FFFFU));
885 }
886
887 /**
888 * @}
889 */
890
891 /** @defgroup GPIO_AF_REMAPPING Alternate Function Remapping
892 * @brief This section propose definition to remap the alternate function to some other port/pins.
893 * @{
894 */
895
896 /**
897 * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
898 * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_EnableRemap_SPI1
899 * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
900 * @retval None
901 */
902 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void)
903 {
904 SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP);
905 }
906
907 /**
908 * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
909 * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_DisableRemap_SPI1
910 * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
911 * @retval None
912 */
913 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void)
914 {
915 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP);
916 }
917
918 /**
919 * @brief Check if SPI1 has been remaped or not
920 * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_IsEnabledRemap_SPI1
921 * @retval State of bit (1 or 0).
922 */
923 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI1(void)
924 {
925 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) == (AFIO_MAPR_SPI1_REMAP));
926 }
927
928 /**
929 * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
930 * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_EnableRemap_I2C1
931 * @note ENABLE: Remap (SCL/PB8, SDA/PB9)
932 * @retval None
933 */
934 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void)
935 {
936 SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP);
937 }
938
939 /**
940 * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
941 * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_DisableRemap_I2C1
942 * @note DISABLE: No remap (SCL/PB6, SDA/PB7)
943 * @retval None
944 */
945 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void)
946 {
947 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP);
948 }
949
950 /**
951 * @brief Check if I2C1 has been remaped or not
952 * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_IsEnabledRemap_I2C1
953 * @retval State of bit (1 or 0).
954 */
955 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_I2C1(void)
956 {
957 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) == (AFIO_MAPR_I2C1_REMAP));
958 }
959
960 /**
961 * @brief Enable the remapping of USART1 alternate function TX and RX.
962 * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_EnableRemap_USART1
963 * @note ENABLE: Remap (TX/PB6, RX/PB7)
964 * @retval None
965 */
966 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void)
967 {
968 SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP);
969 }
970
971 /**
972 * @brief Disable the remapping of USART1 alternate function TX and RX.
973 * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_DisableRemap_USART1
974 * @note DISABLE: No remap (TX/PA9, RX/PA10)
975 * @retval None
976 */
977 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void)
978 {
979 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP);
980 }
981
982 /**
983 * @brief Check if USART1 has been remaped or not
984 * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_IsEnabledRemap_USART1
985 * @retval State of bit (1 or 0).
986 */
987 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART1(void)
988 {
989 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) == (AFIO_MAPR_USART1_REMAP));
990 }
991
992 /**
993 * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
994 * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_EnableRemap_USART2
995 * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
996 * @retval None
997 */
998 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void)
999 {
1000 SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP);
1001 }
1002
1003 /**
1004 * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
1005 * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_DisableRemap_USART2
1006 * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
1007 * @retval None
1008 */
1009 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void)
1010 {
1011 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP);
1012 }
1013
1014 /**
1015 * @brief Check if USART2 has been remaped or not
1016 * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_IsEnabledRemap_USART2
1017 * @retval State of bit (1 or 0).
1018 */
1019 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART2(void)
1020 {
1021 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) == (AFIO_MAPR_USART2_REMAP));
1022 }
1023
1024 #if defined (AFIO_MAPR_USART3_REMAP)
1025 /**
1026 * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
1027 * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_EnableRemap_USART3
1028 * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
1029 * @retval None
1030 */
1031 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void)
1032 {
1033 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
1034 SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_FULLREMAP);
1035 }
1036
1037 /**
1038 * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
1039 * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_RemapPartial_USART3
1040 * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
1041 * @retval None
1042 */
1043 __STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void)
1044 {
1045 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
1046 SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_PARTIALREMAP);
1047 }
1048
1049 /**
1050 * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
1051 * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_DisableRemap_USART3
1052 * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
1053 * @retval None
1054 */
1055 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void)
1056 {
1057 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
1058 SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_NOREMAP);
1059 }
1060 #endif
1061
1062 /**
1063 * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
1064 * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_EnableRemap_TIM1
1065 * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
1066 * @retval None
1067 */
1068 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void)
1069 {
1070 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
1071 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_FULLREMAP);
1072 }
1073
1074 /**
1075 * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
1076 * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_RemapPartial_TIM1
1077 * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
1078 * @retval None
1079 */
1080 __STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void)
1081 {
1082 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
1083 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP);
1084 }
1085
1086 /**
1087 * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
1088 * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_DisableRemap_TIM1
1089 * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
1090 * @retval None
1091 */
1092 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void)
1093 {
1094 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
1095 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_NOREMAP);
1096 }
1097
1098 /**
1099 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
1100 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_EnableRemap_TIM2
1101 * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
1102 * @retval None
1103 */
1104 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void)
1105 {
1106 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
1107 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_FULLREMAP);
1108 }
1109
1110 /**
1111 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
1112 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial2_TIM2
1113 * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
1114 * @retval None
1115 */
1116 __STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void)
1117 {
1118 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
1119 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2);
1120 }
1121
1122 /**
1123 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
1124 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial1_TIM2
1125 * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
1126 * @retval None
1127 */
1128 __STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void)
1129 {
1130 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
1131 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1);
1132 }
1133
1134 /**
1135 * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
1136 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_DisableRemap_TIM2
1137 * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
1138 * @retval None
1139 */
1140 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void)
1141 {
1142 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
1143 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_NOREMAP);
1144 }
1145
1146 /**
1147 * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
1148 * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_EnableRemap_TIM3
1149 * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
1150 * @note TIM3_ETR on PE0 is not re-mapped.
1151 * @retval None
1152 */
1153 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void)
1154 {
1155 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
1156 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_FULLREMAP);
1157 }
1158
1159 /**
1160 * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
1161 * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_RemapPartial_TIM3
1162 * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
1163 * @note TIM3_ETR on PE0 is not re-mapped.
1164 * @retval None
1165 */
1166 __STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void)
1167 {
1168 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
1169 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP);
1170 }
1171
1172 /**
1173 * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
1174 * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_DisableRemap_TIM3
1175 * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
1176 * @note TIM3_ETR on PE0 is not re-mapped.
1177 * @retval None
1178 */
1179 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void)
1180 {
1181 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
1182 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_NOREMAP);
1183 }
1184
1185 #if defined(AFIO_MAPR_TIM4_REMAP)
1186 /**
1187 * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
1188 * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_EnableRemap_TIM4
1189 * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
1190 * @note TIM4_ETR on PE0 is not re-mapped.
1191 * @retval None
1192 */
1193 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void)
1194 {
1195 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP);
1196 }
1197 /**
1198 * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
1199 * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_DisableRemap_TIM4
1200 * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
1201 * @note TIM4_ETR on PE0 is not re-mapped.
1202 * @retval None
1203 */
1204 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void)
1205 {
1206 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP);
1207 }
1208
1209 /**
1210 * @brief Check if TIM4 has been remaped or not
1211 * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_IsEnabledRemap_TIM4
1212 * @retval State of bit (1 or 0).
1213 */
1214 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM4(void)
1215 {
1216 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) == (AFIO_MAPR_TIM4_REMAP));
1217 }
1218 #endif
1219
1220 #if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
1221
1222 /**
1223 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
1224 * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial1_CAN1
1225 * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
1226 * @retval None
1227 */
1228 __STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void)
1229 {
1230 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
1231 SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP1);
1232 }
1233
1234 /**
1235 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
1236 * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial2_CAN1
1237 * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
1238 * @retval None
1239 */
1240 __STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void)
1241 {
1242 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
1243 SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP2);
1244 }
1245
1246 /**
1247 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
1248 * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial3_CAN1
1249 * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
1250 * @retval None
1251 */
1252 __STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void)
1253 {
1254 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
1255 SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP3);
1256 }
1257 #endif
1258
1259 /**
1260 * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
1261 * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
1262 * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
1263 * on 100-pin and 144-pin packages, no need for remapping).
1264 * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_EnableRemap_PD01
1265 * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
1266 * @retval None
1267 */
1268 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void)
1269 {
1270 SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP);
1271 }
1272
1273 /**
1274 * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
1275 * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
1276 * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
1277 * on 100-pin and 144-pin packages, no need for remapping).
1278 * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_DisableRemap_PD01
1279 * @note DISABLE: No remapping of PD0 and PD1
1280 * @retval None
1281 */
1282 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void)
1283 {
1284 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP);
1285 }
1286
1287 /**
1288 * @brief Check if PD01 has been remaped or not
1289 * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_IsEnabledRemap_PD01
1290 * @retval State of bit (1 or 0).
1291 */
1292 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_PD01(void)
1293 {
1294 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) == (AFIO_MAPR_PD01_REMAP));
1295 }
1296
1297 #if defined(AFIO_MAPR_TIM5CH4_IREMAP)
1298 /**
1299 * @brief Enable the remapping of TIM5CH4.
1300 * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_EnableRemap_TIM5CH4
1301 * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
1302 * @note This function is available only in high density value line devices.
1303 * @retval None
1304 */
1305 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void)
1306 {
1307 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP);
1308 }
1309
1310 /**
1311 * @brief Disable the remapping of TIM5CH4.
1312 * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_DisableRemap_TIM5CH4
1313 * @note DISABLE: TIM5_CH4 is connected to PA3
1314 * @note This function is available only in high density value line devices.
1315 * @retval None
1316 */
1317 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void)
1318 {
1319 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP);
1320 }
1321
1322 /**
1323 * @brief Check if TIM5CH4 has been remaped or not
1324 * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_IsEnabledRemap_TIM5CH4
1325 * @retval State of bit (1 or 0).
1326 */
1327 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void)
1328 {
1329 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) == (AFIO_MAPR_TIM5CH4_IREMAP));
1330 }
1331 #endif
1332
1333 #if defined(AFIO_MAPR_ETH_REMAP)
1334 /**
1335 * @brief Enable the remapping of Ethernet MAC connections with the PHY.
1336 * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_EnableRemap_ETH
1337 * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
1338 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1339 * @retval None
1340 */
1341 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void)
1342 {
1343 SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP);
1344 }
1345
1346 /**
1347 * @brief Disable the remapping of Ethernet MAC connections with the PHY.
1348 * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_DisableRemap_ETH
1349 * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
1350 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1351 * @retval None
1352 */
1353 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void)
1354 {
1355 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP);
1356 }
1357
1358 /**
1359 * @brief Check if ETH has been remaped or not
1360 * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_IsEnabledRemap_ETH
1361 * @retval State of bit (1 or 0).
1362 */
1363 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ETH(void)
1364 {
1365 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) == (AFIO_MAPR_ETH_REMAP));
1366 }
1367 #endif
1368
1369 #if defined(AFIO_MAPR_CAN2_REMAP)
1370
1371 /**
1372 * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
1373 * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_EnableRemap_CAN2
1374 * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
1375 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1376 * @retval None
1377 */
1378 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void)
1379 {
1380 SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP);
1381 }
1382 /**
1383 * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
1384 * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_DisableRemap_CAN2
1385 * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
1386 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1387 * @retval None
1388 */
1389 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void)
1390 {
1391 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP);
1392 }
1393
1394 /**
1395 * @brief Check if CAN2 has been remaped or not
1396 * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_IsEnabledRemap_CAN2
1397 * @retval State of bit (1 or 0).
1398 */
1399 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CAN2(void)
1400 {
1401 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) == (AFIO_MAPR_CAN2_REMAP));
1402 }
1403 #endif
1404
1405 #if defined(AFIO_MAPR_MII_RMII_SEL)
1406 /**
1407 * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
1408 * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_RMII
1409 * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
1410 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1411 * @retval None
1412 */
1413 __STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void)
1414 {
1415 SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL);
1416 }
1417
1418 /**
1419 * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
1420 * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_MII
1421 * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY
1422 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1423 * @retval None
1424 */
1425 __STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void)
1426 {
1427 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL);
1428 }
1429 #endif
1430
1431 #if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
1432 /**
1433 * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
1434 * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ
1435 * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
1436 * @retval None
1437 */
1438 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void)
1439 {
1440 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP);
1441 }
1442
1443 /**
1444 * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
1445 * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ
1446 * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
1447 * @retval None
1448 */
1449 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void)
1450 {
1451 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP);
1452 }
1453
1454 /**
1455 * @brief Check if ADC1_ETRGINJ has been remaped or not
1456 * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ
1457 * @retval State of bit (1 or 0).
1458 */
1459 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void)
1460 {
1461 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) == (AFIO_MAPR_ADC1_ETRGINJ_REMAP));
1462 }
1463 #endif
1464
1465 #if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP)
1466 /**
1467 * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
1468 * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGREG
1469 * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
1470 * @retval None
1471 */
1472 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void)
1473 {
1474 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP);
1475 }
1476
1477 /**
1478 * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
1479 * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGREG
1480 * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
1481 * @retval None
1482 */
1483 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void)
1484 {
1485 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP);
1486 }
1487
1488 /**
1489 * @brief Check if ADC1_ETRGREG has been remaped or not
1490 * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG
1491 * @retval State of bit (1 or 0).
1492 */
1493 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void)
1494 {
1495 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) == (AFIO_MAPR_ADC1_ETRGREG_REMAP));
1496 }
1497 #endif
1498
1499 #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
1500
1501 /**
1502 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
1503 * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ
1504 * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
1505 * @retval None
1506 */
1507 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void)
1508 {
1509 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP);
1510 }
1511
1512 /**
1513 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
1514 * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ
1515 * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
1516 * @retval None
1517 */
1518 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void)
1519 {
1520 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP);
1521 }
1522
1523 /**
1524 * @brief Check if ADC2_ETRGINJ has been remaped or not
1525 * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ
1526 * @retval State of bit (1 or 0).
1527 */
1528 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void)
1529 {
1530 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) == (AFIO_MAPR_ADC2_ETRGINJ_REMAP));
1531 }
1532 #endif
1533
1534 #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
1535
1536 /**
1537 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
1538 * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGREG
1539 * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
1540 * @retval None
1541 */
1542 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void)
1543 {
1544 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP);
1545 }
1546
1547 /**
1548 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
1549 * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGREG
1550 * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
1551 * @retval None
1552 */
1553 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void)
1554 {
1555 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP);
1556 }
1557
1558 /**
1559 * @brief Check if ADC2_ETRGREG has been remaped or not
1560 * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG
1561 * @retval State of bit (1 or 0).
1562 */
1563 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void)
1564 {
1565 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) == (AFIO_MAPR_ADC2_ETRGREG_REMAP));
1566 }
1567 #endif
1568
1569 /**
1570 * @brief Enable the Serial wire JTAG configuration
1571 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_EnableRemap_SWJ
1572 * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
1573 * @retval None
1574 */
1575 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void)
1576 {
1577 CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
1578 SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET);
1579 }
1580
1581 /**
1582 * @brief Enable the Serial wire JTAG configuration
1583 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NONJTRST
1584 * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
1585 * @retval None
1586 */
1587 __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void)
1588 {
1589 CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
1590 SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST);
1591 }
1592
1593 /**
1594 * @brief Enable the Serial wire JTAG configuration
1595 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NOJTAG
1596 * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
1597 * @retval None
1598 */
1599 __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void)
1600 {
1601 CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
1602 SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE);
1603 }
1604
1605 /**
1606 * @brief Disable the Serial wire JTAG configuration
1607 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_DisableRemap_SWJ
1608 * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
1609 * @retval None
1610 */
1611 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ(void)
1612 {
1613 CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
1614 SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE);
1615 }
1616
1617 #if defined(AFIO_MAPR_SPI3_REMAP)
1618
1619 /**
1620 * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
1621 * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_EnableRemap_SPI3
1622 * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
1623 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1624 * @retval None
1625 */
1626 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void)
1627 {
1628 SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP);
1629 }
1630
1631 /**
1632 * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
1633 * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_DisableRemap_SPI3
1634 * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5).
1635 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1636 * @retval None
1637 */
1638 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void)
1639 {
1640 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP);
1641 }
1642
1643 /**
1644 * @brief Check if SPI3 has been remaped or not
1645 * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP
1646 * @retval State of bit (1 or 0).
1647 */
1648 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI3(void)
1649 {
1650 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) == (AFIO_MAPR_SPI3_REMAP));
1651 }
1652 #endif
1653
1654 #if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
1655
1656 /**
1657 * @brief Control of TIM2_ITR1 internal mapping.
1658 * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_USB
1659 * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
1660 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1661 * @retval None
1662 */
1663 __STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void)
1664 {
1665 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP);
1666 }
1667
1668 /**
1669 * @brief Control of TIM2_ITR1 internal mapping.
1670 * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH
1671 * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
1672 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1673 * @retval None
1674 */
1675 __STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void)
1676 {
1677 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP);
1678 }
1679 #endif
1680
1681 #if defined(AFIO_MAPR_PTP_PPS_REMAP)
1682
1683 /**
1684 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
1685 * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_EnableRemap_ETH_PTP_PPS
1686 * @note ENABLE: PTP_PPS is output on PB5 pin.
1687 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1688 * @retval None
1689 */
1690 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void)
1691 {
1692 SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP);
1693 }
1694
1695 /**
1696 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
1697 * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_DisableRemap_ETH_PTP_PPS
1698 * @note DISABLE: PTP_PPS not output on PB5 pin.
1699 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1700 * @retval None
1701 */
1702 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void)
1703 {
1704 CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP);
1705 }
1706 #endif
1707
1708 #if defined(AFIO_MAPR2_TIM9_REMAP)
1709
1710 /**
1711 * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
1712 * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_EnableRemap_TIM9
1713 * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
1714 * @retval None
1715 */
1716 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM9(void)
1717 {
1718 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
1719 }
1720
1721 /**
1722 * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
1723 * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_DisableRemap_TIM9
1724 * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
1725 * @retval None
1726 */
1727 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM9(void)
1728 {
1729 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
1730 }
1731
1732 /**
1733 * @brief Check if TIM9_CH1 and TIM9_CH2 have been remaped or not
1734 * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_IsEnabledRemap_TIM9
1735 * @retval State of bit (1 or 0).
1736 */
1737 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM9(void)
1738 {
1739 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) == (AFIO_MAPR2_TIM9_REMAP));
1740 }
1741 #endif
1742
1743 #if defined(AFIO_MAPR2_TIM10_REMAP)
1744
1745 /**
1746 * @brief Enable the remapping of TIM10_CH1.
1747 * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_EnableRemap_TIM10
1748 * @note ENABLE: Remap (TIM10_CH1 on PF6).
1749 * @retval None
1750 */
1751 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM10(void)
1752 {
1753 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
1754 }
1755
1756 /**
1757 * @brief Disable the remapping of TIM10_CH1.
1758 * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_DisableRemap_TIM10
1759 * @note DISABLE: No remap (TIM10_CH1 on PB8).
1760 * @retval None
1761 */
1762 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM10(void)
1763 {
1764 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
1765 }
1766
1767 /**
1768 * @brief Check if TIM10_CH1 has been remaped or not
1769 * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_IsEnabledRemap_TIM10
1770 * @retval State of bit (1 or 0).
1771 */
1772 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM10(void)
1773 {
1774 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) == (AFIO_MAPR2_TIM10_REMAP));
1775 }
1776 #endif
1777
1778 #if defined(AFIO_MAPR2_TIM11_REMAP)
1779 /**
1780 * @brief Enable the remapping of TIM11_CH1.
1781 * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_EnableRemap_TIM11
1782 * @note ENABLE: Remap (TIM11_CH1 on PF7).
1783 * @retval None
1784 */
1785 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM11(void)
1786 {
1787 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
1788 }
1789
1790 /**
1791 * @brief Disable the remapping of TIM11_CH1.
1792 * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_DisableRemap_TIM11
1793 * @note DISABLE: No remap (TIM11_CH1 on PB9).
1794 * @retval None
1795 */
1796 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM11(void)
1797 {
1798 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
1799 }
1800
1801 /**
1802 * @brief Check if TIM11_CH1 has been remaped or not
1803 * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_IsEnabledRemap_TIM11
1804 * @retval State of bit (1 or 0).
1805 */
1806 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM11(void)
1807 {
1808 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) == (AFIO_MAPR2_TIM11_REMAP));
1809 }
1810 #endif
1811
1812 #if defined(AFIO_MAPR2_TIM13_REMAP)
1813
1814 /**
1815 * @brief Enable the remapping of TIM13_CH1.
1816 * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_EnableRemap_TIM13
1817 * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
1818 * @retval None
1819 */
1820 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM13(void)
1821 {
1822 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
1823 }
1824
1825 /**
1826 * @brief Disable the remapping of TIM13_CH1.
1827 * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_DisableRemap_TIM13
1828 * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
1829 * @retval None
1830 */
1831 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM13(void)
1832 {
1833 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
1834 }
1835
1836 /**
1837 * @brief Check if TIM13_CH1 has been remaped or not
1838 * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_IsEnabledRemap_TIM13
1839 * @retval State of bit (1 or 0).
1840 */
1841 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM13(void)
1842 {
1843 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) == (AFIO_MAPR2_TIM13_REMAP));
1844 }
1845 #endif
1846
1847 #if defined(AFIO_MAPR2_TIM14_REMAP)
1848
1849 /**
1850 * @brief Enable the remapping of TIM14_CH1.
1851 * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_EnableRemap_TIM14
1852 * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
1853 * @retval None
1854 */
1855 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM14(void)
1856 {
1857 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
1858 }
1859
1860 /**
1861 * @brief Disable the remapping of TIM14_CH1.
1862 * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_DisableRemap_TIM14
1863 * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
1864 * @retval None
1865 */
1866 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM14(void)
1867 {
1868 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
1869 }
1870
1871 /**
1872 * @brief Check if TIM14_CH1 has been remaped or not
1873 * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_IsEnabledRemap_TIM14
1874 * @retval State of bit (1 or 0).
1875 */
1876 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM14(void)
1877 {
1878 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) == (AFIO_MAPR2_TIM14_REMAP));
1879 }
1880 #endif
1881
1882 #if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
1883
1884 /**
1885 * @brief Controls the use of the optional FSMC_NADV signal.
1886 * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Disconnect_FSMCNADV
1887 * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
1888 * @retval None
1889 */
1890 __STATIC_INLINE void LL_GPIO_AF_Disconnect_FSMCNADV(void)
1891 {
1892 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
1893 }
1894
1895 /**
1896 * @brief Controls the use of the optional FSMC_NADV signal.
1897 * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Connect_FSMCNADV
1898 * @note CONNECTED: The NADV signal is connected to the output (default).
1899 * @retval None
1900 */
1901 __STATIC_INLINE void LL_GPIO_AF_Connect_FSMCNADV(void)
1902 {
1903 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
1904 }
1905 #endif
1906
1907 #if defined(AFIO_MAPR2_TIM15_REMAP)
1908
1909 /**
1910 * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
1911 * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_EnableRemap_TIM15
1912 * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
1913 * @retval None
1914 */
1915 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM15(void)
1916 {
1917 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
1918 }
1919 /**
1920 * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
1921 * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_DisableRemap_TIM15
1922 * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3).
1923 * @retval None
1924 */
1925 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM15(void)
1926 {
1927 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
1928 }
1929
1930 /**
1931 * @brief Check if TIM15_CH1 has been remaped or not
1932 * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_IsEnabledRemap_TIM15
1933 * @retval State of bit (1 or 0).
1934 */
1935 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM15(void)
1936 {
1937 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) == (AFIO_MAPR2_TIM15_REMAP));
1938 }
1939 #endif
1940
1941 #if defined(AFIO_MAPR2_TIM16_REMAP)
1942
1943 /**
1944 * @brief Enable the remapping of TIM16_CH1.
1945 * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_EnableRemap_TIM16
1946 * @note ENABLE: Remap (TIM16_CH1 on PA6).
1947 * @retval None
1948 */
1949 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM16(void)
1950 {
1951 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
1952 }
1953
1954 /**
1955 * @brief Disable the remapping of TIM16_CH1.
1956 * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_DisableRemap_TIM16
1957 * @note DISABLE: No remap (TIM16_CH1 on PB8).
1958 * @retval None
1959 */
1960 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM16(void)
1961 {
1962 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
1963 }
1964
1965 /**
1966 * @brief Check if TIM16_CH1 has been remaped or not
1967 * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_IsEnabledRemap_TIM16
1968 * @retval State of bit (1 or 0).
1969 */
1970 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM16(void)
1971 {
1972 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) == (AFIO_MAPR2_TIM16_REMAP));
1973 }
1974 #endif
1975
1976 #if defined(AFIO_MAPR2_TIM17_REMAP)
1977
1978 /**
1979 * @brief Enable the remapping of TIM17_CH1.
1980 * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_EnableRemap_TIM17
1981 * @note ENABLE: Remap (TIM17_CH1 on PA7).
1982 * @retval None
1983 */
1984 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM17(void)
1985 {
1986 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
1987 }
1988
1989 /**
1990 * @brief Disable the remapping of TIM17_CH1.
1991 * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_DisableRemap_TIM17
1992 * @note DISABLE: No remap (TIM17_CH1 on PB9).
1993 * @retval None
1994 */
1995 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM17(void)
1996 {
1997 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
1998 }
1999
2000 /**
2001 * @brief Check if TIM17_CH1 has been remaped or not
2002 * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_IsEnabledRemap_TIM17
2003 * @retval State of bit (1 or 0).
2004 */
2005 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM17(void)
2006 {
2007 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) == (AFIO_MAPR2_TIM17_REMAP));
2008 }
2009 #endif
2010
2011 #if defined(AFIO_MAPR2_CEC_REMAP)
2012
2013 /**
2014 * @brief Enable the remapping of CEC.
2015 * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_EnableRemap_CEC
2016 * @note ENABLE: Remap (CEC on PB10).
2017 * @retval None
2018 */
2019 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_CEC(void)
2020 {
2021 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
2022 }
2023
2024 /**
2025 * @brief Disable the remapping of CEC.
2026 * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_DisableRemap_CEC
2027 * @note DISABLE: No remap (CEC on PB8).
2028 * @retval None
2029 */
2030 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CEC(void)
2031 {
2032 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
2033 }
2034
2035 /**
2036 * @brief Check if CEC has been remaped or not
2037 * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_IsEnabledRemap_CEC
2038 * @retval State of bit (1 or 0).
2039 */
2040 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CEC(void)
2041 {
2042 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) == (AFIO_MAPR2_CEC_REMAP));
2043 }
2044 #endif
2045
2046 #if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
2047
2048 /**
2049 * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
2050 * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM1DMA
2051 * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
2052 * @retval None
2053 */
2054 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1DMA(void)
2055 {
2056 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
2057 }
2058
2059 /**
2060 * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
2061 * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM1DMA
2062 * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
2063 * @retval None
2064 */
2065 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1DMA(void)
2066 {
2067 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
2068 }
2069
2070 /**
2071 * @brief Check if TIM1DMA has been remaped or not
2072 * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM1DMA
2073 * @retval State of bit (1 or 0).
2074 */
2075 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void)
2076 {
2077 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) == (AFIO_MAPR2_TIM1_DMA_REMAP));
2078 }
2079 #endif
2080
2081 #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
2082
2083 /**
2084 * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
2085 * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM67DACDMA
2086 * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
2087 * @retval None
2088 */
2089 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM67DACDMA(void)
2090 {
2091 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
2092 }
2093
2094 /**
2095 * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
2096 * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM67DACDMA
2097 * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
2098 * @retval None
2099 */
2100 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM67DACDMA(void)
2101 {
2102 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
2103 }
2104
2105 /**
2106 * @brief Check if TIM67DACDMA has been remaped or not
2107 * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA
2108 * @retval State of bit (1 or 0).
2109 */
2110 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void)
2111 {
2112 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) == (AFIO_MAPR2_TIM67_DAC_DMA_REMAP));
2113 }
2114 #endif
2115
2116 #if defined(AFIO_MAPR2_TIM12_REMAP)
2117
2118 /**
2119 * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
2120 * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_EnableRemap_TIM12
2121 * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
2122 * @note This bit is available only in high density value line devices.
2123 * @retval None
2124 */
2125 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM12(void)
2126 {
2127 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
2128 }
2129
2130 /**
2131 * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
2132 * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_DisableRemap_TIM12
2133 * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5).
2134 * @note This bit is available only in high density value line devices.
2135 * @retval None
2136 */
2137 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM12(void)
2138 {
2139 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
2140 }
2141
2142 /**
2143 * @brief Check if TIM12_CH1 has been remaped or not
2144 * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_IsEnabledRemap_TIM12
2145 * @retval State of bit (1 or 0).
2146 */
2147 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM12(void)
2148 {
2149 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) == (AFIO_MAPR2_TIM12_REMAP));
2150 }
2151 #endif
2152
2153 #if defined(AFIO_MAPR2_MISC_REMAP)
2154
2155 /**
2156 * @brief Miscellaneous features remapping.
2157 * This bit is set and cleared by software. It controls miscellaneous features.
2158 * The DMA2 channel 5 interrupt position in the vector table.
2159 * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
2160 * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_EnableRemap_MISC
2161 * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
2162 * selected as DAC Trigger 3, TIM15 triggers TIM1/3.
2163 * @note This bit is available only in high density value line devices.
2164 * @retval None
2165 */
2166 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_MISC(void)
2167 {
2168 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
2169 }
2170
2171 /**
2172 * @brief Miscellaneous features remapping.
2173 * This bit is set and cleared by software. It controls miscellaneous features.
2174 * The DMA2 channel 5 interrupt position in the vector table.
2175 * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
2176 * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_DisableRemap_MISC
2177 * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
2178 * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
2179 * @note This bit is available only in high density value line devices.
2180 * @retval None
2181 */
2182 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_MISC(void)
2183 {
2184 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
2185 }
2186
2187 /**
2188 * @brief Check if MISC has been remaped or not
2189 * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_IsEnabledRemap_MISC
2190 * @retval State of bit (1 or 0).
2191 */
2192 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_MISC(void)
2193 {
2194 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) == (AFIO_MAPR2_MISC_REMAP));
2195 }
2196 #endif
2197
2198 /**
2199 * @}
2200 */
2201
2202 /** @defgroup GPIO_AF_LL_EVENTOUT Output Event configuration
2203 * @brief This section propose definition to Configure EVENTOUT Cortex feature .
2204 * @{
2205 */
2206
2207 /**
2208 * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
2209 * @rmtoll EVCR PORT LL_GPIO_AF_ConfigEventout\n
2210 * EVCR PIN LL_GPIO_AF_ConfigEventout
2211 * @param LL_GPIO_PortSource This parameter can be one of the following values:
2212 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_A
2213 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_B
2214 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_C
2215 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_D
2216 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_E
2217 * @param LL_GPIO_PinSource This parameter can be one of the following values:
2218 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_0
2219 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_1
2220 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_2
2221 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_3
2222 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_4
2223 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_5
2224 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_6
2225 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_7
2226 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_8
2227 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_9
2228 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_10
2229 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_11
2230 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_12
2231 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_13
2232 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_14
2233 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_15
2234 * @retval None
2235 */
2236 __STATIC_INLINE void LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource)
2237 {
2238 MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (LL_GPIO_PortSource) | (LL_GPIO_PinSource));
2239 }
2240
2241 /**
2242 * @brief Enables the Event Output.
2243 * @rmtoll EVCR EVOE LL_GPIO_AF_EnableEventout
2244 * @retval None
2245 */
2246 __STATIC_INLINE void LL_GPIO_AF_EnableEventout(void)
2247 {
2248 SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
2249 }
2250
2251 /**
2252 * @brief Disables the Event Output.
2253 * @rmtoll EVCR EVOE LL_GPIO_AF_DisableEventout
2254 * @retval None
2255 */
2256 __STATIC_INLINE void LL_GPIO_AF_DisableEventout(void)
2257 {
2258 CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
2259 }
2260
2261 /**
2262 * @}
2263 */
2264 /** @defgroup GPIO_AF_LL_EXTI EXTI external interrupt
2265 * @brief This section Configure source input for the EXTI external interrupt .
2266 * @{
2267 */
2268
2269 /**
2270 * @brief Configure source input for the EXTI external interrupt.
2271 * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_SetEXTISource\n
2272 * AFIO_EXTICR2 EXTIx LL_GPIO_AF_SetEXTISource\n
2273 * AFIO_EXTICR3 EXTIx LL_GPIO_AF_SetEXTISource\n
2274 * AFIO_EXTICR4 EXTIx LL_GPIO_AF_SetEXTISource
2275 * @param Port This parameter can be one of the following values:
2276 * @arg @ref LL_GPIO_AF_EXTI_PORTA
2277 * @arg @ref LL_GPIO_AF_EXTI_PORTB
2278 * @arg @ref LL_GPIO_AF_EXTI_PORTC
2279 * @arg @ref LL_GPIO_AF_EXTI_PORTD
2280 * @arg @ref LL_GPIO_AF_EXTI_PORTE
2281 * @arg @ref LL_GPIO_AF_EXTI_PORTF
2282 * @arg @ref LL_GPIO_AF_EXTI_PORTG
2283 * @param Line This parameter can be one of the following values:
2284 * @arg @ref LL_GPIO_AF_EXTI_LINE0
2285 * @arg @ref LL_GPIO_AF_EXTI_LINE1
2286 * @arg @ref LL_GPIO_AF_EXTI_LINE2
2287 * @arg @ref LL_GPIO_AF_EXTI_LINE3
2288 * @arg @ref LL_GPIO_AF_EXTI_LINE4
2289 * @arg @ref LL_GPIO_AF_EXTI_LINE5
2290 * @arg @ref LL_GPIO_AF_EXTI_LINE6
2291 * @arg @ref LL_GPIO_AF_EXTI_LINE7
2292 * @arg @ref LL_GPIO_AF_EXTI_LINE8
2293 * @arg @ref LL_GPIO_AF_EXTI_LINE9
2294 * @arg @ref LL_GPIO_AF_EXTI_LINE10
2295 * @arg @ref LL_GPIO_AF_EXTI_LINE11
2296 * @arg @ref LL_GPIO_AF_EXTI_LINE12
2297 * @arg @ref LL_GPIO_AF_EXTI_LINE13
2298 * @arg @ref LL_GPIO_AF_EXTI_LINE14
2299 * @arg @ref LL_GPIO_AF_EXTI_LINE15
2300 * @retval None
2301 */
2302 __STATIC_INLINE void LL_GPIO_AF_SetEXTISource(uint32_t Port, uint32_t Line)
2303 {
2304 MODIFY_REG(AFIO->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
2305 }
2306
2307 /**
2308 * @brief Get the configured defined for specific EXTI Line
2309 * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_GetEXTISource\n
2310 * AFIO_EXTICR2 EXTIx LL_GPIO_AF_GetEXTISource\n
2311 * AFIO_EXTICR3 EXTIx LL_GPIO_AF_GetEXTISource\n
2312 * AFIO_EXTICR4 EXTIx LL_GPIO_AF_GetEXTISource
2313 * @param Line This parameter can be one of the following values:
2314 * @arg @ref LL_GPIO_AF_EXTI_LINE0
2315 * @arg @ref LL_GPIO_AF_EXTI_LINE1
2316 * @arg @ref LL_GPIO_AF_EXTI_LINE2
2317 * @arg @ref LL_GPIO_AF_EXTI_LINE3
2318 * @arg @ref LL_GPIO_AF_EXTI_LINE4
2319 * @arg @ref LL_GPIO_AF_EXTI_LINE5
2320 * @arg @ref LL_GPIO_AF_EXTI_LINE6
2321 * @arg @ref LL_GPIO_AF_EXTI_LINE7
2322 * @arg @ref LL_GPIO_AF_EXTI_LINE8
2323 * @arg @ref LL_GPIO_AF_EXTI_LINE9
2324 * @arg @ref LL_GPIO_AF_EXTI_LINE10
2325 * @arg @ref LL_GPIO_AF_EXTI_LINE11
2326 * @arg @ref LL_GPIO_AF_EXTI_LINE12
2327 * @arg @ref LL_GPIO_AF_EXTI_LINE13
2328 * @arg @ref LL_GPIO_AF_EXTI_LINE14
2329 * @arg @ref LL_GPIO_AF_EXTI_LINE15
2330 * @retval Returned value can be one of the following values:
2331 * @arg @ref LL_GPIO_AF_EXTI_PORTA
2332 * @arg @ref LL_GPIO_AF_EXTI_PORTB
2333 * @arg @ref LL_GPIO_AF_EXTI_PORTC
2334 * @arg @ref LL_GPIO_AF_EXTI_PORTD
2335 * @arg @ref LL_GPIO_AF_EXTI_PORTE
2336 * @arg @ref LL_GPIO_AF_EXTI_PORTF
2337 * @arg @ref LL_GPIO_AF_EXTI_PORTG
2338 */
2339 __STATIC_INLINE uint32_t LL_GPIO_AF_GetEXTISource(uint32_t Line)
2340 {
2341 return (uint32_t)(READ_BIT(AFIO->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
2342 }
2343
2344 /**
2345 * @}
2346 */
2347
2348 #if defined(USE_FULL_LL_DRIVER)
2349 /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
2350 * @{
2351 */
2352
2353 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
2354 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
2355 void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
2356
2357 /**
2358 * @}
2359 */
2360 #endif /* USE_FULL_LL_DRIVER */
2361
2362 /**
2363 * @}
2364 */
2365
2366 /**
2367 * @}
2368 */
2369
2370 #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
2371 /**
2372 * @}
2373 */
2374
2375 #ifdef __cplusplus
2376 }
2377 #endif
2378
2379 #endif /* __STM32F1xx_LL_GPIO_H */
2380
2381 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/