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Increment eeprom version
[betaflight.git] / lib / main / STM32F1 / Drivers / STM32F1xx_HAL_Driver / Inc / stm32f1xx_ll_rcc.h
blob37345eaeec06b25f0fe2da36f5bcc3cbda80c156
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_rcc.h
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 12-May-2017
7 * @brief Header file of RCC LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F1xx_LL_RCC_H
40 #define __STM32F1xx_LL_RCC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f1xx.h"
48
49 /** @addtogroup STM32F1xx_LL_Driver
50 * @{
51 */
52
53 #if defined(RCC)
54
55 /** @defgroup RCC_LL RCC
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /* Private constants ---------------------------------------------------------*/
62 /* Private macros ------------------------------------------------------------*/
63 #if defined(USE_FULL_LL_DRIVER)
64 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
65 * @{
66 */
67 /**
68 * @}
69 */
70 #endif /*USE_FULL_LL_DRIVER*/
71 /* Exported types ------------------------------------------------------------*/
72 #if defined(USE_FULL_LL_DRIVER)
73 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
74 * @{
75 */
76
77 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
78 * @{
79 */
80
81 /**
82 * @brief RCC Clocks Frequency Structure
83 */
84 typedef struct
85 {
86 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
87 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
88 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
89 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
90 } LL_RCC_ClocksTypeDef;
91
92 /**
93 * @}
94 */
95
96 /**
97 * @}
98 */
99 #endif /* USE_FULL_LL_DRIVER */
100
101 /* Exported constants --------------------------------------------------------*/
102 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
103 * @{
104 */
105
106 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
107 * @brief Defines used to adapt values of different oscillators
108 * @note These values could be modified in the user environment according to
109 * HW set-up.
110 * @{
111 */
112 #if !defined (HSE_VALUE)
113 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
114 #endif /* HSE_VALUE */
115
116 #if !defined (HSI_VALUE)
117 #define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */
118 #endif /* HSI_VALUE */
119
120 #if !defined (LSE_VALUE)
121 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
122 #endif /* LSE_VALUE */
123
124 #if !defined (LSI_VALUE)
125 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
126 #endif /* LSI_VALUE */
127 /**
128 * @}
129 */
130
131 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
132 * @brief Flags defines which can be used with LL_RCC_WriteReg function
133 * @{
134 */
135 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
136 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
137 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
138 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
139 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
140 #define LL_RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC /*!< PLL3(PLLI2S) Ready Interrupt Clear */
141 #define LL_RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC /*!< PLL2 Ready Interrupt Clear */
142 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
143 /**
144 * @}
145 */
146
147 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
148 * @brief Flags defines which can be used with LL_RCC_ReadReg function
149 * @{
150 */
151 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
152 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
153 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
154 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
155 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
156 #define LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF /*!< PLL3(PLLI2S) Ready Interrupt flag */
157 #define LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */
158 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
159 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
160 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
161 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
162 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
163 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
164 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
165 /**
166 * @}
167 */
168
169 /** @defgroup RCC_LL_EC_IT IT Defines
170 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
171 * @{
172 */
173 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
174 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
175 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
176 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
177 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
178 #define LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE /*!< PLL3(PLLI2S) Ready Interrupt Enable */
179 #define LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE /*!< PLL2 Ready Interrupt Enable */
180 /**
181 * @}
182 */
183
184 #if defined(RCC_CFGR2_PREDIV2)
185 /** @defgroup RCC_LL_EC_HSE_PREDIV2_DIV HSE PREDIV2 Division factor
186 * @{
187 */
188 #define LL_RCC_HSE_PREDIV2_DIV_1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */
189 #define LL_RCC_HSE_PREDIV2_DIV_2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */
190 #define LL_RCC_HSE_PREDIV2_DIV_3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */
191 #define LL_RCC_HSE_PREDIV2_DIV_4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */
192 #define LL_RCC_HSE_PREDIV2_DIV_5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */
193 #define LL_RCC_HSE_PREDIV2_DIV_6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */
194 #define LL_RCC_HSE_PREDIV2_DIV_7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */
195 #define LL_RCC_HSE_PREDIV2_DIV_8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */
196 #define LL_RCC_HSE_PREDIV2_DIV_9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */
197 #define LL_RCC_HSE_PREDIV2_DIV_10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */
198 #define LL_RCC_HSE_PREDIV2_DIV_11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */
199 #define LL_RCC_HSE_PREDIV2_DIV_12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */
200 #define LL_RCC_HSE_PREDIV2_DIV_13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */
201 #define LL_RCC_HSE_PREDIV2_DIV_14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */
202 #define LL_RCC_HSE_PREDIV2_DIV_15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */
203 #define LL_RCC_HSE_PREDIV2_DIV_16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */
204 /**
205 * @}
206 */
207
208 #endif /* RCC_CFGR2_PREDIV2 */
209
210 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
211 * @{
212 */
213 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
214 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
215 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
216 /**
217 * @}
218 */
219
220 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
221 * @{
222 */
223 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
224 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
225 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
226 /**
227 * @}
228 */
229
230 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
231 * @{
232 */
233 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
234 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
235 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
236 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
237 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
238 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
239 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
240 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
241 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
242 /**
243 * @}
244 */
245
246 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
247 * @{
248 */
249 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
250 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
251 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
252 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
253 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
254 /**
255 * @}
256 */
257
258 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
259 * @{
260 */
261 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
262 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
263 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
264 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
265 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
266 /**
267 * @}
268 */
269
270 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
271 * @{
272 */
273 #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */
274 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */
275 #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */
276 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */
277 #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/
278 #if defined(RCC_CFGR_MCOSEL_PLL2CLK)
279 #define LL_RCC_MCO1SOURCE_PLL2CLK RCC_CFGR_MCOSEL_PLL2 /*!< PLL2 clock selected as MCO source*/
280 #endif /* RCC_CFGR_MCOSEL_PLL2CLK */
281 #if defined(RCC_CFGR_MCOSEL_PLL3CLK_DIV2)
282 #define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 RCC_CFGR_MCOSEL_PLL3_DIV2 /*!< PLLI2S clock divided by 2 selected as MCO source*/
283 #endif /* RCC_CFGR_MCOSEL_PLL3CLK_DIV2 */
284 #if defined(RCC_CFGR_MCOSEL_EXT_HSE)
285 #define LL_RCC_MCO1SOURCE_EXT_HSE RCC_CFGR_MCOSEL_EXT_HSE /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
286 #endif /* RCC_CFGR_MCOSEL_EXT_HSE */
287 #if defined(RCC_CFGR_MCOSEL_PLL3CLK)
288 #define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCOSEL_PLL3CLK /*!< PLLI2S clock selected as MCO source */
289 #endif /* RCC_CFGR_MCOSEL_PLL3CLK */
290 /**
291 * @}
292 */
293
294 #if defined(USE_FULL_LL_DRIVER)
295 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
296 * @{
297 */
298 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
299 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
300 /**
301 * @}
302 */
303 #endif /* USE_FULL_LL_DRIVER */
304
305 #if defined(RCC_CFGR2_I2S2SRC)
306 /** @defgroup RCC_LL_EC_I2S2CLKSOURCE Peripheral I2S clock source selection
307 * @{
308 */
309 #define LL_RCC_I2S2_CLKSOURCE_SYSCLK RCC_CFGR2_I2S2SRC /*!< System clock (SYSCLK) selected as I2S2 clock entry */
310 #define LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S2SRC | (RCC_CFGR2_I2S2SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S2 clock entry */
311 #define LL_RCC_I2S3_CLKSOURCE_SYSCLK RCC_CFGR2_I2S3SRC /*!< System clock (SYSCLK) selected as I2S3 clock entry */
312 #define LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S3SRC | (RCC_CFGR2_I2S3SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S3 clock entry */
313 /**
314 * @}
315 */
316 #endif /* RCC_CFGR2_I2S2SRC */
317
318 #if defined(USB_OTG_FS) || defined(USB)
319 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
320 * @{
321 */
322 #if defined(RCC_CFGR_USBPRE)
323 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /*!< PLL clock is not divided */
324 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U /*!< PLL clock is divided by 1.5 */
325 #endif /*RCC_CFGR_USBPRE*/
326 #if defined(RCC_CFGR_OTGFSPRE)
327 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /*!< PLL clock is divided by 2 */
328 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 0x00000000U /*!< PLL clock is divided by 3 */
329 #endif /*RCC_CFGR_OTGFSPRE*/
330 /**
331 * @}
332 */
333 #endif /* USB_OTG_FS || USB */
334
335 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE_PCLK2 Peripheral ADC clock source selection
336 * @{
337 */
338 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*ADC prescaler PCLK2 divided by 2*/
339 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*ADC prescaler PCLK2 divided by 4*/
340 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*ADC prescaler PCLK2 divided by 6*/
341 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*ADC prescaler PCLK2 divided by 8*/
342 /**
343 * @}
344 */
345
346 #if defined(RCC_CFGR2_I2S2SRC)
347 /** @defgroup RCC_LL_EC_I2S2 Peripheral I2S get clock source
348 * @{
349 */
350 #define LL_RCC_I2S2_CLKSOURCE RCC_CFGR2_I2S2SRC /*!< I2S2 Clock source selection */
351 #define LL_RCC_I2S3_CLKSOURCE RCC_CFGR2_I2S3SRC /*!< I2S3 Clock source selection */
352 /**
353 * @}
354 */
355
356 #endif /* RCC_CFGR2_I2S2SRC */
357
358 #if defined(USB_OTG_FS) || defined(USB)
359 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
360 * @{
361 */
362 #define LL_RCC_USB_CLKSOURCE 0x00400000U /*!< USB Clock source selection */
363 /**
364 * @}
365 */
366
367 #endif /* USB_OTG_FS || USB */
368
369 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
370 * @{
371 */
372 #define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */
373 /**
374 * @}
375 */
376
377 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
378 * @{
379 */
380 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
381 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
382 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
383 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 128 used as RTC clock */
384 /**
385 * @}
386 */
387
388 /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
389 * @{
390 */
391 #if defined(RCC_CFGR_PLLMULL2)
392 #define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMULL2 /*!< PLL input clock*2 */
393 #endif /*RCC_CFGR_PLLMULL2*/
394 #if defined(RCC_CFGR_PLLMULL3)
395 #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMULL3 /*!< PLL input clock*3 */
396 #endif /*RCC_CFGR_PLLMULL3*/
397 #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMULL4 /*!< PLL input clock*4 */
398 #define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMULL5 /*!< PLL input clock*5 */
399 #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMULL6 /*!< PLL input clock*6 */
400 #define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMULL7 /*!< PLL input clock*7 */
401 #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMULL8 /*!< PLL input clock*8 */
402 #define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMULL9 /*!< PLL input clock*9 */
403 #if defined(RCC_CFGR_PLLMULL6_5)
404 #define LL_RCC_PLL_MUL_6_5 RCC_CFGR_PLLMULL6_5 /*!< PLL input clock*6 */
405 #else
406 #define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMULL10 /*!< PLL input clock*10 */
407 #define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMULL11 /*!< PLL input clock*11 */
408 #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMULL12 /*!< PLL input clock*12 */
409 #define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMULL13 /*!< PLL input clock*13 */
410 #define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMULL14 /*!< PLL input clock*14 */
411 #define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMULL15 /*!< PLL input clock*15 */
412 #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMULL16 /*!< PLL input clock*16 */
413 #endif /*RCC_CFGR_PLLMULL6_5*/
414 /**
415 * @}
416 */
417
418 /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
419 * @{
420 */
421 #define LL_RCC_PLLSOURCE_HSI_DIV_2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */
422 #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE/PREDIV1 clock selected as PLL entry clock source */
423 #if defined(RCC_CFGR2_PREDIV1SRC)
424 #define LL_RCC_PLLSOURCE_PLL2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/PREDIV1 clock selected as PLL entry clock source */
425 #endif /*RCC_CFGR2_PREDIV1SRC*/
426
427 #define LL_RCC_PLLSOURCE_HSE_DIV_1 RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */
428 #if defined(RCC_CFGR2_PREDIV1)
429 #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */
430 #define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */
431 #define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */
432 #define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */
433 #define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */
434 #define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */
435 #define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */
436 #define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */
437 #define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */
438 #define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */
439 #define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */
440 #define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */
441 #define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */
442 #define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */
443 #define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */
444 #if defined(RCC_CFGR2_PREDIV1SRC)
445 #define LL_RCC_PLLSOURCE_PLL2_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/2 clock selected as PLL entry clock source */
446 #define LL_RCC_PLLSOURCE_PLL2_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/3 clock selected as PLL entry clock source */
447 #define LL_RCC_PLLSOURCE_PLL2_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/4 clock selected as PLL entry clock source */
448 #define LL_RCC_PLLSOURCE_PLL2_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/5 clock selected as PLL entry clock source */
449 #define LL_RCC_PLLSOURCE_PLL2_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/6 clock selected as PLL entry clock source */
450 #define LL_RCC_PLLSOURCE_PLL2_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/7 clock selected as PLL entry clock source */
451 #define LL_RCC_PLLSOURCE_PLL2_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/8 clock selected as PLL entry clock source */
452 #define LL_RCC_PLLSOURCE_PLL2_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/9 clock selected as PLL entry clock source */
453 #define LL_RCC_PLLSOURCE_PLL2_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/10 clock selected as PLL entry clock source */
454 #define LL_RCC_PLLSOURCE_PLL2_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/11 clock selected as PLL entry clock source */
455 #define LL_RCC_PLLSOURCE_PLL2_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/12 clock selected as PLL entry clock source */
456 #define LL_RCC_PLLSOURCE_PLL2_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/13 clock selected as PLL entry clock source */
457 #define LL_RCC_PLLSOURCE_PLL2_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/14 clock selected as PLL entry clock source */
458 #define LL_RCC_PLLSOURCE_PLL2_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/15 clock selected as PLL entry clock source */
459 #define LL_RCC_PLLSOURCE_PLL2_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/16 clock selected as PLL entry clock source */
460 #endif /*RCC_CFGR2_PREDIV1SRC*/
461 #else
462 #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE) /*!< HSE/2 clock selected as PLL entry clock source */
463 #endif /*RCC_CFGR2_PREDIV1*/
464 /**
465 * @}
466 */
467
468 /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
469 * @{
470 */
471 #if defined(RCC_CFGR2_PREDIV1)
472 #define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV1_DIV1 /*!< PREDIV1 input clock not divided */
473 #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV1_DIV2 /*!< PREDIV1 input clock divided by 2 */
474 #define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV1_DIV3 /*!< PREDIV1 input clock divided by 3 */
475 #define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV1_DIV4 /*!< PREDIV1 input clock divided by 4 */
476 #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV1_DIV5 /*!< PREDIV1 input clock divided by 5 */
477 #define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV1_DIV6 /*!< PREDIV1 input clock divided by 6 */
478 #define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV1_DIV7 /*!< PREDIV1 input clock divided by 7 */
479 #define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV1_DIV8 /*!< PREDIV1 input clock divided by 8 */
480 #define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV1_DIV9 /*!< PREDIV1 input clock divided by 9 */
481 #define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV1_DIV10 /*!< PREDIV1 input clock divided by 10 */
482 #define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV1_DIV11 /*!< PREDIV1 input clock divided by 11 */
483 #define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV1_DIV12 /*!< PREDIV1 input clock divided by 12 */
484 #define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV1_DIV13 /*!< PREDIV1 input clock divided by 13 */
485 #define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV1_DIV14 /*!< PREDIV1 input clock divided by 14 */
486 #define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV1_DIV15 /*!< PREDIV1 input clock divided by 15 */
487 #define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV1_DIV16 /*!< PREDIV1 input clock divided by 16 */
488 #else
489 #define LL_RCC_PREDIV_DIV_1 0x00000000U /*!< HSE divider clock clock not divided */
490 #define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE /*!< HSE divider clock divided by 2 for PLL entry */
491 #endif /*RCC_CFGR2_PREDIV1*/
492 /**
493 * @}
494 */
495
496 #if defined(RCC_PLLI2S_SUPPORT)
497 /** @defgroup RCC_LL_EC_PLLI2S_MUL PLLI2S MUL
498 * @{
499 */
500 #define LL_RCC_PLLI2S_MUL_8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */
501 #define LL_RCC_PLLI2S_MUL_9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */
502 #define LL_RCC_PLLI2S_MUL_10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */
503 #define LL_RCC_PLLI2S_MUL_11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */
504 #define LL_RCC_PLLI2S_MUL_12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */
505 #define LL_RCC_PLLI2S_MUL_13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */
506 #define LL_RCC_PLLI2S_MUL_14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */
507 #define LL_RCC_PLLI2S_MUL_16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */
508 #define LL_RCC_PLLI2S_MUL_20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */
509 /**
510 * @}
511 */
512
513 #endif /* RCC_PLLI2S_SUPPORT */
514
515 #if defined(RCC_PLL2_SUPPORT)
516 /** @defgroup RCC_LL_EC_PLL2_MUL PLL2 MUL
517 * @{
518 */
519 #define LL_RCC_PLL2_MUL_8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */
520 #define LL_RCC_PLL2_MUL_9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */
521 #define LL_RCC_PLL2_MUL_10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */
522 #define LL_RCC_PLL2_MUL_11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */
523 #define LL_RCC_PLL2_MUL_12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */
524 #define LL_RCC_PLL2_MUL_13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */
525 #define LL_RCC_PLL2_MUL_14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */
526 #define LL_RCC_PLL2_MUL_16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */
527 #define LL_RCC_PLL2_MUL_20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */
528 /**
529 * @}
530 */
531
532 #endif /* RCC_PLL2_SUPPORT */
533
534 /**
535 * @}
536 */
537
538 /* Exported macro ------------------------------------------------------------*/
539 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
540 * @{
541 */
542
543 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
544 * @{
545 */
546
547 /**
548 * @brief Write a value in RCC register
549 * @param __REG__ Register to be written
550 * @param __VALUE__ Value to be written in the register
551 * @retval None
552 */
553 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
554
555 /**
556 * @brief Read a value in RCC register
557 * @param __REG__ Register to be read
558 * @retval Register value
559 */
560 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
561 /**
562 * @}
563 */
564
565 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
566 * @{
567 */
568
569 #if defined(RCC_CFGR_PLLMULL6_5)
570 /**
571 * @brief Helper macro to calculate the PLLCLK frequency
572 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
573 * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 / HSI div 2 / PLL2 div Prediv1)
574 * @param __PLLMUL__: This parameter can be one of the following values:
575 * @arg @ref LL_RCC_PLL_MUL_4
576 * @arg @ref LL_RCC_PLL_MUL_5
577 * @arg @ref LL_RCC_PLL_MUL_6
578 * @arg @ref LL_RCC_PLL_MUL_7
579 * @arg @ref LL_RCC_PLL_MUL_8
580 * @arg @ref LL_RCC_PLL_MUL_9
581 * @arg @ref LL_RCC_PLL_MUL_6_5
582 * @retval PLL clock frequency (in Hz)
583 */
584 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
585 (((__PLLMUL__) != RCC_CFGR_PLLMULL6_5) ? \
586 ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos) + 2U)) :\
587 (((__INPUTFREQ__) * 13U) / 2U))
588
589 #else
590 /**
591 * @brief Helper macro to calculate the PLLCLK frequency
592 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator ());
593 * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 or div 2 / HSI div 2)
594 * @param __PLLMUL__: This parameter can be one of the following values:
595 * @arg @ref LL_RCC_PLL_MUL_2
596 * @arg @ref LL_RCC_PLL_MUL_3
597 * @arg @ref LL_RCC_PLL_MUL_4
598 * @arg @ref LL_RCC_PLL_MUL_5
599 * @arg @ref LL_RCC_PLL_MUL_6
600 * @arg @ref LL_RCC_PLL_MUL_7
601 * @arg @ref LL_RCC_PLL_MUL_8
602 * @arg @ref LL_RCC_PLL_MUL_9
603 * @arg @ref LL_RCC_PLL_MUL_10
604 * @arg @ref LL_RCC_PLL_MUL_11
605 * @arg @ref LL_RCC_PLL_MUL_12
606 * @arg @ref LL_RCC_PLL_MUL_13
607 * @arg @ref LL_RCC_PLL_MUL_14
608 * @arg @ref LL_RCC_PLL_MUL_15
609 * @arg @ref LL_RCC_PLL_MUL_16
610 * @retval PLL clock frequency (in Hz)
611 */
612 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_CFGR_PLLMULL_Pos) + 2U))
613 #endif /* RCC_CFGR_PLLMULL6_5 */
614
615 #if defined(RCC_PLLI2S_SUPPORT)
616 /**
617 * @brief Helper macro to calculate the PLLI2S frequency
618 * @note ex: @ref __LL_RCC_CALC_PLLI2SCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLLI2S_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ());
619 * @param __INPUTFREQ__ PLLI2S Input frequency (based on HSE value)
620 * @param __PLLI2SMUL__: This parameter can be one of the following values:
621 * @arg @ref LL_RCC_PLLI2S_MUL_8
622 * @arg @ref LL_RCC_PLLI2S_MUL_9
623 * @arg @ref LL_RCC_PLLI2S_MUL_10
624 * @arg @ref LL_RCC_PLLI2S_MUL_11
625 * @arg @ref LL_RCC_PLLI2S_MUL_12
626 * @arg @ref LL_RCC_PLLI2S_MUL_13
627 * @arg @ref LL_RCC_PLLI2S_MUL_14
628 * @arg @ref LL_RCC_PLLI2S_MUL_16
629 * @arg @ref LL_RCC_PLLI2S_MUL_20
630 * @param __PLLI2SDIV__: This parameter can be one of the following values:
631 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
632 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
633 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
634 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
635 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
636 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
637 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
638 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
639 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
640 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
641 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
642 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
643 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
644 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
645 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
646 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
647 * @retval PLLI2S clock frequency (in Hz)
648 */
649 #define __LL_RCC_CALC_PLLI2SCLK_FREQ(__INPUTFREQ__, __PLLI2SMUL__, __PLLI2SDIV__) (((__INPUTFREQ__) * (((__PLLI2SMUL__) >> RCC_CFGR2_PLL3MUL_Pos) + 2U)) / (((__PLLI2SDIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U))
650 #endif /* RCC_PLLI2S_SUPPORT */
651
652 #if defined(RCC_PLL2_SUPPORT)
653 /**
654 * @brief Helper macro to calculate the PLL2 frequency
655 * @note ex: @ref __LL_RCC_CALC_PLL2CLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL2_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ());
656 * @param __INPUTFREQ__ PLL2 Input frequency (based on HSE value)
657 * @param __PLL2MUL__: This parameter can be one of the following values:
658 * @arg @ref LL_RCC_PLL2_MUL_8
659 * @arg @ref LL_RCC_PLL2_MUL_9
660 * @arg @ref LL_RCC_PLL2_MUL_10
661 * @arg @ref LL_RCC_PLL2_MUL_11
662 * @arg @ref LL_RCC_PLL2_MUL_12
663 * @arg @ref LL_RCC_PLL2_MUL_13
664 * @arg @ref LL_RCC_PLL2_MUL_14
665 * @arg @ref LL_RCC_PLL2_MUL_16
666 * @arg @ref LL_RCC_PLL2_MUL_20
667 * @param __PLL2DIV__: This parameter can be one of the following values:
668 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
669 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
670 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
671 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
672 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
673 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
674 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
675 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
676 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
677 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
678 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
679 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
680 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
681 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
682 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
683 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
684 * @retval PLL2 clock frequency (in Hz)
685 */
686 #define __LL_RCC_CALC_PLL2CLK_FREQ(__INPUTFREQ__, __PLL2MUL__, __PLL2DIV__) (((__INPUTFREQ__) * (((__PLL2MUL__) >> RCC_CFGR2_PLL2MUL_Pos) + 2U)) / (((__PLL2DIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U))
687 #endif /* RCC_PLL2_SUPPORT */
688
689 /**
690 * @brief Helper macro to calculate the HCLK frequency
691 * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
692 * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
693 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
694 * @param __AHBPRESCALER__: This parameter can be one of the following values:
695 * @arg @ref LL_RCC_SYSCLK_DIV_1
696 * @arg @ref LL_RCC_SYSCLK_DIV_2
697 * @arg @ref LL_RCC_SYSCLK_DIV_4
698 * @arg @ref LL_RCC_SYSCLK_DIV_8
699 * @arg @ref LL_RCC_SYSCLK_DIV_16
700 * @arg @ref LL_RCC_SYSCLK_DIV_64
701 * @arg @ref LL_RCC_SYSCLK_DIV_128
702 * @arg @ref LL_RCC_SYSCLK_DIV_256
703 * @arg @ref LL_RCC_SYSCLK_DIV_512
704 * @retval HCLK clock frequency (in Hz)
705 */
706 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
707
708 /**
709 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
710 * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
711 * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
712 * @param __HCLKFREQ__ HCLK frequency
713 * @param __APB1PRESCALER__: This parameter can be one of the following values:
714 * @arg @ref LL_RCC_APB1_DIV_1
715 * @arg @ref LL_RCC_APB1_DIV_2
716 * @arg @ref LL_RCC_APB1_DIV_4
717 * @arg @ref LL_RCC_APB1_DIV_8
718 * @arg @ref LL_RCC_APB1_DIV_16
719 * @retval PCLK1 clock frequency (in Hz)
720 */
721 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
722
723 /**
724 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
725 * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
726 * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
727 * @param __HCLKFREQ__ HCLK frequency
728 * @param __APB2PRESCALER__: This parameter can be one of the following values:
729 * @arg @ref LL_RCC_APB2_DIV_1
730 * @arg @ref LL_RCC_APB2_DIV_2
731 * @arg @ref LL_RCC_APB2_DIV_4
732 * @arg @ref LL_RCC_APB2_DIV_8
733 * @arg @ref LL_RCC_APB2_DIV_16
734 * @retval PCLK2 clock frequency (in Hz)
735 */
736 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
737
738 /**
739 * @}
740 */
741
742 /**
743 * @}
744 */
745
746 /* Exported functions --------------------------------------------------------*/
747 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
748 * @{
749 */
750
751 /** @defgroup RCC_LL_EF_HSE HSE
752 * @{
753 */
754
755 /**
756 * @brief Enable the Clock Security System.
757 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
758 * @retval None
759 */
760 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
761 {
762 SET_BIT(RCC->CR, RCC_CR_CSSON);
763 }
764
765 /**
766 * @brief Enable HSE external oscillator (HSE Bypass)
767 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
768 * @retval None
769 */
770 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
771 {
772 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
773 }
774
775 /**
776 * @brief Disable HSE external oscillator (HSE Bypass)
777 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
778 * @retval None
779 */
780 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
781 {
782 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
783 }
784
785 /**
786 * @brief Enable HSE crystal oscillator (HSE ON)
787 * @rmtoll CR HSEON LL_RCC_HSE_Enable
788 * @retval None
789 */
790 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
791 {
792 SET_BIT(RCC->CR, RCC_CR_HSEON);
793 }
794
795 /**
796 * @brief Disable HSE crystal oscillator (HSE ON)
797 * @rmtoll CR HSEON LL_RCC_HSE_Disable
798 * @retval None
799 */
800 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
801 {
802 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
803 }
804
805 /**
806 * @brief Check if HSE oscillator Ready
807 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
808 * @retval State of bit (1 or 0).
809 */
810 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
811 {
812 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
813 }
814
815 #if defined(RCC_CFGR2_PREDIV2)
816 /**
817 * @brief Get PREDIV2 division factor
818 * @rmtoll CFGR2 PREDIV2 LL_RCC_HSE_GetPrediv2
819 * @retval Returned value can be one of the following values:
820 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
821 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
822 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
823 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
824 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
825 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
826 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
827 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
828 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
829 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
830 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
831 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
832 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
833 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
834 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
835 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
836 */
837 __STATIC_INLINE uint32_t LL_RCC_HSE_GetPrediv2(void)
838 {
839 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2));
840 }
841 #endif /* RCC_CFGR2_PREDIV2 */
842
843 /**
844 * @}
845 */
846
847 /** @defgroup RCC_LL_EF_HSI HSI
848 * @{
849 */
850
851 /**
852 * @brief Enable HSI oscillator
853 * @rmtoll CR HSION LL_RCC_HSI_Enable
854 * @retval None
855 */
856 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
857 {
858 SET_BIT(RCC->CR, RCC_CR_HSION);
859 }
860
861 /**
862 * @brief Disable HSI oscillator
863 * @rmtoll CR HSION LL_RCC_HSI_Disable
864 * @retval None
865 */
866 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
867 {
868 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
869 }
870
871 /**
872 * @brief Check if HSI clock is ready
873 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
874 * @retval State of bit (1 or 0).
875 */
876 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
877 {
878 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
879 }
880
881 /**
882 * @brief Get HSI Calibration value
883 * @note When HSITRIM is written, HSICAL is updated with the sum of
884 * HSITRIM and the factory trim value
885 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
886 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
887 */
888 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
889 {
890 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
891 }
892
893 /**
894 * @brief Set HSI Calibration trimming
895 * @note user-programmable trimming value that is added to the HSICAL
896 * @note Default value is 16, which, when added to the HSICAL value,
897 * should trim the HSI to 16 MHz +/- 1 %
898 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
899 * @param Value between Min_Data = 0x00 and Max_Data = 0x1F
900 * @retval None
901 */
902 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
903 {
904 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
905 }
906
907 /**
908 * @brief Get HSI Calibration trimming
909 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
910 * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
911 */
912 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
913 {
914 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
915 }
916
917 /**
918 * @}
919 */
920
921 /** @defgroup RCC_LL_EF_LSE LSE
922 * @{
923 */
924
925 /**
926 * @brief Enable Low Speed External (LSE) crystal.
927 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
928 * @retval None
929 */
930 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
931 {
932 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
933 }
934
935 /**
936 * @brief Disable Low Speed External (LSE) crystal.
937 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
938 * @retval None
939 */
940 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
941 {
942 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
943 }
944
945 /**
946 * @brief Enable external clock source (LSE bypass).
947 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
948 * @retval None
949 */
950 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
951 {
952 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
953 }
954
955 /**
956 * @brief Disable external clock source (LSE bypass).
957 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
958 * @retval None
959 */
960 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
961 {
962 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
963 }
964
965 /**
966 * @brief Check if LSE oscillator Ready
967 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
968 * @retval State of bit (1 or 0).
969 */
970 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
971 {
972 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
973 }
974
975 /**
976 * @}
977 */
978
979 /** @defgroup RCC_LL_EF_LSI LSI
980 * @{
981 */
982
983 /**
984 * @brief Enable LSI Oscillator
985 * @rmtoll CSR LSION LL_RCC_LSI_Enable
986 * @retval None
987 */
988 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
989 {
990 SET_BIT(RCC->CSR, RCC_CSR_LSION);
991 }
992
993 /**
994 * @brief Disable LSI Oscillator
995 * @rmtoll CSR LSION LL_RCC_LSI_Disable
996 * @retval None
997 */
998 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
999 {
1000 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
1001 }
1002
1003 /**
1004 * @brief Check if LSI is Ready
1005 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
1006 * @retval State of bit (1 or 0).
1007 */
1008 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
1009 {
1010 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
1011 }
1012
1013 /**
1014 * @}
1015 */
1016
1017 /** @defgroup RCC_LL_EF_System System
1018 * @{
1019 */
1020
1021 /**
1022 * @brief Configure the system clock source
1023 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
1024 * @param Source This parameter can be one of the following values:
1025 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
1026 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
1027 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
1028 * @retval None
1029 */
1030 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1031 {
1032 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
1033 }
1034
1035 /**
1036 * @brief Get the system clock source
1037 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
1038 * @retval Returned value can be one of the following values:
1039 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
1040 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
1041 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
1042 */
1043 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1044 {
1045 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
1046 }
1047
1048 /**
1049 * @brief Set AHB prescaler
1050 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
1051 * @param Prescaler This parameter can be one of the following values:
1052 * @arg @ref LL_RCC_SYSCLK_DIV_1
1053 * @arg @ref LL_RCC_SYSCLK_DIV_2
1054 * @arg @ref LL_RCC_SYSCLK_DIV_4
1055 * @arg @ref LL_RCC_SYSCLK_DIV_8
1056 * @arg @ref LL_RCC_SYSCLK_DIV_16
1057 * @arg @ref LL_RCC_SYSCLK_DIV_64
1058 * @arg @ref LL_RCC_SYSCLK_DIV_128
1059 * @arg @ref LL_RCC_SYSCLK_DIV_256
1060 * @arg @ref LL_RCC_SYSCLK_DIV_512
1061 * @retval None
1062 */
1063 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
1064 {
1065 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
1066 }
1067
1068 /**
1069 * @brief Set APB1 prescaler
1070 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
1071 * @param Prescaler This parameter can be one of the following values:
1072 * @arg @ref LL_RCC_APB1_DIV_1
1073 * @arg @ref LL_RCC_APB1_DIV_2
1074 * @arg @ref LL_RCC_APB1_DIV_4
1075 * @arg @ref LL_RCC_APB1_DIV_8
1076 * @arg @ref LL_RCC_APB1_DIV_16
1077 * @retval None
1078 */
1079 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
1080 {
1081 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
1082 }
1083
1084 /**
1085 * @brief Set APB2 prescaler
1086 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
1087 * @param Prescaler This parameter can be one of the following values:
1088 * @arg @ref LL_RCC_APB2_DIV_1
1089 * @arg @ref LL_RCC_APB2_DIV_2
1090 * @arg @ref LL_RCC_APB2_DIV_4
1091 * @arg @ref LL_RCC_APB2_DIV_8
1092 * @arg @ref LL_RCC_APB2_DIV_16
1093 * @retval None
1094 */
1095 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
1096 {
1097 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
1098 }
1099
1100 /**
1101 * @brief Get AHB prescaler
1102 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
1103 * @retval Returned value can be one of the following values:
1104 * @arg @ref LL_RCC_SYSCLK_DIV_1
1105 * @arg @ref LL_RCC_SYSCLK_DIV_2
1106 * @arg @ref LL_RCC_SYSCLK_DIV_4
1107 * @arg @ref LL_RCC_SYSCLK_DIV_8
1108 * @arg @ref LL_RCC_SYSCLK_DIV_16
1109 * @arg @ref LL_RCC_SYSCLK_DIV_64
1110 * @arg @ref LL_RCC_SYSCLK_DIV_128
1111 * @arg @ref LL_RCC_SYSCLK_DIV_256
1112 * @arg @ref LL_RCC_SYSCLK_DIV_512
1113 */
1114 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
1115 {
1116 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
1117 }
1118
1119 /**
1120 * @brief Get APB1 prescaler
1121 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
1122 * @retval Returned value can be one of the following values:
1123 * @arg @ref LL_RCC_APB1_DIV_1
1124 * @arg @ref LL_RCC_APB1_DIV_2
1125 * @arg @ref LL_RCC_APB1_DIV_4
1126 * @arg @ref LL_RCC_APB1_DIV_8
1127 * @arg @ref LL_RCC_APB1_DIV_16
1128 */
1129 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1130 {
1131 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
1132 }
1133
1134 /**
1135 * @brief Get APB2 prescaler
1136 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
1137 * @retval Returned value can be one of the following values:
1138 * @arg @ref LL_RCC_APB2_DIV_1
1139 * @arg @ref LL_RCC_APB2_DIV_2
1140 * @arg @ref LL_RCC_APB2_DIV_4
1141 * @arg @ref LL_RCC_APB2_DIV_8
1142 * @arg @ref LL_RCC_APB2_DIV_16
1143 */
1144 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
1145 {
1146 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
1147 }
1148
1149 /**
1150 * @}
1151 */
1152
1153 /** @defgroup RCC_LL_EF_MCO MCO
1154 * @{
1155 */
1156
1157 /**
1158 * @brief Configure MCOx
1159 * @rmtoll CFGR MCO LL_RCC_ConfigMCO
1160 * @param MCOxSource This parameter can be one of the following values:
1161 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
1162 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
1163 * @arg @ref LL_RCC_MCO1SOURCE_HSI
1164 * @arg @ref LL_RCC_MCO1SOURCE_HSE
1165 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
1166 * @arg @ref LL_RCC_MCO1SOURCE_PLL2CLK (*)
1167 * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 (*)
1168 * @arg @ref LL_RCC_MCO1SOURCE_EXT_HSE (*)
1169 * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK (*)
1170 *
1171 * (*) value not defined in all devices
1172 * @retval None
1173 */
1174 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource)
1175 {
1176 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
1177 }
1178
1179 /**
1180 * @}
1181 */
1182
1183 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
1184 * @{
1185 */
1186
1187 #if defined(RCC_CFGR2_I2S2SRC)
1188 /**
1189 * @brief Configure I2Sx clock source
1190 * @rmtoll CFGR2 I2S2SRC LL_RCC_SetI2SClockSource\n
1191 * CFGR2 I2S3SRC LL_RCC_SetI2SClockSource
1192 * @param I2SxSource This parameter can be one of the following values:
1193 * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
1194 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
1195 * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
1196 * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
1197 * @retval None
1198 */
1199 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
1200 {
1201 MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U));
1202 }
1203 #endif /* RCC_CFGR2_I2S2SRC */
1204
1205 #if defined(USB_OTG_FS) || defined(USB)
1206 /**
1207 * @brief Configure USB clock source
1208 * @rmtoll CFGR OTGFSPRE LL_RCC_SetUSBClockSource\n
1209 * CFGR USBPRE LL_RCC_SetUSBClockSource
1210 * @param USBxSource This parameter can be one of the following values:
1211 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
1212 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
1213 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
1214 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
1215 *
1216 * (*) value not defined in all devices
1217 * @retval None
1218 */
1219 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
1220 {
1221 #if defined(RCC_CFGR_USBPRE)
1222 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource);
1223 #else /*RCC_CFGR_OTGFSPRE*/
1224 MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, USBxSource);
1225 #endif /*RCC_CFGR_USBPRE*/
1226 }
1227 #endif /* USB_OTG_FS || USB */
1228
1229 /**
1230 * @brief Configure ADC clock source
1231 * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource
1232 * @param ADCxSource This parameter can be one of the following values:
1233 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
1234 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
1235 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
1236 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
1237 * @retval None
1238 */
1239 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
1240 {
1241 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource);
1242 }
1243
1244 #if defined(RCC_CFGR2_I2S2SRC)
1245 /**
1246 * @brief Get I2Sx clock source
1247 * @rmtoll CFGR2 I2S2SRC LL_RCC_GetI2SClockSource\n
1248 * CFGR2 I2S3SRC LL_RCC_GetI2SClockSource
1249 * @param I2Sx This parameter can be one of the following values:
1250 * @arg @ref LL_RCC_I2S2_CLKSOURCE
1251 * @arg @ref LL_RCC_I2S3_CLKSOURCE
1252 * @retval Returned value can be one of the following values:
1253 * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
1254 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
1255 * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
1256 * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
1257 */
1258 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
1259 {
1260 return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16U | I2Sx);
1261 }
1262 #endif /* RCC_CFGR2_I2S2SRC */
1263
1264 #if defined(USB_OTG_FS) || defined(USB)
1265 /**
1266 * @brief Get USBx clock source
1267 * @rmtoll CFGR OTGFSPRE LL_RCC_GetUSBClockSource\n
1268 * CFGR USBPRE LL_RCC_GetUSBClockSource
1269 * @param USBx This parameter can be one of the following values:
1270 * @arg @ref LL_RCC_USB_CLKSOURCE
1271 * @retval Returned value can be one of the following values:
1272 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
1273 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
1274 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
1275 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
1276 *
1277 * (*) value not defined in all devices
1278 */
1279 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
1280 {
1281 return (uint32_t)(READ_BIT(RCC->CFGR, USBx));
1282 }
1283 #endif /* USB_OTG_FS || USB */
1284
1285 /**
1286 * @brief Get ADCx clock source
1287 * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource
1288 * @param ADCx This parameter can be one of the following values:
1289 * @arg @ref LL_RCC_ADC_CLKSOURCE
1290 * @retval Returned value can be one of the following values:
1291 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
1292 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
1293 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
1294 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
1295 */
1296 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
1297 {
1298 return (uint32_t)(READ_BIT(RCC->CFGR, ADCx));
1299 }
1300
1301 /**
1302 * @}
1303 */
1304
1305 /** @defgroup RCC_LL_EF_RTC RTC
1306 * @{
1307 */
1308
1309 /**
1310 * @brief Set RTC Clock Source
1311 * @note Once the RTC clock source has been selected, it cannot be changed any more unless
1312 * the Backup domain is reset. The BDRST bit can be used to reset them.
1313 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
1314 * @param Source This parameter can be one of the following values:
1315 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1316 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1317 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1318 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
1319 * @retval None
1320 */
1321 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
1322 {
1323 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
1324 }
1325
1326 /**
1327 * @brief Get RTC Clock Source
1328 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
1329 * @retval Returned value can be one of the following values:
1330 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1331 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1332 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1333 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
1334 */
1335 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
1336 {
1337 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
1338 }
1339
1340 /**
1341 * @brief Enable RTC
1342 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
1343 * @retval None
1344 */
1345 __STATIC_INLINE void LL_RCC_EnableRTC(void)
1346 {
1347 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
1348 }
1349
1350 /**
1351 * @brief Disable RTC
1352 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
1353 * @retval None
1354 */
1355 __STATIC_INLINE void LL_RCC_DisableRTC(void)
1356 {
1357 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
1358 }
1359
1360 /**
1361 * @brief Check if RTC has been enabled or not
1362 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
1363 * @retval State of bit (1 or 0).
1364 */
1365 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
1366 {
1367 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
1368 }
1369
1370 /**
1371 * @brief Force the Backup domain reset
1372 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
1373 * @retval None
1374 */
1375 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
1376 {
1377 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
1378 }
1379
1380 /**
1381 * @brief Release the Backup domain reset
1382 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
1383 * @retval None
1384 */
1385 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
1386 {
1387 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
1388 }
1389
1390 /**
1391 * @}
1392 */
1393
1394 /** @defgroup RCC_LL_EF_PLL PLL
1395 * @{
1396 */
1397
1398 /**
1399 * @brief Enable PLL
1400 * @rmtoll CR PLLON LL_RCC_PLL_Enable
1401 * @retval None
1402 */
1403 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
1404 {
1405 SET_BIT(RCC->CR, RCC_CR_PLLON);
1406 }
1407
1408 /**
1409 * @brief Disable PLL
1410 * @note Cannot be disabled if the PLL clock is used as the system clock
1411 * @rmtoll CR PLLON LL_RCC_PLL_Disable
1412 * @retval None
1413 */
1414 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
1415 {
1416 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
1417 }
1418
1419 /**
1420 * @brief Check if PLL Ready
1421 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
1422 * @retval State of bit (1 or 0).
1423 */
1424 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
1425 {
1426 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
1427 }
1428
1429 /**
1430 * @brief Configure PLL used for SYSCLK Domain
1431 * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
1432 * CFGR PLLXTPRE LL_RCC_PLL_ConfigDomain_SYS\n
1433 * CFGR PLLMULL LL_RCC_PLL_ConfigDomain_SYS\n
1434 * CFGR2 PREDIV1 LL_RCC_PLL_ConfigDomain_SYS\n
1435 * CFGR2 PREDIV1SRC LL_RCC_PLL_ConfigDomain_SYS
1436 * @param Source This parameter can be one of the following values:
1437 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
1438 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
1439 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 (*)
1440 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 (*)
1441 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 (*)
1442 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 (*)
1443 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 (*)
1444 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 (*)
1445 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 (*)
1446 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 (*)
1447 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 (*)
1448 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 (*)
1449 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 (*)
1450 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 (*)
1451 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 (*)
1452 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 (*)
1453 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 (*)
1454 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_2 (*)
1455 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_3 (*)
1456 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_4 (*)
1457 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_5 (*)
1458 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_6 (*)
1459 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_7 (*)
1460 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_8 (*)
1461 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_9 (*)
1462 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_10 (*)
1463 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_11 (*)
1464 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_12 (*)
1465 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_13 (*)
1466 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_14 (*)
1467 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_15 (*)
1468 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_16 (*)
1469 *
1470 * (*) value not defined in all devices
1471 * @param PLLMul This parameter can be one of the following values:
1472 * @arg @ref LL_RCC_PLL_MUL_2 (*)
1473 * @arg @ref LL_RCC_PLL_MUL_3 (*)
1474 * @arg @ref LL_RCC_PLL_MUL_4
1475 * @arg @ref LL_RCC_PLL_MUL_5
1476 * @arg @ref LL_RCC_PLL_MUL_6
1477 * @arg @ref LL_RCC_PLL_MUL_7
1478 * @arg @ref LL_RCC_PLL_MUL_8
1479 * @arg @ref LL_RCC_PLL_MUL_9
1480 * @arg @ref LL_RCC_PLL_MUL_6_5 (*)
1481 * @arg @ref LL_RCC_PLL_MUL_10 (*)
1482 * @arg @ref LL_RCC_PLL_MUL_11 (*)
1483 * @arg @ref LL_RCC_PLL_MUL_12 (*)
1484 * @arg @ref LL_RCC_PLL_MUL_13 (*)
1485 * @arg @ref LL_RCC_PLL_MUL_14 (*)
1486 * @arg @ref LL_RCC_PLL_MUL_15 (*)
1487 * @arg @ref LL_RCC_PLL_MUL_16 (*)
1488 *
1489 * (*) value not defined in all devices
1490 * @retval None
1491 */
1492 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
1493 {
1494 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL,
1495 (Source & (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)) | PLLMul);
1496 #if defined(RCC_CFGR2_PREDIV1)
1497 #if defined(RCC_CFGR2_PREDIV1SRC)
1498 MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC),
1499 (Source & RCC_CFGR2_PREDIV1) | ((Source & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U));
1500 #else
1501 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1));
1502 #endif /*RCC_CFGR2_PREDIV1SRC*/
1503 #endif /*RCC_CFGR2_PREDIV1*/
1504 }
1505
1506 /**
1507 * @brief Get the oscillator used as PLL clock source.
1508 * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource\n
1509 * CFGR2 PREDIV1SRC LL_RCC_PLL_GetMainSource
1510 * @retval Returned value can be one of the following values:
1511 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
1512 * @arg @ref LL_RCC_PLLSOURCE_HSE
1513 * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*)
1514 *
1515 * (*) value not defined in all devices
1516 */
1517 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
1518 {
1519 #if defined(RCC_CFGR2_PREDIV1SRC)
1520 register uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC);
1521 register uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U);
1522 return (uint32_t)(pllsrc | predivsrc);
1523 #else
1524 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
1525 #endif /*RCC_CFGR2_PREDIV1SRC*/
1526 }
1527
1528 /**
1529 * @brief Get PLL multiplication Factor
1530 * @rmtoll CFGR PLLMULL LL_RCC_PLL_GetMultiplicator
1531 * @retval Returned value can be one of the following values:
1532 * @arg @ref LL_RCC_PLL_MUL_2 (*)
1533 * @arg @ref LL_RCC_PLL_MUL_3 (*)
1534 * @arg @ref LL_RCC_PLL_MUL_4
1535 * @arg @ref LL_RCC_PLL_MUL_5
1536 * @arg @ref LL_RCC_PLL_MUL_6
1537 * @arg @ref LL_RCC_PLL_MUL_7
1538 * @arg @ref LL_RCC_PLL_MUL_8
1539 * @arg @ref LL_RCC_PLL_MUL_9
1540 * @arg @ref LL_RCC_PLL_MUL_6_5 (*)
1541 * @arg @ref LL_RCC_PLL_MUL_10 (*)
1542 * @arg @ref LL_RCC_PLL_MUL_11 (*)
1543 * @arg @ref LL_RCC_PLL_MUL_12 (*)
1544 * @arg @ref LL_RCC_PLL_MUL_13 (*)
1545 * @arg @ref LL_RCC_PLL_MUL_14 (*)
1546 * @arg @ref LL_RCC_PLL_MUL_15 (*)
1547 * @arg @ref LL_RCC_PLL_MUL_16 (*)
1548 *
1549 * (*) value not defined in all devices
1550 */
1551 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
1552 {
1553 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMULL));
1554 }
1555
1556 /**
1557 * @brief Get PREDIV1 division factor for the main PLL
1558 * @note They can be written only when the PLL is disabled
1559 * @rmtoll CFGR2 PREDIV1 LL_RCC_PLL_GetPrediv\n
1560 * CFGR2 PLLXTPRE LL_RCC_PLL_GetPrediv
1561 * @retval Returned value can be one of the following values:
1562 * @arg @ref LL_RCC_PREDIV_DIV_1
1563 * @arg @ref LL_RCC_PREDIV_DIV_2
1564 * @arg @ref LL_RCC_PREDIV_DIV_3 (*)
1565 * @arg @ref LL_RCC_PREDIV_DIV_4 (*)
1566 * @arg @ref LL_RCC_PREDIV_DIV_5 (*)
1567 * @arg @ref LL_RCC_PREDIV_DIV_6 (*)
1568 * @arg @ref LL_RCC_PREDIV_DIV_7 (*)
1569 * @arg @ref LL_RCC_PREDIV_DIV_8 (*)
1570 * @arg @ref LL_RCC_PREDIV_DIV_9 (*)
1571 * @arg @ref LL_RCC_PREDIV_DIV_10 (*)
1572 * @arg @ref LL_RCC_PREDIV_DIV_11 (*)
1573 * @arg @ref LL_RCC_PREDIV_DIV_12 (*)
1574 * @arg @ref LL_RCC_PREDIV_DIV_13 (*)
1575 * @arg @ref LL_RCC_PREDIV_DIV_14 (*)
1576 * @arg @ref LL_RCC_PREDIV_DIV_15 (*)
1577 * @arg @ref LL_RCC_PREDIV_DIV_16 (*)
1578 *
1579 * (*) value not defined in all devices
1580 */
1581 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
1582 {
1583 #if defined(RCC_CFGR2_PREDIV1)
1584 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1));
1585 #else
1586 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE));
1587 #endif /*RCC_CFGR2_PREDIV1*/
1588 }
1589
1590 /**
1591 * @}
1592 */
1593
1594 #if defined(RCC_PLLI2S_SUPPORT)
1595 /** @defgroup RCC_LL_EF_PLLI2S PLLI2S
1596 * @{
1597 */
1598
1599 /**
1600 * @brief Enable PLLI2S
1601 * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Enable
1602 * @retval None
1603 */
1604 __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
1605 {
1606 SET_BIT(RCC->CR, RCC_CR_PLL3ON);
1607 }
1608
1609 /**
1610 * @brief Disable PLLI2S
1611 * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Disable
1612 * @retval None
1613 */
1614 __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
1615 {
1616 CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
1617 }
1618
1619 /**
1620 * @brief Check if PLLI2S Ready
1621 * @rmtoll CR PLL3RDY LL_RCC_PLLI2S_IsReady
1622 * @retval State of bit (1 or 0).
1623 */
1624 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
1625 {
1626 return (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY));
1627 }
1628
1629 /**
1630 * @brief Configure PLLI2S used for I2S Domain
1631 * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLLI2S\n
1632 * CFGR2 PLL3MUL LL_RCC_PLL_ConfigDomain_PLLI2S
1633 * @param Divider This parameter can be one of the following values:
1634 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
1635 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
1636 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
1637 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
1638 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
1639 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
1640 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
1641 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
1642 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
1643 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
1644 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
1645 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
1646 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
1647 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
1648 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
1649 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
1650 * @param Multiplicator This parameter can be one of the following values:
1651 * @arg @ref LL_RCC_PLLI2S_MUL_8
1652 * @arg @ref LL_RCC_PLLI2S_MUL_9
1653 * @arg @ref LL_RCC_PLLI2S_MUL_10
1654 * @arg @ref LL_RCC_PLLI2S_MUL_11
1655 * @arg @ref LL_RCC_PLLI2S_MUL_12
1656 * @arg @ref LL_RCC_PLLI2S_MUL_13
1657 * @arg @ref LL_RCC_PLLI2S_MUL_14
1658 * @arg @ref LL_RCC_PLLI2S_MUL_16
1659 * @arg @ref LL_RCC_PLLI2S_MUL_20
1660 * @retval None
1661 */
1662 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLLI2S(uint32_t Divider, uint32_t Multiplicator)
1663 {
1664 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL3MUL, Divider | Multiplicator);
1665 }
1666
1667 /**
1668 * @brief Get PLLI2S Multiplication Factor
1669 * @rmtoll CFGR2 PLL3MUL LL_RCC_PLLI2S_GetMultiplicator
1670 * @retval Returned value can be one of the following values:
1671 * @arg @ref LL_RCC_PLLI2S_MUL_8
1672 * @arg @ref LL_RCC_PLLI2S_MUL_9
1673 * @arg @ref LL_RCC_PLLI2S_MUL_10
1674 * @arg @ref LL_RCC_PLLI2S_MUL_11
1675 * @arg @ref LL_RCC_PLLI2S_MUL_12
1676 * @arg @ref LL_RCC_PLLI2S_MUL_13
1677 * @arg @ref LL_RCC_PLLI2S_MUL_14
1678 * @arg @ref LL_RCC_PLLI2S_MUL_16
1679 * @arg @ref LL_RCC_PLLI2S_MUL_20
1680 */
1681 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMultiplicator(void)
1682 {
1683 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL));
1684 }
1685
1686 /**
1687 * @}
1688 */
1689 #endif /* RCC_PLLI2S_SUPPORT */
1690
1691 #if defined(RCC_PLL2_SUPPORT)
1692 /** @defgroup RCC_LL_EF_PLL2 PLL2
1693 * @{
1694 */
1695
1696 /**
1697 * @brief Enable PLL2
1698 * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable
1699 * @retval None
1700 */
1701 __STATIC_INLINE void LL_RCC_PLL2_Enable(void)
1702 {
1703 SET_BIT(RCC->CR, RCC_CR_PLL2ON);
1704 }
1705
1706 /**
1707 * @brief Disable PLL2
1708 * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable
1709 * @retval None
1710 */
1711 __STATIC_INLINE void LL_RCC_PLL2_Disable(void)
1712 {
1713 CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
1714 }
1715
1716 /**
1717 * @brief Check if PLL2 Ready
1718 * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady
1719 * @retval State of bit (1 or 0).
1720 */
1721 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
1722 {
1723 return (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY));
1724 }
1725
1726 /**
1727 * @brief Configure PLL2 used for PLL2 Domain
1728 * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLL2\n
1729 * CFGR2 PLL2MUL LL_RCC_PLL_ConfigDomain_PLL2
1730 * @param Divider This parameter can be one of the following values:
1731 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
1732 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
1733 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
1734 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
1735 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
1736 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
1737 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
1738 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
1739 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
1740 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
1741 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
1742 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
1743 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
1744 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
1745 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
1746 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
1747 * @param Multiplicator This parameter can be one of the following values:
1748 * @arg @ref LL_RCC_PLL2_MUL_8
1749 * @arg @ref LL_RCC_PLL2_MUL_9
1750 * @arg @ref LL_RCC_PLL2_MUL_10
1751 * @arg @ref LL_RCC_PLL2_MUL_11
1752 * @arg @ref LL_RCC_PLL2_MUL_12
1753 * @arg @ref LL_RCC_PLL2_MUL_13
1754 * @arg @ref LL_RCC_PLL2_MUL_14
1755 * @arg @ref LL_RCC_PLL2_MUL_16
1756 * @arg @ref LL_RCC_PLL2_MUL_20
1757 * @retval None
1758 */
1759 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLL2(uint32_t Divider, uint32_t Multiplicator)
1760 {
1761 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL, Divider | Multiplicator);
1762 }
1763
1764 /**
1765 * @brief Get PLL2 Multiplication Factor
1766 * @rmtoll CFGR2 PLL2MUL LL_RCC_PLL2_GetMultiplicator
1767 * @retval Returned value can be one of the following values:
1768 * @arg @ref LL_RCC_PLL2_MUL_8
1769 * @arg @ref LL_RCC_PLL2_MUL_9
1770 * @arg @ref LL_RCC_PLL2_MUL_10
1771 * @arg @ref LL_RCC_PLL2_MUL_11
1772 * @arg @ref LL_RCC_PLL2_MUL_12
1773 * @arg @ref LL_RCC_PLL2_MUL_13
1774 * @arg @ref LL_RCC_PLL2_MUL_14
1775 * @arg @ref LL_RCC_PLL2_MUL_16
1776 * @arg @ref LL_RCC_PLL2_MUL_20
1777 */
1778 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetMultiplicator(void)
1779 {
1780 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL2MUL));
1781 }
1782
1783 /**
1784 * @}
1785 */
1786 #endif /* RCC_PLL2_SUPPORT */
1787
1788 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
1789 * @{
1790 */
1791
1792 /**
1793 * @brief Clear LSI ready interrupt flag
1794 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
1795 * @retval None
1796 */
1797 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
1798 {
1799 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
1800 }
1801
1802 /**
1803 * @brief Clear LSE ready interrupt flag
1804 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
1805 * @retval None
1806 */
1807 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
1808 {
1809 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
1810 }
1811
1812 /**
1813 * @brief Clear HSI ready interrupt flag
1814 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
1815 * @retval None
1816 */
1817 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
1818 {
1819 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
1820 }
1821
1822 /**
1823 * @brief Clear HSE ready interrupt flag
1824 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
1825 * @retval None
1826 */
1827 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
1828 {
1829 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
1830 }
1831
1832 /**
1833 * @brief Clear PLL ready interrupt flag
1834 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
1835 * @retval None
1836 */
1837 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
1838 {
1839 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
1840 }
1841
1842 #if defined(RCC_PLLI2S_SUPPORT)
1843 /**
1844 * @brief Clear PLLI2S ready interrupt flag
1845 * @rmtoll CIR PLL3RDYC LL_RCC_ClearFlag_PLLI2SRDY
1846 * @retval None
1847 */
1848 __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
1849 {
1850 SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYC);
1851 }
1852 #endif /* RCC_PLLI2S_SUPPORT */
1853
1854 #if defined(RCC_PLL2_SUPPORT)
1855 /**
1856 * @brief Clear PLL2 ready interrupt flag
1857 * @rmtoll CIR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
1858 * @retval None
1859 */
1860 __STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
1861 {
1862 SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYC);
1863 }
1864 #endif /* RCC_PLL2_SUPPORT */
1865
1866 /**
1867 * @brief Clear Clock security system interrupt flag
1868 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
1869 * @retval None
1870 */
1871 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
1872 {
1873 SET_BIT(RCC->CIR, RCC_CIR_CSSC);
1874 }
1875
1876 /**
1877 * @brief Check if LSI ready interrupt occurred or not
1878 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
1879 * @retval State of bit (1 or 0).
1880 */
1881 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
1882 {
1883 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
1884 }
1885
1886 /**
1887 * @brief Check if LSE ready interrupt occurred or not
1888 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
1889 * @retval State of bit (1 or 0).
1890 */
1891 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
1892 {
1893 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
1894 }
1895
1896 /**
1897 * @brief Check if HSI ready interrupt occurred or not
1898 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
1899 * @retval State of bit (1 or 0).
1900 */
1901 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
1902 {
1903 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
1904 }
1905
1906 /**
1907 * @brief Check if HSE ready interrupt occurred or not
1908 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
1909 * @retval State of bit (1 or 0).
1910 */
1911 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
1912 {
1913 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
1914 }
1915
1916 /**
1917 * @brief Check if PLL ready interrupt occurred or not
1918 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
1919 * @retval State of bit (1 or 0).
1920 */
1921 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
1922 {
1923 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
1924 }
1925
1926 #if defined(RCC_PLLI2S_SUPPORT)
1927 /**
1928 * @brief Check if PLLI2S ready interrupt occurred or not
1929 * @rmtoll CIR PLL3RDYF LL_RCC_IsActiveFlag_PLLI2SRDY
1930 * @retval State of bit (1 or 0).
1931 */
1932 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
1933 {
1934 return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYF) == (RCC_CIR_PLL3RDYF));
1935 }
1936 #endif /* RCC_PLLI2S_SUPPORT */
1937
1938 #if defined(RCC_PLL2_SUPPORT)
1939 /**
1940 * @brief Check if PLL2 ready interrupt occurred or not
1941 * @rmtoll CIR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
1942 * @retval State of bit (1 or 0).
1943 */
1944 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
1945 {
1946 return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYF) == (RCC_CIR_PLL2RDYF));
1947 }
1948 #endif /* RCC_PLL2_SUPPORT */
1949
1950 /**
1951 * @brief Check if Clock security system interrupt occurred or not
1952 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
1953 * @retval State of bit (1 or 0).
1954 */
1955 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
1956 {
1957 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
1958 }
1959
1960 /**
1961 * @brief Check if RCC flag Independent Watchdog reset is set or not.
1962 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
1963 * @retval State of bit (1 or 0).
1964 */
1965 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
1966 {
1967 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
1968 }
1969
1970 /**
1971 * @brief Check if RCC flag Low Power reset is set or not.
1972 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
1973 * @retval State of bit (1 or 0).
1974 */
1975 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
1976 {
1977 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
1978 }
1979
1980 /**
1981 * @brief Check if RCC flag Pin reset is set or not.
1982 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
1983 * @retval State of bit (1 or 0).
1984 */
1985 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
1986 {
1987 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
1988 }
1989
1990 /**
1991 * @brief Check if RCC flag POR/PDR reset is set or not.
1992 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
1993 * @retval State of bit (1 or 0).
1994 */
1995 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
1996 {
1997 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
1998 }
1999
2000 /**
2001 * @brief Check if RCC flag Software reset is set or not.
2002 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
2003 * @retval State of bit (1 or 0).
2004 */
2005 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
2006 {
2007 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
2008 }
2009
2010 /**
2011 * @brief Check if RCC flag Window Watchdog reset is set or not.
2012 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
2013 * @retval State of bit (1 or 0).
2014 */
2015 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
2016 {
2017 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
2018 }
2019
2020 /**
2021 * @brief Set RMVF bit to clear the reset flags.
2022 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
2023 * @retval None
2024 */
2025 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
2026 {
2027 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
2028 }
2029
2030 /**
2031 * @}
2032 */
2033
2034 /** @defgroup RCC_LL_EF_IT_Management IT Management
2035 * @{
2036 */
2037
2038 /**
2039 * @brief Enable LSI ready interrupt
2040 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
2041 * @retval None
2042 */
2043 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
2044 {
2045 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
2046 }
2047
2048 /**
2049 * @brief Enable LSE ready interrupt
2050 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
2051 * @retval None
2052 */
2053 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
2054 {
2055 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
2056 }
2057
2058 /**
2059 * @brief Enable HSI ready interrupt
2060 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
2061 * @retval None
2062 */
2063 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
2064 {
2065 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
2066 }
2067
2068 /**
2069 * @brief Enable HSE ready interrupt
2070 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
2071 * @retval None
2072 */
2073 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
2074 {
2075 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
2076 }
2077
2078 /**
2079 * @brief Enable PLL ready interrupt
2080 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
2081 * @retval None
2082 */
2083 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
2084 {
2085 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
2086 }
2087
2088 #if defined(RCC_PLLI2S_SUPPORT)
2089 /**
2090 * @brief Enable PLLI2S ready interrupt
2091 * @rmtoll CIR PLL3RDYIE LL_RCC_EnableIT_PLLI2SRDY
2092 * @retval None
2093 */
2094 __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
2095 {
2096 SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE);
2097 }
2098 #endif /* RCC_PLLI2S_SUPPORT */
2099
2100 #if defined(RCC_PLL2_SUPPORT)
2101 /**
2102 * @brief Enable PLL2 ready interrupt
2103 * @rmtoll CIR PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
2104 * @retval None
2105 */
2106 __STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
2107 {
2108 SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE);
2109 }
2110 #endif /* RCC_PLL2_SUPPORT */
2111
2112 /**
2113 * @brief Disable LSI ready interrupt
2114 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
2115 * @retval None
2116 */
2117 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
2118 {
2119 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
2120 }
2121
2122 /**
2123 * @brief Disable LSE ready interrupt
2124 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
2125 * @retval None
2126 */
2127 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
2128 {
2129 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
2130 }
2131
2132 /**
2133 * @brief Disable HSI ready interrupt
2134 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
2135 * @retval None
2136 */
2137 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
2138 {
2139 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
2140 }
2141
2142 /**
2143 * @brief Disable HSE ready interrupt
2144 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
2145 * @retval None
2146 */
2147 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
2148 {
2149 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
2150 }
2151
2152 /**
2153 * @brief Disable PLL ready interrupt
2154 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
2155 * @retval None
2156 */
2157 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
2158 {
2159 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
2160 }
2161
2162 #if defined(RCC_PLLI2S_SUPPORT)
2163 /**
2164 * @brief Disable PLLI2S ready interrupt
2165 * @rmtoll CIR PLL3RDYIE LL_RCC_DisableIT_PLLI2SRDY
2166 * @retval None
2167 */
2168 __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
2169 {
2170 CLEAR_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE);
2171 }
2172 #endif /* RCC_PLLI2S_SUPPORT */
2173
2174 #if defined(RCC_PLL2_SUPPORT)
2175 /**
2176 * @brief Disable PLL2 ready interrupt
2177 * @rmtoll CIR PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
2178 * @retval None
2179 */
2180 __STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
2181 {
2182 CLEAR_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE);
2183 }
2184 #endif /* RCC_PLL2_SUPPORT */
2185
2186 /**
2187 * @brief Checks if LSI ready interrupt source is enabled or disabled.
2188 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
2189 * @retval State of bit (1 or 0).
2190 */
2191 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
2192 {
2193 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
2194 }
2195
2196 /**
2197 * @brief Checks if LSE ready interrupt source is enabled or disabled.
2198 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
2199 * @retval State of bit (1 or 0).
2200 */
2201 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
2202 {
2203 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
2204 }
2205
2206 /**
2207 * @brief Checks if HSI ready interrupt source is enabled or disabled.
2208 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
2209 * @retval State of bit (1 or 0).
2210 */
2211 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
2212 {
2213 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
2214 }
2215
2216 /**
2217 * @brief Checks if HSE ready interrupt source is enabled or disabled.
2218 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
2219 * @retval State of bit (1 or 0).
2220 */
2221 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
2222 {
2223 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
2224 }
2225
2226 /**
2227 * @brief Checks if PLL ready interrupt source is enabled or disabled.
2228 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
2229 * @retval State of bit (1 or 0).
2230 */
2231 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
2232 {
2233 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
2234 }
2235
2236 #if defined(RCC_PLLI2S_SUPPORT)
2237 /**
2238 * @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
2239 * @rmtoll CIR PLL3RDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
2240 * @retval State of bit (1 or 0).
2241 */
2242 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
2243 {
2244 return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE) == (RCC_CIR_PLL3RDYIE));
2245 }
2246 #endif /* RCC_PLLI2S_SUPPORT */
2247
2248 #if defined(RCC_PLL2_SUPPORT)
2249 /**
2250 * @brief Checks if PLL2 ready interrupt source is enabled or disabled.
2251 * @rmtoll CIR PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY
2252 * @retval State of bit (1 or 0).
2253 */
2254 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void)
2255 {
2256 return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE) == (RCC_CIR_PLL2RDYIE));
2257 }
2258 #endif /* RCC_PLL2_SUPPORT */
2259
2260 /**
2261 * @}
2262 */
2263
2264 #if defined(USE_FULL_LL_DRIVER)
2265 /** @defgroup RCC_LL_EF_Init De-initialization function
2266 * @{
2267 */
2268 ErrorStatus LL_RCC_DeInit(void);
2269 /**
2270 * @}
2271 */
2272
2273 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
2274 * @{
2275 */
2276 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
2277 #if defined(RCC_CFGR2_I2S2SRC)
2278 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
2279 #endif /* RCC_CFGR2_I2S2SRC */
2280 #if defined(USB_OTG_FS) || defined(USB)
2281 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
2282 #endif /* USB_OTG_FS || USB */
2283 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
2284 /**
2285 * @}
2286 */
2287 #endif /* USE_FULL_LL_DRIVER */
2288
2289 /**
2290 * @}
2291 */
2292
2293 /**
2294 * @}
2295 */
2296
2297 #endif /* RCC */
2298
2299 /**
2300 * @}
2301 */
2302
2303 #ifdef __cplusplus
2304 }
2305 #endif
2306
2307 #endif /* __STM32F1xx_LL_RCC_H */
2308
2309 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/