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Increment eeprom version
[betaflight.git] / lib / main / STM32F1 / Drivers / STM32F1xx_HAL_Driver / Inc / stm32f1xx_ll_sdmmc.h
blobddf47fd0db3a2f52266d6db153825ce15c346547
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_sdmmc.h
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 12-May-2017
7 * @brief Header file of low layer SDMMC HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __stm32f1xx_LL_SD_H
40 #define __stm32f1xx_LL_SD_H
41
42 #if defined(STM32F103xE) || defined(STM32F103xG)
43
44 #ifdef __cplusplus
45 extern "C" {
46 #endif
47
48 /* Includes ------------------------------------------------------------------*/
49 #include "stm32f1xx_hal_def.h"
50
51 /** @addtogroup STM32F1xx_HAL_Driver
52 * @{
53 */
54
55 /** @addtogroup SDMMC_LL
56 * @{
57 */
58
59 /* Exported types ------------------------------------------------------------*/
60 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
61 * @{
62 */
63
64 /**
65 * @brief SDMMC Configuration Structure definition
66 */
67 typedef struct
68 {
69 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
70 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
71
72 uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
73 enabled or disabled.
74 This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
75
76 uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
77 disabled when the bus is idle.
78 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
79
80 uint32_t BusWide; /*!< Specifies the SDIO bus width.
81 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
82
83 uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
84 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
85
86 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
87 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
88
89 }SDIO_InitTypeDef;
90
91
92 /**
93 * @brief SDIO Command Control structure
94 */
95 typedef struct
96 {
97 uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
98 to a card as part of a command message. If a command
99 contains an argument, it must be loaded into this register
100 before writing the command to the command register. */
101
102 uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
103 Max_Data = 64 */
104
105 uint32_t Response; /*!< Specifies the SDIO response type.
106 This parameter can be a value of @ref SDMMC_LL_Response_Type */
107
108 uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
109 enabled or disabled.
110 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
111
112 uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
113 is enabled or disabled.
114 This parameter can be a value of @ref SDMMC_LL_CPSM_State */
115 }SDIO_CmdInitTypeDef;
116
117
118 /**
119 * @brief SDIO Data Control structure
120 */
121 typedef struct
122 {
123 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
124
125 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
126
127 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
128 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
129
130 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
131 is a read or write.
132 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
133
134 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
135 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
136
137 uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
138 is enabled or disabled.
139 This parameter can be a value of @ref SDMMC_LL_DPSM_State */
140 }SDIO_DataInitTypeDef;
141
142 /**
143 * @}
144 */
145
146 /* Exported constants --------------------------------------------------------*/
147 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
148 * @{
149 */
150 #define SDMMC_ERROR_NONE 0x00000000U /*!< No error */
151 #define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */
152 #define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */
153 #define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */
154 #define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */
155 #define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */
156 #define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */
157 #define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */
158 #define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
159 number of transferred bytes does not match the block length */
160 #define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */
161 #define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */
162 #define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */
163 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
164 command or if there was an attempt to access a locked card */
165 #define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */
166 #define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */
167 #define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */
168 #define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */
169 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */
170 #define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */
171 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */
172 #define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */
173 #define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */
174 #define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */
175 #define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
176 of erase sequence command was received */
177 #define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */
178 #define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */
179 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */
180 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */
181 #define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */
182 #define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */
183 #define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */
184 #define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */
185 #define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */
186
187 /**
188 * @brief SDMMC Commands Index
189 */
190 #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */
191 #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */
192 #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
193 #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */
194 #define SDMMC_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */
195 #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
196 operating condition register (OCR) content in the response on the CMD line. */
197 #define SDMMC_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
198 #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */
199 #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
200 and asks the card whether card supports voltage. */
201 #define SDMMC_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
202 #define SDMMC_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */
203 #define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */
204 #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */
205 #define SDMMC_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */
206 #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14) /*!< Reserved */
207 #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */
208 #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands
209 (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
210 for SDHS and SDXC. */
211 #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
212 fixed 512 bytes in case of SDHC and SDXC. */
213 #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by
214 STOP_TRANSMISSION command. */
215 #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
216 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */
217 #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */
218 #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
219 fixed 512 bytes in case of SDHC and SDXC. */
220 #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
221 #define SDMMC_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */
222 #define SDMMC_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */
223 #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */
224 #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */
225 #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */
226 #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */
227 #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */
228 #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command
229 system set by switch function command (CMD6). */
230 #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.
231 Reserved for each command system set by switch function command (CMD6). */
232 #define SDMMC_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */
233 #define SDMMC_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */
234 #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */
235 #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
236 the SET_BLOCK_LEN command. */
237 #define SDMMC_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather
238 than a standard command. */
239 #define SDMMC_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card
240 for general purpose/application specific commands. */
241 #define SDMMC_CMD_NO_CMD ((uint8_t)64) /*!< No command */
242
243 /**
244 * @brief Following commands are SD Card Specific commands.
245 * SDMMC_APP_CMD should be sent before sending these commands.
246 */
247 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
248 widths are given in SCR register. */
249 #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */
250 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
251 32bit+CRC data block. */
252 #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
253 send its operating condition register (OCR) content in the response on the CMD line. */
254 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
255 #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */
256 #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */
257 #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */
258
259 /**
260 * @brief Following commands are SD Card Specific security commands.
261 * SDMMC_CMD_APP_CMD should be sent before sending these commands.
262 */
263 #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43)
264 #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44)
265 #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)
266 #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)
267 #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)
268 #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)
269 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)
270 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)
271 #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)
272 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)
273 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)
274
275 /**
276 * @brief Masks for errors Card Status R1 (OCR Register)
277 */
278 #define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
279 #define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
280 #define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
281 #define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
282 #define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
283 #define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
284 #define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
285 #define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
286 #define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
287 #define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
288 #define SDMMC_OCR_CC_ERROR 0x00100000U
289 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
290 #define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
291 #define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
292 #define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
293 #define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
294 #define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
295 #define SDMMC_OCR_ERASE_RESET 0x00002000U
296 #define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
297 #define SDMMC_OCR_ERRORBITS 0xFDFFE008U
298
299 /**
300 * @brief Masks for R6 Response
301 */
302 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
303 #define SDMMC_R6_ILLEGAL_CMD 0x00004000U
304 #define SDMMC_R6_COM_CRC_FAILED 0x00008000U
305
306 #define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
307 #define SDMMC_HIGH_CAPACITY 0x40000000U
308 #define SDMMC_STD_CAPACITY 0x00000000U
309 #define SDMMC_CHECK_PATTERN 0x000001AAU
310
311 #define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
312
313 #define SDMMC_MAX_TRIAL 0x0000FFFFU
314
315 #define SDMMC_ALLZERO 0x00000000U
316
317 #define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
318 #define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
319 #define SDMMC_CARD_LOCKED 0x02000000U
320
321 #define SDMMC_DATATIMEOUT 0xFFFFFFFFU
322
323 #define SDMMC_0TO7BITS 0x000000FFU
324 #define SDMMC_8TO15BITS 0x0000FF00U
325 #define SDMMC_16TO23BITS 0x00FF0000U
326 #define SDMMC_24TO31BITS 0xFF000000U
327 #define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
328
329 #define SDMMC_HALFFIFO 0x00000008U
330 #define SDMMC_HALFFIFOBYTES 0x00000020U
331
332 /**
333 * @brief Command Class supported
334 */
335 #define SDIO_CCCC_ERASE 0x00000020U
336
337 #define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */
338 #define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
339
340
341 /** @defgroup SDIO_LL_Clock_Edge Clock Edge
342 * @{
343 */
344 #define SDIO_CLOCK_EDGE_RISING 0x00000000U
345 #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
346
347 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
348 ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
349 /**
350 * @}
351 */
352
353 /** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
354 * @{
355 */
356 #define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U
357 #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
358
359 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
360 ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
361 /**
362 * @}
363 */
364
365 /** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
366 * @{
367 */
368 #define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U
369 #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
370
371 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
372 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
373 /**
374 * @}
375 */
376
377 /** @defgroup SDIO_LL_Bus_Wide Bus Width
378 * @{
379 */
380 #define SDIO_BUS_WIDE_1B 0x00000000U
381 #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
382 #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
383
384 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
385 ((WIDE) == SDIO_BUS_WIDE_4B) || \
386 ((WIDE) == SDIO_BUS_WIDE_8B))
387 /**
388 * @}
389 */
390
391 /** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
392 * @{
393 */
394 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U
395 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
396
397 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
398 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
399 /**
400 * @}
401 */
402
403 /** @defgroup SDIO_LL_Clock_Division Clock Division
404 * @{
405 */
406 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU)
407 /**
408 * @}
409 */
410
411 /** @defgroup SDIO_LL_Command_Index Command Index
412 * @{
413 */
414 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
415 /**
416 * @}
417 */
418
419 /** @defgroup SDIO_LL_Response_Type Response Type
420 * @{
421 */
422 #define SDIO_RESPONSE_NO 0x00000000U
423 #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
424 #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
425
426 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
427 ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
428 ((RESPONSE) == SDIO_RESPONSE_LONG))
429 /**
430 * @}
431 */
432
433 /** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
434 * @{
435 */
436 #define SDIO_WAIT_NO 0x00000000U
437 #define SDIO_WAIT_IT SDIO_CMD_WAITINT
438 #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
439
440 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
441 ((WAIT) == SDIO_WAIT_IT) || \
442 ((WAIT) == SDIO_WAIT_PEND))
443 /**
444 * @}
445 */
446
447 /** @defgroup SDIO_LL_CPSM_State CPSM State
448 * @{
449 */
450 #define SDIO_CPSM_DISABLE 0x00000000U
451 #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
452
453 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
454 ((CPSM) == SDIO_CPSM_ENABLE))
455 /**
456 * @}
457 */
458
459 /** @defgroup SDIO_LL_Response_Registers Response Register
460 * @{
461 */
462 #define SDIO_RESP1 0x00000000U
463 #define SDIO_RESP2 0x00000004U
464 #define SDIO_RESP3 0x00000008U
465 #define SDIO_RESP4 0x0000000CU
466
467 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
468 ((RESP) == SDIO_RESP2) || \
469 ((RESP) == SDIO_RESP3) || \
470 ((RESP) == SDIO_RESP4))
471 /**
472 * @}
473 */
474
475 /** @defgroup SDIO_LL_Data_Length Data Lenght
476 * @{
477 */
478 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
479 /**
480 * @}
481 */
482
483 /** @defgroup SDIO_LL_Data_Block_Size Data Block Size
484 * @{
485 */
486 #define SDIO_DATABLOCK_SIZE_1B 0x00000000U
487 #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
488 #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
489 #define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1)
490 #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
491 #define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2)
492 #define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
493 #define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
494 #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
495 #define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3)
496 #define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
497 #define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
498 #define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
499 #define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
500 #define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
501
502 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
503 ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
504 ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
505 ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
506 ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
507 ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
508 ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
509 ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
510 ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
511 ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
512 ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
513 ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
514 ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
515 ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
516 ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
517 /**
518 * @}
519 */
520
521 /** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
522 * @{
523 */
524 #define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U
525 #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
526
527 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
528 ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
529 /**
530 * @}
531 */
532
533 /** @defgroup SDIO_LL_Transfer_Type Transfer Type
534 * @{
535 */
536 #define SDIO_TRANSFER_MODE_BLOCK 0x00000000U
537 #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
538
539 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
540 ((MODE) == SDIO_TRANSFER_MODE_STREAM))
541 /**
542 * @}
543 */
544
545 /** @defgroup SDIO_LL_DPSM_State DPSM State
546 * @{
547 */
548 #define SDIO_DPSM_DISABLE 0x00000000U
549 #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
550
551 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
552 ((DPSM) == SDIO_DPSM_ENABLE))
553 /**
554 * @}
555 */
556
557 /** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
558 * @{
559 */
560 #define SDIO_READ_WAIT_MODE_DATA2 0x00000000U
561 #define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD)
562
563 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
564 ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
565 /**
566 * @}
567 */
568
569 /** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
570 * @{
571 */
572 #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
573 #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
574 #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
575 #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
576 #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
577 #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
578 #define SDIO_IT_CMDREND SDIO_STA_CMDREND
579 #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
580 #define SDIO_IT_DATAEND SDIO_STA_DATAEND
581 #define SDIO_IT_STBITERR SDIO_STA_STBITERR
582 #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
583 #define SDIO_IT_CMDACT SDIO_STA_CMDACT
584 #define SDIO_IT_TXACT SDIO_STA_TXACT
585 #define SDIO_IT_RXACT SDIO_STA_RXACT
586 #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
587 #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
588 #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
589 #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
590 #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
591 #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
592 #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
593 #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
594 #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
595 #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
596 /**
597 * @}
598 */
599
600 /** @defgroup SDMMC_LL_Flags Flags
601 * @{
602 */
603 #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
604 #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
605 #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
606 #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
607 #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
608 #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
609 #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
610 #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
611 #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
612 #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
613 #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
614 #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
615 #define SDIO_FLAG_TXACT SDIO_STA_TXACT
616 #define SDIO_FLAG_RXACT SDIO_STA_RXACT
617 #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
618 #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
619 #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
620 #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
621 #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
622 #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
623 #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
624 #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
625 #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
626 #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
627 #define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
628 SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\
629 SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\
630 SDIO_FLAG_DBCKEND))
631 /**
632 * @}
633 */
634
635 /**
636 * @}
637 */
638
639 /* Exported macro ------------------------------------------------------------*/
640 /** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
641 * @{
642 */
643
644 /** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
645 * @{
646 */
647 /* ------------ SDIO registers bit address in the alias region -------------- */
648 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
649
650 /* --- CLKCR Register ---*/
651 /* Alias word address of CLKEN bit */
652 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04U)
653 #define CLKEN_BITNUMBER 0x08U
654 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
655
656 /* --- CMD Register ---*/
657 /* Alias word address of SDIOSUSPEND bit */
658 #define CMD_OFFSET (SDIO_OFFSET + 0x0CU)
659 #define SDIOSUSPEND_BITNUMBER 0x0BU
660 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
661
662 /* Alias word address of ENCMDCOMPL bit */
663 #define ENCMDCOMPL_BITNUMBER 0x0CU
664 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
665
666 /* Alias word address of NIEN bit */
667 #define NIEN_BITNUMBER 0x0DU
668 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
669
670 /* Alias word address of ATACMD bit */
671 #define ATACMD_BITNUMBER 0x0EU
672 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
673
674 /* --- DCTRL Register ---*/
675 /* Alias word address of DMAEN bit */
676 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU)
677 #define DMAEN_BITNUMBER 0x03U
678 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
679
680 /* Alias word address of RWSTART bit */
681 #define RWSTART_BITNUMBER 0x08U
682 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
683
684 /* Alias word address of RWSTOP bit */
685 #define RWSTOP_BITNUMBER 0x09U
686 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
687
688 /* Alias word address of RWMOD bit */
689 #define RWMOD_BITNUMBER 0x0AU
690 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
691
692 /* Alias word address of SDIOEN bit */
693 #define SDIOEN_BITNUMBER 0x0BU
694 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
695 /**
696 * @}
697 */
698
699 /** @defgroup SDIO_LL_Register Bits And Addresses Definitions
700 * @brief SDIO_LL registers bit address in the alias region
701 * @{
702 */
703 /* ---------------------- SDIO registers bit mask --------------------------- */
704 /* --- CLKCR Register ---*/
705 /* CLKCR register clear mask */
706 #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\
707 SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\
708 SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
709
710 /* --- DCTRL Register ---*/
711 /* SDIO DCTRL Clear Mask */
712 #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\
713 SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE))
714
715 /* --- CMD Register ---*/
716 /* CMD Register clear mask */
717 #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
718 SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\
719 SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
720
721 /* SDIO RESP Registers Address */
722 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
723
724 /* SDIO Intialization Frequency (400KHz max) */
725 #define SDIO_INIT_CLK_DIV ((uint8_t)0xC3)
726
727 /* SDIO Data Transfer Frequency */
728 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x9)
729
730 /**
731 * @}
732 */
733
734 /** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
735 * @brief macros to handle interrupts and specific clock configurations
736 * @{
737 */
738
739 /**
740 * @brief Enable the SDIO device.
741 * @param __INSTANCE__: SDIO Instance
742 * @retval None
743 */
744 #define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
745
746 /**
747 * @brief Disable the SDIO device.
748 * @param __INSTANCE__: SDIO Instance
749 * @retval None
750 */
751 #define __SDIO_DISABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
752
753 /**
754 * @brief Enable the SDIO DMA transfer.
755 * @param __INSTANCE__: SDIO Instance
756 * @retval None
757 */
758 #define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
759 /**
760 * @brief Disable the SDIO DMA transfer.
761 * @param __INSTANCE__: SDIO Instance
762 * @retval None
763 */
764 #define __SDIO_DMA_DISABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
765
766 /**
767 * @brief Enable the SDIO device interrupt.
768 * @param __INSTANCE__ : Pointer to SDIO register base
769 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
770 * This parameter can be one or a combination of the following values:
771 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
772 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
773 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
774 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
775 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
776 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
777 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
778 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
779 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
780 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
781 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
782 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
783 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
784 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
785 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
786 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
787 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
788 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
789 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
790 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
791 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
792 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
793 * @retval None
794 */
795 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
796
797 /**
798 * @brief Disable the SDIO device interrupt.
799 * @param __INSTANCE__ : Pointer to SDIO register base
800 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
801 * This parameter can be one or a combination of the following values:
802 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
803 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
804 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
805 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
806 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
807 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
808 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
809 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
810 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
811 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
812 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
813 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
814 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
815 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
816 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
817 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
818 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
819 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
820 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
821 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
822 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
823 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
824 * @retval None
825 */
826 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
827
828 /**
829 * @brief Checks whether the specified SDIO flag is set or not.
830 * @param __INSTANCE__ : Pointer to SDIO register base
831 * @param __FLAG__: specifies the flag to check.
832 * This parameter can be one of the following values:
833 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
834 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
835 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
836 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
837 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
838 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
839 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
840 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
841 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
842 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
843 * @arg SDIO_FLAG_CMDACT: Command transfer in progress
844 * @arg SDIO_FLAG_TXACT: Data transmit in progress
845 * @arg SDIO_FLAG_RXACT: Data receive in progress
846 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
847 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
848 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
849 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
850 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
851 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
852 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
853 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
854 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
855 * @retval The new state of SDIO_FLAG (SET or RESET).
856 */
857 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
858
859
860 /**
861 * @brief Clears the SDIO pending flags.
862 * @param __INSTANCE__ : Pointer to SDIO register base
863 * @param __FLAG__: specifies the flag to clear.
864 * This parameter can be one or a combination of the following values:
865 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
866 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
867 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
868 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
869 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
870 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
871 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
872 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
873 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
874 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
875 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
876 * @retval None
877 */
878 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
879
880 /**
881 * @brief Checks whether the specified SDIO interrupt has occurred or not.
882 * @param __INSTANCE__ : Pointer to SDIO register base
883 * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
884 * This parameter can be one of the following values:
885 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
886 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
887 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
888 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
889 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
890 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
891 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
892 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
893 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
894 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
895 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
896 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
897 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
898 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
899 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
900 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
901 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
902 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
903 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
904 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
905 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
906 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
907 * @retval The new state of SDIO_IT (SET or RESET).
908 */
909 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
910
911 /**
912 * @brief Clears the SDIO's interrupt pending bits.
913 * @param __INSTANCE__ : Pointer to SDIO register base
914 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
915 * This parameter can be one or a combination of the following values:
916 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
917 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
918 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
919 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
920 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
921 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
922 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
923 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
924 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
925 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
926 * @retval None
927 */
928 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
929
930 /**
931 * @brief Enable Start the SD I/O Read Wait operation.
932 * @param __INSTANCE__ : Pointer to SDIO register base
933 * @retval None
934 */
935 #define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
936
937 /**
938 * @brief Disable Start the SD I/O Read Wait operations.
939 * @param __INSTANCE__ : Pointer to SDIO register base
940 * @retval None
941 */
942 #define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
943
944 /**
945 * @brief Enable Start the SD I/O Read Wait operation.
946 * @param __INSTANCE__ : Pointer to SDIO register base
947 * @retval None
948 */
949 #define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
950
951 /**
952 * @brief Disable Stop the SD I/O Read Wait operations.
953 * @param __INSTANCE__ : Pointer to SDIO register base
954 * @retval None
955 */
956 #define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
957
958 /**
959 * @brief Enable the SD I/O Mode Operation.
960 * @param __INSTANCE__ : Pointer to SDIO register base
961 * @retval None
962 */
963 #define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
964
965 /**
966 * @brief Disable the SD I/O Mode Operation.
967 * @param __INSTANCE__ : Pointer to SDIO register base
968 * @retval None
969 */
970 #define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
971
972 /**
973 * @brief Enable the SD I/O Suspend command sending.
974 * @param __INSTANCE__ : Pointer to SDIO register base
975 * @retval None
976 */
977 #define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
978
979 /**
980 * @brief Disable the SD I/O Suspend command sending.
981 * @param __INSTANCE__ : Pointer to SDIO register base
982 * @retval None
983 */
984 #define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
985 /**
986 * @brief Enable the command completion signal.
987 * @retval None
988 */
989 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
990
991 /**
992 * @brief Disable the command completion signal.
993 * @retval None
994 */
995 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
996
997 /**
998 * @brief Enable the CE-ATA interrupt.
999 * @retval None
1000 */
1001 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U)
1002
1003 /**
1004 * @brief Disable the CE-ATA interrupt.
1005 * @retval None
1006 */
1007 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U)
1008
1009 /**
1010 * @brief Enable send CE-ATA command (CMD61).
1011 * @retval None
1012 */
1013 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
1014
1015 /**
1016 * @brief Disable send CE-ATA command (CMD61).
1017 * @retval None
1018 */
1019 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
1020
1021 /**
1022 * @}
1023 */
1024
1025 /**
1026 * @}
1027 */
1028
1029 /* Exported functions --------------------------------------------------------*/
1030 /** @addtogroup SDMMC_LL_Exported_Functions
1031 * @{
1032 */
1033
1034 /* Initialization/de-initialization functions **********************************/
1035 /** @addtogroup HAL_SDMMC_LL_Group1
1036 * @{
1037 */
1038 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
1039 /**
1040 * @}
1041 */
1042
1043 /* I/O operation functions *****************************************************/
1044 /** @addtogroup HAL_SDMMC_LL_Group2
1045 * @{
1046 */
1047 /* Blocking mode: Polling */
1048 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
1049 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
1050 /**
1051 * @}
1052 */
1053
1054 /* Peripheral Control functions ************************************************/
1055 /** @addtogroup HAL_SDMMC_LL_Group3
1056 * @{
1057 */
1058 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
1059 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
1060 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
1061
1062 /* Command path state machine (CPSM) management functions */
1063 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command);
1064 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
1065 uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
1066
1067 /* Data path state machine (DPSM) management functions */
1068 HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data);
1069 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
1070 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
1071
1072 /* SDMMC Cards mode management functions */
1073 HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
1074
1075 /* SDMMC Commands management functions */
1076 uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
1077 uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
1078 uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
1079 uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
1080 uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
1081 uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
1082 uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
1083 uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
1084 uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
1085 uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
1086 uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
1087 uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
1088 uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
1089 uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType);
1090 uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
1091 uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
1092 uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
1093 uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
1094 uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA);
1095 uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
1096 uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
1097
1098 uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
1099 uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
1100 uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
1101 uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
1102
1103 /**
1104 * @}
1105 */
1106
1107 /**
1108 * @}
1109 */
1110
1111 /**
1112 * @}
1113 */
1114
1115 /**
1116 * @}
1117 */
1118
1119 #ifdef __cplusplus
1120 }
1121 #endif
1122
1123 #endif /* STM32F103xE || STM32F103xG */
1124
1125 #endif /* __stm32f1xx_LL_SD_H */
1126
1127 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/