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Increment eeprom version
[betaflight.git] / lib / main / STM32F1 / Drivers / STM32F1xx_HAL_Driver / Inc / stm32f1xx_ll_spi.h
blob689d12f518d414aa437bfec27a101a04d3c07d61
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_spi.h
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 12-May-2017
7 * @brief Header file of SPI LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F1xx_LL_SPI_H
40 #define __STM32F1xx_LL_SPI_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f1xx.h"
48
49 /** @addtogroup STM32F1xx_LL_Driver
50 * @{
51 */
52
53 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
54
55 /** @defgroup SPI_LL SPI
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /* Private macros ------------------------------------------------------------*/
62
63 /* Exported types ------------------------------------------------------------*/
64 #if defined(USE_FULL_LL_DRIVER)
65 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
66 * @{
67 */
68
69 /**
70 * @brief SPI Init structures definition
71 */
72 typedef struct
73 {
74 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
75 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
76
77 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
78
79 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
80 This parameter can be a value of @ref SPI_LL_EC_MODE.
81
82 This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
83
84 uint32_t DataWidth; /*!< Specifies the SPI data width.
85 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
86
87 This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
88
89 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
90 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
91
92 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
93
94 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
95 This parameter can be a value of @ref SPI_LL_EC_PHASE.
96
97 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
98
99 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
100 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
101
102 This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
103
104 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
105 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
106 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
107
108 This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
109
110 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
111 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
112
113 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
114
115 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
116 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
117
118 This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
119
120 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
121 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
122
123 This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
124
125 } LL_SPI_InitTypeDef;
126
127 /**
128 * @}
129 */
130 #endif /* USE_FULL_LL_DRIVER */
131
132 /* Exported constants --------------------------------------------------------*/
133 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
134 * @{
135 */
136
137 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
138 * @brief Flags defines which can be used with LL_SPI_ReadReg function
139 * @{
140 */
141 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
142 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
143 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
144 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
145 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
146 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
147 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
148 /**
149 * @}
150 */
151
152 /** @defgroup SPI_LL_EC_IT IT Defines
153 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
154 * @{
155 */
156 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
157 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
158 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
159 /**
160 * @}
161 */
162
163 /** @defgroup SPI_LL_EC_MODE Operation Mode
164 * @{
165 */
166 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
167 #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
168 /**
169 * @}
170 */
171
172
173 /** @defgroup SPI_LL_EC_PHASE Clock Phase
174 * @{
175 */
176 #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
177 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
178 /**
179 * @}
180 */
181
182 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
183 * @{
184 */
185 #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
186 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
187 /**
188 * @}
189 */
190
191 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
192 * @{
193 */
194 #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
195 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
196 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
197 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
198 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
199 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
200 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
201 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
202 /**
203 * @}
204 */
205
206 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
207 * @{
208 */
209 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
210 #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
211 /**
212 * @}
213 */
214
215 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
216 * @{
217 */
218 #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
219 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
220 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
221 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
222 /**
223 * @}
224 */
225
226 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
227 * @{
228 */
229 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
230 #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
231 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
232 /**
233 * @}
234 */
235
236 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
237 * @{
238 */
239 #define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
240 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
241 /**
242 * @}
243 */
244 #if defined(USE_FULL_LL_DRIVER)
245
246 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
247 * @{
248 */
249 #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
250 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
251 /**
252 * @}
253 */
254 #endif /* USE_FULL_LL_DRIVER */
255
256 /**
257 * @}
258 */
259
260 /* Exported macro ------------------------------------------------------------*/
261 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
262 * @{
263 */
264
265 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
266 * @{
267 */
268
269 /**
270 * @brief Write a value in SPI register
271 * @param __INSTANCE__ SPI Instance
272 * @param __REG__ Register to be written
273 * @param __VALUE__ Value to be written in the register
274 * @retval None
275 */
276 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
277
278 /**
279 * @brief Read a value in SPI register
280 * @param __INSTANCE__ SPI Instance
281 * @param __REG__ Register to be read
282 * @retval Register value
283 */
284 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
285 /**
286 * @}
287 */
288
289 /**
290 * @}
291 */
292
293 /* Exported functions --------------------------------------------------------*/
294 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
295 * @{
296 */
297
298 /** @defgroup SPI_LL_EF_Configuration Configuration
299 * @{
300 */
301
302 /**
303 * @brief Enable SPI peripheral
304 * @rmtoll CR1 SPE LL_SPI_Enable
305 * @param SPIx SPI Instance
306 * @retval None
307 */
308 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
309 {
310 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
311 }
312
313 /**
314 * @brief Disable SPI peripheral
315 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
316 * @rmtoll CR1 SPE LL_SPI_Disable
317 * @param SPIx SPI Instance
318 * @retval None
319 */
320 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
321 {
322 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
323 }
324
325 /**
326 * @brief Check if SPI peripheral is enabled
327 * @rmtoll CR1 SPE LL_SPI_IsEnabled
328 * @param SPIx SPI Instance
329 * @retval State of bit (1 or 0).
330 */
331 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
332 {
333 return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
334 }
335
336 /**
337 * @brief Set SPI operation mode to Master or Slave
338 * @note This bit should not be changed when communication is ongoing.
339 * @rmtoll CR1 MSTR LL_SPI_SetMode\n
340 * CR1 SSI LL_SPI_SetMode
341 * @param SPIx SPI Instance
342 * @param Mode This parameter can be one of the following values:
343 * @arg @ref LL_SPI_MODE_MASTER
344 * @arg @ref LL_SPI_MODE_SLAVE
345 * @retval None
346 */
347 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
348 {
349 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
350 }
351
352 /**
353 * @brief Get SPI operation mode (Master or Slave)
354 * @rmtoll CR1 MSTR LL_SPI_GetMode\n
355 * CR1 SSI LL_SPI_GetMode
356 * @param SPIx SPI Instance
357 * @retval Returned value can be one of the following values:
358 * @arg @ref LL_SPI_MODE_MASTER
359 * @arg @ref LL_SPI_MODE_SLAVE
360 */
361 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
362 {
363 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
364 }
365
366
367 /**
368 * @brief Set clock phase
369 * @note This bit should not be changed when communication is ongoing.
370 * This bit is not used in SPI TI mode.
371 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
372 * @param SPIx SPI Instance
373 * @param ClockPhase This parameter can be one of the following values:
374 * @arg @ref LL_SPI_PHASE_1EDGE
375 * @arg @ref LL_SPI_PHASE_2EDGE
376 * @retval None
377 */
378 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
379 {
380 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
381 }
382
383 /**
384 * @brief Get clock phase
385 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
386 * @param SPIx SPI Instance
387 * @retval Returned value can be one of the following values:
388 * @arg @ref LL_SPI_PHASE_1EDGE
389 * @arg @ref LL_SPI_PHASE_2EDGE
390 */
391 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
392 {
393 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
394 }
395
396 /**
397 * @brief Set clock polarity
398 * @note This bit should not be changed when communication is ongoing.
399 * This bit is not used in SPI TI mode.
400 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
401 * @param SPIx SPI Instance
402 * @param ClockPolarity This parameter can be one of the following values:
403 * @arg @ref LL_SPI_POLARITY_LOW
404 * @arg @ref LL_SPI_POLARITY_HIGH
405 * @retval None
406 */
407 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
408 {
409 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
410 }
411
412 /**
413 * @brief Get clock polarity
414 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
415 * @param SPIx SPI Instance
416 * @retval Returned value can be one of the following values:
417 * @arg @ref LL_SPI_POLARITY_LOW
418 * @arg @ref LL_SPI_POLARITY_HIGH
419 */
420 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
421 {
422 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
423 }
424
425 /**
426 * @brief Set baud rate prescaler
427 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
428 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
429 * @param SPIx SPI Instance
430 * @param BaudRate This parameter can be one of the following values:
431 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
432 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
433 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
434 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
435 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
436 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
437 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
438 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
439 * @retval None
440 */
441 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
442 {
443 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
444 }
445
446 /**
447 * @brief Get baud rate prescaler
448 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
449 * @param SPIx SPI Instance
450 * @retval Returned value can be one of the following values:
451 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
452 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
453 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
454 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
455 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
456 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
457 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
458 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
459 */
460 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
461 {
462 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
463 }
464
465 /**
466 * @brief Set transfer bit order
467 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
468 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
469 * @param SPIx SPI Instance
470 * @param BitOrder This parameter can be one of the following values:
471 * @arg @ref LL_SPI_LSB_FIRST
472 * @arg @ref LL_SPI_MSB_FIRST
473 * @retval None
474 */
475 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
476 {
477 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
478 }
479
480 /**
481 * @brief Get transfer bit order
482 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
483 * @param SPIx SPI Instance
484 * @retval Returned value can be one of the following values:
485 * @arg @ref LL_SPI_LSB_FIRST
486 * @arg @ref LL_SPI_MSB_FIRST
487 */
488 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
489 {
490 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
491 }
492
493 /**
494 * @brief Set transfer direction mode
495 * @note For Half-Duplex mode, Rx Direction is set by default.
496 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
497 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
498 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
499 * CR1 BIDIOE LL_SPI_SetTransferDirection
500 * @param SPIx SPI Instance
501 * @param TransferDirection This parameter can be one of the following values:
502 * @arg @ref LL_SPI_FULL_DUPLEX
503 * @arg @ref LL_SPI_SIMPLEX_RX
504 * @arg @ref LL_SPI_HALF_DUPLEX_RX
505 * @arg @ref LL_SPI_HALF_DUPLEX_TX
506 * @retval None
507 */
508 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
509 {
510 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
511 }
512
513 /**
514 * @brief Get transfer direction mode
515 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
516 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
517 * CR1 BIDIOE LL_SPI_GetTransferDirection
518 * @param SPIx SPI Instance
519 * @retval Returned value can be one of the following values:
520 * @arg @ref LL_SPI_FULL_DUPLEX
521 * @arg @ref LL_SPI_SIMPLEX_RX
522 * @arg @ref LL_SPI_HALF_DUPLEX_RX
523 * @arg @ref LL_SPI_HALF_DUPLEX_TX
524 */
525 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
526 {
527 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
528 }
529
530 /**
531 * @brief Set frame data width
532 * @rmtoll CR1 DFF LL_SPI_SetDataWidth
533 * @param SPIx SPI Instance
534 * @param DataWidth This parameter can be one of the following values:
535 * @arg @ref LL_SPI_DATAWIDTH_8BIT
536 * @arg @ref LL_SPI_DATAWIDTH_16BIT
537 * @retval None
538 */
539 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
540 {
541 MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
542 }
543
544 /**
545 * @brief Get frame data width
546 * @rmtoll CR1 DFF LL_SPI_GetDataWidth
547 * @param SPIx SPI Instance
548 * @retval Returned value can be one of the following values:
549 * @arg @ref LL_SPI_DATAWIDTH_8BIT
550 * @arg @ref LL_SPI_DATAWIDTH_16BIT
551 */
552 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
553 {
554 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
555 }
556
557 /**
558 * @}
559 */
560
561 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
562 * @{
563 */
564
565 /**
566 * @brief Enable CRC
567 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
568 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
569 * @param SPIx SPI Instance
570 * @retval None
571 */
572 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
573 {
574 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
575 }
576
577 /**
578 * @brief Disable CRC
579 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
580 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
581 * @param SPIx SPI Instance
582 * @retval None
583 */
584 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
585 {
586 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
587 }
588
589 /**
590 * @brief Check if CRC is enabled
591 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
592 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
593 * @param SPIx SPI Instance
594 * @retval State of bit (1 or 0).
595 */
596 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
597 {
598 return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
599 }
600
601 /**
602 * @brief Set CRCNext to transfer CRC on the line
603 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
604 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
605 * @param SPIx SPI Instance
606 * @retval None
607 */
608 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
609 {
610 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
611 }
612
613 /**
614 * @brief Set polynomial for CRC calculation
615 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
616 * @param SPIx SPI Instance
617 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
618 * @retval None
619 */
620 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
621 {
622 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
623 }
624
625 /**
626 * @brief Get polynomial for CRC calculation
627 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
628 * @param SPIx SPI Instance
629 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
630 */
631 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
632 {
633 return (uint32_t)(READ_REG(SPIx->CRCPR));
634 }
635
636 /**
637 * @brief Get Rx CRC
638 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
639 * @param SPIx SPI Instance
640 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
641 */
642 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
643 {
644 return (uint32_t)(READ_REG(SPIx->RXCRCR));
645 }
646
647 /**
648 * @brief Get Tx CRC
649 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
650 * @param SPIx SPI Instance
651 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
652 */
653 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
654 {
655 return (uint32_t)(READ_REG(SPIx->TXCRCR));
656 }
657
658 /**
659 * @}
660 */
661
662 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
663 * @{
664 */
665
666 /**
667 * @brief Set NSS mode
668 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
669 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
670 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
671 * @param SPIx SPI Instance
672 * @param NSS This parameter can be one of the following values:
673 * @arg @ref LL_SPI_NSS_SOFT
674 * @arg @ref LL_SPI_NSS_HARD_INPUT
675 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
676 * @retval None
677 */
678 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
679 {
680 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
681 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
682 }
683
684 /**
685 * @brief Get NSS mode
686 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
687 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
688 * @param SPIx SPI Instance
689 * @retval Returned value can be one of the following values:
690 * @arg @ref LL_SPI_NSS_SOFT
691 * @arg @ref LL_SPI_NSS_HARD_INPUT
692 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
693 */
694 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
695 {
696 register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
697 register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
698 return (Ssm | Ssoe);
699 }
700
701 /**
702 * @}
703 */
704
705 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
706 * @{
707 */
708
709 /**
710 * @brief Check if Rx buffer is not empty
711 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
712 * @param SPIx SPI Instance
713 * @retval State of bit (1 or 0).
714 */
715 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
716 {
717 return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
718 }
719
720 /**
721 * @brief Check if Tx buffer is empty
722 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
723 * @param SPIx SPI Instance
724 * @retval State of bit (1 or 0).
725 */
726 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
727 {
728 return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
729 }
730
731 /**
732 * @brief Get CRC error flag
733 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
734 * @param SPIx SPI Instance
735 * @retval State of bit (1 or 0).
736 */
737 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
738 {
739 return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
740 }
741
742 /**
743 * @brief Get mode fault error flag
744 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
745 * @param SPIx SPI Instance
746 * @retval State of bit (1 or 0).
747 */
748 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
749 {
750 return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
751 }
752
753 /**
754 * @brief Get overrun error flag
755 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
756 * @param SPIx SPI Instance
757 * @retval State of bit (1 or 0).
758 */
759 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
760 {
761 return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
762 }
763
764 /**
765 * @brief Get busy flag
766 * @note The BSY flag is cleared under any one of the following conditions:
767 * -When the SPI is correctly disabled
768 * -When a fault is detected in Master mode (MODF bit set to 1)
769 * -In Master mode, when it finishes a data transmission and no new data is ready to be
770 * sent
771 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
772 * each data transfer.
773 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
774 * @param SPIx SPI Instance
775 * @retval State of bit (1 or 0).
776 */
777 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
778 {
779 return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
780 }
781
782
783 /**
784 * @brief Clear CRC error flag
785 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
786 * @param SPIx SPI Instance
787 * @retval None
788 */
789 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
790 {
791 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
792 }
793
794 /**
795 * @brief Clear mode fault error flag
796 * @note Clearing this flag is done by a read access to the SPIx_SR
797 * register followed by a write access to the SPIx_CR1 register
798 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
799 * @param SPIx SPI Instance
800 * @retval None
801 */
802 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
803 {
804 __IO uint32_t tmpreg;
805 tmpreg = SPIx->SR;
806 (void) tmpreg;
807 tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
808 (void) tmpreg;
809 }
810
811 /**
812 * @brief Clear overrun error flag
813 * @note Clearing this flag is done by a read access to the SPIx_DR
814 * register followed by a read access to the SPIx_SR register
815 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
816 * @param SPIx SPI Instance
817 * @retval None
818 */
819 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
820 {
821 __IO uint32_t tmpreg;
822 tmpreg = SPIx->DR;
823 (void) tmpreg;
824 tmpreg = SPIx->SR;
825 (void) tmpreg;
826 }
827
828
829 /**
830 * @}
831 */
832
833 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
834 * @{
835 */
836
837 /**
838 * @brief Enable error interrupt
839 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
840 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
841 * @param SPIx SPI Instance
842 * @retval None
843 */
844 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
845 {
846 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
847 }
848
849 /**
850 * @brief Enable Rx buffer not empty interrupt
851 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
852 * @param SPIx SPI Instance
853 * @retval None
854 */
855 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
856 {
857 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
858 }
859
860 /**
861 * @brief Enable Tx buffer empty interrupt
862 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
863 * @param SPIx SPI Instance
864 * @retval None
865 */
866 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
867 {
868 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
869 }
870
871 /**
872 * @brief Disable error interrupt
873 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
874 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
875 * @param SPIx SPI Instance
876 * @retval None
877 */
878 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
879 {
880 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
881 }
882
883 /**
884 * @brief Disable Rx buffer not empty interrupt
885 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
886 * @param SPIx SPI Instance
887 * @retval None
888 */
889 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
890 {
891 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
892 }
893
894 /**
895 * @brief Disable Tx buffer empty interrupt
896 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
897 * @param SPIx SPI Instance
898 * @retval None
899 */
900 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
901 {
902 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
903 }
904
905 /**
906 * @brief Check if error interrupt is enabled
907 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
908 * @param SPIx SPI Instance
909 * @retval State of bit (1 or 0).
910 */
911 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
912 {
913 return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
914 }
915
916 /**
917 * @brief Check if Rx buffer not empty interrupt is enabled
918 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
919 * @param SPIx SPI Instance
920 * @retval State of bit (1 or 0).
921 */
922 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
923 {
924 return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
925 }
926
927 /**
928 * @brief Check if Tx buffer empty interrupt
929 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
930 * @param SPIx SPI Instance
931 * @retval State of bit (1 or 0).
932 */
933 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
934 {
935 return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
936 }
937
938 /**
939 * @}
940 */
941
942 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
943 * @{
944 */
945
946 /**
947 * @brief Enable DMA Rx
948 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
949 * @param SPIx SPI Instance
950 * @retval None
951 */
952 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
953 {
954 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
955 }
956
957 /**
958 * @brief Disable DMA Rx
959 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
960 * @param SPIx SPI Instance
961 * @retval None
962 */
963 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
964 {
965 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
966 }
967
968 /**
969 * @brief Check if DMA Rx is enabled
970 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
971 * @param SPIx SPI Instance
972 * @retval State of bit (1 or 0).
973 */
974 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
975 {
976 return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
977 }
978
979 /**
980 * @brief Enable DMA Tx
981 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
982 * @param SPIx SPI Instance
983 * @retval None
984 */
985 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
986 {
987 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
988 }
989
990 /**
991 * @brief Disable DMA Tx
992 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
993 * @param SPIx SPI Instance
994 * @retval None
995 */
996 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
997 {
998 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
999 }
1000
1001 /**
1002 * @brief Check if DMA Tx is enabled
1003 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
1004 * @param SPIx SPI Instance
1005 * @retval State of bit (1 or 0).
1006 */
1007 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
1008 {
1009 return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
1010 }
1011
1012 /**
1013 * @brief Get the data register address used for DMA transfer
1014 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
1015 * @param SPIx SPI Instance
1016 * @retval Address of data register
1017 */
1018 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
1019 {
1020 return (uint32_t) & (SPIx->DR);
1021 }
1022
1023 /**
1024 * @}
1025 */
1026
1027 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
1028 * @{
1029 */
1030
1031 /**
1032 * @brief Read 8-Bits in the data register
1033 * @rmtoll DR DR LL_SPI_ReceiveData8
1034 * @param SPIx SPI Instance
1035 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
1036 */
1037 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
1038 {
1039 return (uint8_t)(READ_REG(SPIx->DR));
1040 }
1041
1042 /**
1043 * @brief Read 16-Bits in the data register
1044 * @rmtoll DR DR LL_SPI_ReceiveData16
1045 * @param SPIx SPI Instance
1046 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1047 */
1048 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
1049 {
1050 return (uint16_t)(READ_REG(SPIx->DR));
1051 }
1052
1053 /**
1054 * @brief Write 8-Bits in the data register
1055 * @rmtoll DR DR LL_SPI_TransmitData8
1056 * @param SPIx SPI Instance
1057 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
1058 * @retval None
1059 */
1060 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
1061 {
1062 SPIx->DR = TxData;
1063 }
1064
1065 /**
1066 * @brief Write 16-Bits in the data register
1067 * @rmtoll DR DR LL_SPI_TransmitData16
1068 * @param SPIx SPI Instance
1069 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1070 * @retval None
1071 */
1072 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1073 {
1074 SPIx->DR = TxData;
1075 }
1076
1077 /**
1078 * @}
1079 */
1080 #if defined(USE_FULL_LL_DRIVER)
1081 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
1082 * @{
1083 */
1084
1085 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
1086 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
1087 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
1088
1089 /**
1090 * @}
1091 */
1092 #endif /* USE_FULL_LL_DRIVER */
1093 /**
1094 * @}
1095 */
1096
1097 /**
1098 * @}
1099 */
1100
1101 #if defined(SPI_I2S_SUPPORT)
1102 /** @defgroup I2S_LL I2S
1103 * @{
1104 */
1105
1106 /* Private variables ---------------------------------------------------------*/
1107 /* Private constants ---------------------------------------------------------*/
1108 /* Private macros ------------------------------------------------------------*/
1109
1110 /* Exported types ------------------------------------------------------------*/
1111 #if defined(USE_FULL_LL_DRIVER)
1112 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
1113 * @{
1114 */
1115
1116 /**
1117 * @brief I2S Init structure definition
1118 */
1119
1120 typedef struct
1121 {
1122 uint32_t Mode; /*!< Specifies the I2S operating mode.
1123 This parameter can be a value of @ref I2S_LL_EC_MODE
1124
1125 This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
1126
1127 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
1128 This parameter can be a value of @ref I2S_LL_EC_STANDARD
1129
1130 This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
1131
1132
1133 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
1134 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
1135
1136 This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
1137
1138
1139 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
1140 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
1141
1142 This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
1143
1144
1145 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
1146 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
1147
1148 Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
1149 and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
1150
1151
1152 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
1153 This parameter can be a value of @ref I2S_LL_EC_POLARITY
1154
1155 This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
1156
1157 } LL_I2S_InitTypeDef;
1158
1159 /**
1160 * @}
1161 */
1162 #endif /*USE_FULL_LL_DRIVER*/
1163
1164 /* Exported constants --------------------------------------------------------*/
1165 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
1166 * @{
1167 */
1168
1169 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
1170 * @brief Flags defines which can be used with LL_I2S_ReadReg function
1171 * @{
1172 */
1173 #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
1174 #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
1175 #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
1176 #define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
1177 #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
1178 #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
1179 /**
1180 * @}
1181 */
1182
1183 /** @defgroup SPI_LL_EC_IT IT Defines
1184 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
1185 * @{
1186 */
1187 #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
1188 #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
1189 #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
1190 /**
1191 * @}
1192 */
1193
1194 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
1195 * @{
1196 */
1197 #define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
1198 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
1199 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
1200 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
1201 /**
1202 * @}
1203 */
1204
1205 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
1206 * @{
1207 */
1208 #define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
1209 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
1210 /**
1211 * @}
1212 */
1213
1214 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
1215 * @{
1216 */
1217 #define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
1218 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
1219 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
1220 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
1221 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
1222 /**
1223 * @}
1224 */
1225
1226 /** @defgroup I2S_LL_EC_MODE Operation Mode
1227 * @{
1228 */
1229 #define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
1230 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
1231 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
1232 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
1233 /**
1234 * @}
1235 */
1236
1237 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
1238 * @{
1239 */
1240 #define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
1241 #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
1242 /**
1243 * @}
1244 */
1245
1246 #if defined(USE_FULL_LL_DRIVER)
1247
1248 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
1249 * @{
1250 */
1251 #define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
1252 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
1253 /**
1254 * @}
1255 */
1256
1257 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
1258 * @{
1259 */
1260
1261 #define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
1262 #define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
1263 #define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
1264 #define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
1265 #define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
1266 #define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
1267 #define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
1268 #define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
1269 #define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
1270 #define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
1271 /**
1272 * @}
1273 */
1274 #endif /* USE_FULL_LL_DRIVER */
1275
1276 /**
1277 * @}
1278 */
1279
1280 /* Exported macro ------------------------------------------------------------*/
1281 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
1282 * @{
1283 */
1284
1285 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
1286 * @{
1287 */
1288
1289 /**
1290 * @brief Write a value in I2S register
1291 * @param __INSTANCE__ I2S Instance
1292 * @param __REG__ Register to be written
1293 * @param __VALUE__ Value to be written in the register
1294 * @retval None
1295 */
1296 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1297
1298 /**
1299 * @brief Read a value in I2S register
1300 * @param __INSTANCE__ I2S Instance
1301 * @param __REG__ Register to be read
1302 * @retval Register value
1303 */
1304 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1305 /**
1306 * @}
1307 */
1308
1309 /**
1310 * @}
1311 */
1312
1313
1314 /* Exported functions --------------------------------------------------------*/
1315
1316 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
1317 * @{
1318 */
1319
1320 /** @defgroup I2S_LL_EF_Configuration Configuration
1321 * @{
1322 */
1323
1324 /**
1325 * @brief Select I2S mode and Enable I2S peripheral
1326 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
1327 * I2SCFGR I2SE LL_I2S_Enable
1328 * @param SPIx SPI Instance
1329 * @retval None
1330 */
1331 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
1332 {
1333 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1334 }
1335
1336 /**
1337 * @brief Disable I2S peripheral
1338 * @rmtoll I2SCFGR I2SE LL_I2S_Disable
1339 * @param SPIx SPI Instance
1340 * @retval None
1341 */
1342 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
1343 {
1344 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1345 }
1346
1347 /**
1348 * @brief Check if I2S peripheral is enabled
1349 * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
1350 * @param SPIx SPI Instance
1351 * @retval State of bit (1 or 0).
1352 */
1353 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
1354 {
1355 return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
1356 }
1357
1358 /**
1359 * @brief Set I2S data frame length
1360 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
1361 * I2SCFGR CHLEN LL_I2S_SetDataFormat
1362 * @param SPIx SPI Instance
1363 * @param DataFormat This parameter can be one of the following values:
1364 * @arg @ref LL_I2S_DATAFORMAT_16B
1365 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1366 * @arg @ref LL_I2S_DATAFORMAT_24B
1367 * @arg @ref LL_I2S_DATAFORMAT_32B
1368 * @retval None
1369 */
1370 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
1371 {
1372 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
1373 }
1374
1375 /**
1376 * @brief Get I2S data frame length
1377 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
1378 * I2SCFGR CHLEN LL_I2S_GetDataFormat
1379 * @param SPIx SPI Instance
1380 * @retval Returned value can be one of the following values:
1381 * @arg @ref LL_I2S_DATAFORMAT_16B
1382 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1383 * @arg @ref LL_I2S_DATAFORMAT_24B
1384 * @arg @ref LL_I2S_DATAFORMAT_32B
1385 */
1386 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
1387 {
1388 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
1389 }
1390
1391 /**
1392 * @brief Set I2S clock polarity
1393 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
1394 * @param SPIx SPI Instance
1395 * @param ClockPolarity This parameter can be one of the following values:
1396 * @arg @ref LL_I2S_POLARITY_LOW
1397 * @arg @ref LL_I2S_POLARITY_HIGH
1398 * @retval None
1399 */
1400 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1401 {
1402 SET_BIT(SPIx->I2SCFGR, ClockPolarity);
1403 }
1404
1405 /**
1406 * @brief Get I2S clock polarity
1407 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
1408 * @param SPIx SPI Instance
1409 * @retval Returned value can be one of the following values:
1410 * @arg @ref LL_I2S_POLARITY_LOW
1411 * @arg @ref LL_I2S_POLARITY_HIGH
1412 */
1413 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
1414 {
1415 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
1416 }
1417
1418 /**
1419 * @brief Set I2S standard protocol
1420 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
1421 * I2SCFGR PCMSYNC LL_I2S_SetStandard
1422 * @param SPIx SPI Instance
1423 * @param Standard This parameter can be one of the following values:
1424 * @arg @ref LL_I2S_STANDARD_PHILIPS
1425 * @arg @ref LL_I2S_STANDARD_MSB
1426 * @arg @ref LL_I2S_STANDARD_LSB
1427 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1428 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1429 * @retval None
1430 */
1431 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1432 {
1433 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
1434 }
1435
1436 /**
1437 * @brief Get I2S standard protocol
1438 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
1439 * I2SCFGR PCMSYNC LL_I2S_GetStandard
1440 * @param SPIx SPI Instance
1441 * @retval Returned value can be one of the following values:
1442 * @arg @ref LL_I2S_STANDARD_PHILIPS
1443 * @arg @ref LL_I2S_STANDARD_MSB
1444 * @arg @ref LL_I2S_STANDARD_LSB
1445 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1446 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1447 */
1448 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
1449 {
1450 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
1451 }
1452
1453 /**
1454 * @brief Set I2S transfer mode
1455 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
1456 * @param SPIx SPI Instance
1457 * @param Mode This parameter can be one of the following values:
1458 * @arg @ref LL_I2S_MODE_SLAVE_TX
1459 * @arg @ref LL_I2S_MODE_SLAVE_RX
1460 * @arg @ref LL_I2S_MODE_MASTER_TX
1461 * @arg @ref LL_I2S_MODE_MASTER_RX
1462 * @retval None
1463 */
1464 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
1465 {
1466 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
1467 }
1468
1469 /**
1470 * @brief Get I2S transfer mode
1471 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
1472 * @param SPIx SPI Instance
1473 * @retval Returned value can be one of the following values:
1474 * @arg @ref LL_I2S_MODE_SLAVE_TX
1475 * @arg @ref LL_I2S_MODE_SLAVE_RX
1476 * @arg @ref LL_I2S_MODE_MASTER_TX
1477 * @arg @ref LL_I2S_MODE_MASTER_RX
1478 */
1479 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
1480 {
1481 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
1482 }
1483
1484 /**
1485 * @brief Set I2S linear prescaler
1486 * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
1487 * @param SPIx SPI Instance
1488 * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1489 * @retval None
1490 */
1491 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
1492 {
1493 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
1494 }
1495
1496 /**
1497 * @brief Get I2S linear prescaler
1498 * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
1499 * @param SPIx SPI Instance
1500 * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1501 */
1502 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
1503 {
1504 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
1505 }
1506
1507 /**
1508 * @brief Set I2S parity prescaler
1509 * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
1510 * @param SPIx SPI Instance
1511 * @param PrescalerParity This parameter can be one of the following values:
1512 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1513 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1514 * @retval None
1515 */
1516 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
1517 {
1518 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
1519 }
1520
1521 /**
1522 * @brief Get I2S parity prescaler
1523 * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
1524 * @param SPIx SPI Instance
1525 * @retval Returned value can be one of the following values:
1526 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1527 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1528 */
1529 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
1530 {
1531 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
1532 }
1533
1534 /**
1535 * @brief Enable the master clock ouput (Pin MCK)
1536 * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
1537 * @param SPIx SPI Instance
1538 * @retval None
1539 */
1540 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
1541 {
1542 SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1543 }
1544
1545 /**
1546 * @brief Disable the master clock ouput (Pin MCK)
1547 * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
1548 * @param SPIx SPI Instance
1549 * @retval None
1550 */
1551 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
1552 {
1553 CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1554 }
1555
1556 /**
1557 * @brief Check if the master clock ouput (Pin MCK) is enabled
1558 * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
1559 * @param SPIx SPI Instance
1560 * @retval State of bit (1 or 0).
1561 */
1562 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
1563 {
1564 return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
1565 }
1566
1567 /**
1568 * @}
1569 */
1570
1571 /** @defgroup I2S_LL_EF_FLAG FLAG Management
1572 * @{
1573 */
1574
1575 /**
1576 * @brief Check if Rx buffer is not empty
1577 * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
1578 * @param SPIx SPI Instance
1579 * @retval State of bit (1 or 0).
1580 */
1581 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
1582 {
1583 return LL_SPI_IsActiveFlag_RXNE(SPIx);
1584 }
1585
1586 /**
1587 * @brief Check if Tx buffer is empty
1588 * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
1589 * @param SPIx SPI Instance
1590 * @retval State of bit (1 or 0).
1591 */
1592 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
1593 {
1594 return LL_SPI_IsActiveFlag_TXE(SPIx);
1595 }
1596
1597 /**
1598 * @brief Get busy flag
1599 * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
1600 * @param SPIx SPI Instance
1601 * @retval State of bit (1 or 0).
1602 */
1603 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
1604 {
1605 return LL_SPI_IsActiveFlag_BSY(SPIx);
1606 }
1607
1608 /**
1609 * @brief Get overrun error flag
1610 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
1611 * @param SPIx SPI Instance
1612 * @retval State of bit (1 or 0).
1613 */
1614 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
1615 {
1616 return LL_SPI_IsActiveFlag_OVR(SPIx);
1617 }
1618
1619 /**
1620 * @brief Get underrun error flag
1621 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
1622 * @param SPIx SPI Instance
1623 * @retval State of bit (1 or 0).
1624 */
1625 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
1626 {
1627 return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
1628 }
1629
1630 /**
1631 * @brief Get channel side flag.
1632 * @note 0: Channel Left has to be transmitted or has been received\n
1633 * 1: Channel Right has to be transmitted or has been received\n
1634 * It has no significance in PCM mode.
1635 * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
1636 * @param SPIx SPI Instance
1637 * @retval State of bit (1 or 0).
1638 */
1639 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
1640 {
1641 return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
1642 }
1643
1644 /**
1645 * @brief Clear overrun error flag
1646 * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
1647 * @param SPIx SPI Instance
1648 * @retval None
1649 */
1650 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
1651 {
1652 LL_SPI_ClearFlag_OVR(SPIx);
1653 }
1654
1655 /**
1656 * @brief Clear underrun error flag
1657 * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
1658 * @param SPIx SPI Instance
1659 * @retval None
1660 */
1661 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
1662 {
1663 __IO uint32_t tmpreg;
1664 tmpreg = SPIx->SR;
1665 (void)tmpreg;
1666 }
1667
1668 /**
1669 * @}
1670 */
1671
1672 /** @defgroup I2S_LL_EF_IT Interrupt Management
1673 * @{
1674 */
1675
1676 /**
1677 * @brief Enable error IT
1678 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
1679 * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
1680 * @param SPIx SPI Instance
1681 * @retval None
1682 */
1683 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
1684 {
1685 LL_SPI_EnableIT_ERR(SPIx);
1686 }
1687
1688 /**
1689 * @brief Enable Rx buffer not empty IT
1690 * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
1691 * @param SPIx SPI Instance
1692 * @retval None
1693 */
1694 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
1695 {
1696 LL_SPI_EnableIT_RXNE(SPIx);
1697 }
1698
1699 /**
1700 * @brief Enable Tx buffer empty IT
1701 * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
1702 * @param SPIx SPI Instance
1703 * @retval None
1704 */
1705 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
1706 {
1707 LL_SPI_EnableIT_TXE(SPIx);
1708 }
1709
1710 /**
1711 * @brief Disable error IT
1712 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
1713 * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
1714 * @param SPIx SPI Instance
1715 * @retval None
1716 */
1717 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
1718 {
1719 LL_SPI_DisableIT_ERR(SPIx);
1720 }
1721
1722 /**
1723 * @brief Disable Rx buffer not empty IT
1724 * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
1725 * @param SPIx SPI Instance
1726 * @retval None
1727 */
1728 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
1729 {
1730 LL_SPI_DisableIT_RXNE(SPIx);
1731 }
1732
1733 /**
1734 * @brief Disable Tx buffer empty IT
1735 * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
1736 * @param SPIx SPI Instance
1737 * @retval None
1738 */
1739 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
1740 {
1741 LL_SPI_DisableIT_TXE(SPIx);
1742 }
1743
1744 /**
1745 * @brief Check if ERR IT is enabled
1746 * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
1747 * @param SPIx SPI Instance
1748 * @retval State of bit (1 or 0).
1749 */
1750 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
1751 {
1752 return LL_SPI_IsEnabledIT_ERR(SPIx);
1753 }
1754
1755 /**
1756 * @brief Check if RXNE IT is enabled
1757 * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
1758 * @param SPIx SPI Instance
1759 * @retval State of bit (1 or 0).
1760 */
1761 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
1762 {
1763 return LL_SPI_IsEnabledIT_RXNE(SPIx);
1764 }
1765
1766 /**
1767 * @brief Check if TXE IT is enabled
1768 * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
1769 * @param SPIx SPI Instance
1770 * @retval State of bit (1 or 0).
1771 */
1772 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
1773 {
1774 return LL_SPI_IsEnabledIT_TXE(SPIx);
1775 }
1776
1777 /**
1778 * @}
1779 */
1780
1781 /** @defgroup I2S_LL_EF_DMA DMA Management
1782 * @{
1783 */
1784
1785 /**
1786 * @brief Enable DMA Rx
1787 * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
1788 * @param SPIx SPI Instance
1789 * @retval None
1790 */
1791 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
1792 {
1793 LL_SPI_EnableDMAReq_RX(SPIx);
1794 }
1795
1796 /**
1797 * @brief Disable DMA Rx
1798 * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
1799 * @param SPIx SPI Instance
1800 * @retval None
1801 */
1802 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1803 {
1804 LL_SPI_DisableDMAReq_RX(SPIx);
1805 }
1806
1807 /**
1808 * @brief Check if DMA Rx is enabled
1809 * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
1810 * @param SPIx SPI Instance
1811 * @retval State of bit (1 or 0).
1812 */
1813 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
1814 {
1815 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
1816 }
1817
1818 /**
1819 * @brief Enable DMA Tx
1820 * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
1821 * @param SPIx SPI Instance
1822 * @retval None
1823 */
1824 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1825 {
1826 LL_SPI_EnableDMAReq_TX(SPIx);
1827 }
1828
1829 /**
1830 * @brief Disable DMA Tx
1831 * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
1832 * @param SPIx SPI Instance
1833 * @retval None
1834 */
1835 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1836 {
1837 LL_SPI_DisableDMAReq_TX(SPIx);
1838 }
1839
1840 /**
1841 * @brief Check if DMA Tx is enabled
1842 * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
1843 * @param SPIx SPI Instance
1844 * @retval State of bit (1 or 0).
1845 */
1846 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
1847 {
1848 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
1849 }
1850
1851 /**
1852 * @}
1853 */
1854
1855 /** @defgroup I2S_LL_EF_DATA DATA Management
1856 * @{
1857 */
1858
1859 /**
1860 * @brief Read 16-Bits in data register
1861 * @rmtoll DR DR LL_I2S_ReceiveData16
1862 * @param SPIx SPI Instance
1863 * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
1864 */
1865 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
1866 {
1867 return LL_SPI_ReceiveData16(SPIx);
1868 }
1869
1870 /**
1871 * @brief Write 16-Bits in data register
1872 * @rmtoll DR DR LL_I2S_TransmitData16
1873 * @param SPIx SPI Instance
1874 * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
1875 * @retval None
1876 */
1877 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1878 {
1879 LL_SPI_TransmitData16(SPIx, TxData);
1880 }
1881
1882 /**
1883 * @}
1884 */
1885
1886 #if defined(USE_FULL_LL_DRIVER)
1887 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
1888 * @{
1889 */
1890
1891 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
1892 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
1893 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
1894 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
1895
1896 /**
1897 * @}
1898 */
1899 #endif /* USE_FULL_LL_DRIVER */
1900
1901 /**
1902 * @}
1903 */
1904
1905 /**
1906 * @}
1907 */
1908 #endif /* SPI_I2S_SUPPORT */
1909
1910 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
1911
1912 /**
1913 * @}
1914 */
1915
1916 #ifdef __cplusplus
1917 }
1918 #endif
1919
1920 #endif /* __STM32F1xx_LL_SPI_H */
1921
1922 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/