lib/main/STM32F1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f1xx_ll_system.h
   4   * @author  MCD Application Team
   5   * @version V1.1.1
   6   * @date    12-May-2017
   7   * @brief   Header file of SYSTEM LL module.
   8   @verbatim
   9   ==============================================================================
  10                      ##### How to use this driver #####
  11   ==============================================================================
  12     [..]
  13     The LL SYSTEM driver contains a set of generic APIs that can be
  14     used by user:
  15       (+) Some of the FLASH features need to be handled in the SYSTEM file.
  16       (+) Access to DBGCMU registers
  17       (+) Access to SYSCFG registers
  18
  19   @endverbatim
  20   ******************************************************************************
  21   * @attention
  22   *
  23   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  24   *
  25   * Redistribution and use in source and binary forms, with or without modification,
  26   * are permitted provided that the following conditions are met:
  27   *   1. Redistributions of source code must retain the above copyright notice,
  28   *      this list of conditions and the following disclaimer.
  29   *   2. Redistributions in binary form must reproduce the above copyright notice,
  30   *      this list of conditions and the following disclaimer in the documentation
  31   *      and/or other materials provided with the distribution.
  32   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  33   *      may be used to endorse or promote products derived from this software
  34   *      without specific prior written permission.
  35   *
  36   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  37   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  38   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  39   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  40   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  41   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  42   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  43   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  44   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  45   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  46   *
  47   ******************************************************************************
  48   */
  49
  50 /* Define to prevent recursive inclusion -------------------------------------*/
  51 #ifndef __STM32F1xx_LL_SYSTEM_H
  52 #define __STM32F1xx_LL_SYSTEM_H
  53
  54 #ifdef __cplusplus
  55 extern "C" {
  56 #endif
  57
  58 /* Includes ------------------------------------------------------------------*/
  59 #include "stm32f1xx.h"
  60
  61 /** @addtogroup STM32F1xx_LL_Driver
  62   * @{
  63   */
  64
  65 #if defined (FLASH) || defined (DBGMCU)
  66
  67 /** @defgroup SYSTEM_LL SYSTEM
  68   * @{
  69   */
  70
  71 /* Private types -------------------------------------------------------------*/
  72 /* Private variables ---------------------------------------------------------*/
  73
  74 /* Private constants ---------------------------------------------------------*/
  75 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
  76   * @{
  77   */
  78
  79 /**
  80   * @}
  81   */
  82
  83 /* Private macros ------------------------------------------------------------*/
  84
  85 /* Exported types ------------------------------------------------------------*/
  86 /* Exported constants --------------------------------------------------------*/
  87 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
  88   * @{
  89   */
  90
  91
  92
  93 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
  94   * @{
  95   */
  96 #define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
  97 #define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
  98 #define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
  99 #define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
 100 #define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
 101 /**
 102   * @}
 103   */
 104
 105 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
 106   * @{
 107   */
 108 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_CR_DBG_TIM2_STOP          /*!< TIM2 counter stopped when core is halted */
 109 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_CR_DBG_TIM3_STOP          /*!< TIM3 counter stopped when core is halted */
 110 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_CR_DBG_TIM4_STOP          /*!< TIM4 counter stopped when core is halted */
 111 #if defined(DBGMCU_CR_DBG_TIM5_STOP)
 112 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_CR_DBG_TIM5_STOP          /*!< TIM5 counter stopped when core is halted */
 113 #endif /* DBGMCU_CR_DBG_TIM5_STOP */
 114 #if defined(DBGMCU_CR_DBG_TIM6_STOP)
 115 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_CR_DBG_TIM6_STOP          /*!< TIM6 counter stopped when core is halted */
 116 #endif /* DBGMCU_CR_DBG_TIM6_STOP */
 117 #if defined(DBGMCU_CR_DBG_TIM7_STOP)
 118 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_CR_DBG_TIM7_STOP          /*!< TIM7 counter stopped when core is halted */
 119 #endif /* DBGMCU_CR_DBG_TIM7_STOP */
 120 #if defined(DBGMCU_CR_DBG_TIM12_STOP)
 121 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_CR_DBG_TIM12_STOP         /*!< TIM12 counter stopped when core is halted */
 122 #endif /* DBGMCU_CR_DBG_TIM12_STOP */
 123 #if defined(DBGMCU_CR_DBG_TIM13_STOP)
 124 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_CR_DBG_TIM13_STOP         /*!< TIM13 counter stopped when core is halted */
 125 #endif /* DBGMCU_CR_DBG_TIM13_STOP */
 126 #if defined(DBGMCU_CR_DBG_TIM14_STOP)
 127 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_CR_DBG_TIM14_STOP         /*!< TIM14 counter stopped when core is halted */
 128 #endif /* DBGMCU_CR_DBG_TIM14_STOP */
 129 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_CR_DBG_WWDG_STOP          /*!< Debug Window Watchdog stopped when Core is halted */
 130 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_CR_DBG_IWDG_STOP          /*!< Debug Independent Watchdog stopped when Core is halted */
 131 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
 132 #if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
 133 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
 134 #endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */
 135 #if defined(DBGMCU_CR_DBG_CAN1_STOP)
 136 #define LL_DBGMCU_APB1_GRP1_CAN1_STOP      DBGMCU_CR_DBG_CAN1_STOP          /*!< CAN1 debug stopped when Core is halted  */
 137 #endif /* DBGMCU_CR_DBG_CAN1_STOP */
 138 #if defined(DBGMCU_CR_DBG_CAN2_STOP)
 139 #define LL_DBGMCU_APB1_GRP1_CAN2_STOP      DBGMCU_CR_DBG_CAN2_STOP          /*!< CAN2 debug stopped when Core is halted  */
 140 #endif /* DBGMCU_CR_DBG_CAN2_STOP */
 141 /**
 142   * @}
 143   */
 144
 145 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
 146   * @{
 147   */
 148 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_CR_DBG_TIM1_STOP   /*!< TIM1 counter stopped when core is halted */
 149 #if defined(DBGMCU_CR_DBG_TIM8_STOP)
 150 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_CR_DBG_TIM8_STOP   /*!< TIM8 counter stopped when core is halted */
 151 #endif /* DBGMCU_CR_DBG_CAN1_STOP */
 152 #if defined(DBGMCU_CR_DBG_TIM9_STOP)
 153 #define LL_DBGMCU_APB2_GRP1_TIM9_STOP      DBGMCU_CR_DBG_TIM9_STOP   /*!< TIM9 counter stopped when core is halted */
 154 #endif /* DBGMCU_CR_DBG_TIM9_STOP */
 155 #if defined(DBGMCU_CR_DBG_TIM10_STOP)
 156 #define LL_DBGMCU_APB2_GRP1_TIM10_STOP     DBGMCU_CR_DBG_TIM10_STOP   /*!< TIM10 counter stopped when core is halted */
 157 #endif /* DBGMCU_CR_DBG_TIM10_STOP */
 158 #if defined(DBGMCU_CR_DBG_TIM11_STOP)
 159 #define LL_DBGMCU_APB2_GRP1_TIM11_STOP     DBGMCU_CR_DBG_TIM11_STOP   /*!< TIM11 counter stopped when core is halted */
 160 #endif /* DBGMCU_CR_DBG_TIM11_STOP */
 161 #if defined(DBGMCU_CR_DBG_TIM15_STOP)
 162 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_CR_DBG_TIM15_STOP   /*!< TIM15 counter stopped when core is halted */
 163 #endif /* DBGMCU_CR_DBG_TIM15_STOP */
 164 #if defined(DBGMCU_CR_DBG_TIM16_STOP)
 165 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_CR_DBG_TIM16_STOP   /*!< TIM16 counter stopped when core is halted */
 166 #endif /* DBGMCU_CR_DBG_TIM16_STOP */
 167 #if defined(DBGMCU_CR_DBG_TIM17_STOP)
 168 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_CR_DBG_TIM17_STOP   /*!< TIM17 counter stopped when core is halted */
 169 #endif /* DBGMCU_CR_DBG_TIM17_STOP */
 170 /**
 171   * @}
 172   */
 173
 174 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
 175   * @{
 176   */
 177 #if defined(FLASH_ACR_LATENCY)
 178 #define LL_FLASH_LATENCY_0                 0x00000000U             /*!< FLASH Zero Latency cycle */
 179 #define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_0     /*!< FLASH One Latency cycle */
 180 #define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_1     /*!< FLASH Two wait states */
 181 #else
 182 #endif /* FLASH_ACR_LATENCY */
 183 /**
 184   * @}
 185   */
 186
 187 /**
 188   * @}
 189   */
 190
 191 /* Exported macro ------------------------------------------------------------*/
 192
 193 /* Exported functions --------------------------------------------------------*/
 194 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
 195   * @{
 196   */
 197
 198
 199
 200 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
 201   * @{
 202   */
 203
 204 /**
 205   * @brief  Return the device identifier
 206   * @note For Low Density devices, the device ID is 0x412
 207   * @note For Medium Density devices, the device ID is 0x410
 208   * @note For High Density devices, the device ID is 0x414
 209   * @note For XL Density devices, the device ID is 0x430
 210   * @note For Connectivity Line devices, the device ID is 0x418
 211   * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
 212   * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
 213   */
 214 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
 215 {
 216   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
 217 }
 218
 219 /**
 220   * @brief  Return the device revision identifier
 221   * @note This field indicates the revision of the device.
 222           For example, it is read as revA -> 0x1000,for Low Density devices
 223           For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices
 224           For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices
 225           For example, it is read as revA or 1 -> 0x1003,for XL Density devices
 226           For example, it is read as revA -> 0x1000, revZ -> 0x1001 for  Connectivity line devices
 227   * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
 228   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
 229   */
 230 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
 231 {
 232   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
 233 }
 234
 235 /**
 236   * @brief  Enable the Debug Module during SLEEP mode
 237   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
 238   * @retval None
 239   */
 240 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
 241 {
 242   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
 243 }
 244
 245 /**
 246   * @brief  Disable the Debug Module during SLEEP mode
 247   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
 248   * @retval None
 249   */
 250 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
 251 {
 252   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
 253 }
 254
 255 /**
 256   * @brief  Enable the Debug Module during STOP mode
 257   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
 258   * @retval None
 259   */
 260 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
 261 {
 262   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
 263 }
 264
 265 /**
 266   * @brief  Disable the Debug Module during STOP mode
 267   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
 268   * @retval None
 269   */
 270 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
 271 {
 272   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
 273 }
 274
 275 /**
 276   * @brief  Enable the Debug Module during STANDBY mode
 277   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
 278   * @retval None
 279   */
 280 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
 281 {
 282   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
 283 }
 284
 285 /**
 286   * @brief  Disable the Debug Module during STANDBY mode
 287   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
 288   * @retval None
 289   */
 290 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
 291 {
 292   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
 293 }
 294
 295 /**
 296   * @brief  Set Trace pin assignment control
 297   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\n
 298   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment
 299   * @param  PinAssignment This parameter can be one of the following values:
 300   *         @arg @ref LL_DBGMCU_TRACE_NONE
 301   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
 302   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
 303   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
 304   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
 305   * @retval None
 306   */
 307 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
 308 {
 309   MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
 310 }
 311
 312 /**
 313   * @brief  Get Trace pin assignment control
 314   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\n
 315   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment
 316   * @retval Returned value can be one of the following values:
 317   *         @arg @ref LL_DBGMCU_TRACE_NONE
 318   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
 319   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
 320   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
 321   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
 322   */
 323 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
 324 {
 325   return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
 326 }
 327
 328 /**
 329   * @brief  Freeze APB1 peripherals (group1 peripherals)
 330   * @rmtoll DBGMCU_CR_APB1      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
 331   *         DBGMCU_CR_APB1      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
 332   *         DBGMCU_CR_APB1      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
 333   *         DBGMCU_CR_APB1      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
 334   *         DBGMCU_CR_APB1      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
 335   *         DBGMCU_CR_APB1      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
 336   *         DBGMCU_CR_APB1      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
 337   *         DBGMCU_CR_APB1      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
 338   *         DBGMCU_CR_APB1      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
 339   *         DBGMCU_CR_APB1      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_FreezePeriph\n
 340   *         DBGMCU_CR_APB1      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
 341   *         DBGMCU_CR_APB1      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
 342   *         DBGMCU_CR_APB1      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
 343   *         DBGMCU_CR_APB1      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
 344   *         DBGMCU_CR_APB1      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
 345   *         DBGMCU_CR_APB1      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph
 346   * @param  Periphs This parameter can be a combination of the following values:
 347   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
 348   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
 349   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
 350   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
 351   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
 352   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
 353   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
 354   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
 355   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
 356   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
 357   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
 358   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
 359   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
 360   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
 361   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
 362   *
 363   *         (*) value not defined in all devices.
 364   * @retval None
 365   */
 366 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
 367 {
 368   SET_BIT(DBGMCU->CR, Periphs);
 369 }
 370
 371 /**
 372   * @brief  Unfreeze APB1 peripherals (group1 peripherals)
 373   * @rmtoll DBGMCU_CR_APB1      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
 374   *         DBGMCU_CR_APB1      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
 375   *         DBGMCU_CR_APB1      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
 376   *         DBGMCU_CR_APB1      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
 377   *         DBGMCU_CR_APB1      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
 378   *         DBGMCU_CR_APB1      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
 379   *         DBGMCU_CR_APB1      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
 380   *         DBGMCU_CR_APB1      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
 381   *         DBGMCU_CR_APB1      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
 382   *         DBGMCU_CR_APB1      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
 383   *         DBGMCU_CR_APB1      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
 384   *         DBGMCU_CR_APB1      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
 385   *         DBGMCU_CR_APB1      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
 386   *         DBGMCU_CR_APB1      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
 387   *         DBGMCU_CR_APB1      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
 388   *         DBGMCU_CR_APB1      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 389   * @param  Periphs This parameter can be a combination of the following values:
 390   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
 391   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
 392   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
 393   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
 394   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
 395   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
 396   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
 397   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
 398   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
 399   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
 400   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
 401   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
 402   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
 403   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
 404   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
 405   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
 406   *
 407   *         (*) value not defined in all devices.
 408   * @retval None
 409   */
 410 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
 411 {
 412   CLEAR_BIT(DBGMCU->CR, Periphs);
 413 }
 414
 415 /**
 416   * @brief  Freeze APB2 peripherals
 417   * @rmtoll DBGMCU_CR_APB2      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
 418   *         DBGMCU_CR_APB2      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
 419   *         DBGMCU_CR_APB2      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
 420   *         DBGMCU_CR_APB2      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
 421   *         DBGMCU_CR_APB2      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
 422   *         DBGMCU_CR_APB2      DBG_TIM15_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
 423   *         DBGMCU_CR_APB2      DBG_TIM16_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
 424   *         DBGMCU_CR_APB2      DBG_TIM17_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph
 425   * @param  Periphs This parameter can be a combination of the following values:
 426   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
 427   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
 428   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
 429   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
 430   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
 431   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
 432   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
 433   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
 434   *
 435   *         (*) value not defined in all devices.
 436   * @retval None
 437   */
 438 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
 439 {
 440   SET_BIT(DBGMCU->CR, Periphs);
 441 }
 442
 443 /**
 444   * @brief  Unfreeze APB2 peripherals
 445   * @rmtoll DBGMCU_CR_APB2      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
 446   *         DBGMCU_CR_APB2      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
 447   *         DBGMCU_CR_APB2      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
 448   *         DBGMCU_CR_APB2      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
 449   *         DBGMCU_CR_APB2      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
 450   *         DBGMCU_CR_APB2      DBG_TIM15_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
 451   *         DBGMCU_CR_APB2      DBG_TIM16_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
 452   *         DBGMCU_CR_APB2      DBG_TIM17_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph
 453   * @param  Periphs This parameter can be a combination of the following values:
 454   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
 455   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
 456   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
 457   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
 458   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
 459   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
 460   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
 461   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
 462   *
 463   *         (*) value not defined in all devices.
 464   * @retval None
 465   */
 466 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
 467 {
 468   CLEAR_BIT(DBGMCU->CR, Periphs);
 469 }
 470 /**
 471   * @}
 472   */
 473
 474 #if defined(FLASH_ACR_LATENCY)
 475 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
 476   * @{
 477   */
 478
 479 /**
 480   * @brief  Set FLASH Latency
 481   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
 482   * @param  Latency This parameter can be one of the following values:
 483   *         @arg @ref LL_FLASH_LATENCY_0
 484   *         @arg @ref LL_FLASH_LATENCY_1
 485   *         @arg @ref LL_FLASH_LATENCY_2
 486   * @retval None
 487   */
 488 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
 489 {
 490   MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
 491 }
 492
 493 /**
 494   * @brief  Get FLASH Latency
 495   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
 496   * @retval Returned value can be one of the following values:
 497   *         @arg @ref LL_FLASH_LATENCY_0
 498   *         @arg @ref LL_FLASH_LATENCY_1
 499   *         @arg @ref LL_FLASH_LATENCY_2
 500   */
 501 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
 502 {
 503   return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
 504 }
 505
 506 /**
 507   * @brief  Enable Prefetch
 508   * @rmtoll FLASH_ACR    PRFTBE        LL_FLASH_EnablePrefetch
 509   * @retval None
 510   */
 511 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
 512 {
 513   SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
 514 }
 515
 516 /**
 517   * @brief  Disable Prefetch
 518   * @rmtoll FLASH_ACR    PRFTBE        LL_FLASH_DisablePrefetch
 519   * @retval None
 520   */
 521 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
 522 {
 523   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
 524 }
 525
 526 /**
 527   * @brief  Check if Prefetch buffer is enabled
 528   * @rmtoll FLASH_ACR    PRFTBS        LL_FLASH_IsPrefetchEnabled
 529   * @retval State of bit (1 or 0).
 530   */
 531 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
 532 {
 533   return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
 534 }
 535
 536 #endif /* FLASH_ACR_LATENCY */
 537 /**
 538   * @brief  Enable Flash Half Cycle Access
 539   * @rmtoll FLASH_ACR    HLFCYA        LL_FLASH_EnableHalfCycleAccess
 540   * @retval None
 541   */
 542 __STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
 543 {
 544   SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
 545 }
 546
 547 /**
 548   * @brief  Disable Flash Half Cycle Access
 549   * @rmtoll FLASH_ACR    HLFCYA        LL_FLASH_DisableHalfCycleAccess
 550   * @retval None
 551   */
 552 __STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
 553 {
 554   CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
 555 }
 556
 557 /**
 558   * @brief  Check if  Flash Half Cycle Access is enabled or not
 559   * @rmtoll FLASH_ACR    HLFCYA        LL_FLASH_IsHalfCycleAccessEnabled
 560   * @retval State of bit (1 or 0).
 561   */
 562 __STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
 563 {
 564   return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
 565 }
 566
 567
 568 /**
 569   * @}
 570   */
 571
 572 /**
 573   * @}
 574   */
 575
 576 /**
 577   * @}
 578   */
 579
 580 #endif /* defined (FLASH) || defined (DBGMCU) */
 581
 582 /**
 583   * @}
 584   */
 585
 586 #ifdef __cplusplus
 587 }
 588 #endif
 589
 590 #endif /* __STM32F1xx_LL_SYSTEM_H */
 591
 592 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/