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[betaflight.git] / lib / main / STM32F1 / Drivers / STM32F1xx_HAL_Driver / Src / stm32f1xx_hal_can.c
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1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_can.c
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 12-May-2017
7 * @brief CAN HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Controller Area Network (CAN) peripheral:
10 * + Initialization and de-initialization functions
11 * + IO operation functions
12 * + Peripheral Control functions
13 * + Peripheral State and Error functions
15 @verbatim
16 ==============================================================================
17 ##### How to use this driver #####
18 ==============================================================================
19 [..]
20 (#) Enable the CAN controller interface clock using
21 __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
22 -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
24 (#) CAN pins configuration
25 (++) Enable the clock for the CAN GPIOs using the following function:
26 __HAL_RCC_GPIOx_CLK_ENABLE();
27 (++) Connect and configure the involved CAN pins using the
28 following function HAL_GPIO_Init();
30 (#) Initialize and configure the CAN using HAL_CAN_Init() function.
32 (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
34 (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
36 (#) Receive a CAN frame using HAL_CAN_Receive() function.
38 (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
40 *** Polling mode IO operation ***
41 =================================
42 [..]
43 (+) Start the CAN peripheral transmission and wait the end of this operation
44 using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
45 according to his end application
46 (+) Start the CAN peripheral reception and wait the end of this operation
47 using HAL_CAN_Receive(), at this stage user can specify the value of timeout
48 according to his end application
50 *** Interrupt mode IO operation ***
51 ===================================
52 [..]
53 (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
54 (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
55 (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
56 (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
57 add his own code by customization of function pointer HAL_CAN_TxCpltCallback
58 (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
59 add his own code by customization of function pointer HAL_CAN_ErrorCallback
61 *** CAN HAL driver macros list ***
62 =============================================
63 [..]
64 Below the list of most used macros in CAN HAL driver.
66 (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
67 (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
68 (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
69 (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
70 (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
72 [..]
73 (@) You can refer to the CAN HAL driver header file for more useful macros
75 @endverbatim
77 ******************************************************************************
78 * @attention
80 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
82 * Redistribution and use in source and binary forms, with or without modification,
83 * are permitted provided that the following conditions are met:
84 * 1. Redistributions of source code must retain the above copyright notice,
85 * this list of conditions and the following disclaimer.
86 * 2. Redistributions in binary form must reproduce the above copyright notice,
87 * this list of conditions and the following disclaimer in the documentation
88 * and/or other materials provided with the distribution.
89 * 3. Neither the name of STMicroelectronics nor the names of its contributors
90 * may be used to endorse or promote products derived from this software
91 * without specific prior written permission.
93 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
94 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
95 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
96 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
97 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
98 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
99 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
100 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
101 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
102 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
104 ******************************************************************************
107 /* Includes ------------------------------------------------------------------*/
108 #include "stm32f1xx_hal.h"
110 /** @addtogroup STM32F1xx_HAL_Driver
111 * @{
114 /** @defgroup CAN CAN
115 * @brief CAN driver modules
116 * @{
119 #ifdef HAL_CAN_MODULE_ENABLED
121 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
122 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
125 /* Private typedef -----------------------------------------------------------*/
126 /* Private define ------------------------------------------------------------*/
127 /** @defgroup CAN_Private_Constants CAN Private Constants
128 * @{
130 #define CAN_TIMEOUT_VALUE 10U
132 * @}
134 /* Private macro -------------------------------------------------------------*/
135 /* Private variables ---------------------------------------------------------*/
136 /* Private function prototypes -----------------------------------------------*/
137 /** @defgroup CAN_Private_Functions CAN Private Functions
138 * @{
140 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
141 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
143 * @}
146 /* Exported functions --------------------------------------------------------*/
147 /** @defgroup CAN_Exported_Functions CAN Exported Functions
148 * @{
151 /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
152 * @brief Initialization and Configuration functions
154 @verbatim
155 ==============================================================================
156 ##### Initialization and de-initialization functions #####
157 ==============================================================================
158 [..] This section provides functions allowing to:
159 (+) Initialize and configure the CAN.
160 (+) De-initialize the CAN.
162 @endverbatim
163 * @{
167 * @brief Initializes the CAN peripheral according to the specified
168 * parameters in the CAN_InitStruct.
169 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
170 * the configuration information for the specified CAN.
171 * @retval HAL status
173 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
175 uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
176 uint32_t tickstart = 0U;
177 uint32_t tmp_mcr = 0U;
179 /* Check CAN handle */
180 if(hcan == NULL)
182 return HAL_ERROR;
185 /* Check the parameters */
186 assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
187 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
188 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
189 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
190 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
191 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
192 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
193 assert_param(IS_CAN_MODE(hcan->Init.Mode));
194 assert_param(IS_CAN_SJW(hcan->Init.SJW));
195 assert_param(IS_CAN_BS1(hcan->Init.BS1));
196 assert_param(IS_CAN_BS2(hcan->Init.BS2));
197 assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
199 if(hcan->State == HAL_CAN_STATE_RESET)
201 /* Allocate lock resource and initialize it */
202 hcan->Lock = HAL_UNLOCKED;
203 /* Init the low level hardware */
204 HAL_CAN_MspInit(hcan);
207 /* Initialize the CAN state*/
208 hcan->State = HAL_CAN_STATE_BUSY;
210 /* Exit from sleep mode */
211 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
213 /* Request initialisation */
214 SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
216 /* Get timeout */
217 tickstart = HAL_GetTick();
219 /* Wait the acknowledge */
220 while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
222 if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
224 hcan->State= HAL_CAN_STATE_TIMEOUT;
225 /* Process unlocked */
226 __HAL_UNLOCK(hcan);
227 return HAL_TIMEOUT;
231 /* Check acknowledge */
232 if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
234 /* Set the time triggered communication mode */
235 if (hcan->Init.TTCM == ENABLE)
237 SET_BIT(tmp_mcr, CAN_MCR_TTCM);
239 else
241 CLEAR_BIT(tmp_mcr, CAN_MCR_TTCM);
244 /* Set the automatic bus-off management */
245 if (hcan->Init.ABOM == ENABLE)
247 SET_BIT(tmp_mcr, CAN_MCR_ABOM);
249 else
251 CLEAR_BIT(tmp_mcr, CAN_MCR_ABOM);
254 /* Set the automatic wake-up mode */
255 if (hcan->Init.AWUM == ENABLE)
257 SET_BIT(tmp_mcr, CAN_MCR_AWUM);
259 else
261 CLEAR_BIT(tmp_mcr, CAN_MCR_AWUM);
263 /* Set the no automatic retransmission */
264 if (hcan->Init.NART == ENABLE)
266 SET_BIT(tmp_mcr, CAN_MCR_NART);
268 else
270 CLEAR_BIT(tmp_mcr, CAN_MCR_NART);
273 /* Set the receive FIFO locked mode */
274 if (hcan->Init.RFLM == ENABLE)
276 SET_BIT(tmp_mcr, CAN_MCR_RFLM);
278 else
280 CLEAR_BIT(tmp_mcr, CAN_MCR_RFLM);
282 /* Set the transmit FIFO priority */
283 if (hcan->Init.TXFP == ENABLE)
285 SET_BIT(tmp_mcr, CAN_MCR_TXFP);
287 else
289 CLEAR_BIT(tmp_mcr, CAN_MCR_TXFP);
292 /* Update register MCR */
293 MODIFY_REG(hcan->Instance->MCR,
294 CAN_MCR_TTCM |
295 CAN_MCR_ABOM |
296 CAN_MCR_AWUM |
297 CAN_MCR_NART |
298 CAN_MCR_RFLM |
299 CAN_MCR_TXFP,
300 tmp_mcr);
302 /* Set the bit timing register */
303 WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
304 hcan->Init.SJW |
305 hcan->Init.BS1 |
306 hcan->Init.BS2 |
307 (hcan->Init.Prescaler - 1U)));
309 /* Request leave initialisation */
310 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
312 /* Get timeout */
313 tickstart = HAL_GetTick();
315 /* Wait the acknowledge */
316 while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
318 if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
320 hcan->State= HAL_CAN_STATE_TIMEOUT;
322 /* Process unlocked */
323 __HAL_UNLOCK(hcan);
325 return HAL_TIMEOUT;
329 /* Check acknowledged */
330 if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
332 status = CAN_INITSTATUS_SUCCESS;
336 if(status == CAN_INITSTATUS_SUCCESS)
338 /* Set CAN error code to none */
339 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
341 /* Initialize the CAN state */
342 hcan->State = HAL_CAN_STATE_READY;
344 /* Return function status */
345 return HAL_OK;
347 else
349 /* Initialize the CAN state */
350 hcan->State = HAL_CAN_STATE_ERROR;
352 /* Return function status */
353 return HAL_ERROR;
358 * @brief Configures the CAN reception filter according to the specified
359 * parameters in the CAN_FilterInitStruct.
360 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
361 * the configuration information for the specified CAN.
362 * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
363 * contains the filter configuration information.
364 * @retval None
366 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
368 uint32_t filternbrbitpos = 0U;
370 /* Prevent unused argument(s) compilation warning */
371 UNUSED(hcan);
373 /* Check the parameters */
374 assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
375 assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
376 assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
377 assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
378 assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
379 assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
381 filternbrbitpos = (1U) << sFilterConfig->FilterNumber;
383 /* Initialisation mode for the filter */
384 /* Select the start slave bank */
385 MODIFY_REG(hcan->Instance->FMR ,
386 CAN_FMR_CAN2SB ,
387 CAN_FMR_FINIT |
388 (uint32_t)(sFilterConfig->BankNumber << 8U) );
390 /* Filter Deactivation */
391 CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos);
393 /* Filter Scale */
394 if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
396 /* 16-bit scale for the filter */
397 CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos);
399 /* First 16-bit identifier and First 16-bit mask */
400 /* Or First 16-bit identifier and Second 16-bit identifier */
401 hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
402 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
403 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
405 /* Second 16-bit identifier and Second 16-bit mask */
406 /* Or Third 16-bit identifier and Fourth 16-bit identifier */
407 hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
408 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
409 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
412 if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
414 /* 32-bit scale for the filter */
415 SET_BIT(hcan->Instance->FS1R, filternbrbitpos);
416 /* 32-bit identifier or First 32-bit identifier */
417 hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
418 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
419 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
420 /* 32-bit mask or Second 32-bit identifier */
421 hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
422 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
423 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
426 /* Filter Mode */
427 if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
429 /*Id/Mask mode for the filter*/
430 CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos);
432 else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
434 /*Identifier list mode for the filter*/
435 SET_BIT(hcan->Instance->FM1R, filternbrbitpos);
438 /* Filter FIFO assignment */
439 if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
441 /* FIFO 0 assignation for the filter */
442 CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos);
444 else
446 /* FIFO 1 assignation for the filter */
447 SET_BIT(hcan->Instance->FFA1R, filternbrbitpos);
450 /* Filter activation */
451 if (sFilterConfig->FilterActivation == ENABLE)
453 SET_BIT(hcan->Instance->FA1R, filternbrbitpos);
456 /* Leave the initialisation mode for the filter */
457 CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT));
459 /* Return function status */
460 return HAL_OK;
464 * @brief Deinitializes the CANx peripheral registers to their default reset values.
465 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
466 * the configuration information for the specified CAN.
467 * @retval HAL status
469 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
471 /* Check CAN handle */
472 if(hcan == NULL)
474 return HAL_ERROR;
477 /* Check the parameters */
478 assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
480 /* Change CAN state */
481 hcan->State = HAL_CAN_STATE_BUSY;
483 /* DeInit the low level hardware */
484 HAL_CAN_MspDeInit(hcan);
486 /* Change CAN state */
487 hcan->State = HAL_CAN_STATE_RESET;
489 /* Release Lock */
490 __HAL_UNLOCK(hcan);
492 /* Return function status */
493 return HAL_OK;
497 * @brief Initializes the CAN MSP.
498 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
499 * the configuration information for the specified CAN.
500 * @retval None
502 __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
504 /* Prevent unused argument(s) compilation warning */
505 UNUSED(hcan);
506 /* NOTE : This function Should not be modified, when the callback is needed,
507 the HAL_CAN_MspInit can be implemented in the user file
512 * @brief DeInitializes the CAN MSP.
513 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
514 * the configuration information for the specified CAN.
515 * @retval None
517 __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
519 /* Prevent unused argument(s) compilation warning */
520 UNUSED(hcan);
521 /* NOTE : This function Should not be modified, when the callback is needed,
522 the HAL_CAN_MspDeInit can be implemented in the user file
527 * @}
530 /** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
531 * @brief I/O operation functions
533 @verbatim
534 ==============================================================================
535 ##### IO operation functions #####
536 ==============================================================================
537 [..] This section provides functions allowing to:
538 (+) Transmit a CAN frame message.
539 (+) Receive a CAN frame message.
540 (+) Enter CAN peripheral in sleep mode.
541 (+) Wake up the CAN peripheral from sleep mode.
543 @endverbatim
544 * @{
548 * @brief Initiates and transmits a CAN frame message.
549 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
550 * the configuration information for the specified CAN.
551 * @param Timeout: Specify Timeout value
552 * @retval HAL status
554 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
556 uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
557 uint32_t tickstart = 0U;
559 /* Check the parameters */
560 assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
561 assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
562 assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
564 if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
565 ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
566 ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
568 /* Process locked */
569 __HAL_LOCK(hcan);
571 /* Change CAN state */
572 switch(hcan->State)
574 case(HAL_CAN_STATE_BUSY_RX0):
575 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
576 break;
577 case(HAL_CAN_STATE_BUSY_RX1):
578 hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
579 break;
580 case(HAL_CAN_STATE_BUSY_RX0_RX1):
581 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
582 break;
583 default: /* HAL_CAN_STATE_READY */
584 hcan->State = HAL_CAN_STATE_BUSY_TX;
585 break;
588 /* Select one empty transmit mailbox */
589 if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
591 transmitmailbox = CAN_TXMAILBOX_0;
593 else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
595 transmitmailbox = CAN_TXMAILBOX_1;
597 else
599 transmitmailbox = CAN_TXMAILBOX_2;
602 /* Set up the Id */
603 hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
604 if (hcan->pTxMsg->IDE == CAN_ID_STD)
606 assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
607 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) |
608 hcan->pTxMsg->RTR);
610 else
612 assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
613 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) |
614 hcan->pTxMsg->IDE |
615 hcan->pTxMsg->RTR);
618 /* Set up the DLC */
619 hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
620 hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
621 hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
623 /* Set up the data field */
624 WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
625 ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
626 ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
627 ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
628 WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
629 ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
630 ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
631 ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
632 /* Request transmission */
633 SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
635 /* Get tick */
636 tickstart = HAL_GetTick();
638 /* Check End of transmission flag */
639 while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
641 /* Check for the Timeout */
642 if(Timeout != HAL_MAX_DELAY)
644 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
646 hcan->State = HAL_CAN_STATE_TIMEOUT;
648 /* Cancel transmission */
649 __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
651 /* Process unlocked */
652 __HAL_UNLOCK(hcan);
653 return HAL_TIMEOUT;
657 /* Change CAN state */
658 switch(hcan->State)
660 case(HAL_CAN_STATE_BUSY_TX_RX0):
661 hcan->State = HAL_CAN_STATE_BUSY_RX0;
662 break;
663 case(HAL_CAN_STATE_BUSY_TX_RX1):
664 hcan->State = HAL_CAN_STATE_BUSY_RX1;
665 break;
666 case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
667 hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
668 break;
669 default: /* HAL_CAN_STATE_BUSY_TX */
670 hcan->State = HAL_CAN_STATE_READY;
671 break;
674 /* Process unlocked */
675 __HAL_UNLOCK(hcan);
677 /* Return function status */
678 return HAL_OK;
680 else
682 /* Change CAN state */
683 hcan->State = HAL_CAN_STATE_ERROR;
685 /* Return function status */
686 return HAL_ERROR;
691 * @brief Initiates and transmits a CAN frame message.
692 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
693 * the configuration information for the specified CAN.
694 * @retval HAL status
696 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
698 uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
700 /* Check the parameters */
701 assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
702 assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
703 assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
705 if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
706 ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
707 ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
709 /* Process Locked */
710 __HAL_LOCK(hcan);
712 /* Select one empty transmit mailbox */
713 if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
715 transmitmailbox = CAN_TXMAILBOX_0;
717 else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
719 transmitmailbox = CAN_TXMAILBOX_1;
721 else
723 transmitmailbox = CAN_TXMAILBOX_2;
726 /* Set up the Id */
727 hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
728 if(hcan->pTxMsg->IDE == CAN_ID_STD)
730 assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
731 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
732 hcan->pTxMsg->RTR);
734 else
736 assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
737 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
738 hcan->pTxMsg->IDE |
739 hcan->pTxMsg->RTR);
742 /* Set up the DLC */
743 hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
744 hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
745 hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
747 /* Set up the data field */
748 WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3U] << CAN_TDL0R_DATA3_Pos) |
749 ((uint32_t)hcan->pTxMsg->Data[2U] << CAN_TDL0R_DATA2_Pos) |
750 ((uint32_t)hcan->pTxMsg->Data[1U] << CAN_TDL0R_DATA1_Pos) |
751 ((uint32_t)hcan->pTxMsg->Data[0U] << CAN_TDL0R_DATA0_Pos));
752 WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7U] << CAN_TDL0R_DATA3_Pos) |
753 ((uint32_t)hcan->pTxMsg->Data[6U] << CAN_TDL0R_DATA2_Pos) |
754 ((uint32_t)hcan->pTxMsg->Data[5U] << CAN_TDL0R_DATA1_Pos) |
755 ((uint32_t)hcan->pTxMsg->Data[4U] << CAN_TDL0R_DATA0_Pos));
757 /* Change CAN state */
758 switch(hcan->State)
760 case(HAL_CAN_STATE_BUSY_RX0):
761 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
762 break;
763 case(HAL_CAN_STATE_BUSY_RX1):
764 hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
765 break;
766 case(HAL_CAN_STATE_BUSY_RX0_RX1):
767 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
768 break;
769 default: /* HAL_CAN_STATE_READY */
770 hcan->State = HAL_CAN_STATE_BUSY_TX;
771 break;
774 /* Set CAN error code to none */
775 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
777 /* Process Unlocked */
778 __HAL_UNLOCK(hcan);
780 /* Request transmission */
781 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
783 /* Enable interrupts: */
784 /* - Enable Error warning Interrupt */
785 /* - Enable Error passive Interrupt */
786 /* - Enable Bus-off Interrupt */
787 /* - Enable Last error code Interrupt */
788 /* - Enable Error Interrupt */
789 /* - Enable Transmit mailbox empty Interrupt */
790 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
791 CAN_IT_EPV |
792 CAN_IT_BOF |
793 CAN_IT_LEC |
794 CAN_IT_ERR |
795 CAN_IT_TME );
797 else
799 /* Change CAN state */
800 hcan->State = HAL_CAN_STATE_ERROR;
802 /* Return function status */
803 return HAL_ERROR;
806 return HAL_OK;
810 * @brief Receives a correct CAN frame.
811 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
812 * the configuration information for the specified CAN.
813 * @param FIFONumber: FIFO Number value
814 * @param Timeout: Specify Timeout value
815 * @retval HAL status
817 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
819 uint32_t tickstart = 0U;
820 CanRxMsgTypeDef* pRxMsg = NULL;
822 /* Check the parameters */
823 assert_param(IS_CAN_FIFO(FIFONumber));
825 /* Check if CAN state is not busy for RX FIFO0 */
826 if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
827 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
828 (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
829 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
831 return HAL_BUSY;
834 /* Check if CAN state is not busy for RX FIFO1 */
835 if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
836 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
837 (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
838 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
840 return HAL_BUSY;
843 /* Process locked */
844 __HAL_LOCK(hcan);
846 /* Change CAN state */
847 if (FIFONumber == CAN_FIFO0)
849 switch(hcan->State)
851 case(HAL_CAN_STATE_BUSY_TX):
852 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
853 break;
854 case(HAL_CAN_STATE_BUSY_RX1):
855 hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
856 break;
857 case(HAL_CAN_STATE_BUSY_TX_RX1):
858 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
859 break;
860 default: /* HAL_CAN_STATE_READY */
861 hcan->State = HAL_CAN_STATE_BUSY_RX0;
862 break;
865 else /* FIFONumber == CAN_FIFO1 */
867 switch(hcan->State)
869 case(HAL_CAN_STATE_BUSY_TX):
870 hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
871 break;
872 case(HAL_CAN_STATE_BUSY_RX0):
873 hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
874 break;
875 case(HAL_CAN_STATE_BUSY_TX_RX0):
876 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
877 break;
878 default: /* HAL_CAN_STATE_READY */
879 hcan->State = HAL_CAN_STATE_BUSY_RX1;
880 break;
883 /* Get tick */
884 tickstart = HAL_GetTick();
886 /* Check pending message */
887 while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
889 /* Check for the Timeout */
890 if(Timeout != HAL_MAX_DELAY)
892 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
894 hcan->State = HAL_CAN_STATE_TIMEOUT;
895 /* Process unlocked */
896 __HAL_UNLOCK(hcan);
897 return HAL_TIMEOUT;
902 /* Set RxMsg pointer */
903 if(FIFONumber == CAN_FIFO0)
905 pRxMsg = hcan->pRxMsg;
907 else /* FIFONumber == CAN_FIFO1 */
909 pRxMsg = hcan->pRx1Msg;
912 /* Get the Id */
913 pRxMsg->IDE = (uint8_t)CAN_ID_EXT & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
914 if (pRxMsg->IDE == CAN_ID_STD)
916 pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
918 else
920 pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
923 pRxMsg->RTR = (uint8_t)CAN_RTR_REMOTE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
924 /* Get the DLC */
925 pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
926 /* Get the FMI */
927 pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
928 /* Get the FIFONumber */
929 pRxMsg->FIFONumber = FIFONumber;
930 /* Get the data field */
931 pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
932 pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
933 pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
934 pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
935 pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
936 pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
937 pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
938 pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
940 /* Release the FIFO */
941 if(FIFONumber == CAN_FIFO0)
943 /* Release FIFO0 */
944 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
946 else /* FIFONumber == CAN_FIFO1 */
948 /* Release FIFO1 */
949 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
952 /* Change CAN state */
953 if (FIFONumber == CAN_FIFO0)
955 switch(hcan->State)
957 case(HAL_CAN_STATE_BUSY_TX_RX0):
958 hcan->State = HAL_CAN_STATE_BUSY_TX;
959 break;
960 case(HAL_CAN_STATE_BUSY_RX0_RX1):
961 hcan->State = HAL_CAN_STATE_BUSY_RX1;
962 break;
963 case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
964 hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
965 break;
966 default: /* HAL_CAN_STATE_BUSY_RX0 */
967 hcan->State = HAL_CAN_STATE_READY;
968 break;
971 else /* FIFONumber == CAN_FIFO1 */
973 switch(hcan->State)
975 case(HAL_CAN_STATE_BUSY_TX_RX1):
976 hcan->State = HAL_CAN_STATE_BUSY_TX;
977 break;
978 case(HAL_CAN_STATE_BUSY_RX0_RX1):
979 hcan->State = HAL_CAN_STATE_BUSY_RX0;
980 break;
981 case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
982 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
983 break;
984 default: /* HAL_CAN_STATE_BUSY_RX1 */
985 hcan->State = HAL_CAN_STATE_READY;
986 break;
990 /* Process unlocked */
991 __HAL_UNLOCK(hcan);
993 /* Return function status */
994 return HAL_OK;
998 * @brief Receives a correct CAN frame.
999 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
1000 * the configuration information for the specified CAN.
1001 * @param FIFONumber: Specify the FIFO number
1002 * @retval HAL status
1004 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
1006 /* Check the parameters */
1007 assert_param(IS_CAN_FIFO(FIFONumber));
1009 /* Check if CAN state is not busy for RX FIFO0 */
1010 if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
1011 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
1012 (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
1013 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
1015 return HAL_BUSY;
1018 /* Check if CAN state is not busy for RX FIFO1 */
1019 if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
1020 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
1021 (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
1022 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
1024 return HAL_BUSY;
1027 /* Process locked */
1028 __HAL_LOCK(hcan);
1030 /* Change CAN state */
1031 if(FIFONumber == CAN_FIFO0)
1033 switch(hcan->State)
1035 case(HAL_CAN_STATE_BUSY_TX):
1036 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
1037 break;
1038 case(HAL_CAN_STATE_BUSY_RX1):
1039 hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
1040 break;
1041 case(HAL_CAN_STATE_BUSY_TX_RX1):
1042 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
1043 break;
1044 default: /* HAL_CAN_STATE_READY */
1045 hcan->State = HAL_CAN_STATE_BUSY_RX0;
1046 break;
1049 else /* FIFONumber == CAN_FIFO1 */
1051 switch(hcan->State)
1053 case(HAL_CAN_STATE_BUSY_TX):
1054 hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
1055 break;
1056 case(HAL_CAN_STATE_BUSY_RX0):
1057 hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
1058 break;
1059 case(HAL_CAN_STATE_BUSY_TX_RX0):
1060 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
1061 break;
1062 default: /* HAL_CAN_STATE_READY */
1063 hcan->State = HAL_CAN_STATE_BUSY_RX1;
1064 break;
1067 /* Set CAN error code to none */
1068 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
1071 /* Enable interrupts: */
1072 /* - Enable Error warning Interrupt */
1073 /* - Enable Error passive Interrupt */
1074 /* - Enable Bus-off Interrupt */
1075 /* - Enable Last error code Interrupt */
1076 /* - Enable Error Interrupt */
1077 /* - Enable Transmit mailbox empty Interrupt */
1078 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
1079 CAN_IT_EPV |
1080 CAN_IT_BOF |
1081 CAN_IT_LEC |
1082 CAN_IT_ERR |
1083 CAN_IT_TME );
1085 /* Process unlocked */
1086 __HAL_UNLOCK(hcan);
1088 if(FIFONumber == CAN_FIFO0)
1090 /* Enable FIFO 0 overrun and message pending Interrupt */
1091 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
1093 else
1095 /* Enable FIFO 1 overrun and message pending Interrupt */
1096 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
1099 /* Return function status */
1100 return HAL_OK;
1104 * @brief Enters the Sleep (low power) mode.
1105 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
1106 * the configuration information for the specified CAN.
1107 * @retval HAL status.
1109 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
1111 uint32_t tickstart = 0U;
1113 /* Process locked */
1114 __HAL_LOCK(hcan);
1116 /* Change CAN state */
1117 hcan->State = HAL_CAN_STATE_BUSY;
1119 /* Request Sleep mode */
1120 MODIFY_REG(hcan->Instance->MCR,
1121 CAN_MCR_INRQ ,
1122 CAN_MCR_SLEEP );
1124 /* Sleep mode status */
1125 if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
1126 HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
1128 /* Process unlocked */
1129 __HAL_UNLOCK(hcan);
1131 /* Return function status */
1132 return HAL_ERROR;
1135 /* Get tick */
1136 tickstart = HAL_GetTick();
1138 /* Wait the acknowledge */
1139 while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
1140 HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
1142 if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
1144 hcan->State = HAL_CAN_STATE_TIMEOUT;
1146 /* Process unlocked */
1147 __HAL_UNLOCK(hcan);
1149 return HAL_TIMEOUT;
1153 /* Change CAN state */
1154 hcan->State = HAL_CAN_STATE_READY;
1156 /* Process unlocked */
1157 __HAL_UNLOCK(hcan);
1159 /* Return function status */
1160 return HAL_OK;
1164 * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
1165 * is in the normal mode.
1166 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
1167 * the configuration information for the specified CAN.
1168 * @retval HAL status.
1170 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
1172 uint32_t tickstart = 0U;
1174 /* Process locked */
1175 __HAL_LOCK(hcan);
1177 /* Change CAN state */
1178 hcan->State = HAL_CAN_STATE_BUSY;
1180 /* Wake up request */
1181 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
1183 /* Get timeout */
1184 tickstart = HAL_GetTick();
1186 /* Sleep mode status */
1187 while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
1189 if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
1191 hcan->State= HAL_CAN_STATE_TIMEOUT;
1192 /* Process unlocked */
1193 __HAL_UNLOCK(hcan);
1194 return HAL_TIMEOUT;
1197 if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
1199 /* Process unlocked */
1200 __HAL_UNLOCK(hcan);
1202 /* Return function status */
1203 return HAL_ERROR;
1206 /* Change CAN state */
1207 hcan->State = HAL_CAN_STATE_READY;
1209 /* Process unlocked */
1210 __HAL_UNLOCK(hcan);
1212 /* Return function status */
1213 return HAL_OK;
1217 * @brief Handles CAN interrupt request
1218 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
1219 * the configuration information for the specified CAN.
1220 * @retval None
1222 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
1224 uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
1225 uint32_t errorcode = HAL_CAN_ERROR_NONE;
1227 /* Check Overrun flag for FIFO0 */
1228 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0);
1229 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0);
1230 if((tmp1 != 0U) && tmp2)
1232 /* Set CAN error code to FOV0 error */
1233 errorcode |= HAL_CAN_ERROR_FOV0;
1235 /* Clear FIFO0 Overrun Flag */
1236 __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
1239 /* Check Overrun flag for FIFO1 */
1240 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1);
1241 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1);
1242 if((tmp1 != 0U) && tmp2)
1244 /* Set CAN error code to FOV1 error */
1245 errorcode |= HAL_CAN_ERROR_FOV1;
1247 /* Clear FIFO1 Overrun Flag */
1248 __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
1251 /* Check End of transmission flag */
1252 if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
1254 /* Check Transmit request completion status */
1255 tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
1256 tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
1257 tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
1258 if(tmp1 || tmp2 || tmp3)
1260 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0);
1261 tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1);
1262 tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2);
1263 /* Check Transmit success */
1264 if((tmp1) || (tmp2) || (tmp3))
1266 /* Call transmit function */
1267 CAN_Transmit_IT(hcan);
1269 else /* Transmit failure */
1271 /* Set CAN error code to TXFAIL error */
1272 errorcode |= HAL_CAN_ERROR_TXFAIL;
1275 /* Clear transmission status flags (RQCPx and TXOKx) */
1276 SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
1277 CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
1281 tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
1282 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
1283 /* Check End of reception flag for FIFO0 */
1284 if((tmp1 != 0U) && tmp2)
1286 /* Call receive function */
1287 CAN_Receive_IT(hcan, CAN_FIFO0);
1290 tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
1291 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
1292 /* Check End of reception flag for FIFO1 */
1293 if((tmp1 != 0U) && tmp2)
1295 /* Call receive function */
1296 CAN_Receive_IT(hcan, CAN_FIFO1);
1299 /* Set error code in handle */
1300 hcan->ErrorCode |= errorcode;
1302 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
1303 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
1304 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
1305 /* Check Error Warning Flag */
1306 if(tmp1 && tmp2 && tmp3)
1308 /* Set CAN error code to EWG error */
1309 hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
1310 /* No need for clear of Error Warning Flag as read-only */
1313 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
1314 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
1315 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
1316 /* Check Error Passive Flag */
1317 if(tmp1 && tmp2 && tmp3)
1319 /* Set CAN error code to EPV error */
1320 hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
1321 /* No need for clear of Error Passive Flag as read-only */
1324 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
1325 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
1326 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
1327 /* Check Bus-Off Flag */
1328 if(tmp1 && tmp2 && tmp3)
1330 /* Set CAN error code to BOF error */
1331 hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
1332 /* No need for clear of Bus-Off Flag as read-only */
1335 tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
1336 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
1337 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
1338 /* Check Last error code Flag */
1339 if((!tmp1) && tmp2 && tmp3)
1341 tmp1 = (hcan->Instance->ESR & CAN_ESR_LEC);
1342 switch(tmp1)
1344 case(CAN_ESR_LEC_0):
1345 /* Set CAN error code to STF error */
1346 hcan->ErrorCode |= HAL_CAN_ERROR_STF;
1347 break;
1348 case(CAN_ESR_LEC_1):
1349 /* Set CAN error code to FOR error */
1350 hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
1351 break;
1352 case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
1353 /* Set CAN error code to ACK error */
1354 hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
1355 break;
1356 case(CAN_ESR_LEC_2):
1357 /* Set CAN error code to BR error */
1358 hcan->ErrorCode |= HAL_CAN_ERROR_BR;
1359 break;
1360 case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
1361 /* Set CAN error code to BD error */
1362 hcan->ErrorCode |= HAL_CAN_ERROR_BD;
1363 break;
1364 case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
1365 /* Set CAN error code to CRC error */
1366 hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
1367 break;
1368 default:
1369 break;
1372 /* Clear Last error code Flag */
1373 CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
1376 /* Call the Error call Back in case of Errors */
1377 if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
1379 /* Clear ERRI Flag */
1380 hcan->Instance->MSR = CAN_MSR_ERRI;
1381 /* Set the CAN state ready to be able to start again the process */
1382 hcan->State = HAL_CAN_STATE_READY;
1384 /* Disable interrupts: */
1385 /* - Disable Error warning Interrupt */
1386 /* - Disable Error passive Interrupt */
1387 /* - Disable Bus-off Interrupt */
1388 /* - Disable Last error code Interrupt */
1389 /* - Disable Error Interrupt */
1390 /* - Disable FIFO 0 message pending Interrupt */
1391 /* - Disable FIFO 0 Overrun Interrupt */
1392 /* - Disable FIFO 1 message pending Interrupt */
1393 /* - Disable FIFO 1 Overrun Interrupt */
1394 /* - Disable Transmit mailbox empty Interrupt */
1395 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
1396 CAN_IT_EPV |
1397 CAN_IT_BOF |
1398 CAN_IT_LEC |
1399 CAN_IT_ERR |
1400 CAN_IT_FMP0|
1401 CAN_IT_FOV0|
1402 CAN_IT_FMP1|
1403 CAN_IT_FOV1|
1404 CAN_IT_TME );
1406 /* Call Error callback function */
1407 HAL_CAN_ErrorCallback(hcan);
1412 * @brief Transmission complete callback in non blocking mode
1413 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
1414 * the configuration information for the specified CAN.
1415 * @retval None
1417 __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
1419 /* Prevent unused argument(s) compilation warning */
1420 UNUSED(hcan);
1421 /* NOTE : This function Should not be modified, when the callback is needed,
1422 the HAL_CAN_TxCpltCallback can be implemented in the user file
1427 * @brief Transmission complete callback in non blocking mode
1428 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
1429 * the configuration information for the specified CAN.
1430 * @retval None
1432 __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
1434 /* Prevent unused argument(s) compilation warning */
1435 UNUSED(hcan);
1436 /* NOTE : This function Should not be modified, when the callback is needed,
1437 the HAL_CAN_RxCpltCallback can be implemented in the user file
1442 * @brief Error CAN callback.
1443 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
1444 * the configuration information for the specified CAN.
1445 * @retval None
1447 __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
1449 /* Prevent unused argument(s) compilation warning */
1450 UNUSED(hcan);
1451 /* NOTE : This function Should not be modified, when the callback is needed,
1452 the HAL_CAN_ErrorCallback can be implemented in the user file
1457 * @}
1460 /** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
1461 * @brief CAN Peripheral State functions
1463 @verbatim
1464 ==============================================================================
1465 ##### Peripheral State and Error functions #####
1466 ==============================================================================
1467 [..]
1468 This subsection provides functions allowing to :
1469 (+) Check the CAN state.
1470 (+) Check CAN Errors detected during interrupt process
1472 @endverbatim
1473 * @{
1477 * @brief return the CAN state
1478 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
1479 * the configuration information for the specified CAN.
1480 * @retval HAL state
1482 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
1484 /* Return CAN state */
1485 return hcan->State;
1489 * @brief Return the CAN error code
1490 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
1491 * the configuration information for the specified CAN.
1492 * @retval CAN Error Code
1494 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
1496 return hcan->ErrorCode;
1500 * @}
1504 * @}
1507 /** @addtogroup CAN_Private_Functions
1508 * @{
1511 * @brief Initiates and transmits a CAN frame message.
1512 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
1513 * the configuration information for the specified CAN.
1514 * @retval HAL status
1516 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
1518 /* Disable Transmit mailbox empty Interrupt */
1519 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
1521 if(hcan->State == HAL_CAN_STATE_BUSY_TX)
1523 /* Disable interrupts: */
1524 /* - Disable Error warning Interrupt */
1525 /* - Disable Error passive Interrupt */
1526 /* - Disable Bus-off Interrupt */
1527 /* - Disable Last error code Interrupt */
1528 /* - Disable Error Interrupt */
1529 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
1530 CAN_IT_EPV |
1531 CAN_IT_BOF |
1532 CAN_IT_LEC |
1533 CAN_IT_ERR);
1536 /* Change CAN state */
1537 switch(hcan->State)
1539 case(HAL_CAN_STATE_BUSY_TX_RX0):
1540 hcan->State = HAL_CAN_STATE_BUSY_RX0;
1541 break;
1542 case(HAL_CAN_STATE_BUSY_TX_RX1):
1543 hcan->State = HAL_CAN_STATE_BUSY_RX1;
1544 break;
1545 case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
1546 hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
1547 break;
1548 default: /* HAL_CAN_STATE_BUSY_TX */
1549 hcan->State = HAL_CAN_STATE_READY;
1550 break;
1553 /* Transmission complete callback */
1554 HAL_CAN_TxCpltCallback(hcan);
1556 return HAL_OK;
1560 * @brief Receives a correct CAN frame.
1561 * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
1562 * the configuration information for the specified CAN.
1563 * @param FIFONumber: Specify the FIFO number
1564 * @retval HAL status
1565 * @retval None
1567 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
1569 uint32_t tmp1 = 0U;
1570 CanRxMsgTypeDef* pRxMsg = NULL;
1572 /* Set RxMsg pointer */
1573 if(FIFONumber == CAN_FIFO0)
1575 pRxMsg = hcan->pRxMsg;
1577 else /* FIFONumber == CAN_FIFO1 */
1579 pRxMsg = hcan->pRx1Msg;
1582 /* Get the Id */
1583 pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
1584 if (pRxMsg->IDE == CAN_ID_STD)
1586 pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
1588 else
1590 pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
1593 pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
1594 /* Get the DLC */
1595 pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
1596 /* Get the FIFONumber */
1597 pRxMsg->FIFONumber = FIFONumber;
1598 /* Get the FMI */
1599 pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
1600 /* Get the data field */
1601 pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
1602 pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
1603 pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
1604 pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
1605 pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
1606 pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
1607 pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
1608 pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
1609 /* Release the FIFO */
1610 /* Release FIFO0 */
1611 if (FIFONumber == CAN_FIFO0)
1613 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
1615 /* Disable FIFO 0 overrun and message pending Interrupt */
1616 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
1618 /* Release FIFO1 */
1619 else /* FIFONumber == CAN_FIFO1 */
1621 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
1623 /* Disable FIFO 1 overrun and message pending Interrupt */
1624 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
1627 tmp1 = hcan->State;
1628 if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1))
1630 /* Disable interrupts: */
1631 /* - Disable Error warning Interrupt */
1632 /* - Disable Error passive Interrupt */
1633 /* - Disable Bus-off Interrupt */
1634 /* - Disable Last error code Interrupt */
1635 /* - Disable Error Interrupt */
1636 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
1637 CAN_IT_EPV |
1638 CAN_IT_BOF |
1639 CAN_IT_LEC |
1640 CAN_IT_ERR);
1643 /* Change CAN state */
1644 if (FIFONumber == CAN_FIFO0)
1646 switch(hcan->State)
1648 case(HAL_CAN_STATE_BUSY_TX_RX0):
1649 hcan->State = HAL_CAN_STATE_BUSY_TX;
1650 break;
1651 case(HAL_CAN_STATE_BUSY_RX0_RX1):
1652 hcan->State = HAL_CAN_STATE_BUSY_RX1;
1653 break;
1654 case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
1655 hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
1656 break;
1657 default: /* HAL_CAN_STATE_BUSY_RX0 */
1658 hcan->State = HAL_CAN_STATE_READY;
1659 break;
1662 else /* FIFONumber == CAN_FIFO1 */
1664 switch(hcan->State)
1666 case(HAL_CAN_STATE_BUSY_TX_RX1):
1667 hcan->State = HAL_CAN_STATE_BUSY_TX;
1668 break;
1669 case(HAL_CAN_STATE_BUSY_RX0_RX1):
1670 hcan->State = HAL_CAN_STATE_BUSY_RX0;
1671 break;
1672 case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
1673 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
1674 break;
1675 default: /* HAL_CAN_STATE_BUSY_RX1 */
1676 hcan->State = HAL_CAN_STATE_READY;
1677 break;
1681 /* Receive complete callback */
1682 HAL_CAN_RxCpltCallback(hcan);
1684 /* Return function status */
1685 return HAL_OK;
1689 * @}
1691 #endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
1693 #endif /* HAL_CAN_MODULE_ENABLED */
1695 * @}
1699 * @}
1702 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/