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Increment eeprom version
[betaflight.git] / lib / main / STM32F1 / Drivers / STM32F1xx_HAL_Driver / Src / stm32f1xx_hal_spi.c
blob744e5f2415404a75d174ac067717fa9d8b345af6
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_spi.c
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 12-May-2017
7 * @brief SPI HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
10 * + Initialization and de-initialization functions
11 * + IO operation functions
12 * + Peripheral Control functions
13 * + Peripheral State functions
14 *
15 @verbatim
16 ==============================================================================
17 ##### How to use this driver #####
18 ==============================================================================
19 [..]
20 The SPI HAL driver can be used as follows:
21
22 (#) Declare a SPI_HandleTypeDef handle structure, for example:
23 SPI_HandleTypeDef hspi;
24
25 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
26 (##) Enable the SPIx interface clock
27 (##) SPI pins configuration
28 (+++) Enable the clock for the SPI GPIOs
29 (+++) Configure these SPI pins as alternate function push-pull
30 (##) NVIC configuration if you need to use interrupt process
31 (+++) Configure the SPIx interrupt priority
32 (+++) Enable the NVIC SPI IRQ handle
33 (##) DMA Configuration if you need to use DMA process
34 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
35 (+++) Enable the DMAx clock
36 (+++) Configure the DMA handle parameters
37 (+++) Configure the DMA Tx or Rx Channel
38 (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
39 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
40
41 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
42 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
43
44 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
45 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
46 by calling the customized HAL_SPI_MspInit() API.
47 [..]
48 Circular mode restriction:
49 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
50 (##) Master 2Lines RxOnly
51 (##) Master 1Line Rx
52 (#) The CRC feature is not managed when the DMA circular mode is enabled
53 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
54 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
55 [..]
56 Master Receive mode restriction:
57 (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
58 bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
59 does not initiate a new transfer the following procedure has to be respected:
60 (##) HAL_SPI_DeInit()
61 (##) HAL_SPI_Init()
62
63 @endverbatim
64
65 Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
66 the following tables resume the max SPI frequency reached with data size 8bits/16bits,
67 according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
68
69 DataSize = SPI_DATASIZE_8BIT:
70 +--------------------------------------------------------------------------------------------------+
71 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
72 | Process | Tranfert mode |-----------------------|-----------------------|-----------------------|
73 | | | Master | Slave | Master | Slave | Master | Slave |
74 |==================================================================================================|
75 | T | Polling | fPCLK/2 | fPCLK/16 | NA | NA | NA | NA |
76 | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
77 | / | Interrupt | fPCLK/8 | fPCLK/32 | NA | NA | NA | NA |
78 | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
79 | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA |
80 |=========|================|===========|===========|===========|===========|===========|===========|
81 | | Polling | fPCLK/4 | fPCLK/8 | fPCLK/8 | fPCLK/16 | fPCLK/64 | fPCLK/2 |
82 | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
83 | R | Interrupt | fPCLK/8 | fPCLK/16 | fPCLK/32 | fPCLK/16 | fPCLK/64 | fPCLK/4 |
84 | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
85 | | DMA | fPCLK/2 | fPCLK/16 | fPCLK/8 | fPCLK/16 | fPCLK/64 | fPCLK/2 |
86 |=========|================|===========|===========|===========|===========|===========|===========|
87 | | Polling | fPCLK/2 | fPCLK/2 | NA | NA | fPCLK/2 | fPCLK/32 |
88 | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
89 | T | Interrupt | fPCLK/8 | fPCLK/16 | NA | NA | fPCLK/2 | fPCLK/64 |
90 | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
91 | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/32 |
92 +--------------------------------------------------------------------------------------------------+
93
94 DataSize = SPI_DATASIZE_16BIT:
95 +--------------------------------------------------------------------------------------------------+
96 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
97 | Process | Tranfert mode |-----------------------|-----------------------|-----------------------|
98 | | | Master | Slave | Master | Slave | Master | Slave |
99 |==================================================================================================|
100 | T | Polling | fPCLK/4 | fPCLK/4 | NA | NA | NA | NA |
101 | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
102 | / | Interrupt | fPCLK/8 | fPCLK/16 | NA | NA | NA | NA |
103 | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
104 | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA |
105 |=========|================|===========|===========|===========|===========|===========|===========|
106 | | Polling | fPCLK/4 | fPCLK/8 | fPCLK/4 | fPCLK/8 | fPCLK/64 | fPCLK/2 |
107 | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
108 | R | Interrupt | fPCLK/8 | fPCLK/8 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/4 |
109 | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
110 | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/16 | fPCLK/64 | fPCLK/2 |
111 |=========|================|===========|===========|===========|===========|===========|===========|
112 | | Polling | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/4 | fPCLK/8 |
113 | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
114 | T | Interrupt | fPCLK/4 | fPCLK/8 | NA | NA | fPCLK/4 | fPCLK/4 |
115 | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
116 | | DMA | fPCLK/2 | fPCLK/2 | NA | NA | fPCLK/4 | fPCLK/8 |
117 +--------------------------------------------------------------------------------------------------+
118 [..]
119 (@) The max SPI frequency depend on SPI data size (8bits, 16bits),
120 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
121 (@)
122 (+@) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
123 (+@) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
124 (+@) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
125 ******************************************************************************
126 * @attention
127 *
128 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
129 *
130 * Redistribution and use in source and binary forms, with or without modification,
131 * are permitted provided that the following conditions are met:
132 * 1. Redistributions of source code must retain the above copyright notice,
133 * this list of conditions and the following disclaimer.
134 * 2. Redistributions in binary form must reproduce the above copyright notice,
135 * this list of conditions and the following disclaimer in the documentation
136 * and/or other materials provided with the distribution.
137 * 3. Neither the name of STMicroelectronics nor the names of its contributors
138 * may be used to endorse or promote products derived from this software
139 * without specific prior written permission.
140 *
141 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
142 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
143 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
144 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
145 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
146 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
147 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
148 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
149 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
150 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
151 *
152 ******************************************************************************
153 */
154
155 /* Includes ------------------------------------------------------------------*/
156 #include "stm32f1xx_hal.h"
157
158 /** @addtogroup STM32F1xx_HAL_Driver
159 * @{
160 */
161 /** @defgroup SPI SPI
162 * @brief SPI HAL module driver
163 * @{
164 */
165 #ifdef HAL_SPI_MODULE_ENABLED
166
167 /* Private typedef -----------------------------------------------------------*/
168 /* Private defines -----------------------------------------------------------*/
169 /** @defgroup SPI_Private_Constants SPI Private Constants
170 * @{
171 */
172 #define SPI_DEFAULT_TIMEOUT 100U
173 /**
174 * @}
175 */
176
177 /* Private macros ------------------------------------------------------------*/
178 /* Private variables ---------------------------------------------------------*/
179 /* Private function prototypes -----------------------------------------------*/
180 /** @addtogroup SPI_Private_Functions
181 * @{
182 */
183 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
184 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
185 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
186 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
187 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
188 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
189 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
190 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
191 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
192 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
193 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);
194 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
195 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
196 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
197 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
198 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
199 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
200 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
201 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
202 #if (USE_SPI_CRC != 0U)
203 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
204 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
205 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
206 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
207 #endif /* USE_SPI_CRC */
208 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
209 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
210 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
211 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
212 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
213 static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
214 /**
215 * @}
216 */
217
218 /* Exported functions --------------------------------------------------------*/
219 /** @defgroup SPI_Exported_Functions SPI Exported Functions
220 * @{
221 */
222
223 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
224 * @brief Initialization and Configuration functions
225 *
226 @verbatim
227 ===============================================================================
228 ##### Initialization and de-initialization functions #####
229 ===============================================================================
230 [..] This subsection provides a set of functions allowing to initialize and
231 de-initialize the SPIx peripheral:
232
233 (+) User must implement HAL_SPI_MspInit() function in which he configures
234 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
235
236 (+) Call the function HAL_SPI_Init() to configure the selected device with
237 the selected configuration:
238 (++) Mode
239 (++) Direction
240 (++) Data Size
241 (++) Clock Polarity and Phase
242 (++) NSS Management
243 (++) BaudRate Prescaler
244 (++) FirstBit
245 (++) TIMode
246 (++) CRC Calculation
247 (++) CRC Polynomial if CRC enabled
248
249 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
250 of the selected SPIx peripheral.
251
252 @endverbatim
253 * @{
254 */
255
256 /**
257 * @brief Initialize the SPI according to the specified parameters
258 * in the SPI_InitTypeDef and initialize the associated handle.
259 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
260 * the configuration information for SPI module.
261 * @retval HAL status
262 */
263 __weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
264 {
265 /* Check the SPI handle allocation */
266 if(hspi == NULL)
267 {
268 return HAL_ERROR;
269 }
270
271 /* Check the parameters */
272 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
273 assert_param(IS_SPI_MODE(hspi->Init.Mode));
274 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
275 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
276 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
277 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
278 assert_param(IS_SPI_NSS(hspi->Init.NSS));
279 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
280 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
281
282 #if (USE_SPI_CRC != 0U)
283 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
284 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
285 {
286 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
287 }
288 #else
289 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
290 #endif /* USE_SPI_CRC */
291
292 if(hspi->State == HAL_SPI_STATE_RESET)
293 {
294 /* Allocate lock resource and initialize it */
295 hspi->Lock = HAL_UNLOCKED;
296
297 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
298 HAL_SPI_MspInit(hspi);
299 }
300
301 hspi->State = HAL_SPI_STATE_BUSY;
302
303 /* Disable the selected SPI peripheral */
304 __HAL_SPI_DISABLE(hspi);
305
306 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
307 /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
308 Communication speed, First bit and CRC calculation state */
309 WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
310 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
311 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) );
312
313 /* Configure : NSS management */
314 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
315
316 #if (USE_SPI_CRC != 0U)
317 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
318 /* Configure : CRC Polynomial */
319 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
320 {
321 WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
322 }
323 #endif /* USE_SPI_CRC */
324
325 #if defined(SPI_I2SCFGR_I2SMOD)
326 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
327 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
328 #endif /* SPI_I2SCFGR_I2SMOD */
329
330 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
331 hspi->State = HAL_SPI_STATE_READY;
332
333 return HAL_OK;
334 }
335
336 /**
337 * @brief De Initialize the SPI peripheral.
338 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
339 * the configuration information for SPI module.
340 * @retval HAL status
341 */
342 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
343 {
344 /* Check the SPI handle allocation */
345 if(hspi == NULL)
346 {
347 return HAL_ERROR;
348 }
349
350 /* Check SPI Instance parameter */
351 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
352
353 hspi->State = HAL_SPI_STATE_BUSY;
354
355 /* Disable the SPI Peripheral Clock */
356 __HAL_SPI_DISABLE(hspi);
357
358 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
359 HAL_SPI_MspDeInit(hspi);
360
361 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
362 hspi->State = HAL_SPI_STATE_RESET;
363
364 /* Release Lock */
365 __HAL_UNLOCK(hspi);
366
367 return HAL_OK;
368 }
369
370 /**
371 * @brief Initialize the SPI MSP.
372 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
373 * the configuration information for SPI module.
374 * @retval None
375 */
376 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
377 {
378 /* Prevent unused argument(s) compilation warning */
379 UNUSED(hspi);
380 /* NOTE : This function should not be modified, when the callback is needed,
381 the HAL_SPI_MspInit should be implemented in the user file
382 */
383 }
384
385 /**
386 * @brief De-Initialize the SPI MSP.
387 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
388 * the configuration information for SPI module.
389 * @retval None
390 */
391 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
392 {
393 /* Prevent unused argument(s) compilation warning */
394 UNUSED(hspi);
395 /* NOTE : This function should not be modified, when the callback is needed,
396 the HAL_SPI_MspDeInit should be implemented in the user file
397 */
398 }
399
400 /**
401 * @}
402 */
403
404 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
405 * @brief Data transfers functions
406 *
407 @verbatim
408 ==============================================================================
409 ##### IO operation functions #####
410 ===============================================================================
411 [..]
412 This subsection provides a set of functions allowing to manage the SPI
413 data transfers.
414
415 [..] The SPI supports master and slave mode :
416
417 (#) There are two modes of transfer:
418 (++) Blocking mode: The communication is performed in polling mode.
419 The HAL status of all data processing is returned by the same function
420 after finishing transfer.
421 (++) No-Blocking mode: The communication is performed using Interrupts
422 or DMA, These APIs return the HAL status.
423 The end of the data processing will be indicated through the
424 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
425 using DMA mode.
426 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
427 will be executed respectively at the end of the transmit or Receive process
428 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
429
430 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
431 exist for 1Line (simplex) and 2Lines (full duplex) modes.
432
433 @endverbatim
434 * @{
435 */
436
437 /**
438 * @brief Transmit an amount of data in blocking mode.
439 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
440 * the configuration information for SPI module.
441 * @param pData: pointer to data buffer
442 * @param Size: amount of data to be sent
443 * @param Timeout: Timeout duration
444 * @retval HAL status
445 */
446 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
447 {
448 uint32_t tickstart = 0U;
449 HAL_StatusTypeDef errorcode = HAL_OK;
450
451 /* Check Direction parameter */
452 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
453
454 /* Process Locked */
455 __HAL_LOCK(hspi);
456
457 /* Init tickstart for timeout management*/
458 tickstart = HAL_GetTick();
459
460 if(hspi->State != HAL_SPI_STATE_READY)
461 {
462 errorcode = HAL_BUSY;
463 goto error;
464 }
465
466 if((pData == NULL ) || (Size == 0U))
467 {
468 errorcode = HAL_ERROR;
469 goto error;
470 }
471
472 /* Set the transaction information */
473 hspi->State = HAL_SPI_STATE_BUSY_TX;
474 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
475 hspi->pTxBuffPtr = (uint8_t *)pData;
476 hspi->TxXferSize = Size;
477 hspi->TxXferCount = Size;
478
479 /*Init field not used in handle to zero */
480 hspi->pRxBuffPtr = (uint8_t *)NULL;
481 hspi->RxXferSize = 0U;
482 hspi->RxXferCount = 0U;
483 hspi->TxISR = NULL;
484 hspi->RxISR = NULL;
485
486 /* Configure communication direction : 1Line */
487 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
488 {
489 SPI_1LINE_TX(hspi);
490 }
491
492 #if (USE_SPI_CRC != 0U)
493 /* Reset CRC Calculation */
494 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
495 {
496 SPI_RESET_CRC(hspi);
497 }
498 #endif /* USE_SPI_CRC */
499
500 /* Check if the SPI is already enabled */
501 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
502 {
503 /* Enable SPI peripheral */
504 __HAL_SPI_ENABLE(hspi);
505 }
506
507 /* Transmit data in 16 Bit mode */
508 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
509 {
510 if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
511 {
512 hspi->Instance->DR = *((uint16_t *)pData);
513 pData += sizeof(uint16_t);
514 hspi->TxXferCount--;
515 }
516 /* Transmit data in 16 Bit mode */
517 while (hspi->TxXferCount > 0U)
518 {
519 /* Wait until TXE flag is set to send data */
520 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
521 {
522 hspi->Instance->DR = *((uint16_t *)pData);
523 pData += sizeof(uint16_t);
524 hspi->TxXferCount--;
525 }
526 else
527 {
528 /* Timeout management */
529 if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
530 {
531 errorcode = HAL_TIMEOUT;
532 goto error;
533 }
534 }
535 }
536 }
537 /* Transmit data in 8 Bit mode */
538 else
539 {
540 if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01))
541 {
542 *((__IO uint8_t*)&hspi->Instance->DR) = (*pData);
543 pData += sizeof(uint8_t);
544 hspi->TxXferCount--;
545 }
546 while (hspi->TxXferCount > 0U)
547 {
548 /* Wait until TXE flag is set to send data */
549 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
550 {
551 *((__IO uint8_t*)&hspi->Instance->DR) = (*pData);
552 pData += sizeof(uint8_t);
553 hspi->TxXferCount--;
554 }
555 else
556 {
557 /* Timeout management */
558 if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
559 {
560 errorcode = HAL_TIMEOUT;
561 goto error;
562 }
563 }
564 }
565 }
566
567 /* Wait until TXE flag */
568 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK)
569 {
570 errorcode = HAL_TIMEOUT;
571 goto error;
572 }
573
574 /* Check Busy flag */
575 if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
576 {
577 errorcode = HAL_ERROR;
578 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
579 goto error;
580 }
581
582 /* Clear overrun flag in 2 Lines communication mode because received is not read */
583 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
584 {
585 __HAL_SPI_CLEAR_OVRFLAG(hspi);
586 }
587 #if (USE_SPI_CRC != 0U)
588 /* Enable CRC Transmission */
589 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
590 {
591 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
592 }
593 #endif /* USE_SPI_CRC */
594
595 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
596 {
597 errorcode = HAL_ERROR;
598 }
599
600 error:
601 hspi->State = HAL_SPI_STATE_READY;
602 /* Process Unlocked */
603 __HAL_UNLOCK(hspi);
604 return errorcode;
605 }
606
607 /**
608 * @brief Receive an amount of data in blocking mode.
609 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
610 * the configuration information for SPI module.
611 * @param pData: pointer to data buffer
612 * @param Size: amount of data to be received
613 * @param Timeout: Timeout duration
614 * @retval HAL status
615 */
616 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
617 {
618 #if (USE_SPI_CRC != 0U)
619 __IO uint16_t tmpreg = 0U;
620 #endif /* USE_SPI_CRC */
621 uint32_t tickstart = 0U;
622 HAL_StatusTypeDef errorcode = HAL_OK;
623
624 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
625 {
626 hspi->State = HAL_SPI_STATE_BUSY_RX;
627 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
628 return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
629 }
630
631 /* Process Locked */
632 __HAL_LOCK(hspi);
633
634 /* Init tickstart for timeout management*/
635 tickstart = HAL_GetTick();
636
637 if(hspi->State != HAL_SPI_STATE_READY)
638 {
639 errorcode = HAL_BUSY;
640 goto error;
641 }
642
643 if((pData == NULL ) || (Size == 0U))
644 {
645 errorcode = HAL_ERROR;
646 goto error;
647 }
648
649 /* Set the transaction information */
650 hspi->State = HAL_SPI_STATE_BUSY_RX;
651 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
652 hspi->pRxBuffPtr = (uint8_t *)pData;
653 hspi->RxXferSize = Size;
654 hspi->RxXferCount = Size;
655
656 /*Init field not used in handle to zero */
657 hspi->pTxBuffPtr = (uint8_t *)NULL;
658 hspi->TxXferSize = 0U;
659 hspi->TxXferCount = 0U;
660 hspi->RxISR = NULL;
661 hspi->TxISR = NULL;
662
663 #if (USE_SPI_CRC != 0U)
664 /* Reset CRC Calculation */
665 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
666 {
667 SPI_RESET_CRC(hspi);
668 /* this is done to handle the CRCNEXT before the latest data */
669 hspi->RxXferCount--;
670 }
671 #endif /* USE_SPI_CRC */
672
673 /* Configure communication direction: 1Line */
674 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
675 {
676 SPI_1LINE_RX(hspi);
677 }
678
679 /* Check if the SPI is already enabled */
680 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
681 {
682 /* Enable SPI peripheral */
683 __HAL_SPI_ENABLE(hspi);
684 }
685
686 /* Receive data in 8 Bit mode */
687 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
688 {
689 /* Transfer loop */
690 while(hspi->RxXferCount > 0U)
691 {
692 /* Check the RXNE flag */
693 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
694 {
695 /* read the received data */
696 (* (uint8_t *)pData)= *(__IO uint8_t *)&hspi->Instance->DR;
697 pData += sizeof(uint8_t);
698 hspi->RxXferCount--;
699 }
700 else
701 {
702 /* Timeout management */
703 if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
704 {
705 errorcode = HAL_TIMEOUT;
706 goto error;
707 }
708 }
709 }
710 }
711 else
712 {
713 /* Transfer loop */
714 while(hspi->RxXferCount > 0U)
715 {
716 /* Check the RXNE flag */
717 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
718 {
719 *((uint16_t*)pData) = hspi->Instance->DR;
720 pData += sizeof(uint16_t);
721 hspi->RxXferCount--;
722 }
723 else
724 {
725 /* Timeout management */
726 if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
727 {
728 errorcode = HAL_TIMEOUT;
729 goto error;
730 }
731 }
732 }
733 }
734
735 #if (USE_SPI_CRC != 0U)
736 /* Handle the CRC Transmission */
737 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
738 {
739 /* freeze the CRC before the latest data */
740 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
741
742 /* Read the latest data */
743 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
744 {
745 /* the latest data has not been received */
746 errorcode = HAL_TIMEOUT;
747 goto error;
748 }
749
750 /* Receive last data in 16 Bit mode */
751 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
752 {
753 *((uint16_t*)pData) = hspi->Instance->DR;
754 }
755 /* Receive last data in 8 Bit mode */
756 else
757 {
758 (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
759 }
760
761 /* Wait the CRC data */
762 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
763 {
764 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
765 errorcode = HAL_TIMEOUT;
766 goto error;
767 }
768
769 /* Read CRC to Flush DR and RXNE flag */
770 tmpreg = hspi->Instance->DR;
771 /* To avoid GCC warning */
772 UNUSED(tmpreg);
773 }
774 #endif /* USE_SPI_CRC */
775
776 /* Check the end of the transaction */
777 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
778 {
779 /* Disable SPI peripheral */
780 __HAL_SPI_DISABLE(hspi);
781 }
782
783 #if (USE_SPI_CRC != 0U)
784 /* Check if CRC error occurred */
785 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
786 {
787 /* Check if CRC error is valid or not (workaround to be applied or not) */
788 if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
789 {
790 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
791
792 /* Reset CRC Calculation */
793 SPI_RESET_CRC(hspi);
794 }
795 else
796 {
797 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
798 }
799 }
800 #endif /* USE_SPI_CRC */
801
802 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
803 {
804 errorcode = HAL_ERROR;
805 }
806
807 error :
808 hspi->State = HAL_SPI_STATE_READY;
809 __HAL_UNLOCK(hspi);
810 return errorcode;
811 }
812
813 /**
814 * @brief Transmit and Receive an amount of data in blocking mode.
815 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
816 * the configuration information for SPI module.
817 * @param pTxData: pointer to transmission data buffer
818 * @param pRxData: pointer to reception data buffer
819 * @param Size: amount of data to be sent and received
820 * @param Timeout: Timeout duration
821 * @retval HAL status
822 */
823 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
824 {
825 uint32_t tmp = 0U, tmp1 = 0U;
826 #if (USE_SPI_CRC != 0U)
827 __IO uint16_t tmpreg1 = 0U;
828 #endif /* USE_SPI_CRC */
829 uint32_t tickstart = 0U;
830 /* Variable used to alternate Rx and Tx during transfer */
831 uint32_t txallowed = 1U;
832 HAL_StatusTypeDef errorcode = HAL_OK;
833
834 /* Check Direction parameter */
835 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
836
837 /* Process Locked */
838 __HAL_LOCK(hspi);
839
840 /* Init tickstart for timeout management*/
841 tickstart = HAL_GetTick();
842
843 tmp = hspi->State;
844 tmp1 = hspi->Init.Mode;
845
846 if(!((tmp == HAL_SPI_STATE_READY) || \
847 ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
848 {
849 errorcode = HAL_BUSY;
850 goto error;
851 }
852
853 if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
854 {
855 errorcode = HAL_ERROR;
856 goto error;
857 }
858
859 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
860 if(hspi->State == HAL_SPI_STATE_READY)
861 {
862 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
863 }
864
865 /* Set the transaction information */
866 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
867 hspi->pRxBuffPtr = (uint8_t *)pRxData;
868 hspi->RxXferCount = Size;
869 hspi->RxXferSize = Size;
870 hspi->pTxBuffPtr = (uint8_t *)pTxData;
871 hspi->TxXferCount = Size;
872 hspi->TxXferSize = Size;
873
874 /*Init field not used in handle to zero */
875 hspi->RxISR = NULL;
876 hspi->TxISR = NULL;
877
878 #if (USE_SPI_CRC != 0U)
879 /* Reset CRC Calculation */
880 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
881 {
882 SPI_RESET_CRC(hspi);
883 }
884 #endif /* USE_SPI_CRC */
885
886 /* Check if the SPI is already enabled */
887 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
888 {
889 /* Enable SPI peripheral */
890 __HAL_SPI_ENABLE(hspi);
891 }
892
893 /* Transmit and Receive data in 16 Bit mode */
894 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
895 {
896 if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
897 {
898 hspi->Instance->DR = *((uint16_t *)pTxData);
899 pTxData += sizeof(uint16_t);
900 hspi->TxXferCount--;
901 }
902 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
903 {
904 /* Check TXE flag */
905 if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
906 {
907 hspi->Instance->DR = *((uint16_t *)pTxData);
908 pTxData += sizeof(uint16_t);
909 hspi->TxXferCount--;
910 /* Next Data is a reception (Rx). Tx not allowed */
911 txallowed = 0U;
912
913 #if (USE_SPI_CRC != 0U)
914 /* Enable CRC Transmission */
915 if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
916 {
917 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
918 }
919 #endif /* USE_SPI_CRC */
920 }
921
922 /* Check RXNE flag */
923 if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
924 {
925 *((uint16_t *)pRxData) = hspi->Instance->DR;
926 pRxData += sizeof(uint16_t);
927 hspi->RxXferCount--;
928 /* Next Data is a Transmission (Tx). Tx is allowed */
929 txallowed = 1U;
930 }
931 if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
932 {
933 errorcode = HAL_TIMEOUT;
934 goto error;
935 }
936 }
937 }
938 /* Transmit and Receive data in 8 Bit mode */
939 else
940 {
941 if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
942 {
943 *((__IO uint8_t*)&hspi->Instance->DR) = (*pTxData);
944 pTxData += sizeof(uint8_t);
945 hspi->TxXferCount--;
946 }
947 while((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
948 {
949 /* check TXE flag */
950 if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
951 {
952 *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
953 hspi->TxXferCount--;
954 /* Next Data is a reception (Rx). Tx not allowed */
955 txallowed = 0U;
956
957 #if (USE_SPI_CRC != 0U)
958 /* Enable CRC Transmission */
959 if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
960 {
961 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
962 }
963 #endif /* USE_SPI_CRC */
964 }
965
966 /* Wait until RXNE flag is reset */
967 if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
968 {
969 (*(uint8_t *)pRxData++) = hspi->Instance->DR;
970 hspi->RxXferCount--;
971 /* Next Data is a Transmission (Tx). Tx is allowed */
972 txallowed = 1U;
973 }
974 if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
975 {
976 errorcode = HAL_TIMEOUT;
977 goto error;
978 }
979 }
980 }
981
982 #if (USE_SPI_CRC != 0U)
983 /* Read CRC from DR to close CRC calculation process */
984 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
985 {
986 /* Wait until TXE flag */
987 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
988 {
989 /* Error on the CRC reception */
990 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
991 errorcode = HAL_TIMEOUT;
992 goto error;
993 }
994 /* Read CRC */
995 tmpreg1 = hspi->Instance->DR;
996 /* To avoid GCC warning */
997 UNUSED(tmpreg1);
998 }
999
1000 /* Check if CRC error occurred */
1001 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
1002 {
1003 /* Check if CRC error is valid or not (workaround to be applied or not) */
1004 if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
1005 {
1006 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1007
1008 /* Reset CRC Calculation */
1009 SPI_RESET_CRC(hspi);
1010
1011 errorcode = HAL_ERROR;
1012 }
1013 else
1014 {
1015 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1016 }
1017 }
1018 #endif /* USE_SPI_CRC */
1019
1020 /* Wait until TXE flag */
1021 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK)
1022 {
1023 errorcode = HAL_TIMEOUT;
1024 goto error;
1025 }
1026
1027 /* Check Busy flag */
1028 if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
1029 {
1030 errorcode = HAL_ERROR;
1031 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1032 goto error;
1033 }
1034
1035 /* Clear overrun flag in 2 Lines communication mode because received is not read */
1036 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
1037 {
1038 __HAL_SPI_CLEAR_OVRFLAG(hspi);
1039 }
1040
1041 error :
1042 hspi->State = HAL_SPI_STATE_READY;
1043 __HAL_UNLOCK(hspi);
1044 return errorcode;
1045 }
1046
1047 /**
1048 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
1049 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1050 * the configuration information for SPI module.
1051 * @param pData: pointer to data buffer
1052 * @param Size: amount of data to be sent
1053 * @retval HAL status
1054 */
1055 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1056 {
1057 HAL_StatusTypeDef errorcode = HAL_OK;
1058
1059 /* Check Direction parameter */
1060 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1061
1062 /* Process Locked */
1063 __HAL_LOCK(hspi);
1064
1065 if((pData == NULL) || (Size == 0U))
1066 {
1067 errorcode = HAL_ERROR;
1068 goto error;
1069 }
1070
1071 if(hspi->State != HAL_SPI_STATE_READY)
1072 {
1073 errorcode = HAL_BUSY;
1074 goto error;
1075 }
1076
1077 /* Set the transaction information */
1078 hspi->State = HAL_SPI_STATE_BUSY_TX;
1079 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1080 hspi->pTxBuffPtr = (uint8_t *)pData;
1081 hspi->TxXferSize = Size;
1082 hspi->TxXferCount = Size;
1083
1084 /* Init field not used in handle to zero */
1085 hspi->pRxBuffPtr = (uint8_t *)NULL;
1086 hspi->RxXferSize = 0U;
1087 hspi->RxXferCount = 0U;
1088 hspi->RxISR = NULL;
1089
1090 /* Set the function for IT treatment */
1091 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
1092 {
1093 hspi->TxISR = SPI_TxISR_16BIT;
1094 }
1095 else
1096 {
1097 hspi->TxISR = SPI_TxISR_8BIT;
1098 }
1099
1100 /* Configure communication direction : 1Line */
1101 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
1102 {
1103 SPI_1LINE_TX(hspi);
1104 }
1105
1106 #if (USE_SPI_CRC != 0U)
1107 /* Reset CRC Calculation */
1108 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1109 {
1110 SPI_RESET_CRC(hspi);
1111 }
1112 #endif /* USE_SPI_CRC */
1113
1114 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
1115 {
1116 /* Enable TXE interrupt */
1117 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
1118 }
1119 else
1120 {
1121 /* Enable TXE and ERR interrupt */
1122 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
1123 }
1124
1125 /* Check if the SPI is already enabled */
1126 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
1127 {
1128 /* Enable SPI peripheral */
1129 __HAL_SPI_ENABLE(hspi);
1130 }
1131
1132 error :
1133 __HAL_UNLOCK(hspi);
1134 return errorcode;
1135 }
1136
1137 /**
1138 * @brief Receive an amount of data in non-blocking mode with Interrupt.
1139 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1140 * the configuration information for SPI module.
1141 * @param pData: pointer to data buffer
1142 * @param Size: amount of data to be sent
1143 * @retval HAL status
1144 */
1145 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1146 {
1147 HAL_StatusTypeDef errorcode = HAL_OK;
1148
1149 if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1150 {
1151 hspi->State = HAL_SPI_STATE_BUSY_RX;
1152 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1153 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1154 }
1155
1156 /* Process Locked */
1157 __HAL_LOCK(hspi);
1158
1159 if(hspi->State != HAL_SPI_STATE_READY)
1160 {
1161 errorcode = HAL_BUSY;
1162 goto error;
1163 }
1164
1165 if((pData == NULL) || (Size == 0U))
1166 {
1167 errorcode = HAL_ERROR;
1168 goto error;
1169 }
1170
1171 /* Set the transaction information */
1172 hspi->State = HAL_SPI_STATE_BUSY_RX;
1173 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1174 hspi->pRxBuffPtr = (uint8_t *)pData;
1175 hspi->RxXferSize = Size;
1176 hspi->RxXferCount = Size;
1177
1178 /* Init field not used in handle to zero */
1179 hspi->pTxBuffPtr = (uint8_t *)NULL;
1180 hspi->TxXferSize = 0U;
1181 hspi->TxXferCount = 0U;
1182 hspi->TxISR = NULL;
1183
1184 /* Set the function for IT treatment */
1185 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
1186 {
1187 hspi->RxISR = SPI_RxISR_16BIT;
1188 }
1189 else
1190 {
1191 hspi->RxISR = SPI_RxISR_8BIT;
1192 }
1193
1194 /* Configure communication direction : 1Line */
1195 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
1196 {
1197 SPI_1LINE_RX(hspi);
1198 }
1199
1200 #if (USE_SPI_CRC != 0U)
1201 /* Reset CRC Calculation */
1202 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1203 {
1204 SPI_RESET_CRC(hspi);
1205 }
1206 #endif /* USE_SPI_CRC */
1207
1208 /* Enable TXE and ERR interrupt */
1209 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1210
1211 /* Note : The SPI must be enabled after unlocking current process
1212 to avoid the risk of SPI interrupt handle execution before current
1213 process unlock */
1214
1215 /* Check if the SPI is already enabled */
1216 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
1217 {
1218 /* Enable SPI peripheral */
1219 __HAL_SPI_ENABLE(hspi);
1220 }
1221
1222 error :
1223 /* Process Unlocked */
1224 __HAL_UNLOCK(hspi);
1225 return errorcode;
1226 }
1227
1228 /**
1229 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1230 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1231 * the configuration information for SPI module.
1232 * @param pTxData: pointer to transmission data buffer
1233 * @param pRxData: pointer to reception data buffer
1234 * @param Size: amount of data to be sent and received
1235 * @retval HAL status
1236 */
1237 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1238 {
1239 uint32_t tmp = 0U, tmp1 = 0U;
1240 HAL_StatusTypeDef errorcode = HAL_OK;
1241
1242 /* Check Direction parameter */
1243 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1244
1245 /* Process locked */
1246 __HAL_LOCK(hspi);
1247
1248 tmp = hspi->State;
1249 tmp1 = hspi->Init.Mode;
1250
1251 if(!((tmp == HAL_SPI_STATE_READY) || \
1252 ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
1253 {
1254 errorcode = HAL_BUSY;
1255 goto error;
1256 }
1257
1258 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
1259 {
1260 errorcode = HAL_ERROR;
1261 goto error;
1262 }
1263
1264 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1265 if(hspi->State == HAL_SPI_STATE_READY)
1266 {
1267 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1268 }
1269
1270 /* Set the transaction information */
1271 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1272 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1273 hspi->TxXferSize = Size;
1274 hspi->TxXferCount = Size;
1275 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1276 hspi->RxXferSize = Size;
1277 hspi->RxXferCount = Size;
1278
1279 /* Set the function for IT treatment */
1280 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
1281 {
1282 hspi->RxISR = SPI_2linesRxISR_16BIT;
1283 hspi->TxISR = SPI_2linesTxISR_16BIT;
1284 }
1285 else
1286 {
1287 hspi->RxISR = SPI_2linesRxISR_8BIT;
1288 hspi->TxISR = SPI_2linesTxISR_8BIT;
1289 }
1290
1291 #if (USE_SPI_CRC != 0U)
1292 /* Reset CRC Calculation */
1293 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1294 {
1295 SPI_RESET_CRC(hspi);
1296 }
1297 #endif /* USE_SPI_CRC */
1298
1299 /* Enable TXE, RXNE and ERR interrupt */
1300 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1301
1302 /* Check if the SPI is already enabled */
1303 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
1304 {
1305 /* Enable SPI peripheral */
1306 __HAL_SPI_ENABLE(hspi);
1307 }
1308
1309 error :
1310 /* Process Unlocked */
1311 __HAL_UNLOCK(hspi);
1312 return errorcode;
1313 }
1314
1315 /**
1316 * @brief Transmit an amount of data in non-blocking mode with DMA.
1317 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1318 * the configuration information for SPI module.
1319 * @param pData: pointer to data buffer
1320 * @param Size: amount of data to be sent
1321 * @retval HAL status
1322 */
1323 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1324 {
1325 HAL_StatusTypeDef errorcode = HAL_OK;
1326
1327 /* Check Direction parameter */
1328 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1329
1330 /* Process Locked */
1331 __HAL_LOCK(hspi);
1332
1333 if(hspi->State != HAL_SPI_STATE_READY)
1334 {
1335 errorcode = HAL_BUSY;
1336 goto error;
1337 }
1338
1339 if((pData == NULL) || (Size == 0U))
1340 {
1341 errorcode = HAL_ERROR;
1342 goto error;
1343 }
1344
1345 /* Set the transaction information */
1346 hspi->State = HAL_SPI_STATE_BUSY_TX;
1347 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1348 hspi->pTxBuffPtr = (uint8_t *)pData;
1349 hspi->TxXferSize = Size;
1350 hspi->TxXferCount = Size;
1351
1352 /* Init field not used in handle to zero */
1353 hspi->pRxBuffPtr = (uint8_t *)NULL;
1354 hspi->TxISR = NULL;
1355 hspi->RxISR = NULL;
1356 hspi->RxXferSize = 0U;
1357 hspi->RxXferCount = 0U;
1358
1359 /* Configure communication direction : 1Line */
1360 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
1361 {
1362 SPI_1LINE_TX(hspi);
1363 }
1364
1365 #if (USE_SPI_CRC != 0U)
1366 /* Reset CRC Calculation */
1367 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1368 {
1369 SPI_RESET_CRC(hspi);
1370 }
1371 #endif /* USE_SPI_CRC */
1372
1373 /* Set the SPI TxDMA Half transfer complete callback */
1374 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1375
1376 /* Set the SPI TxDMA transfer complete callback */
1377 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1378
1379 /* Set the DMA error callback */
1380 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1381
1382 /* Set the DMA AbortCpltCallback */
1383 hspi->hdmatx->XferAbortCallback = NULL;
1384
1385 /* Enable the Tx DMA Stream */
1386 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
1387
1388 /* Check if the SPI is already enabled */
1389 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
1390 {
1391 /* Enable SPI peripheral */
1392 __HAL_SPI_ENABLE(hspi);
1393 }
1394
1395 /* Enable the SPI Error Interrupt Bit */
1396 SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
1397
1398 /* Enable Tx DMA Request */
1399 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1400
1401 error :
1402 /* Process Unlocked */
1403 __HAL_UNLOCK(hspi);
1404 return errorcode;
1405 }
1406
1407 /**
1408 * @brief Receive an amount of data in non-blocking mode with DMA.
1409 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1410 * the configuration information for SPI module.
1411 * @param pData: pointer to data buffer
1412 * @note When the CRC feature is enabled the pData Length must be Size + 1.
1413 * @param Size: amount of data to be sent
1414 * @retval HAL status
1415 */
1416 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1417 {
1418 HAL_StatusTypeDef errorcode = HAL_OK;
1419
1420 if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
1421 {
1422 hspi->State = HAL_SPI_STATE_BUSY_RX;
1423 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1424 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
1425 }
1426
1427 /* Process Locked */
1428 __HAL_LOCK(hspi);
1429
1430 if(hspi->State != HAL_SPI_STATE_READY)
1431 {
1432 errorcode = HAL_BUSY;
1433 goto error;
1434 }
1435
1436 if((pData == NULL) || (Size == 0U))
1437 {
1438 errorcode = HAL_ERROR;
1439 goto error;
1440 }
1441
1442 /* Set the transaction information */
1443 hspi->State = HAL_SPI_STATE_BUSY_RX;
1444 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1445 hspi->pRxBuffPtr = (uint8_t *)pData;
1446 hspi->RxXferSize = Size;
1447 hspi->RxXferCount = Size;
1448
1449 /*Init field not used in handle to zero */
1450 hspi->RxISR = NULL;
1451 hspi->TxISR = NULL;
1452 hspi->TxXferSize = 0U;
1453 hspi->TxXferCount = 0U;
1454
1455 /* Configure communication direction : 1Line */
1456 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
1457 {
1458 SPI_1LINE_RX(hspi);
1459 }
1460
1461 #if (USE_SPI_CRC != 0U)
1462 /* Reset CRC Calculation */
1463 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1464 {
1465 SPI_RESET_CRC(hspi);
1466 }
1467 #endif /* USE_SPI_CRC */
1468
1469 /* Set the SPI RxDMA Half transfer complete callback */
1470 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
1471
1472 /* Set the SPI Rx DMA transfer complete callback */
1473 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
1474
1475 /* Set the DMA error callback */
1476 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
1477
1478 /* Set the DMA AbortCpltCallback */
1479 hspi->hdmarx->XferAbortCallback = NULL;
1480
1481 /* Enable the Rx DMA Stream */
1482 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
1483
1484 /* Check if the SPI is already enabled */
1485 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
1486 {
1487 /* Enable SPI peripheral */
1488 __HAL_SPI_ENABLE(hspi);
1489 }
1490
1491 /* Enable the SPI Error Interrupt Bit */
1492 SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
1493
1494 /* Enable Rx DMA Request */
1495 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
1496
1497 error:
1498 /* Process Unlocked */
1499 __HAL_UNLOCK(hspi);
1500 return errorcode;
1501 }
1502
1503 /**
1504 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
1505 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1506 * the configuration information for SPI module.
1507 * @param pTxData: pointer to transmission data buffer
1508 * @param pRxData: pointer to reception data buffer
1509 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
1510 * @param Size: amount of data to be sent
1511 * @retval HAL status
1512 */
1513 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1514 {
1515 uint32_t tmp = 0U, tmp1 = 0U;
1516 HAL_StatusTypeDef errorcode = HAL_OK;
1517
1518 /* Check Direction parameter */
1519 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1520
1521 /* Process locked */
1522 __HAL_LOCK(hspi);
1523
1524 tmp = hspi->State;
1525 tmp1 = hspi->Init.Mode;
1526 if(!((tmp == HAL_SPI_STATE_READY) ||
1527 ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
1528 {
1529 errorcode = HAL_BUSY;
1530 goto error;
1531 }
1532
1533 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
1534 {
1535 errorcode = HAL_ERROR;
1536 goto error;
1537 }
1538
1539 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1540 if(hspi->State == HAL_SPI_STATE_READY)
1541 {
1542 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1543 }
1544
1545 /* Set the transaction information */
1546 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1547 hspi->pTxBuffPtr = (uint8_t*)pTxData;
1548 hspi->TxXferSize = Size;
1549 hspi->TxXferCount = Size;
1550 hspi->pRxBuffPtr = (uint8_t*)pRxData;
1551 hspi->RxXferSize = Size;
1552 hspi->RxXferCount = Size;
1553
1554 /* Init field not used in handle to zero */
1555 hspi->RxISR = NULL;
1556 hspi->TxISR = NULL;
1557
1558 #if (USE_SPI_CRC != 0U)
1559 /* Reset CRC Calculation */
1560 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1561 {
1562 SPI_RESET_CRC(hspi);
1563 }
1564 #endif /* USE_SPI_CRC */
1565
1566 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
1567 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
1568 {
1569 /* Set the SPI Rx DMA Half transfer complete callback */
1570 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
1571 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
1572 }
1573 else
1574 {
1575 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
1576 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
1577 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
1578 }
1579
1580 /* Set the DMA error callback */
1581 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
1582
1583 /* Set the DMA AbortCpltCallback */
1584 hspi->hdmarx->XferAbortCallback = NULL;
1585
1586 /* Enable the Rx DMA Stream */
1587 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
1588
1589 /* Enable Rx DMA Request */
1590 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
1591
1592 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
1593 is performed in DMA reception complete callback */
1594 hspi->hdmatx->XferHalfCpltCallback = NULL;
1595 hspi->hdmatx->XferCpltCallback = NULL;
1596 hspi->hdmatx->XferErrorCallback = NULL;
1597 hspi->hdmatx->XferAbortCallback = NULL;
1598
1599 /* Enable the Tx DMA Stream */
1600 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
1601
1602 /* Check if the SPI is already enabled */
1603 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
1604 {
1605 /* Enable SPI peripheral */
1606 __HAL_SPI_ENABLE(hspi);
1607 }
1608 /* Enable the SPI Error Interrupt Bit */
1609 SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
1610
1611 /* Enable Tx DMA Request */
1612 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1613
1614 error :
1615 /* Process Unlocked */
1616 __HAL_UNLOCK(hspi);
1617 return errorcode;
1618 }
1619
1620 /**
1621 * @brief Abort ongoing transfer (blocking mode).
1622 * @param hspi SPI handle.
1623 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
1624 * started in Interrupt or DMA mode.
1625 * This procedure performs following operations :
1626 * - Disable SPI Interrupts (depending of transfer direction)
1627 * - Disable the DMA transfer in the peripheral register (if enabled)
1628 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
1629 * - Set handle State to READY
1630 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
1631 * @note Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application
1632 * before starting new SPI receive process.
1633 * @retval HAL status
1634 */
1635 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
1636 {
1637 __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
1638
1639 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
1640 if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
1641 {
1642 hspi->TxISR = SPI_AbortTx_ISR;
1643 }
1644
1645 if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
1646 {
1647 hspi->RxISR = SPI_AbortRx_ISR;
1648 }
1649
1650 /* Clear ERRIE interrupts in case of DMA Mode */
1651 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
1652
1653 /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
1654 if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
1655 {
1656 /* Abort the SPI DMA Tx channel : use blocking DMA Abort API (no callback) */
1657 if(hspi->hdmatx != NULL)
1658 {
1659 /* Set the SPI DMA Abort callback :
1660 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
1661 hspi->hdmatx->XferAbortCallback = NULL;
1662
1663 /* Abort DMA Tx Handle linked to SPI Peripheral */
1664 HAL_DMA_Abort(hspi->hdmatx);
1665
1666 /* Disable Tx DMA Request */
1667 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
1668
1669 /* Wait until TXE flag is set */
1670 do
1671 {
1672 if(count-- == 0U)
1673 {
1674 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
1675 break;
1676 }
1677 }
1678 while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
1679 }
1680 /* Abort the SPI DMA Rx channel : use blocking DMA Abort API (no callback) */
1681 if(hspi->hdmarx != NULL)
1682 {
1683 /* Set the SPI DMA Abort callback :
1684 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
1685 hspi->hdmarx->XferAbortCallback = NULL;
1686
1687 /* Abort DMA Rx Handle linked to SPI Peripheral */
1688 HAL_DMA_Abort(hspi->hdmarx);
1689
1690 /* Disable peripheral */
1691 __HAL_SPI_DISABLE(hspi);
1692
1693 /* Disable Rx DMA Request */
1694 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
1695
1696 }
1697 }
1698 /* Reset Tx and Rx transfer counters */
1699 hspi->RxXferCount = 0U;
1700 hspi->TxXferCount = 0U;
1701
1702 /* Reset errorCode */
1703 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1704
1705 /* Clear the Error flags in the SR register */
1706 __HAL_SPI_CLEAR_OVRFLAG(hspi);
1707
1708 /* Restore hspi->state to ready */
1709 hspi->State = HAL_SPI_STATE_READY;
1710
1711 return HAL_OK;
1712 }
1713
1714 /**
1715 * @brief Abort ongoing transfer (Interrupt mode).
1716 * @param hspi SPI handle.
1717 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
1718 * started in Interrupt or DMA mode.
1719 * This procedure performs following operations :
1720 * - Disable SPI Interrupts (depending of transfer direction)
1721 * - Disable the DMA transfer in the peripheral register (if enabled)
1722 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
1723 * - Set handle State to READY
1724 * - At abort completion, call user abort complete callback
1725 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
1726 * considered as completed only when user abort complete callback is executed (not when exiting function).
1727 * @note Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application
1728 * before starting new SPI receive process.
1729 * @retval HAL status
1730 */
1731 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
1732 {
1733 uint32_t abortcplt;
1734
1735 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
1736 if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
1737 {
1738 hspi->TxISR = SPI_AbortTx_ISR;
1739 }
1740
1741 if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
1742 {
1743 hspi->RxISR = SPI_AbortRx_ISR;
1744 }
1745
1746 /* Clear ERRIE interrupts in case of DMA Mode */
1747 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
1748
1749 abortcplt = 1U;
1750
1751 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
1752 before any call to DMA Abort functions */
1753 /* DMA Tx Handle is valid */
1754 if(hspi->hdmatx != NULL)
1755 {
1756 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
1757 Otherwise, set it to NULL */
1758 if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
1759 {
1760 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
1761 }
1762 else
1763 {
1764 hspi->hdmatx->XferAbortCallback = NULL;
1765 }
1766 }
1767 /* DMA Rx Handle is valid */
1768 if(hspi->hdmarx != NULL)
1769 {
1770 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
1771 Otherwise, set it to NULL */
1772 if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
1773 {
1774 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
1775 }
1776 else
1777 {
1778 hspi->hdmarx->XferAbortCallback = NULL;
1779 }
1780 }
1781
1782 /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
1783 if((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
1784 {
1785 /* Abort the SPI DMA Tx channel */
1786 if(hspi->hdmatx != NULL)
1787 {
1788 /* Abort DMA Tx Handle linked to SPI Peripheral */
1789 if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
1790 {
1791 hspi->hdmatx->XferAbortCallback = NULL;
1792 }
1793 else
1794 {
1795 abortcplt = 0U;
1796 }
1797 }
1798 /* Abort the SPI DMA Rx channel */
1799 if(hspi->hdmarx != NULL)
1800 {
1801 /* Abort DMA Rx Handle linked to SPI Peripheral */
1802 if(HAL_DMA_Abort_IT(hspi->hdmarx)!= HAL_OK)
1803 {
1804 hspi->hdmarx->XferAbortCallback = NULL;
1805 abortcplt = 1U;
1806 }
1807 else
1808 {
1809 abortcplt = 0U;
1810 }
1811 }
1812 }
1813
1814 /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
1815 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
1816 {
1817 /* Abort the SPI DMA Tx channel */
1818 if(hspi->hdmatx != NULL)
1819 {
1820 /* Abort DMA Tx Handle linked to SPI Peripheral */
1821 if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
1822 {
1823 hspi->hdmatx->XferAbortCallback = NULL;
1824 }
1825 else
1826 {
1827 abortcplt = 0U;
1828 }
1829 }
1830 }
1831 /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
1832 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
1833 {
1834 /* Abort the SPI DMA Rx channel */
1835 if(hspi->hdmarx != NULL)
1836 {
1837 /* Abort DMA Rx Handle linked to SPI Peripheral */
1838 if(HAL_DMA_Abort_IT(hspi->hdmarx)!= HAL_OK)
1839 {
1840 hspi->hdmarx->XferAbortCallback = NULL;
1841 }
1842 else
1843 {
1844 abortcplt = 0U;
1845 }
1846 }
1847 }
1848
1849 if(abortcplt == 1U)
1850 {
1851 /* Reset Tx and Rx transfer counters */
1852 hspi->RxXferCount = 0U;
1853 hspi->TxXferCount = 0U;
1854
1855 /* Reset errorCode */
1856 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1857
1858 /* Clear the Error flags in the SR register */
1859 __HAL_SPI_CLEAR_OVRFLAG(hspi);
1860
1861 /* Restore hspi->State to Ready */
1862 hspi->State = HAL_SPI_STATE_READY;
1863
1864 /* As no DMA to be aborted, call directly user Abort complete callback */
1865 HAL_SPI_AbortCpltCallback(hspi);
1866 }
1867 return HAL_OK;
1868 }
1869
1870 /**
1871 * @brief Pause the DMA Transfer.
1872 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1873 * the configuration information for the specified SPI module.
1874 * @retval HAL status
1875 */
1876 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
1877 {
1878 /* Process Locked */
1879 __HAL_LOCK(hspi);
1880
1881 /* Disable the SPI DMA Tx & Rx requests */
1882 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
1883
1884 /* Process Unlocked */
1885 __HAL_UNLOCK(hspi);
1886
1887 return HAL_OK;
1888 }
1889
1890 /**
1891 * @brief Resume the DMA Transfer.
1892 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1893 * the configuration information for the specified SPI module.
1894 * @retval HAL status
1895 */
1896 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
1897 {
1898 /* Process Locked */
1899 __HAL_LOCK(hspi);
1900
1901 /* Enable the SPI DMA Tx & Rx requests */
1902 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
1903
1904 /* Process Unlocked */
1905 __HAL_UNLOCK(hspi);
1906
1907 return HAL_OK;
1908 }
1909
1910 /**
1911 * @brief Stop the DMA Transfer.
1912 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1913 * the configuration information for the specified SPI module.
1914 * @retval HAL status
1915 */
1916 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
1917 {
1918 /* The Lock is not implemented on this API to allow the user application
1919 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
1920 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
1921 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
1922 */
1923
1924 /* Abort the SPI DMA tx Stream */
1925 if(hspi->hdmatx != NULL)
1926 {
1927 HAL_DMA_Abort(hspi->hdmatx);
1928 }
1929 /* Abort the SPI DMA rx Stream */
1930 if(hspi->hdmarx != NULL)
1931 {
1932 HAL_DMA_Abort(hspi->hdmarx);
1933 }
1934
1935 /* Disable the SPI DMA Tx & Rx requests */
1936 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
1937 hspi->State = HAL_SPI_STATE_READY;
1938 return HAL_OK;
1939 }
1940
1941 /**
1942 * @brief Handle SPI interrupt request.
1943 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1944 * the configuration information for the specified SPI module.
1945 * @retval None
1946 */
1947 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
1948 {
1949 uint32_t itsource = hspi->Instance->CR2;
1950 uint32_t itflag = hspi->Instance->SR;
1951
1952 /* SPI in mode Receiver ----------------------------------------------------*/
1953 if(((itflag & SPI_FLAG_OVR) == RESET) &&
1954 ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
1955 {
1956 hspi->RxISR(hspi);
1957 return;
1958 }
1959
1960 /* SPI in mode Transmitter -------------------------------------------------*/
1961 if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
1962 {
1963 hspi->TxISR(hspi);
1964 return;
1965 }
1966
1967 /* SPI in Error Treatment --------------------------------------------------*/
1968 if(((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
1969 {
1970 /* SPI Overrun error interrupt occurred ----------------------------------*/
1971 if((itflag & SPI_FLAG_OVR) != RESET)
1972 {
1973 if(hspi->State != HAL_SPI_STATE_BUSY_TX)
1974 {
1975 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
1976 __HAL_SPI_CLEAR_OVRFLAG(hspi);
1977 }
1978 else
1979 {
1980 __HAL_SPI_CLEAR_OVRFLAG(hspi);
1981 return;
1982 }
1983 }
1984
1985 /* SPI Mode Fault error interrupt occurred -------------------------------*/
1986 if((itflag & SPI_FLAG_MODF) != RESET)
1987 {
1988 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
1989 __HAL_SPI_CLEAR_MODFFLAG(hspi);
1990 }
1991
1992 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1993 {
1994 /* Disable all interrupts */
1995 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
1996
1997 hspi->State = HAL_SPI_STATE_READY;
1998 /* Disable the SPI DMA requests if enabled */
1999 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN))||(HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
2000 {
2001 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
2002
2003 /* Abort the SPI DMA Rx channel */
2004 if(hspi->hdmarx != NULL)
2005 {
2006 /* Set the SPI DMA Abort callback :
2007 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2008 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
2009 HAL_DMA_Abort_IT(hspi->hdmarx);
2010 }
2011 /* Abort the SPI DMA Tx channel */
2012 if(hspi->hdmatx != NULL)
2013 {
2014 /* Set the SPI DMA Abort callback :
2015 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2016 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
2017 HAL_DMA_Abort_IT(hspi->hdmatx);
2018 }
2019 }
2020 else
2021 {
2022 /* Call user error callback */
2023 HAL_SPI_ErrorCallback(hspi);
2024 }
2025 }
2026 return;
2027 }
2028 }
2029
2030 /**
2031 * @brief Tx Transfer completed callback.
2032 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2033 * the configuration information for SPI module.
2034 * @retval None
2035 */
2036 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
2037 {
2038 /* Prevent unused argument(s) compilation warning */
2039 UNUSED(hspi);
2040 /* NOTE : This function should not be modified, when the callback is needed,
2041 the HAL_SPI_TxCpltCallback should be implemented in the user file
2042 */
2043 }
2044
2045 /**
2046 * @brief Rx Transfer completed callback.
2047 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2048 * the configuration information for SPI module.
2049 * @retval None
2050 */
2051 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
2052 {
2053 /* Prevent unused argument(s) compilation warning */
2054 UNUSED(hspi);
2055 /* NOTE : This function should not be modified, when the callback is needed,
2056 the HAL_SPI_RxCpltCallback should be implemented in the user file
2057 */
2058 }
2059
2060 /**
2061 * @brief Tx and Rx Transfer completed callback.
2062 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2063 * the configuration information for SPI module.
2064 * @retval None
2065 */
2066 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
2067 {
2068 /* Prevent unused argument(s) compilation warning */
2069 UNUSED(hspi);
2070 /* NOTE : This function should not be modified, when the callback is needed,
2071 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
2072 */
2073 }
2074
2075 /**
2076 * @brief Tx Half Transfer completed callback.
2077 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2078 * the configuration information for SPI module.
2079 * @retval None
2080 */
2081 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2082 {
2083 /* Prevent unused argument(s) compilation warning */
2084 UNUSED(hspi);
2085 /* NOTE : This function should not be modified, when the callback is needed,
2086 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
2087 */
2088 }
2089
2090 /**
2091 * @brief Rx Half Transfer completed callback.
2092 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2093 * the configuration information for SPI module.
2094 * @retval None
2095 */
2096 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2097 {
2098 /* Prevent unused argument(s) compilation warning */
2099 UNUSED(hspi);
2100 /* NOTE : This function should not be modified, when the callback is needed,
2101 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
2102 */
2103 }
2104
2105 /**
2106 * @brief Tx and Rx Half Transfer callback.
2107 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2108 * the configuration information for SPI module.
2109 * @retval None
2110 */
2111 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2112 {
2113 /* Prevent unused argument(s) compilation warning */
2114 UNUSED(hspi);
2115 /* NOTE : This function should not be modified, when the callback is needed,
2116 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
2117 */
2118 }
2119
2120 /**
2121 * @brief SPI error callback.
2122 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2123 * the configuration information for SPI module.
2124 * @retval None
2125 */
2126 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
2127 {
2128 /* Prevent unused argument(s) compilation warning */
2129 UNUSED(hspi);
2130 /* NOTE : This function should not be modified, when the callback is needed,
2131 the HAL_SPI_ErrorCallback should be implemented in the user file
2132 */
2133 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
2134 and user can use HAL_SPI_GetError() API to check the latest error occurred
2135 */
2136 }
2137
2138 /**
2139 * @brief SPI Abort Complete callback.
2140 * @param hspi SPI handle.
2141 * @retval None
2142 */
2143 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
2144 {
2145 /* Prevent unused argument(s) compilation warning */
2146 UNUSED(hspi);
2147
2148 /* NOTE : This function should not be modified, when the callback is needed,
2149 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
2150 */
2151 }
2152
2153 /**
2154 * @}
2155 */
2156
2157 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
2158 * @brief SPI control functions
2159 *
2160 @verbatim
2161 ===============================================================================
2162 ##### Peripheral State and Errors functions #####
2163 ===============================================================================
2164 [..]
2165 This subsection provides a set of functions allowing to control the SPI.
2166 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
2167 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
2168 @endverbatim
2169 * @{
2170 */
2171
2172 /**
2173 * @brief Return the SPI handle state.
2174 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2175 * the configuration information for SPI module.
2176 * @retval SPI state
2177 */
2178 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
2179 {
2180 /* Return SPI handle state */
2181 return hspi->State;
2182 }
2183
2184 /**
2185 * @brief Return the SPI error code.
2186 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2187 * the configuration information for SPI module.
2188 * @retval SPI error code in bitmap format
2189 */
2190 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
2191 {
2192 /* Return SPI ErrorCode */
2193 return hspi->ErrorCode;
2194 }
2195
2196 /**
2197 * @}
2198 */
2199
2200 /**
2201 * @}
2202 */
2203
2204 /** @addtogroup SPI_Private_Functions
2205 * @brief Private functions
2206 * @{
2207 */
2208
2209 /**
2210 * @brief DMA SPI transmit process complete callback.
2211 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2212 * the configuration information for the specified DMA module.
2213 * @retval None
2214 */
2215 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
2216 {
2217 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2218 uint32_t tickstart = 0U;
2219
2220 /* Init tickstart for timeout managment*/
2221 tickstart = HAL_GetTick();
2222
2223 /* DMA Normal Mode */
2224 if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
2225 {
2226 /* Disable Tx DMA Request */
2227 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2228
2229 /* Check the end of the transaction */
2230 if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2231 {
2232 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2233 }
2234
2235 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
2236 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
2237 {
2238 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2239 }
2240
2241 hspi->TxXferCount = 0U;
2242 hspi->State = HAL_SPI_STATE_READY;
2243
2244 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2245 {
2246 HAL_SPI_ErrorCallback(hspi);
2247 return;
2248 }
2249 }
2250 HAL_SPI_TxCpltCallback(hspi);
2251 }
2252
2253 /**
2254 * @brief DMA SPI receive process complete callback.
2255 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2256 * the configuration information for the specified DMA module.
2257 * @retval None
2258 */
2259 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
2260 {
2261 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2262 #if (USE_SPI_CRC != 0U)
2263 uint32_t tickstart = 0U;
2264 __IO uint16_t tmpreg = 0U;
2265
2266 /* Init tickstart for timeout management*/
2267 tickstart = HAL_GetTick();
2268 #endif /* USE_SPI_CRC */
2269
2270 if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
2271 {
2272 #if (USE_SPI_CRC != 0U)
2273 /* CRC handling */
2274 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2275 {
2276 /* Wait until RXNE flag */
2277 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2278 {
2279 /* Error on the CRC reception */
2280 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2281 }
2282 /* Read CRC */
2283 tmpreg = hspi->Instance->DR;
2284 /* To avoid GCC warning */
2285 UNUSED(tmpreg);
2286 }
2287 #endif /* USE_SPI_CRC */
2288
2289 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
2290 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2291
2292 /* Check the end of the transaction */
2293 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
2294 {
2295 /* Disable SPI peripheral */
2296 __HAL_SPI_DISABLE(hspi);
2297 }
2298
2299 hspi->RxXferCount = 0U;
2300 hspi->State = HAL_SPI_STATE_READY;
2301
2302 #if (USE_SPI_CRC != 0U)
2303 /* Check if CRC error occurred */
2304 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
2305 {
2306 /* Check if CRC error is valid or not (workaround to be applied or not) */
2307 if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
2308 {
2309 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2310
2311 /* Reset CRC Calculation */
2312 SPI_RESET_CRC(hspi);
2313 }
2314 else
2315 {
2316 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2317 }
2318 }
2319 #endif /* USE_SPI_CRC */
2320
2321 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2322 {
2323 HAL_SPI_ErrorCallback(hspi);
2324 return;
2325 }
2326 }
2327 HAL_SPI_RxCpltCallback(hspi);
2328 }
2329
2330 /**
2331 * @brief DMA SPI transmit receive process complete callback.
2332 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2333 * the configuration information for the specified DMA module.
2334 * @retval None
2335 */
2336 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
2337 {
2338 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2339 uint32_t tickstart = 0U;
2340 #if (USE_SPI_CRC != 0U)
2341 __IO int16_t tmpreg = 0U;
2342 #endif /* USE_SPI_CRC */
2343 /* Init tickstart for timeout management*/
2344 tickstart = HAL_GetTick();
2345
2346 if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
2347 {
2348 #if (USE_SPI_CRC != 0U)
2349 /* CRC handling */
2350 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2351 {
2352 /* Wait the CRC data */
2353 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2354 {
2355 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2356 }
2357 /* Read CRC to Flush DR and RXNE flag */
2358 tmpreg = hspi->Instance->DR;
2359 /* To avoid GCC warning */
2360 UNUSED(tmpreg);
2361 }
2362 #endif /* USE_SPI_CRC */
2363 /* Check the end of the transaction */
2364 if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2365 {
2366 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2367 }
2368
2369 /* Disable Rx/Tx DMA Request */
2370 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2371
2372 hspi->TxXferCount = 0U;
2373 hspi->RxXferCount = 0U;
2374 hspi->State = HAL_SPI_STATE_READY;
2375
2376 #if (USE_SPI_CRC != 0U)
2377 /* Check if CRC error occurred */
2378 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
2379 {
2380 /* Check if CRC error is valid or not (workaround to be applied or not) */
2381 if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
2382 {
2383 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2384
2385 /* Reset CRC Calculation */
2386 SPI_RESET_CRC(hspi);
2387 }
2388 else
2389 {
2390 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2391 }
2392 }
2393 #endif /* USE_SPI_CRC */
2394
2395 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2396 {
2397 HAL_SPI_ErrorCallback(hspi);
2398 return;
2399 }
2400 }
2401 HAL_SPI_TxRxCpltCallback(hspi);
2402 }
2403
2404 /**
2405 * @brief DMA SPI half transmit process complete callback.
2406 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2407 * the configuration information for the specified DMA module.
2408 * @retval None
2409 */
2410 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
2411 {
2412 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2413
2414 HAL_SPI_TxHalfCpltCallback(hspi);
2415 }
2416
2417 /**
2418 * @brief DMA SPI half receive process complete callback
2419 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2420 * the configuration information for the specified DMA module.
2421 * @retval None
2422 */
2423 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
2424 {
2425 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2426
2427 HAL_SPI_RxHalfCpltCallback(hspi);
2428 }
2429
2430 /**
2431 * @brief DMA SPI half transmit receive process complete callback.
2432 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2433 * the configuration information for the specified DMA module.
2434 * @retval None
2435 */
2436 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
2437 {
2438 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2439
2440 HAL_SPI_TxRxHalfCpltCallback(hspi);
2441 }
2442
2443 /**
2444 * @brief DMA SPI communication error callback.
2445 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2446 * the configuration information for the specified DMA module.
2447 * @retval None
2448 */
2449 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
2450 {
2451 SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2452
2453 /* Stop the disable DMA transfer on SPI side */
2454 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2455
2456 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2457 hspi->State = HAL_SPI_STATE_READY;
2458 HAL_SPI_ErrorCallback(hspi);
2459 }
2460
2461 /**
2462 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
2463 * (To be called at end of DMA Abort procedure following error occurrence).
2464 * @param hdma DMA handle.
2465 * @retval None
2466 */
2467 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
2468 {
2469 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2470 hspi->RxXferCount = 0U;
2471 hspi->TxXferCount = 0U;
2472
2473 HAL_SPI_ErrorCallback(hspi);
2474 }
2475
2476 /**
2477 * @brief DMA SPI Tx communication abort callback, when initiated by user
2478 * (To be called at end of DMA Tx Abort procedure following user abort request).
2479 * @note When this callback is executed, User Abort complete call back is called only if no
2480 * Abort still ongoing for Rx DMA Handle.
2481 * @param hdma DMA handle.
2482 * @retval None
2483 */
2484 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
2485 {
2486 __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2487 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2488
2489 hspi->hdmatx->XferAbortCallback = NULL;
2490
2491 /* Disable Tx DMA Request */
2492 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN );
2493
2494 /* Wait until TXE flag is set */
2495 do
2496 {
2497 if(count-- == 0U)
2498 {
2499 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2500 break;
2501 }
2502 }
2503 while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
2504
2505 /* Check if an Abort process is still ongoing */
2506 if(hspi->hdmarx != NULL)
2507 {
2508 if(hspi->hdmarx->XferAbortCallback != NULL)
2509 {
2510 return;
2511 }
2512 }
2513
2514 /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
2515 hspi->RxXferCount = 0U;
2516 hspi->TxXferCount = 0U;
2517
2518 /* Reset errorCode */
2519 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2520
2521 /* Restore hspi->State to Ready */
2522 hspi->State = HAL_SPI_STATE_READY;
2523
2524 /* Call user Abort complete callback */
2525 HAL_SPI_AbortCpltCallback(hspi);
2526 }
2527
2528 /**
2529 * @brief DMA SPI Rx communication abort callback, when initiated by user
2530 * (To be called at end of DMA Rx Abort procedure following user abort request).
2531 * @note When this callback is executed, User Abort complete call back is called only if no
2532 * Abort still ongoing for Tx DMA Handle.
2533 * @param hdma DMA handle.
2534 * @retval None
2535 */
2536 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
2537 {
2538 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2539
2540 /* Disable SPI Peripheral */
2541 __HAL_SPI_DISABLE(hspi);
2542
2543 hspi->hdmarx->XferAbortCallback = NULL;
2544
2545 /* Disable Rx DMA Request */
2546 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2547
2548 /* Check if an Abort process is still ongoing */
2549 if(hspi->hdmatx != NULL)
2550 {
2551 if(hspi->hdmatx->XferAbortCallback != NULL)
2552 {
2553 return;
2554 }
2555 }
2556
2557 /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
2558 hspi->RxXferCount = 0U;
2559 hspi->TxXferCount = 0U;
2560
2561 /* Reset errorCode */
2562 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2563
2564 /* Clear the Error flags in the SR register */
2565 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2566
2567 /* Restore hspi->State to Ready */
2568 hspi->State = HAL_SPI_STATE_READY;
2569
2570 /* Call user Abort complete callback */
2571 HAL_SPI_AbortCpltCallback(hspi);
2572 }
2573
2574 /**
2575 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
2576 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2577 * the configuration information for SPI module.
2578 * @retval None
2579 */
2580 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
2581 {
2582 /* Receive data in 8bit mode */
2583 *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
2584 hspi->RxXferCount--;
2585
2586 /* check end of the reception */
2587 if(hspi->RxXferCount == 0U)
2588 {
2589 #if (USE_SPI_CRC != 0U)
2590 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2591 {
2592 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
2593 return;
2594 }
2595 #endif /* USE_SPI_CRC */
2596
2597 /* Disable RXNE interrupt */
2598 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
2599
2600 if(hspi->TxXferCount == 0U)
2601 {
2602 SPI_CloseRxTx_ISR(hspi);
2603 }
2604 }
2605 }
2606
2607 #if (USE_SPI_CRC != 0U)
2608 /**
2609 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
2610 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2611 * the configuration information for SPI module.
2612 * @retval None
2613 */
2614 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
2615 {
2616 __IO uint8_t tmpreg = 0U;
2617
2618 /* Read data register to flush CRC */
2619 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
2620
2621 /* To avoid GCC warning */
2622
2623 UNUSED(tmpreg);
2624
2625 /* Disable RXNE interrupt */
2626 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
2627
2628 if(hspi->TxXferCount == 0U)
2629 {
2630 SPI_CloseRxTx_ISR(hspi);
2631 }
2632 }
2633 #endif /* USE_SPI_CRC */
2634
2635 /**
2636 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
2637 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2638 * the configuration information for SPI module.
2639 * @retval None
2640 */
2641 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
2642 {
2643 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
2644 hspi->TxXferCount--;
2645
2646 /* check the end of the transmission */
2647 if(hspi->TxXferCount == 0U)
2648 {
2649 #if (USE_SPI_CRC != 0U)
2650 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2651 {
2652 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
2653 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
2654 return;
2655 }
2656 #endif /* USE_SPI_CRC */
2657
2658 /* Disable TXE interrupt */
2659 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
2660
2661 if(hspi->RxXferCount == 0U)
2662 {
2663 SPI_CloseRxTx_ISR(hspi);
2664 }
2665 }
2666 }
2667
2668 /**
2669 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
2670 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2671 * the configuration information for SPI module.
2672 * @retval None
2673 */
2674 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
2675 {
2676 /* Receive data in 16 Bit mode */
2677 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
2678 hspi->pRxBuffPtr += sizeof(uint16_t);
2679 hspi->RxXferCount--;
2680
2681 if(hspi->RxXferCount == 0U)
2682 {
2683 #if (USE_SPI_CRC != 0U)
2684 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2685 {
2686 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
2687 return;
2688 }
2689 #endif /* USE_SPI_CRC */
2690
2691 /* Disable RXNE interrupt */
2692 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
2693
2694 if(hspi->TxXferCount == 0U)
2695 {
2696 SPI_CloseRxTx_ISR(hspi);
2697 }
2698 }
2699 }
2700
2701 #if (USE_SPI_CRC != 0U)
2702 /**
2703 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
2704 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2705 * the configuration information for SPI module.
2706 * @retval None
2707 */
2708 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
2709 {
2710 /* Receive data in 16 Bit mode */
2711 __IO uint16_t tmpreg = 0U;
2712
2713 /* Read data register to flush CRC */
2714 tmpreg = hspi->Instance->DR;
2715
2716 /* To avoid GCC warning */
2717 UNUSED(tmpreg);
2718
2719 /* Disable RXNE interrupt */
2720 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
2721
2722 SPI_CloseRxTx_ISR(hspi);
2723 }
2724 #endif /* USE_SPI_CRC */
2725
2726 /**
2727 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
2728 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2729 * the configuration information for SPI module.
2730 * @retval None
2731 */
2732 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
2733 {
2734 /* Transmit data in 16 Bit mode */
2735 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
2736 hspi->pTxBuffPtr += sizeof(uint16_t);
2737 hspi->TxXferCount--;
2738
2739 /* Enable CRC Transmission */
2740 if(hspi->TxXferCount == 0U)
2741 {
2742 #if (USE_SPI_CRC != 0U)
2743 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2744 {
2745 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
2746 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
2747 return;
2748 }
2749 #endif /* USE_SPI_CRC */
2750
2751 /* Disable TXE interrupt */
2752 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
2753
2754 if(hspi->RxXferCount == 0U)
2755 {
2756 SPI_CloseRxTx_ISR(hspi);
2757 }
2758 }
2759 }
2760
2761 #if (USE_SPI_CRC != 0U)
2762 /**
2763 * @brief Manage the CRC 8-bit receive in Interrupt context.
2764 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2765 * the configuration information for SPI module.
2766 * @retval None
2767 */
2768 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
2769 {
2770 __IO uint8_t tmpreg = 0U;
2771
2772 /* Read data register to flush CRC */
2773 tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
2774
2775 /* To avoid GCC warning */
2776 UNUSED(tmpreg);
2777
2778 SPI_CloseRx_ISR(hspi);
2779 }
2780 #endif /* USE_SPI_CRC */
2781
2782 /**
2783 * @brief Manage the receive 8-bit in Interrupt context.
2784 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2785 * the configuration information for SPI module.
2786 * @retval None
2787 */
2788 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
2789 {
2790 *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
2791 hspi->RxXferCount--;
2792
2793 #if (USE_SPI_CRC != 0U)
2794 /* Enable CRC Transmission */
2795 if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
2796 {
2797 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
2798 }
2799 #endif /* USE_SPI_CRC */
2800
2801 if(hspi->RxXferCount == 0U)
2802 {
2803 #if (USE_SPI_CRC != 0U)
2804 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2805 {
2806 hspi->RxISR = SPI_RxISR_8BITCRC;
2807 return;
2808 }
2809 #endif /* USE_SPI_CRC */
2810 SPI_CloseRx_ISR(hspi);
2811 }
2812 }
2813
2814 #if (USE_SPI_CRC != 0U)
2815 /**
2816 * @brief Manage the CRC 16-bit receive in Interrupt context.
2817 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2818 * the configuration information for SPI module.
2819 * @retval None
2820 */
2821 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
2822 {
2823 __IO uint16_t tmpreg = 0U;
2824
2825 /* Read data register to flush CRC */
2826 tmpreg = hspi->Instance->DR;
2827
2828 /* To avoid GCC warning */
2829 UNUSED(tmpreg);
2830
2831 /* Disable RXNE and ERR interrupt */
2832 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
2833
2834 SPI_CloseRx_ISR(hspi);
2835 }
2836 #endif /* USE_SPI_CRC */
2837
2838 /**
2839 * @brief Manage the 16-bit receive in Interrupt context.
2840 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2841 * the configuration information for SPI module.
2842 * @retval None
2843 */
2844 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
2845 {
2846 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
2847 hspi->pRxBuffPtr += sizeof(uint16_t);
2848 hspi->RxXferCount--;
2849
2850 #if (USE_SPI_CRC != 0U)
2851 /* Enable CRC Transmission */
2852 if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
2853 {
2854 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
2855 }
2856 #endif /* USE_SPI_CRC */
2857
2858 if(hspi->RxXferCount == 0U)
2859 {
2860 #if (USE_SPI_CRC != 0U)
2861 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2862 {
2863 hspi->RxISR = SPI_RxISR_16BITCRC;
2864 return;
2865 }
2866 #endif /* USE_SPI_CRC */
2867 SPI_CloseRx_ISR(hspi);
2868 }
2869 }
2870
2871 /**
2872 * @brief Handle the data 8-bit transmit in Interrupt mode.
2873 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2874 * the configuration information for SPI module.
2875 * @retval None
2876 */
2877 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
2878 {
2879 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
2880 hspi->TxXferCount--;
2881
2882 if(hspi->TxXferCount == 0U)
2883 {
2884 #if (USE_SPI_CRC != 0U)
2885 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2886 {
2887 /* Enable CRC Transmission */
2888 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
2889 }
2890 #endif /* USE_SPI_CRC */
2891 SPI_CloseTx_ISR(hspi);
2892 }
2893 }
2894
2895 /**
2896 * @brief Handle the data 16-bit transmit in Interrupt mode.
2897 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2898 * the configuration information for SPI module.
2899 * @retval None
2900 */
2901 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
2902 {
2903 /* Transmit data in 16 Bit mode */
2904 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
2905 hspi->pTxBuffPtr += sizeof(uint16_t);
2906 hspi->TxXferCount--;
2907
2908 if(hspi->TxXferCount == 0U)
2909 {
2910 #if (USE_SPI_CRC != 0U)
2911 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2912 {
2913 /* Enable CRC Transmission */
2914 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
2915 }
2916 #endif /* USE_SPI_CRC */
2917 SPI_CloseTx_ISR(hspi);
2918 }
2919 }
2920
2921 /**
2922 * @brief Handle SPI Communication Timeout.
2923 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2924 * the configuration information for SPI module.
2925 * @param Flag: SPI flag to check
2926 * @param State: flag state to check
2927 * @param Timeout: Timeout duration
2928 * @param Tickstart: tick start value
2929 * @retval HAL status
2930 */
2931 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
2932 {
2933 while((((hspi->Instance->SR & Flag) == (Flag)) ? SET : RESET) != State)
2934 {
2935 if(Timeout != HAL_MAX_DELAY)
2936 {
2937 if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout))
2938 {
2939 /* Disable the SPI and reset the CRC: the CRC value should be cleared
2940 on both master and slave sides in order to resynchronize the master
2941 and slave for their respective CRC calculation */
2942
2943 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
2944 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
2945
2946 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
2947 {
2948 /* Disable SPI peripheral */
2949 __HAL_SPI_DISABLE(hspi);
2950 }
2951
2952 /* Reset CRC Calculation */
2953 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2954 {
2955 SPI_RESET_CRC(hspi);
2956 }
2957
2958 hspi->State= HAL_SPI_STATE_READY;
2959
2960 /* Process Unlocked */
2961 __HAL_UNLOCK(hspi);
2962
2963 return HAL_TIMEOUT;
2964 }
2965 }
2966 }
2967
2968 return HAL_OK;
2969 }
2970 /**
2971 * @brief Handle to check BSY flag before start a new transaction.
2972 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2973 * the configuration information for SPI module.
2974 * @param Timeout: Timeout duration
2975 * @param Tickstart: tick start value
2976 * @retval HAL status
2977 */
2978 static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
2979 {
2980 /* Control the BSY flag */
2981 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
2982 {
2983 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2984 return HAL_TIMEOUT;
2985 }
2986 return HAL_OK;
2987 }
2988
2989 /**
2990 * @brief Handle the end of the RXTX transaction.
2991 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2992 * the configuration information for SPI module.
2993 * @retval None
2994 */
2995 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
2996 {
2997 uint32_t tickstart = 0U;
2998 __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2999 /* Init tickstart for timeout managment*/
3000 tickstart = HAL_GetTick();
3001
3002 /* Disable ERR interrupt */
3003 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3004
3005 /* Wait until TXE flag is set */
3006 do
3007 {
3008 if(count-- == 0U)
3009 {
3010 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3011 break;
3012 }
3013 }
3014 while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
3015
3016 /* Check the end of the transaction */
3017 if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)
3018 {
3019 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3020 }
3021
3022 /* Clear overrun flag in 2 Lines communication mode because received is not read */
3023 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
3024 {
3025 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3026 }
3027
3028 #if (USE_SPI_CRC != 0U)
3029 /* Check if CRC error occurred */
3030 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
3031 {
3032 /* Check if CRC error is valid or not (workaround to be applied or not) */
3033 if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
3034 {
3035 hspi->State = HAL_SPI_STATE_READY;
3036 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3037
3038 /* Reset CRC Calculation */
3039 SPI_RESET_CRC(hspi);
3040
3041 HAL_SPI_ErrorCallback(hspi);
3042 }
3043 else
3044 {
3045 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3046 }
3047 }
3048 else
3049 {
3050 #endif /* USE_SPI_CRC */
3051 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
3052 {
3053 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
3054 {
3055 hspi->State = HAL_SPI_STATE_READY;
3056 HAL_SPI_RxCpltCallback(hspi);
3057 }
3058 else
3059 {
3060 hspi->State = HAL_SPI_STATE_READY;
3061 HAL_SPI_TxRxCpltCallback(hspi);
3062 }
3063 }
3064 else
3065 {
3066 hspi->State = HAL_SPI_STATE_READY;
3067 HAL_SPI_ErrorCallback(hspi);
3068 }
3069 #if (USE_SPI_CRC != 0U)
3070 }
3071 #endif /* USE_SPI_CRC */
3072 }
3073
3074 /**
3075 * @brief Handle the end of the RX transaction.
3076 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3077 * the configuration information for SPI module.
3078 * @retval None
3079 */
3080 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
3081 {
3082 /* Disable RXNE and ERR interrupt */
3083 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3084
3085 /* Check the end of the transaction */
3086 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3087 {
3088 /* Disable SPI peripheral */
3089 __HAL_SPI_DISABLE(hspi);
3090 }
3091
3092 /* Clear overrun flag in 2 Lines communication mode because received is not read */
3093 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
3094 {
3095 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3096 }
3097 hspi->State = HAL_SPI_STATE_READY;
3098
3099 #if (USE_SPI_CRC != 0U)
3100 /* Check if CRC error occurred */
3101 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
3102 {
3103 /* Check if CRC error is valid or not (workaround to be applied or not) */
3104 if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
3105 {
3106 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3107
3108 /* Reset CRC Calculation */
3109 SPI_RESET_CRC(hspi);
3110
3111 HAL_SPI_ErrorCallback(hspi);
3112 }
3113 else
3114 {
3115 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3116 }
3117 }
3118 else
3119 {
3120 #endif /* USE_SPI_CRC */
3121 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
3122 {
3123 HAL_SPI_RxCpltCallback(hspi);
3124 }
3125 else
3126 {
3127 HAL_SPI_ErrorCallback(hspi);
3128 }
3129 #if (USE_SPI_CRC != 0U)
3130 }
3131 #endif /* USE_SPI_CRC */
3132 }
3133
3134 /**
3135 * @brief Handle the end of the TX transaction.
3136 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3137 * the configuration information for SPI module.
3138 * @retval None
3139 */
3140 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
3141 {
3142 uint32_t tickstart = 0U;
3143 __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
3144
3145 /* Init tickstart for timeout management*/
3146 tickstart = HAL_GetTick();
3147
3148 /* Wait until TXE flag is set */
3149 do
3150 {
3151 if(count-- == 0U)
3152 {
3153 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3154 break;
3155 }
3156 }
3157 while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
3158
3159 /* Disable TXE and ERR interrupt */
3160 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
3161
3162 /* Check Busy flag */
3163 if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3164 {
3165 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3166 }
3167
3168 /* Clear overrun flag in 2 Lines communication mode because received is not read */
3169 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
3170 {
3171 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3172 }
3173
3174 hspi->State = HAL_SPI_STATE_READY;
3175 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3176 {
3177 HAL_SPI_ErrorCallback(hspi);
3178 }
3179 else
3180 {
3181 HAL_SPI_TxCpltCallback(hspi);
3182 }
3183 }
3184
3185 /**
3186 * @}
3187 */
3188
3189 /**
3190 * @brief Handle abort a Tx or Rx transaction.
3191 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3192 * the configuration information for SPI module.
3193 * @retval None
3194 */
3195 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
3196 {
3197 __IO uint32_t tmpreg = 0U;
3198 __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
3199
3200 /* Wait until TXE flag is set */
3201 do
3202 {
3203 if(count-- == 0U)
3204 {
3205 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3206 break;
3207 }
3208 }
3209 while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
3210
3211 /* Disable SPI Peripheral */
3212 __HAL_SPI_DISABLE(hspi);
3213
3214 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
3215 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
3216
3217 /* Flush DR Register */
3218 tmpreg = (*(__IO uint32_t *)&hspi->Instance->DR);
3219
3220 /* To avoid GCC warning */
3221 UNUSED(tmpreg);
3222 }
3223
3224 /**
3225 * @brief Handle abort a Tx or Rx transaction.
3226 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3227 * the configuration information for SPI module.
3228 * @retval None
3229 */
3230 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
3231 {
3232 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
3233 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
3234
3235 /* Disable SPI Peripheral */
3236 __HAL_SPI_DISABLE(hspi);
3237 }
3238
3239 /**
3240 * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
3241 * according to SPI instance, Device type, and revision ID.
3242 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3243 * the configuration information for SPI module.
3244 * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
3245 */
3246 __weak uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
3247 {
3248 /* Prevent unused argument(s) compilation warning */
3249 UNUSED(hspi);
3250
3251 return (SPI_VALID_CRC_ERROR);
3252 }
3253 /**
3254 * @}
3255 */
3256 #endif /* HAL_SPI_MODULE_ENABLED */
3257
3258 /**
3259 * @}
3260 */
3261
3262 /**
3263 * @}
3264 */
3265
3266 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/