2 ******************************************************************************
3 * @file stm32f1xx_hal_tim.c
4 * @author MCD Application Team
7 * @brief TIM HAL module driver
8 * This file provides firmware functions to manage the following
9 * functionalities of the Timer (TIM) peripheral:
10 * + Time Base Initialization
12 * + Time Base Start Interruption
13 * + Time Base Start DMA
14 * + Time Output Compare/PWM Initialization
15 * + Time Output Compare/PWM Channel Configuration
16 * + Time Output Compare/PWM Start
17 * + Time Output Compare/PWM Start Interruption
18 * + Time Output Compare/PWM Start DMA
19 * + Time Input Capture Initialization
20 * + Time Input Capture Channel Configuration
21 * + Time Input Capture Start
22 * + Time Input Capture Start Interruption
23 * + Time Input Capture Start DMA
24 * + Time One Pulse Initialization
25 * + Time One Pulse Channel Configuration
26 * + Time One Pulse Start
27 * + Time Encoder Interface Initialization
28 * + Time Encoder Interface Start
29 * + Time Encoder Interface Start Interruption
30 * + Time Encoder Interface Start DMA
31 * + Commutation Event configuration with Interruption and DMA
32 * + Time OCRef clear configuration
33 * + Time External Clock configuration
35 ==============================================================================
36 ##### TIMER Generic features #####
37 ==============================================================================
38 [..] The Timer features include:
39 (#) 16-bit up, down, up/down auto-reload counter.
40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
41 counter clock frequency either by any factor between 1 and 65536.
42 (#) Up to 4 independent channels for:
45 (++) PWM generation (Edge and Center-aligned Mode)
46 (++) One-pulse mode output
48 ##### How to use this driver #####
49 ==============================================================================
51 (#) Initialize the TIM low level resources by implementing the following functions
52 depending from feature used :
53 (++) Time Base : HAL_TIM_Base_MspInit()
54 (++) Input Capture : HAL_TIM_IC_MspInit()
55 (++) Output Compare : HAL_TIM_OC_MspInit()
56 (++) PWM generation : HAL_TIM_PWM_MspInit()
57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
60 (#) Initialize the TIM low level resources :
61 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
62 (##) TIM pins configuration
63 (+++) Enable the clock for the TIM GPIOs using the following function:
64 __HAL_RCC_GPIOx_CLK_ENABLE();
65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
67 (#) The external Clock can be configured, if needed (the default clock is the
68 internal clock from the APBx), using the following function:
69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
72 (#) Configure the TIM in the desired functioning mode using one of the
73 Initialization function of this driver:
74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
76 Output Compare signal.
77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
93 (#) The DMA Burst is managed with the two following functions:
94 HAL_TIM_DMABurst_WriteStart()
95 HAL_TIM_DMABurst_ReadStart()
98 ******************************************************************************
101 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
103 * Redistribution and use in source and binary forms, with or without modification,
104 * are permitted provided that the following conditions are met:
105 * 1. Redistributions of source code must retain the above copyright notice,
106 * this list of conditions and the following disclaimer.
107 * 2. Redistributions in binary form must reproduce the above copyright notice,
108 * this list of conditions and the following disclaimer in the documentation
109 * and/or other materials provided with the distribution.
110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
111 * may be used to endorse or promote products derived from this software
112 * without specific prior written permission.
114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
125 ******************************************************************************
128 /* Includes ------------------------------------------------------------------*/
129 #include "stm32f1xx_hal.h"
131 /** @addtogroup STM32F1xx_HAL_Driver
135 /** @defgroup TIM TIM
136 * @brief TIM HAL module driver
140 #ifdef HAL_TIM_MODULE_ENABLED
142 /* Private typedef -----------------------------------------------------------*/
143 /* Private define ------------------------------------------------------------*/
144 /* Private macro -------------------------------------------------------------*/
145 /* Private variables ---------------------------------------------------------*/
146 /* Private function prototypes -----------------------------------------------*/
147 /** @defgroup TIM_Private_Functions TIM Private Functions
150 static void TIM_OC1_SetConfig(TIM_TypeDef
*TIMx
, TIM_OC_InitTypeDef
*OC_Config
);
151 static void TIM_OC3_SetConfig(TIM_TypeDef
*TIMx
, TIM_OC_InitTypeDef
*OC_Config
);
152 static void TIM_OC4_SetConfig(TIM_TypeDef
*TIMx
, TIM_OC_InitTypeDef
*OC_Config
);
153 static void TIM_TI1_ConfigInputStage(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICFilter
);
154 static void TIM_TI2_SetConfig(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICSelection
,
155 uint32_t TIM_ICFilter
);
156 static void TIM_TI2_ConfigInputStage(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICFilter
);
157 static void TIM_TI3_SetConfig(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICSelection
,
158 uint32_t TIM_ICFilter
);
159 static void TIM_TI4_SetConfig(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICSelection
,
160 uint32_t TIM_ICFilter
);
161 static void TIM_ETR_SetConfig(TIM_TypeDef
* TIMx
, uint32_t TIM_ExtTRGPrescaler
,
162 uint32_t TIM_ExtTRGPolarity
, uint32_t ExtTRGFilter
);
163 static void TIM_ITRx_SetConfig(TIM_TypeDef
* TIMx
, uint16_t InputTriggerSource
);
164 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef
*hdma
);
165 static void TIM_DMATriggerCplt(DMA_HandleTypeDef
*hdma
);
166 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef
*htim
,
167 TIM_SlaveConfigTypeDef
* sSlaveConfig
);
173 /* Exported functions ---------------------------------------------------------*/
175 /** @defgroup TIM_Exported_Functions TIM Exported Functions
179 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
180 * @brief Time Base functions
183 ==============================================================================
184 ##### Time Base functions #####
185 ==============================================================================
187 This section provides functions allowing to:
188 (+) Initialize and configure the TIM base.
189 (+) De-initialize the TIM base.
190 (+) Start the Time Base.
191 (+) Stop the Time Base.
192 (+) Start the Time Base and enable interrupt.
193 (+) Stop the Time Base and disable interrupt.
194 (+) Start the Time Base and enable DMA transfer.
195 (+) Stop the Time Base and disable DMA transfer.
201 * @brief Initializes the TIM Time base Unit according to the specified
202 * parameters in the TIM_HandleTypeDef and create the associated handle.
203 * @param htim : TIM Base handle
206 HAL_StatusTypeDef
HAL_TIM_Base_Init(TIM_HandleTypeDef
*htim
)
208 /* Check the TIM handle allocation */
214 /* Check the parameters */
215 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
216 assert_param(IS_TIM_COUNTER_MODE(htim
->Init
.CounterMode
));
217 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim
->Init
.ClockDivision
));
218 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim
->Init
.AutoReloadPreload
));
220 if(htim
->State
== HAL_TIM_STATE_RESET
)
222 /* Allocate lock resource and initialize it */
223 htim
->Lock
= HAL_UNLOCKED
;
225 /* Init the low level hardware : GPIO, CLOCK, NVIC */
226 HAL_TIM_Base_MspInit(htim
);
229 /* Set the TIM state */
230 htim
->State
= HAL_TIM_STATE_BUSY
;
232 /* Set the Time Base configuration */
233 TIM_Base_SetConfig(htim
->Instance
, &htim
->Init
);
235 /* Initialize the TIM state*/
236 htim
->State
= HAL_TIM_STATE_READY
;
242 * @brief DeInitializes the TIM Base peripheral
243 * @param htim : TIM Base handle
246 HAL_StatusTypeDef
HAL_TIM_Base_DeInit(TIM_HandleTypeDef
*htim
)
248 /* Check the parameters */
249 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
251 htim
->State
= HAL_TIM_STATE_BUSY
;
253 /* Disable the TIM Peripheral Clock */
254 __HAL_TIM_DISABLE(htim
);
256 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
257 HAL_TIM_Base_MspDeInit(htim
);
259 /* Change TIM state */
260 htim
->State
= HAL_TIM_STATE_RESET
;
269 * @brief Initializes the TIM Base MSP.
270 * @param htim : TIM handle
273 __weak
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef
*htim
)
275 /* Prevent unused argument(s) compilation warning */
277 /* NOTE : This function Should not be modified, when the callback is needed,
278 the HAL_TIM_Base_MspInit could be implemented in the user file
283 * @brief DeInitializes TIM Base MSP.
284 * @param htim : TIM handle
287 __weak
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef
*htim
)
289 /* Prevent unused argument(s) compilation warning */
291 /* NOTE : This function Should not be modified, when the callback is needed,
292 the HAL_TIM_Base_MspDeInit could be implemented in the user file
298 * @brief Starts the TIM Base generation.
299 * @param htim : TIM handle
302 HAL_StatusTypeDef
HAL_TIM_Base_Start(TIM_HandleTypeDef
*htim
)
304 /* Check the parameters */
305 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
307 /* Set the TIM state */
308 htim
->State
= HAL_TIM_STATE_BUSY
;
310 /* Enable the Peripheral */
311 __HAL_TIM_ENABLE(htim
);
313 /* Change the TIM state*/
314 htim
->State
= HAL_TIM_STATE_READY
;
316 /* Return function status */
321 * @brief Stops the TIM Base generation.
322 * @param htim : TIM handle
325 HAL_StatusTypeDef
HAL_TIM_Base_Stop(TIM_HandleTypeDef
*htim
)
327 /* Check the parameters */
328 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
330 /* Set the TIM state */
331 htim
->State
= HAL_TIM_STATE_BUSY
;
333 /* Disable the Peripheral */
334 __HAL_TIM_DISABLE(htim
);
336 /* Change the TIM state*/
337 htim
->State
= HAL_TIM_STATE_READY
;
339 /* Return function status */
344 * @brief Starts the TIM Base generation in interrupt mode.
345 * @param htim : TIM handle
348 HAL_StatusTypeDef
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef
*htim
)
350 /* Check the parameters */
351 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
353 /* Enable the TIM Update interrupt */
354 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_UPDATE
);
356 /* Enable the Peripheral */
357 __HAL_TIM_ENABLE(htim
);
359 /* Return function status */
364 * @brief Stops the TIM Base generation in interrupt mode.
365 * @param htim : TIM handle
368 HAL_StatusTypeDef
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef
*htim
)
370 /* Check the parameters */
371 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
372 /* Disable the TIM Update interrupt */
373 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_UPDATE
);
375 /* Disable the Peripheral */
376 __HAL_TIM_DISABLE(htim
);
378 /* Return function status */
383 * @brief Starts the TIM Base generation in DMA mode.
384 * @param htim : TIM handle
385 * @param pData : The source Buffer address.
386 * @param Length : The length of data to be transferred from memory to peripheral.
389 HAL_StatusTypeDef
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef
*htim
, uint32_t *pData
, uint16_t Length
)
391 /* Check the parameters */
392 assert_param(IS_TIM_DMA_INSTANCE(htim
->Instance
));
394 if((htim
->State
== HAL_TIM_STATE_BUSY
))
398 else if((htim
->State
== HAL_TIM_STATE_READY
))
400 if((pData
== 0U) && (Length
> 0U))
406 htim
->State
= HAL_TIM_STATE_BUSY
;
409 /* Set the DMA Period elapsed callback */
410 htim
->hdma
[TIM_DMA_ID_UPDATE
]->XferCpltCallback
= TIM_DMAPeriodElapsedCplt
;
412 /* Set the DMA error callback */
413 htim
->hdma
[TIM_DMA_ID_UPDATE
]->XferErrorCallback
= TIM_DMAError
;
415 /* Enable the DMA channel */
416 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_UPDATE
], (uint32_t)pData
, (uint32_t)&htim
->Instance
->ARR
, Length
);
418 /* Enable the TIM Update DMA request */
419 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_UPDATE
);
421 /* Enable the Peripheral */
422 __HAL_TIM_ENABLE(htim
);
424 /* Return function status */
429 * @brief Stops the TIM Base generation in DMA mode.
430 * @param htim : TIM handle
433 HAL_StatusTypeDef
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef
*htim
)
435 /* Check the parameters */
436 assert_param(IS_TIM_DMA_INSTANCE(htim
->Instance
));
438 /* Disable the TIM Update DMA request */
439 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_UPDATE
);
441 /* Disable the Peripheral */
442 __HAL_TIM_DISABLE(htim
);
444 /* Change the htim state */
445 htim
->State
= HAL_TIM_STATE_READY
;
447 /* Return function status */
455 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
456 * @brief Time Output Compare functions
459 ==============================================================================
460 ##### Time Output Compare functions #####
461 ==============================================================================
463 This section provides functions allowing to:
464 (+) Initialize and configure the TIM Output Compare.
465 (+) De-initialize the TIM Output Compare.
466 (+) Start the Time Output Compare.
467 (+) Stop the Time Output Compare.
468 (+) Start the Time Output Compare and enable interrupt.
469 (+) Stop the Time Output Compare and disable interrupt.
470 (+) Start the Time Output Compare and enable DMA transfer.
471 (+) Stop the Time Output Compare and disable DMA transfer.
477 * @brief Initializes the TIM Output Compare according to the specified
478 * parameters in the TIM_HandleTypeDef and create the associated handle.
479 * @param htim : TIM Output Compare handle
482 HAL_StatusTypeDef
HAL_TIM_OC_Init(TIM_HandleTypeDef
* htim
)
484 /* Check the TIM handle allocation */
490 /* Check the parameters */
491 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
492 assert_param(IS_TIM_COUNTER_MODE(htim
->Init
.CounterMode
));
493 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim
->Init
.ClockDivision
));
494 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim
->Init
.AutoReloadPreload
));
496 if(htim
->State
== HAL_TIM_STATE_RESET
)
498 /* Allocate lock resource and initialize it */
499 htim
->Lock
= HAL_UNLOCKED
;
501 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
502 HAL_TIM_OC_MspInit(htim
);
505 /* Set the TIM state */
506 htim
->State
= HAL_TIM_STATE_BUSY
;
508 /* Init the base time for the Output Compare */
509 TIM_Base_SetConfig(htim
->Instance
, &htim
->Init
);
511 /* Initialize the TIM state*/
512 htim
->State
= HAL_TIM_STATE_READY
;
518 * @brief DeInitializes the TIM peripheral
519 * @param htim : TIM Output Compare handle
522 HAL_StatusTypeDef
HAL_TIM_OC_DeInit(TIM_HandleTypeDef
*htim
)
524 /* Check the parameters */
525 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
527 htim
->State
= HAL_TIM_STATE_BUSY
;
529 /* Disable the TIM Peripheral Clock */
530 __HAL_TIM_DISABLE(htim
);
532 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
533 HAL_TIM_OC_MspDeInit(htim
);
535 /* Change TIM state */
536 htim
->State
= HAL_TIM_STATE_RESET
;
545 * @brief Initializes the TIM Output Compare MSP.
546 * @param htim : TIM handle
549 __weak
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef
*htim
)
551 /* Prevent unused argument(s) compilation warning */
553 /* NOTE : This function Should not be modified, when the callback is needed,
554 the HAL_TIM_OC_MspInit could be implemented in the user file
559 * @brief DeInitializes TIM Output Compare MSP.
560 * @param htim : TIM handle
563 __weak
void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef
*htim
)
565 /* Prevent unused argument(s) compilation warning */
567 /* NOTE : This function Should not be modified, when the callback is needed,
568 the HAL_TIM_OC_MspDeInit could be implemented in the user file
573 * @brief Starts the TIM Output Compare signal generation.
574 * @param htim : TIM Output Compare handle
575 * @param Channel : TIM Channel to be enabled
576 * This parameter can be one of the following values:
577 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
578 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
579 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
580 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
583 HAL_StatusTypeDef
HAL_TIM_OC_Start(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
585 /* Check the parameters */
586 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
588 /* Enable the Output compare channel */
589 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_ENABLE
);
591 if(IS_TIM_BREAK_INSTANCE(htim
->Instance
) != RESET
)
593 /* Enable the main output */
594 __HAL_TIM_MOE_ENABLE(htim
);
597 /* Enable the Peripheral */
598 __HAL_TIM_ENABLE(htim
);
600 /* Return function status */
605 * @brief Stops the TIM Output Compare signal generation.
606 * @param htim : TIM handle
607 * @param Channel : TIM Channel to be disabled
608 * This parameter can be one of the following values:
609 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
610 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
611 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
612 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
615 HAL_StatusTypeDef
HAL_TIM_OC_Stop(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
617 /* Check the parameters */
618 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
620 /* Disable the Output compare channel */
621 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_DISABLE
);
623 if(IS_TIM_BREAK_INSTANCE(htim
->Instance
) != RESET
)
625 /* Disable the Main Ouput */
626 __HAL_TIM_MOE_DISABLE(htim
);
629 /* Disable the Peripheral */
630 __HAL_TIM_DISABLE(htim
);
632 /* Return function status */
637 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
638 * @param htim : TIM OC handle
639 * @param Channel : TIM Channel to be enabled
640 * This parameter can be one of the following values:
641 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
642 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
643 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
644 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
647 HAL_StatusTypeDef
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
649 /* Check the parameters */
650 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
656 /* Enable the TIM Capture/Compare 1 interrupt */
657 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC1
);
663 /* Enable the TIM Capture/Compare 2 interrupt */
664 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC2
);
670 /* Enable the TIM Capture/Compare 3 interrupt */
671 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC3
);
677 /* Enable the TIM Capture/Compare 4 interrupt */
678 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC4
);
686 /* Enable the Output compare channel */
687 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_ENABLE
);
689 if(IS_TIM_BREAK_INSTANCE(htim
->Instance
) != RESET
)
691 /* Enable the main output */
692 __HAL_TIM_MOE_ENABLE(htim
);
695 /* Enable the Peripheral */
696 __HAL_TIM_ENABLE(htim
);
698 /* Return function status */
703 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
704 * @param htim : TIM Output Compare handle
705 * @param Channel : TIM Channel to be disabled
706 * This parameter can be one of the following values:
707 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
708 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
709 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
710 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
713 HAL_StatusTypeDef
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
715 /* Check the parameters */
716 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
722 /* Disable the TIM Capture/Compare 1 interrupt */
723 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC1
);
729 /* Disable the TIM Capture/Compare 2 interrupt */
730 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC2
);
736 /* Disable the TIM Capture/Compare 3 interrupt */
737 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC3
);
743 /* Disable the TIM Capture/Compare 4 interrupt */
744 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC4
);
752 /* Disable the Output compare channel */
753 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_DISABLE
);
755 if(IS_TIM_BREAK_INSTANCE(htim
->Instance
) != RESET
)
757 /* Disable the Main Ouput */
758 __HAL_TIM_MOE_DISABLE(htim
);
761 /* Disable the Peripheral */
762 __HAL_TIM_DISABLE(htim
);
764 /* Return function status */
769 * @brief Starts the TIM Output Compare signal generation in DMA mode.
770 * @param htim : TIM Output Compare handle
771 * @param Channel : TIM Channel to be enabled
772 * This parameter can be one of the following values:
773 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
774 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
775 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
776 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
777 * @param pData : The source Buffer address.
778 * @param Length : The length of data to be transferred from memory to TIM peripheral
781 HAL_StatusTypeDef
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef
*htim
, uint32_t Channel
, uint32_t *pData
, uint16_t Length
)
783 /* Check the parameters */
784 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
786 if((htim
->State
== HAL_TIM_STATE_BUSY
))
790 else if((htim
->State
== HAL_TIM_STATE_READY
))
792 if(((uint32_t)pData
== 0U) && (Length
> 0U))
798 htim
->State
= HAL_TIM_STATE_BUSY
;
805 /* Set the DMA Period elapsed callback */
806 htim
->hdma
[TIM_DMA_ID_CC1
]->XferCpltCallback
= TIM_DMADelayPulseCplt
;
808 /* Set the DMA error callback */
809 htim
->hdma
[TIM_DMA_ID_CC1
]->XferErrorCallback
= TIM_DMAError
;
811 /* Enable the DMA channel */
812 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC1
], (uint32_t)pData
, (uint32_t)&htim
->Instance
->CCR1
, Length
);
814 /* Enable the TIM Capture/Compare 1 DMA request */
815 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC1
);
821 /* Set the DMA Period elapsed callback */
822 htim
->hdma
[TIM_DMA_ID_CC2
]->XferCpltCallback
= TIM_DMADelayPulseCplt
;
824 /* Set the DMA error callback */
825 htim
->hdma
[TIM_DMA_ID_CC2
]->XferErrorCallback
= TIM_DMAError
;
827 /* Enable the DMA channel */
828 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC2
], (uint32_t)pData
, (uint32_t)&htim
->Instance
->CCR2
, Length
);
830 /* Enable the TIM Capture/Compare 2 DMA request */
831 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC2
);
837 /* Set the DMA Period elapsed callback */
838 htim
->hdma
[TIM_DMA_ID_CC3
]->XferCpltCallback
= TIM_DMADelayPulseCplt
;
840 /* Set the DMA error callback */
841 htim
->hdma
[TIM_DMA_ID_CC3
]->XferErrorCallback
= TIM_DMAError
;
843 /* Enable the DMA channel */
844 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC3
], (uint32_t)pData
, (uint32_t)&htim
->Instance
->CCR3
,Length
);
846 /* Enable the TIM Capture/Compare 3 DMA request */
847 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC3
);
853 /* Set the DMA Period elapsed callback */
854 htim
->hdma
[TIM_DMA_ID_CC4
]->XferCpltCallback
= TIM_DMADelayPulseCplt
;
856 /* Set the DMA error callback */
857 htim
->hdma
[TIM_DMA_ID_CC4
]->XferErrorCallback
= TIM_DMAError
;
859 /* Enable the DMA channel */
860 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC4
], (uint32_t)pData
, (uint32_t)&htim
->Instance
->CCR4
, Length
);
862 /* Enable the TIM Capture/Compare 4 DMA request */
863 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC4
);
871 /* Enable the Output compare channel */
872 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_ENABLE
);
874 if(IS_TIM_BREAK_INSTANCE(htim
->Instance
) != RESET
)
876 /* Enable the main output */
877 __HAL_TIM_MOE_ENABLE(htim
);
880 /* Enable the Peripheral */
881 __HAL_TIM_ENABLE(htim
);
883 /* Return function status */
888 * @brief Stops the TIM Output Compare signal generation in DMA mode.
889 * @param htim : TIM Output Compare handle
890 * @param Channel : TIM Channel to be disabled
891 * This parameter can be one of the following values:
892 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
893 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
894 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
895 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
898 HAL_StatusTypeDef
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
900 /* Check the parameters */
901 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
907 /* Disable the TIM Capture/Compare 1 DMA request */
908 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC1
);
914 /* Disable the TIM Capture/Compare 2 DMA request */
915 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC2
);
921 /* Disable the TIM Capture/Compare 3 DMA request */
922 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC3
);
928 /* Disable the TIM Capture/Compare 4 interrupt */
929 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC4
);
937 /* Disable the Output compare channel */
938 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_DISABLE
);
940 if(IS_TIM_BREAK_INSTANCE(htim
->Instance
) != RESET
)
942 /* Disable the Main Ouput */
943 __HAL_TIM_MOE_DISABLE(htim
);
946 /* Disable the Peripheral */
947 __HAL_TIM_DISABLE(htim
);
949 /* Change the htim state */
950 htim
->State
= HAL_TIM_STATE_READY
;
952 /* Return function status */
960 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
961 * @brief Time PWM functions
964 ==============================================================================
965 ##### Time PWM functions #####
966 ==============================================================================
968 This section provides functions allowing to:
969 (+) Initialize and configure the TIM PWM.
970 (+) De-initialize the TIM PWM.
971 (+) Start the Time PWM.
972 (+) Stop the Time PWM.
973 (+) Start the Time PWM and enable interrupt.
974 (+) Stop the Time PWM and disable interrupt.
975 (+) Start the Time PWM and enable DMA transfer.
976 (+) Stop the Time PWM and disable DMA transfer.
982 * @brief Initializes the TIM PWM Time Base according to the specified
983 * parameters in the TIM_HandleTypeDef and create the associated handle.
984 * @param htim : TIM handle
987 HAL_StatusTypeDef
HAL_TIM_PWM_Init(TIM_HandleTypeDef
*htim
)
989 /* Check the TIM handle allocation */
995 /* Check the parameters */
996 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
997 assert_param(IS_TIM_COUNTER_MODE(htim
->Init
.CounterMode
));
998 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim
->Init
.ClockDivision
));
999 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim
->Init
.AutoReloadPreload
));
1001 if(htim
->State
== HAL_TIM_STATE_RESET
)
1003 /* Allocate lock resource and initialize it */
1004 htim
->Lock
= HAL_UNLOCKED
;
1006 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1007 HAL_TIM_PWM_MspInit(htim
);
1010 /* Set the TIM state */
1011 htim
->State
= HAL_TIM_STATE_BUSY
;
1013 /* Init the base time for the PWM */
1014 TIM_Base_SetConfig(htim
->Instance
, &htim
->Init
);
1016 /* Initialize the TIM state*/
1017 htim
->State
= HAL_TIM_STATE_READY
;
1023 * @brief DeInitializes the TIM peripheral
1024 * @param htim : TIM handle
1025 * @retval HAL status
1027 HAL_StatusTypeDef
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef
*htim
)
1029 /* Check the parameters */
1030 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
1032 htim
->State
= HAL_TIM_STATE_BUSY
;
1034 /* Disable the TIM Peripheral Clock */
1035 __HAL_TIM_DISABLE(htim
);
1037 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1038 HAL_TIM_PWM_MspDeInit(htim
);
1040 /* Change TIM state */
1041 htim
->State
= HAL_TIM_STATE_RESET
;
1050 * @brief Initializes the TIM PWM MSP.
1051 * @param htim : TIM handle
1054 __weak
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef
*htim
)
1056 /* Prevent unused argument(s) compilation warning */
1058 /* NOTE : This function Should not be modified, when the callback is needed,
1059 the HAL_TIM_PWM_MspInit could be implemented in the user file
1064 * @brief DeInitializes TIM PWM MSP.
1065 * @param htim : TIM handle
1068 __weak
void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef
*htim
)
1070 /* Prevent unused argument(s) compilation warning */
1072 /* NOTE : This function Should not be modified, when the callback is needed,
1073 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1078 * @brief Starts the PWM signal generation.
1079 * @param htim : TIM handle
1080 * @param Channel : TIM Channels to be enabled
1081 * This parameter can be one of the following values:
1082 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1083 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1084 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1085 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1086 * @retval HAL status
1088 HAL_StatusTypeDef
HAL_TIM_PWM_Start(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1090 /* Check the parameters */
1091 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1093 /* Enable the Capture compare channel */
1094 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_ENABLE
);
1096 if(IS_TIM_BREAK_INSTANCE(htim
->Instance
) != RESET
)
1098 /* Enable the main output */
1099 __HAL_TIM_MOE_ENABLE(htim
);
1102 /* Enable the Peripheral */
1103 __HAL_TIM_ENABLE(htim
);
1105 /* Return function status */
1110 * @brief Stops the PWM signal generation.
1111 * @param htim : TIM handle
1112 * @param Channel : TIM Channels to be disabled
1113 * This parameter can be one of the following values:
1114 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1115 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1116 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1117 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1118 * @retval HAL status
1120 HAL_StatusTypeDef
HAL_TIM_PWM_Stop(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1122 /* Check the parameters */
1123 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1125 /* Disable the Capture compare channel */
1126 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_DISABLE
);
1128 if(IS_TIM_BREAK_INSTANCE(htim
->Instance
) != RESET
)
1130 /* Disable the Main Ouput */
1131 __HAL_TIM_MOE_DISABLE(htim
);
1134 /* Disable the Peripheral */
1135 __HAL_TIM_DISABLE(htim
);
1137 /* Change the htim state */
1138 htim
->State
= HAL_TIM_STATE_READY
;
1140 /* Return function status */
1145 * @brief Starts the PWM signal generation in interrupt mode.
1146 * @param htim : TIM handle
1147 * @param Channel : TIM Channel to be enabled
1148 * This parameter can be one of the following values:
1149 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1150 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1151 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1152 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1153 * @retval HAL status
1155 HAL_StatusTypeDef
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1157 /* Check the parameters */
1158 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1164 /* Enable the TIM Capture/Compare 1 interrupt */
1165 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC1
);
1171 /* Enable the TIM Capture/Compare 2 interrupt */
1172 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC2
);
1178 /* Enable the TIM Capture/Compare 3 interrupt */
1179 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC3
);
1185 /* Enable the TIM Capture/Compare 4 interrupt */
1186 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC4
);
1194 /* Enable the Capture compare channel */
1195 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_ENABLE
);
1197 if(IS_TIM_BREAK_INSTANCE(htim
->Instance
) != RESET
)
1199 /* Enable the main output */
1200 __HAL_TIM_MOE_ENABLE(htim
);
1203 /* Enable the Peripheral */
1204 __HAL_TIM_ENABLE(htim
);
1206 /* Return function status */
1211 * @brief Stops the PWM signal generation in interrupt mode.
1212 * @param htim : TIM handle
1213 * @param Channel : TIM Channels to be disabled
1214 * This parameter can be one of the following values:
1215 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1216 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1217 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1218 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1219 * @retval HAL status
1221 HAL_StatusTypeDef
HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1223 /* Check the parameters */
1224 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1230 /* Disable the TIM Capture/Compare 1 interrupt */
1231 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC1
);
1237 /* Disable the TIM Capture/Compare 2 interrupt */
1238 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC2
);
1244 /* Disable the TIM Capture/Compare 3 interrupt */
1245 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC3
);
1251 /* Disable the TIM Capture/Compare 4 interrupt */
1252 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC4
);
1260 /* Disable the Capture compare channel */
1261 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_DISABLE
);
1263 if(IS_TIM_BREAK_INSTANCE(htim
->Instance
) != RESET
)
1265 /* Disable the Main Ouput */
1266 __HAL_TIM_MOE_DISABLE(htim
);
1269 /* Disable the Peripheral */
1270 __HAL_TIM_DISABLE(htim
);
1272 /* Return function status */
1277 * @brief Starts the TIM PWM signal generation in DMA mode.
1278 * @param htim : TIM handle
1279 * @param Channel : TIM Channels to be enabled
1280 * This parameter can be one of the following values:
1281 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1282 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1283 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1284 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1285 * @param pData : The source Buffer address.
1286 * @param Length : The length of data to be transferred from memory to TIM peripheral
1287 * @retval HAL status
1289 HAL_StatusTypeDef
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef
*htim
, uint32_t Channel
, uint32_t *pData
, uint16_t Length
)
1291 /* Check the parameters */
1292 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1294 if((htim
->State
== HAL_TIM_STATE_BUSY
))
1298 else if((htim
->State
== HAL_TIM_STATE_READY
))
1300 if(((uint32_t)pData
== 0U) && (Length
> 0U))
1306 htim
->State
= HAL_TIM_STATE_BUSY
;
1313 /* Set the DMA Period elapsed callback */
1314 htim
->hdma
[TIM_DMA_ID_CC1
]->XferCpltCallback
= TIM_DMADelayPulseCplt
;
1316 /* Set the DMA error callback */
1317 htim
->hdma
[TIM_DMA_ID_CC1
]->XferErrorCallback
= TIM_DMAError
;
1319 /* Enable the DMA channel */
1320 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC1
], (uint32_t)pData
, (uint32_t)&htim
->Instance
->CCR1
, Length
);
1322 /* Enable the TIM Capture/Compare 1 DMA request */
1323 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC1
);
1329 /* Set the DMA Period elapsed callback */
1330 htim
->hdma
[TIM_DMA_ID_CC2
]->XferCpltCallback
= TIM_DMADelayPulseCplt
;
1332 /* Set the DMA error callback */
1333 htim
->hdma
[TIM_DMA_ID_CC2
]->XferErrorCallback
= TIM_DMAError
;
1335 /* Enable the DMA channel */
1336 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC2
], (uint32_t)pData
, (uint32_t)&htim
->Instance
->CCR2
, Length
);
1338 /* Enable the TIM Capture/Compare 2 DMA request */
1339 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC2
);
1345 /* Set the DMA Period elapsed callback */
1346 htim
->hdma
[TIM_DMA_ID_CC3
]->XferCpltCallback
= TIM_DMADelayPulseCplt
;
1348 /* Set the DMA error callback */
1349 htim
->hdma
[TIM_DMA_ID_CC3
]->XferErrorCallback
= TIM_DMAError
;
1351 /* Enable the DMA channel */
1352 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC3
], (uint32_t)pData
, (uint32_t)&htim
->Instance
->CCR3
,Length
);
1354 /* Enable the TIM Output Capture/Compare 3 request */
1355 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC3
);
1361 /* Set the DMA Period elapsed callback */
1362 htim
->hdma
[TIM_DMA_ID_CC4
]->XferCpltCallback
= TIM_DMADelayPulseCplt
;
1364 /* Set the DMA error callback */
1365 htim
->hdma
[TIM_DMA_ID_CC4
]->XferErrorCallback
= TIM_DMAError
;
1367 /* Enable the DMA channel */
1368 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC4
], (uint32_t)pData
, (uint32_t)&htim
->Instance
->CCR4
, Length
);
1370 /* Enable the TIM Capture/Compare 4 DMA request */
1371 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC4
);
1379 /* Enable the Capture compare channel */
1380 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_ENABLE
);
1382 if(IS_TIM_BREAK_INSTANCE(htim
->Instance
) != RESET
)
1384 /* Enable the main output */
1385 __HAL_TIM_MOE_ENABLE(htim
);
1388 /* Enable the Peripheral */
1389 __HAL_TIM_ENABLE(htim
);
1391 /* Return function status */
1396 * @brief Stops the TIM PWM signal generation in DMA mode.
1397 * @param htim : TIM handle
1398 * @param Channel : TIM Channels to be disabled
1399 * This parameter can be one of the following values:
1400 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1401 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1402 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1403 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1404 * @retval HAL status
1406 HAL_StatusTypeDef
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1408 /* Check the parameters */
1409 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1415 /* Disable the TIM Capture/Compare 1 DMA request */
1416 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC1
);
1422 /* Disable the TIM Capture/Compare 2 DMA request */
1423 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC2
);
1429 /* Disable the TIM Capture/Compare 3 DMA request */
1430 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC3
);
1436 /* Disable the TIM Capture/Compare 4 interrupt */
1437 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC4
);
1445 /* Disable the Capture compare channel */
1446 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_DISABLE
);
1448 if(IS_TIM_BREAK_INSTANCE(htim
->Instance
) != RESET
)
1450 /* Disable the Main Ouput */
1451 __HAL_TIM_MOE_DISABLE(htim
);
1454 /* Disable the Peripheral */
1455 __HAL_TIM_DISABLE(htim
);
1457 /* Change the htim state */
1458 htim
->State
= HAL_TIM_STATE_READY
;
1460 /* Return function status */
1468 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
1469 * @brief Time Input Capture functions
1472 ==============================================================================
1473 ##### Time Input Capture functions #####
1474 ==============================================================================
1476 This section provides functions allowing to:
1477 (+) Initialize and configure the TIM Input Capture.
1478 (+) De-initialize the TIM Input Capture.
1479 (+) Start the Time Input Capture.
1480 (+) Stop the Time Input Capture.
1481 (+) Start the Time Input Capture and enable interrupt.
1482 (+) Stop the Time Input Capture and disable interrupt.
1483 (+) Start the Time Input Capture and enable DMA transfer.
1484 (+) Stop the Time Input Capture and disable DMA transfer.
1490 * @brief Initializes the TIM Input Capture Time base according to the specified
1491 * parameters in the TIM_HandleTypeDef and create the associated handle.
1492 * @param htim : TIM Input Capture handle
1493 * @retval HAL status
1495 HAL_StatusTypeDef
HAL_TIM_IC_Init(TIM_HandleTypeDef
*htim
)
1497 /* Check the TIM handle allocation */
1503 /* Check the parameters */
1504 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
1505 assert_param(IS_TIM_COUNTER_MODE(htim
->Init
.CounterMode
));
1506 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim
->Init
.ClockDivision
));
1507 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim
->Init
.AutoReloadPreload
));
1509 if(htim
->State
== HAL_TIM_STATE_RESET
)
1511 /* Allocate lock resource and initialize it */
1512 htim
->Lock
= HAL_UNLOCKED
;
1514 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1515 HAL_TIM_IC_MspInit(htim
);
1518 /* Set the TIM state */
1519 htim
->State
= HAL_TIM_STATE_BUSY
;
1521 /* Init the base time for the input capture */
1522 TIM_Base_SetConfig(htim
->Instance
, &htim
->Init
);
1524 /* Initialize the TIM state*/
1525 htim
->State
= HAL_TIM_STATE_READY
;
1531 * @brief DeInitializes the TIM peripheral
1532 * @param htim : TIM Input Capture handle
1533 * @retval HAL status
1535 HAL_StatusTypeDef
HAL_TIM_IC_DeInit(TIM_HandleTypeDef
*htim
)
1537 /* Check the parameters */
1538 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
1540 htim
->State
= HAL_TIM_STATE_BUSY
;
1542 /* Disable the TIM Peripheral Clock */
1543 __HAL_TIM_DISABLE(htim
);
1545 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1546 HAL_TIM_IC_MspDeInit(htim
);
1548 /* Change TIM state */
1549 htim
->State
= HAL_TIM_STATE_RESET
;
1558 * @brief Initializes the TIM Input Capture MSP.
1559 * @param htim : TIM handle
1562 __weak
void HAL_TIM_IC_MspInit(TIM_HandleTypeDef
*htim
)
1564 /* Prevent unused argument(s) compilation warning */
1566 /* NOTE : This function Should not be modified, when the callback is needed,
1567 the HAL_TIM_IC_MspInit could be implemented in the user file
1572 * @brief DeInitializes TIM Input Capture MSP.
1573 * @param htim : TIM handle
1576 __weak
void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef
*htim
)
1578 /* Prevent unused argument(s) compilation warning */
1580 /* NOTE : This function Should not be modified, when the callback is needed,
1581 the HAL_TIM_IC_MspDeInit could be implemented in the user file
1586 * @brief Starts the TIM Input Capture measurement.
1587 * @param htim : TIM Input Capture handle
1588 * @param Channel : TIM Channels to be enabled
1589 * This parameter can be one of the following values:
1590 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1591 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1592 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1593 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1594 * @retval HAL status
1596 HAL_StatusTypeDef
HAL_TIM_IC_Start (TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1598 /* Check the parameters */
1599 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1601 /* Enable the Input Capture channel */
1602 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_ENABLE
);
1604 /* Enable the Peripheral */
1605 __HAL_TIM_ENABLE(htim
);
1607 /* Return function status */
1612 * @brief Stops the TIM Input Capture measurement.
1613 * @param htim : TIM handle
1614 * @param Channel : TIM Channels to be disabled
1615 * This parameter can be one of the following values:
1616 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1617 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1618 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1619 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1620 * @retval HAL status
1622 HAL_StatusTypeDef
HAL_TIM_IC_Stop(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1624 /* Check the parameters */
1625 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1627 /* Disable the Input Capture channel */
1628 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_DISABLE
);
1630 /* Disable the Peripheral */
1631 __HAL_TIM_DISABLE(htim
);
1633 /* Return function status */
1638 * @brief Starts the TIM Input Capture measurement in interrupt mode.
1639 * @param htim : TIM Input Capture handle
1640 * @param Channel : TIM Channels to be enabled
1641 * This parameter can be one of the following values:
1642 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1643 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1644 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1645 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1646 * @retval HAL status
1648 HAL_StatusTypeDef
HAL_TIM_IC_Start_IT (TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1650 /* Check the parameters */
1651 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1657 /* Enable the TIM Capture/Compare 1 interrupt */
1658 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC1
);
1664 /* Enable the TIM Capture/Compare 2 interrupt */
1665 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC2
);
1671 /* Enable the TIM Capture/Compare 3 interrupt */
1672 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC3
);
1678 /* Enable the TIM Capture/Compare 4 interrupt */
1679 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC4
);
1686 /* Enable the Input Capture channel */
1687 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_ENABLE
);
1689 /* Enable the Peripheral */
1690 __HAL_TIM_ENABLE(htim
);
1692 /* Return function status */
1697 * @brief Stops the TIM Input Capture measurement in interrupt mode.
1698 * @param htim : TIM handle
1699 * @param Channel : TIM Channels to be disabled
1700 * This parameter can be one of the following values:
1701 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1702 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1703 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1704 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1705 * @retval HAL status
1707 HAL_StatusTypeDef
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1709 /* Check the parameters */
1710 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1716 /* Disable the TIM Capture/Compare 1 interrupt */
1717 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC1
);
1723 /* Disable the TIM Capture/Compare 2 interrupt */
1724 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC2
);
1730 /* Disable the TIM Capture/Compare 3 interrupt */
1731 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC3
);
1737 /* Disable the TIM Capture/Compare 4 interrupt */
1738 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC4
);
1746 /* Disable the Input Capture channel */
1747 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_DISABLE
);
1749 /* Disable the Peripheral */
1750 __HAL_TIM_DISABLE(htim
);
1752 /* Return function status */
1757 * @brief Starts the TIM Input Capture measurement in DMA mode.
1758 * @param htim : TIM Input Capture handle
1759 * @param Channel : TIM Channels to be enabled
1760 * This parameter can be one of the following values:
1761 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1762 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1763 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1764 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1765 * @param pData : The destination Buffer address.
1766 * @param Length : The length of data to be transferred from TIM peripheral to memory.
1767 * @retval HAL status
1769 HAL_StatusTypeDef
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef
*htim
, uint32_t Channel
, uint32_t *pData
, uint16_t Length
)
1771 /* Check the parameters */
1772 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1773 assert_param(IS_TIM_DMA_CC_INSTANCE(htim
->Instance
));
1775 if((htim
->State
== HAL_TIM_STATE_BUSY
))
1779 else if((htim
->State
== HAL_TIM_STATE_READY
))
1781 if((pData
== 0U) && (Length
> 0U))
1787 htim
->State
= HAL_TIM_STATE_BUSY
;
1795 /* Set the DMA Period elapsed callback */
1796 htim
->hdma
[TIM_DMA_ID_CC1
]->XferCpltCallback
= TIM_DMACaptureCplt
;
1798 /* Set the DMA error callback */
1799 htim
->hdma
[TIM_DMA_ID_CC1
]->XferErrorCallback
= TIM_DMAError
;
1801 /* Enable the DMA channel */
1802 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC1
], (uint32_t)&htim
->Instance
->CCR1
, (uint32_t)pData
, Length
);
1804 /* Enable the TIM Capture/Compare 1 DMA request */
1805 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC1
);
1811 /* Set the DMA Period elapsed callback */
1812 htim
->hdma
[TIM_DMA_ID_CC2
]->XferCpltCallback
= TIM_DMACaptureCplt
;
1814 /* Set the DMA error callback */
1815 htim
->hdma
[TIM_DMA_ID_CC2
]->XferErrorCallback
= TIM_DMAError
;
1817 /* Enable the DMA channel */
1818 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC2
], (uint32_t)&htim
->Instance
->CCR2
, (uint32_t)pData
, Length
);
1820 /* Enable the TIM Capture/Compare 2 DMA request */
1821 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC2
);
1827 /* Set the DMA Period elapsed callback */
1828 htim
->hdma
[TIM_DMA_ID_CC3
]->XferCpltCallback
= TIM_DMACaptureCplt
;
1830 /* Set the DMA error callback */
1831 htim
->hdma
[TIM_DMA_ID_CC3
]->XferErrorCallback
= TIM_DMAError
;
1833 /* Enable the DMA channel */
1834 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC3
], (uint32_t)&htim
->Instance
->CCR3
, (uint32_t)pData
, Length
);
1836 /* Enable the TIM Capture/Compare 3 DMA request */
1837 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC3
);
1843 /* Set the DMA Period elapsed callback */
1844 htim
->hdma
[TIM_DMA_ID_CC4
]->XferCpltCallback
= TIM_DMACaptureCplt
;
1846 /* Set the DMA error callback */
1847 htim
->hdma
[TIM_DMA_ID_CC4
]->XferErrorCallback
= TIM_DMAError
;
1849 /* Enable the DMA channel */
1850 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC4
], (uint32_t)&htim
->Instance
->CCR4
, (uint32_t)pData
, Length
);
1852 /* Enable the TIM Capture/Compare 4 DMA request */
1853 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC4
);
1861 /* Enable the Input Capture channel */
1862 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_ENABLE
);
1864 /* Enable the Peripheral */
1865 __HAL_TIM_ENABLE(htim
);
1867 /* Return function status */
1872 * @brief Stops the TIM Input Capture measurement in DMA mode.
1873 * @param htim : TIM Input Capture handle
1874 * @param Channel : TIM Channels to be disabled
1875 * This parameter can be one of the following values:
1876 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1877 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1878 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1879 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1880 * @retval HAL status
1882 HAL_StatusTypeDef
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1884 /* Check the parameters */
1885 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1886 assert_param(IS_TIM_DMA_CC_INSTANCE(htim
->Instance
));
1892 /* Disable the TIM Capture/Compare 1 DMA request */
1893 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC1
);
1899 /* Disable the TIM Capture/Compare 2 DMA request */
1900 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC2
);
1906 /* Disable the TIM Capture/Compare 3 DMA request */
1907 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC3
);
1913 /* Disable the TIM Capture/Compare 4 DMA request */
1914 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC4
);
1922 /* Disable the Input Capture channel */
1923 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_DISABLE
);
1925 /* Disable the Peripheral */
1926 __HAL_TIM_DISABLE(htim
);
1928 /* Change the htim state */
1929 htim
->State
= HAL_TIM_STATE_READY
;
1931 /* Return function status */
1938 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
1939 * @brief Time One Pulse functions
1942 ==============================================================================
1943 ##### Time One Pulse functions #####
1944 ==============================================================================
1946 This section provides functions allowing to:
1947 (+) Initialize and configure the TIM One Pulse.
1948 (+) De-initialize the TIM One Pulse.
1949 (+) Start the Time One Pulse.
1950 (+) Stop the Time One Pulse.
1951 (+) Start the Time One Pulse and enable interrupt.
1952 (+) Stop the Time One Pulse and disable interrupt.
1953 (+) Start the Time One Pulse and enable DMA transfer.
1954 (+) Stop the Time One Pulse and disable DMA transfer.
1960 * @brief Initializes the TIM One Pulse Time Base according to the specified
1961 * parameters in the TIM_HandleTypeDef and create the associated handle.
1962 * @param htim : TIM OnePulse handle
1963 * @param OnePulseMode : Select the One pulse mode.
1964 * This parameter can be one of the following values:
1965 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
1966 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
1967 * @retval HAL status
1969 HAL_StatusTypeDef
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef
*htim
, uint32_t OnePulseMode
)
1971 /* Check the TIM handle allocation */
1977 /* Check the parameters */
1978 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
1979 assert_param(IS_TIM_COUNTER_MODE(htim
->Init
.CounterMode
));
1980 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim
->Init
.ClockDivision
));
1981 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim
->Init
.AutoReloadPreload
));
1982 assert_param(IS_TIM_OPM_MODE(OnePulseMode
));
1984 if(htim
->State
== HAL_TIM_STATE_RESET
)
1986 /* Allocate lock resource and initialize it */
1987 htim
->Lock
= HAL_UNLOCKED
;
1989 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1990 HAL_TIM_OnePulse_MspInit(htim
);
1993 /* Set the TIM state */
1994 htim
->State
= HAL_TIM_STATE_BUSY
;
1996 /* Configure the Time base in the One Pulse Mode */
1997 TIM_Base_SetConfig(htim
->Instance
, &htim
->Init
);
1999 /* Reset the OPM Bit */
2000 htim
->Instance
->CR1
&= ~TIM_CR1_OPM
;
2002 /* Configure the OPM Mode */
2003 htim
->Instance
->CR1
|= OnePulseMode
;
2005 /* Initialize the TIM state*/
2006 htim
->State
= HAL_TIM_STATE_READY
;
2012 * @brief DeInitializes the TIM One Pulse
2013 * @param htim : TIM One Pulse handle
2014 * @retval HAL status
2016 HAL_StatusTypeDef
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef
*htim
)
2018 /* Check the parameters */
2019 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
2021 htim
->State
= HAL_TIM_STATE_BUSY
;
2023 /* Disable the TIM Peripheral Clock */
2024 __HAL_TIM_DISABLE(htim
);
2026 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2027 HAL_TIM_OnePulse_MspDeInit(htim
);
2029 /* Change TIM state */
2030 htim
->State
= HAL_TIM_STATE_RESET
;
2039 * @brief Initializes the TIM One Pulse MSP.
2040 * @param htim : TIM handle
2043 __weak
void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef
*htim
)
2045 /* Prevent unused argument(s) compilation warning */
2047 /* NOTE : This function Should not be modified, when the callback is needed,
2048 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2053 * @brief DeInitializes TIM One Pulse MSP.
2054 * @param htim : TIM handle
2057 __weak
void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef
*htim
)
2059 /* Prevent unused argument(s) compilation warning */
2061 /* NOTE : This function Should not be modified, when the callback is needed,
2062 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2067 * @brief Starts the TIM One Pulse signal generation.
2068 * @param htim : TIM One Pulse handle
2069 * @param OutputChannel : TIM Channels to be enabled
2070 * This parameter can be one of the following values:
2071 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2072 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2073 * @retval HAL status
2075 HAL_StatusTypeDef
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef
*htim
, uint32_t OutputChannel
)
2077 /* Prevent unused argument(s) compilation warning */
2078 UNUSED(OutputChannel
);
2080 /* Enable the Capture compare and the Input Capture channels
2081 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2082 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2083 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2084 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2086 No need to enable the counter, it's enabled automatically by hardware
2087 (the counter starts in response to a stimulus and generate a pulse */
2089 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_ENABLE
);
2090 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_ENABLE
);
2092 if(IS_TIM_BREAK_INSTANCE(htim
->Instance
) != RESET
)
2094 /* Enable the main output */
2095 __HAL_TIM_MOE_ENABLE(htim
);
2098 /* Return function status */
2103 * @brief Stops the TIM One Pulse signal generation.
2104 * @param htim : TIM One Pulse handle
2105 * @param OutputChannel : TIM Channels to be disable
2106 * This parameter can be one of the following values:
2107 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2108 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2109 * @retval HAL status
2111 HAL_StatusTypeDef
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef
*htim
, uint32_t OutputChannel
)
2113 /* Prevent unused argument(s) compilation warning */
2114 UNUSED(OutputChannel
);
2116 /* Disable the Capture compare and the Input Capture channels
2117 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2118 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2119 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2120 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2122 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_DISABLE
);
2123 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_DISABLE
);
2125 if(IS_TIM_BREAK_INSTANCE(htim
->Instance
) != RESET
)
2127 /* Disable the Main Ouput */
2128 __HAL_TIM_MOE_DISABLE(htim
);
2131 /* Disable the Peripheral */
2132 __HAL_TIM_DISABLE(htim
);
2134 /* Return function status */
2139 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2140 * @param htim : TIM One Pulse handle
2141 * @param OutputChannel : TIM Channels to be enabled
2142 * This parameter can be one of the following values:
2143 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2144 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2145 * @retval HAL status
2147 HAL_StatusTypeDef
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef
*htim
, uint32_t OutputChannel
)
2149 /* Prevent unused argument(s) compilation warning */
2150 UNUSED(OutputChannel
);
2152 /* Enable the Capture compare and the Input Capture channels
2153 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2154 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2155 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2156 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2158 No need to enable the counter, it's enabled automatically by hardware
2159 (the counter starts in response to a stimulus and generate a pulse */
2161 /* Enable the TIM Capture/Compare 1 interrupt */
2162 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC1
);
2164 /* Enable the TIM Capture/Compare 2 interrupt */
2165 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC2
);
2167 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_ENABLE
);
2168 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_ENABLE
);
2170 if(IS_TIM_BREAK_INSTANCE(htim
->Instance
) != RESET
)
2172 /* Enable the main output */
2173 __HAL_TIM_MOE_ENABLE(htim
);
2176 /* Return function status */
2181 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2182 * @param htim : TIM One Pulse handle
2183 * @param OutputChannel : TIM Channels to be enabled
2184 * This parameter can be one of the following values:
2185 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2186 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2187 * @retval HAL status
2189 HAL_StatusTypeDef
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef
*htim
, uint32_t OutputChannel
)
2191 /* Prevent unused argument(s) compilation warning */
2192 UNUSED(OutputChannel
);
2194 /* Disable the TIM Capture/Compare 1 interrupt */
2195 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC1
);
2197 /* Disable the TIM Capture/Compare 2 interrupt */
2198 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC2
);
2200 /* Disable the Capture compare and the Input Capture channels
2201 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2202 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2203 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2204 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2205 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_DISABLE
);
2206 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_DISABLE
);
2208 if(IS_TIM_BREAK_INSTANCE(htim
->Instance
) != RESET
)
2210 /* Disable the Main Ouput */
2211 __HAL_TIM_MOE_DISABLE(htim
);
2214 /* Disable the Peripheral */
2215 __HAL_TIM_DISABLE(htim
);
2217 /* Return function status */
2225 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
2226 * @brief Time Encoder functions
2229 ==============================================================================
2230 ##### Time Encoder functions #####
2231 ==============================================================================
2233 This section provides functions allowing to:
2234 (+) Initialize and configure the TIM Encoder.
2235 (+) De-initialize the TIM Encoder.
2236 (+) Start the Time Encoder.
2237 (+) Stop the Time Encoder.
2238 (+) Start the Time Encoder and enable interrupt.
2239 (+) Stop the Time Encoder and disable interrupt.
2240 (+) Start the Time Encoder and enable DMA transfer.
2241 (+) Stop the Time Encoder and disable DMA transfer.
2247 * @brief Initializes the TIM Encoder Interface and create the associated handle.
2248 * @param htim : TIM Encoder Interface handle
2249 * @param sConfig : TIM Encoder Interface configuration structure
2250 * @retval HAL status
2252 HAL_StatusTypeDef
HAL_TIM_Encoder_Init(TIM_HandleTypeDef
*htim
, TIM_Encoder_InitTypeDef
* sConfig
)
2254 uint32_t tmpsmcr
= 0U;
2255 uint32_t tmpccmr1
= 0U;
2256 uint32_t tmpccer
= 0U;
2258 /* Check the TIM handle allocation */
2264 /* Check the parameters */
2265 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
2266 assert_param(IS_TIM_COUNTER_MODE(htim
->Init
.CounterMode
));
2267 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim
->Init
.ClockDivision
));
2268 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim
->Init
.AutoReloadPreload
));
2269 assert_param(IS_TIM_ENCODER_MODE(sConfig
->EncoderMode
));
2270 assert_param(IS_TIM_IC_SELECTION(sConfig
->IC1Selection
));
2271 assert_param(IS_TIM_IC_SELECTION(sConfig
->IC2Selection
));
2272 assert_param(IS_TIM_IC_POLARITY(sConfig
->IC1Polarity
));
2273 assert_param(IS_TIM_IC_POLARITY(sConfig
->IC2Polarity
));
2274 assert_param(IS_TIM_IC_PRESCALER(sConfig
->IC1Prescaler
));
2275 assert_param(IS_TIM_IC_PRESCALER(sConfig
->IC2Prescaler
));
2276 assert_param(IS_TIM_IC_FILTER(sConfig
->IC1Filter
));
2277 assert_param(IS_TIM_IC_FILTER(sConfig
->IC2Filter
));
2279 if(htim
->State
== HAL_TIM_STATE_RESET
)
2281 /* Allocate lock resource and initialize it */
2282 htim
->Lock
= HAL_UNLOCKED
;
2284 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2285 HAL_TIM_Encoder_MspInit(htim
);
2288 /* Set the TIM state */
2289 htim
->State
= HAL_TIM_STATE_BUSY
;
2291 /* Reset the SMS bits */
2292 htim
->Instance
->SMCR
&= ~TIM_SMCR_SMS
;
2294 /* Configure the Time base in the Encoder Mode */
2295 TIM_Base_SetConfig(htim
->Instance
, &htim
->Init
);
2297 /* Get the TIMx SMCR register value */
2298 tmpsmcr
= htim
->Instance
->SMCR
;
2300 /* Get the TIMx CCMR1 register value */
2301 tmpccmr1
= htim
->Instance
->CCMR1
;
2303 /* Get the TIMx CCER register value */
2304 tmpccer
= htim
->Instance
->CCER
;
2306 /* Set the encoder Mode */
2307 tmpsmcr
|= sConfig
->EncoderMode
;
2309 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2310 tmpccmr1
&= ~(TIM_CCMR1_CC1S
| TIM_CCMR1_CC2S
);
2311 tmpccmr1
|= (sConfig
->IC1Selection
| (sConfig
->IC2Selection
<< 8U));
2313 /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2314 tmpccmr1
&= ~(TIM_CCMR1_IC1PSC
| TIM_CCMR1_IC2PSC
);
2315 tmpccmr1
&= ~(TIM_CCMR1_IC1F
| TIM_CCMR1_IC2F
);
2316 tmpccmr1
|= sConfig
->IC1Prescaler
| (sConfig
->IC2Prescaler
<< 8U);
2317 tmpccmr1
|= (sConfig
->IC1Filter
<< 4U) | (sConfig
->IC2Filter
<< 12U);
2319 /* Set the TI1 and the TI2 Polarities */
2320 tmpccer
&= ~(TIM_CCER_CC1P
| TIM_CCER_CC2P
);
2321 tmpccer
&= ~(TIM_CCER_CC1NP
| TIM_CCER_CC2NP
);
2322 tmpccer
|= sConfig
->IC1Polarity
| (sConfig
->IC2Polarity
<< 4U);
2324 /* Write to TIMx SMCR */
2325 htim
->Instance
->SMCR
= tmpsmcr
;
2327 /* Write to TIMx CCMR1 */
2328 htim
->Instance
->CCMR1
= tmpccmr1
;
2330 /* Write to TIMx CCER */
2331 htim
->Instance
->CCER
= tmpccer
;
2333 /* Initialize the TIM state*/
2334 htim
->State
= HAL_TIM_STATE_READY
;
2341 * @brief DeInitializes the TIM Encoder interface
2342 * @param htim : TIM Encoder handle
2343 * @retval HAL status
2345 HAL_StatusTypeDef
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef
*htim
)
2347 /* Check the parameters */
2348 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
2350 htim
->State
= HAL_TIM_STATE_BUSY
;
2352 /* Disable the TIM Peripheral Clock */
2353 __HAL_TIM_DISABLE(htim
);
2355 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2356 HAL_TIM_Encoder_MspDeInit(htim
);
2358 /* Change TIM state */
2359 htim
->State
= HAL_TIM_STATE_RESET
;
2368 * @brief Initializes the TIM Encoder Interface MSP.
2369 * @param htim : TIM handle
2372 __weak
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef
*htim
)
2374 /* Prevent unused argument(s) compilation warning */
2376 /* NOTE : This function Should not be modified, when the callback is needed,
2377 the HAL_TIM_Encoder_MspInit could be implemented in the user file
2382 * @brief DeInitializes TIM Encoder Interface MSP.
2383 * @param htim : TIM handle
2386 __weak
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef
*htim
)
2388 /* Prevent unused argument(s) compilation warning */
2390 /* NOTE : This function Should not be modified, when the callback is needed,
2391 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
2396 * @brief Starts the TIM Encoder Interface.
2397 * @param htim : TIM Encoder Interface handle
2398 * @param Channel : TIM Channels to be enabled
2399 * This parameter can be one of the following values:
2400 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2401 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2402 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2403 * @retval HAL status
2405 HAL_StatusTypeDef
HAL_TIM_Encoder_Start(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
2407 /* Check the parameters */
2408 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
2410 /* Enable the encoder interface channels */
2415 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_ENABLE
);
2420 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_ENABLE
);
2425 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_ENABLE
);
2426 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_ENABLE
);
2430 /* Enable the Peripheral */
2431 __HAL_TIM_ENABLE(htim
);
2433 /* Return function status */
2438 * @brief Stops the TIM Encoder Interface.
2439 * @param htim : TIM Encoder Interface handle
2440 * @param Channel : TIM Channels to be disabled
2441 * This parameter can be one of the following values:
2442 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2443 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2444 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2445 * @retval HAL status
2447 HAL_StatusTypeDef
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
2449 /* Check the parameters */
2450 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
2452 /* Disable the Input Capture channels 1 and 2
2453 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2458 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_DISABLE
);
2463 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_DISABLE
);
2468 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_DISABLE
);
2469 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_DISABLE
);
2474 /* Disable the Peripheral */
2475 __HAL_TIM_DISABLE(htim
);
2477 /* Return function status */
2482 * @brief Starts the TIM Encoder Interface in interrupt mode.
2483 * @param htim : TIM Encoder Interface handle
2484 * @param Channel : TIM Channels to be enabled
2485 * This parameter can be one of the following values:
2486 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2487 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2488 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2489 * @retval HAL status
2491 HAL_StatusTypeDef
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
2493 /* Check the parameters */
2494 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
2496 /* Enable the encoder interface channels */
2497 /* Enable the capture compare Interrupts 1 and/or 2 */
2502 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_ENABLE
);
2503 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC1
);
2508 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_ENABLE
);
2509 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC2
);
2514 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_ENABLE
);
2515 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_ENABLE
);
2516 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC1
);
2517 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC2
);
2522 /* Enable the Peripheral */
2523 __HAL_TIM_ENABLE(htim
);
2525 /* Return function status */
2530 * @brief Stops the TIM Encoder Interface in interrupt mode.
2531 * @param htim : TIM Encoder Interface handle
2532 * @param Channel : TIM Channels to be disabled
2533 * This parameter can be one of the following values:
2534 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2535 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2536 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2537 * @retval HAL status
2539 HAL_StatusTypeDef
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
2541 /* Check the parameters */
2542 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
2544 /* Disable the Input Capture channels 1 and 2
2545 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2546 if(Channel
== TIM_CHANNEL_1
)
2548 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_DISABLE
);
2550 /* Disable the capture compare Interrupts 1 */
2551 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC1
);
2553 else if(Channel
== TIM_CHANNEL_2
)
2555 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_DISABLE
);
2557 /* Disable the capture compare Interrupts 2 */
2558 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC2
);
2562 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_DISABLE
);
2563 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_DISABLE
);
2565 /* Disable the capture compare Interrupts 1 and 2 */
2566 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC1
);
2567 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC2
);
2570 /* Disable the Peripheral */
2571 __HAL_TIM_DISABLE(htim
);
2573 /* Change the htim state */
2574 htim
->State
= HAL_TIM_STATE_READY
;
2576 /* Return function status */
2581 * @brief Starts the TIM Encoder Interface in DMA mode.
2582 * @param htim : TIM Encoder Interface handle
2583 * @param Channel : TIM Channels to be enabled
2584 * This parameter can be one of the following values:
2585 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2586 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2587 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2588 * @param pData1 : The destination Buffer address for IC1.
2589 * @param pData2 : The destination Buffer address for IC2.
2590 * @param Length : The length of data to be transferred from TIM peripheral to memory.
2591 * @retval HAL status
2593 HAL_StatusTypeDef
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef
*htim
, uint32_t Channel
, uint32_t *pData1
, uint32_t *pData2
, uint16_t Length
)
2595 /* Check the parameters */
2596 assert_param(IS_TIM_DMA_CC_INSTANCE(htim
->Instance
));
2598 if((htim
->State
== HAL_TIM_STATE_BUSY
))
2602 else if((htim
->State
== HAL_TIM_STATE_READY
))
2604 if((((pData1
== 0U) || (pData2
== 0U) )) && (Length
> 0U))
2610 htim
->State
= HAL_TIM_STATE_BUSY
;
2618 /* Set the DMA Period elapsed callback */
2619 htim
->hdma
[TIM_DMA_ID_CC1
]->XferCpltCallback
= TIM_DMACaptureCplt
;
2621 /* Set the DMA error callback */
2622 htim
->hdma
[TIM_DMA_ID_CC1
]->XferErrorCallback
= TIM_DMAError
;
2624 /* Enable the DMA channel */
2625 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC1
], (uint32_t)&htim
->Instance
->CCR1
, (uint32_t )pData1
, Length
);
2627 /* Enable the TIM Input Capture DMA request */
2628 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC1
);
2630 /* Enable the Peripheral */
2631 __HAL_TIM_ENABLE(htim
);
2633 /* Enable the Capture compare channel */
2634 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_ENABLE
);
2640 /* Set the DMA Period elapsed callback */
2641 htim
->hdma
[TIM_DMA_ID_CC2
]->XferCpltCallback
= TIM_DMACaptureCplt
;
2643 /* Set the DMA error callback */
2644 htim
->hdma
[TIM_DMA_ID_CC2
]->XferErrorCallback
= TIM_DMAError
;
2645 /* Enable the DMA channel */
2646 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC2
], (uint32_t)&htim
->Instance
->CCR2
, (uint32_t)pData2
, Length
);
2648 /* Enable the TIM Input Capture DMA request */
2649 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC2
);
2651 /* Enable the Peripheral */
2652 __HAL_TIM_ENABLE(htim
);
2654 /* Enable the Capture compare channel */
2655 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_ENABLE
);
2659 case TIM_CHANNEL_ALL
:
2661 /* Set the DMA Period elapsed callback */
2662 htim
->hdma
[TIM_DMA_ID_CC1
]->XferCpltCallback
= TIM_DMACaptureCplt
;
2664 /* Set the DMA error callback */
2665 htim
->hdma
[TIM_DMA_ID_CC1
]->XferErrorCallback
= TIM_DMAError
;
2667 /* Enable the DMA channel */
2668 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC1
], (uint32_t)&htim
->Instance
->CCR1
, (uint32_t)pData1
, Length
);
2670 /* Set the DMA Period elapsed callback */
2671 htim
->hdma
[TIM_DMA_ID_CC2
]->XferCpltCallback
= TIM_DMACaptureCplt
;
2673 /* Set the DMA error callback */
2674 htim
->hdma
[TIM_DMA_ID_CC2
]->XferErrorCallback
= TIM_DMAError
;
2676 /* Enable the DMA channel */
2677 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC2
], (uint32_t)&htim
->Instance
->CCR2
, (uint32_t)pData2
, Length
);
2679 /* Enable the Peripheral */
2680 __HAL_TIM_ENABLE(htim
);
2682 /* Enable the Capture compare channel */
2683 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_ENABLE
);
2684 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_ENABLE
);
2686 /* Enable the TIM Input Capture DMA request */
2687 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC1
);
2688 /* Enable the TIM Input Capture DMA request */
2689 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC2
);
2696 /* Return function status */
2701 * @brief Stops the TIM Encoder Interface in DMA mode.
2702 * @param htim : TIM Encoder Interface handle
2703 * @param Channel : TIM Channels to be enabled
2704 * This parameter can be one of the following values:
2705 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2706 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2707 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2708 * @retval HAL status
2710 HAL_StatusTypeDef
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
2712 /* Check the parameters */
2713 assert_param(IS_TIM_DMA_CC_INSTANCE(htim
->Instance
));
2715 /* Disable the Input Capture channels 1 and 2
2716 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2717 if(Channel
== TIM_CHANNEL_1
)
2719 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_DISABLE
);
2721 /* Disable the capture compare DMA Request 1 */
2722 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC1
);
2724 else if(Channel
== TIM_CHANNEL_2
)
2726 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_DISABLE
);
2728 /* Disable the capture compare DMA Request 2 */
2729 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC2
);
2733 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_DISABLE
);
2734 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_DISABLE
);
2736 /* Disable the capture compare DMA Request 1 and 2 */
2737 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC1
);
2738 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC2
);
2741 /* Disable the Peripheral */
2742 __HAL_TIM_DISABLE(htim
);
2744 /* Change the htim state */
2745 htim
->State
= HAL_TIM_STATE_READY
;
2747 /* Return function status */
2754 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
2755 * @brief IRQ handler management
2758 ==============================================================================
2759 ##### IRQ handler management #####
2760 ==============================================================================
2762 This section provides Timer IRQ handler function.
2768 * @brief This function handles TIM interrupts requests.
2769 * @param htim : TIM handle
2772 void HAL_TIM_IRQHandler(TIM_HandleTypeDef
*htim
)
2774 /* Capture compare 1 event */
2775 if(__HAL_TIM_GET_FLAG(htim
, TIM_FLAG_CC1
) != RESET
)
2777 if(__HAL_TIM_GET_IT_SOURCE(htim
, TIM_IT_CC1
) !=RESET
)
2780 __HAL_TIM_CLEAR_IT(htim
, TIM_IT_CC1
);
2781 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_1
;
2783 /* Input capture event */
2784 if((htim
->Instance
->CCMR1
& TIM_CCMR1_CC1S
) != 0x00U
)
2786 HAL_TIM_IC_CaptureCallback(htim
);
2788 /* Output compare event */
2791 HAL_TIM_OC_DelayElapsedCallback(htim
);
2792 HAL_TIM_PWM_PulseFinishedCallback(htim
);
2794 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_CLEARED
;
2798 /* Capture compare 2 event */
2799 if(__HAL_TIM_GET_FLAG(htim
, TIM_FLAG_CC2
) != RESET
)
2801 if(__HAL_TIM_GET_IT_SOURCE(htim
, TIM_IT_CC2
) !=RESET
)
2803 __HAL_TIM_CLEAR_IT(htim
, TIM_IT_CC2
);
2804 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_2
;
2805 /* Input capture event */
2806 if((htim
->Instance
->CCMR1
& TIM_CCMR1_CC2S
) != 0x00U
)
2808 HAL_TIM_IC_CaptureCallback(htim
);
2810 /* Output compare event */
2813 HAL_TIM_OC_DelayElapsedCallback(htim
);
2814 HAL_TIM_PWM_PulseFinishedCallback(htim
);
2816 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_CLEARED
;
2819 /* Capture compare 3 event */
2820 if(__HAL_TIM_GET_FLAG(htim
, TIM_FLAG_CC3
) != RESET
)
2822 if(__HAL_TIM_GET_IT_SOURCE(htim
, TIM_IT_CC3
) !=RESET
)
2824 __HAL_TIM_CLEAR_IT(htim
, TIM_IT_CC3
);
2825 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_3
;
2826 /* Input capture event */
2827 if((htim
->Instance
->CCMR2
& TIM_CCMR2_CC3S
) != 0x00U
)
2829 HAL_TIM_IC_CaptureCallback(htim
);
2831 /* Output compare event */
2834 HAL_TIM_OC_DelayElapsedCallback(htim
);
2835 HAL_TIM_PWM_PulseFinishedCallback(htim
);
2837 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_CLEARED
;
2840 /* Capture compare 4 event */
2841 if(__HAL_TIM_GET_FLAG(htim
, TIM_FLAG_CC4
) != RESET
)
2843 if(__HAL_TIM_GET_IT_SOURCE(htim
, TIM_IT_CC4
) !=RESET
)
2845 __HAL_TIM_CLEAR_IT(htim
, TIM_IT_CC4
);
2846 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_4
;
2847 /* Input capture event */
2848 if((htim
->Instance
->CCMR2
& TIM_CCMR2_CC4S
) != 0x00U
)
2850 HAL_TIM_IC_CaptureCallback(htim
);
2852 /* Output compare event */
2855 HAL_TIM_OC_DelayElapsedCallback(htim
);
2856 HAL_TIM_PWM_PulseFinishedCallback(htim
);
2858 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_CLEARED
;
2861 /* TIM Update event */
2862 if(__HAL_TIM_GET_FLAG(htim
, TIM_FLAG_UPDATE
) != RESET
)
2864 if(__HAL_TIM_GET_IT_SOURCE(htim
, TIM_IT_UPDATE
) !=RESET
)
2866 __HAL_TIM_CLEAR_IT(htim
, TIM_IT_UPDATE
);
2867 HAL_TIM_PeriodElapsedCallback(htim
);
2870 /* TIM Break input event */
2871 if(__HAL_TIM_GET_FLAG(htim
, TIM_FLAG_BREAK
) != RESET
)
2873 if(__HAL_TIM_GET_IT_SOURCE(htim
, TIM_IT_BREAK
) !=RESET
)
2875 __HAL_TIM_CLEAR_IT(htim
, TIM_IT_BREAK
);
2876 HAL_TIMEx_BreakCallback(htim
);
2879 /* TIM Trigger detection event */
2880 if(__HAL_TIM_GET_FLAG(htim
, TIM_FLAG_TRIGGER
) != RESET
)
2882 if(__HAL_TIM_GET_IT_SOURCE(htim
, TIM_IT_TRIGGER
) !=RESET
)
2884 __HAL_TIM_CLEAR_IT(htim
, TIM_IT_TRIGGER
);
2885 HAL_TIM_TriggerCallback(htim
);
2888 /* TIM commutation event */
2889 if(__HAL_TIM_GET_FLAG(htim
, TIM_FLAG_COM
) != RESET
)
2891 if(__HAL_TIM_GET_IT_SOURCE(htim
, TIM_IT_COM
) !=RESET
)
2893 __HAL_TIM_CLEAR_IT(htim
, TIM_FLAG_COM
);
2894 HAL_TIMEx_CommutationCallback(htim
);
2903 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
2904 * @brief Peripheral Control functions
2907 ==============================================================================
2908 ##### Peripheral Control functions #####
2909 ==============================================================================
2911 This section provides functions allowing to:
2912 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
2913 (+) Configure External Clock source.
2914 (+) Configure Complementary channels, break features and dead time.
2915 (+) Configure Master and the Slave synchronization.
2916 (+) Configure the DMA Burst Mode.
2923 * @brief Initializes the TIM Output Compare Channels according to the specified
2924 * parameters in the TIM_OC_InitTypeDef.
2925 * @param htim : TIM Output Compare handle
2926 * @param sConfig : TIM Output Compare configuration structure
2927 * @param Channel : TIM Channels to be enabled
2928 * This parameter can be one of the following values:
2929 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2930 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2931 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2932 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2933 * @retval HAL status
2935 HAL_StatusTypeDef
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef
*htim
, TIM_OC_InitTypeDef
* sConfig
, uint32_t Channel
)
2937 /* Check the parameters */
2938 assert_param(IS_TIM_CHANNELS(Channel
));
2939 assert_param(IS_TIM_OC_MODE(sConfig
->OCMode
));
2940 assert_param(IS_TIM_OC_POLARITY(sConfig
->OCPolarity
));
2942 /* Check input state */
2945 htim
->State
= HAL_TIM_STATE_BUSY
;
2951 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
2952 /* Configure the TIM Channel 1 in Output Compare */
2953 TIM_OC1_SetConfig(htim
->Instance
, sConfig
);
2959 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
2960 /* Configure the TIM Channel 2 in Output Compare */
2961 TIM_OC2_SetConfig(htim
->Instance
, sConfig
);
2967 assert_param(IS_TIM_CC3_INSTANCE(htim
->Instance
));
2968 /* Configure the TIM Channel 3 in Output Compare */
2969 TIM_OC3_SetConfig(htim
->Instance
, sConfig
);
2975 assert_param(IS_TIM_CC4_INSTANCE(htim
->Instance
));
2976 /* Configure the TIM Channel 4 in Output Compare */
2977 TIM_OC4_SetConfig(htim
->Instance
, sConfig
);
2984 htim
->State
= HAL_TIM_STATE_READY
;
2992 * @brief Initializes the TIM Input Capture Channels according to the specified
2993 * parameters in the TIM_IC_InitTypeDef.
2994 * @param htim : TIM IC handle
2995 * @param sConfig : TIM Input Capture configuration structure
2996 * @param Channel : TIM Channels to be enabled
2997 * This parameter can be one of the following values:
2998 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2999 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3000 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3001 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3002 * @retval HAL status
3004 HAL_StatusTypeDef
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef
*htim
, TIM_IC_InitTypeDef
* sConfig
, uint32_t Channel
)
3006 /* Check the parameters */
3007 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
3008 assert_param(IS_TIM_IC_POLARITY(sConfig
->ICPolarity
));
3009 assert_param(IS_TIM_IC_SELECTION(sConfig
->ICSelection
));
3010 assert_param(IS_TIM_IC_PRESCALER(sConfig
->ICPrescaler
));
3011 assert_param(IS_TIM_IC_FILTER(sConfig
->ICFilter
));
3015 htim
->State
= HAL_TIM_STATE_BUSY
;
3017 if (Channel
== TIM_CHANNEL_1
)
3019 /* TI1 Configuration */
3020 TIM_TI1_SetConfig(htim
->Instance
,
3021 sConfig
->ICPolarity
,
3022 sConfig
->ICSelection
,
3025 /* Reset the IC1PSC Bits */
3026 htim
->Instance
->CCMR1
&= ~TIM_CCMR1_IC1PSC
;
3028 /* Set the IC1PSC value */
3029 htim
->Instance
->CCMR1
|= sConfig
->ICPrescaler
;
3031 else if (Channel
== TIM_CHANNEL_2
)
3033 /* TI2 Configuration */
3034 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
3036 TIM_TI2_SetConfig(htim
->Instance
,
3037 sConfig
->ICPolarity
,
3038 sConfig
->ICSelection
,
3041 /* Reset the IC2PSC Bits */
3042 htim
->Instance
->CCMR1
&= ~TIM_CCMR1_IC2PSC
;
3044 /* Set the IC2PSC value */
3045 htim
->Instance
->CCMR1
|= (sConfig
->ICPrescaler
<< 8U);
3047 else if (Channel
== TIM_CHANNEL_3
)
3049 /* TI3 Configuration */
3050 assert_param(IS_TIM_CC3_INSTANCE(htim
->Instance
));
3052 TIM_TI3_SetConfig(htim
->Instance
,
3053 sConfig
->ICPolarity
,
3054 sConfig
->ICSelection
,
3057 /* Reset the IC3PSC Bits */
3058 htim
->Instance
->CCMR2
&= ~TIM_CCMR2_IC3PSC
;
3060 /* Set the IC3PSC value */
3061 htim
->Instance
->CCMR2
|= sConfig
->ICPrescaler
;
3065 /* TI4 Configuration */
3066 assert_param(IS_TIM_CC4_INSTANCE(htim
->Instance
));
3068 TIM_TI4_SetConfig(htim
->Instance
,
3069 sConfig
->ICPolarity
,
3070 sConfig
->ICSelection
,
3073 /* Reset the IC4PSC Bits */
3074 htim
->Instance
->CCMR2
&= ~TIM_CCMR2_IC4PSC
;
3076 /* Set the IC4PSC value */
3077 htim
->Instance
->CCMR2
|= (sConfig
->ICPrescaler
<< 8U);
3080 htim
->State
= HAL_TIM_STATE_READY
;
3088 * @brief Initializes the TIM PWM channels according to the specified
3089 * parameters in the TIM_OC_InitTypeDef.
3090 * @param htim : TIM handle
3091 * @param sConfig : TIM PWM configuration structure
3092 * @param Channel : TIM Channels to be enabled
3093 * This parameter can be one of the following values:
3094 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3095 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3096 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3097 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3098 * @retval HAL status
3100 HAL_StatusTypeDef
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef
*htim
, TIM_OC_InitTypeDef
* sConfig
, uint32_t Channel
)
3104 /* Check the parameters */
3105 assert_param(IS_TIM_CHANNELS(Channel
));
3106 assert_param(IS_TIM_PWM_MODE(sConfig
->OCMode
));
3107 assert_param(IS_TIM_OC_POLARITY(sConfig
->OCPolarity
));
3108 assert_param(IS_TIM_FAST_STATE(sConfig
->OCFastMode
));
3110 htim
->State
= HAL_TIM_STATE_BUSY
;
3116 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
3117 /* Configure the Channel 1 in PWM mode */
3118 TIM_OC1_SetConfig(htim
->Instance
, sConfig
);
3120 /* Set the Preload enable bit for channel1 */
3121 htim
->Instance
->CCMR1
|= TIM_CCMR1_OC1PE
;
3123 /* Configure the Output Fast mode */
3124 htim
->Instance
->CCMR1
&= ~TIM_CCMR1_OC1FE
;
3125 htim
->Instance
->CCMR1
|= sConfig
->OCFastMode
;
3131 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
3132 /* Configure the Channel 2 in PWM mode */
3133 TIM_OC2_SetConfig(htim
->Instance
, sConfig
);
3135 /* Set the Preload enable bit for channel2 */
3136 htim
->Instance
->CCMR1
|= TIM_CCMR1_OC2PE
;
3138 /* Configure the Output Fast mode */
3139 htim
->Instance
->CCMR1
&= ~TIM_CCMR1_OC2FE
;
3140 htim
->Instance
->CCMR1
|= sConfig
->OCFastMode
<< 8;
3146 assert_param(IS_TIM_CC3_INSTANCE(htim
->Instance
));
3147 /* Configure the Channel 3 in PWM mode */
3148 TIM_OC3_SetConfig(htim
->Instance
, sConfig
);
3150 /* Set the Preload enable bit for channel3 */
3151 htim
->Instance
->CCMR2
|= TIM_CCMR2_OC3PE
;
3153 /* Configure the Output Fast mode */
3154 htim
->Instance
->CCMR2
&= ~TIM_CCMR2_OC3FE
;
3155 htim
->Instance
->CCMR2
|= sConfig
->OCFastMode
;
3161 assert_param(IS_TIM_CC4_INSTANCE(htim
->Instance
));
3162 /* Configure the Channel 4 in PWM mode */
3163 TIM_OC4_SetConfig(htim
->Instance
, sConfig
);
3165 /* Set the Preload enable bit for channel4 */
3166 htim
->Instance
->CCMR2
|= TIM_CCMR2_OC4PE
;
3168 /* Configure the Output Fast mode */
3169 htim
->Instance
->CCMR2
&= ~TIM_CCMR2_OC4FE
;
3170 htim
->Instance
->CCMR2
|= sConfig
->OCFastMode
<< 8;
3178 htim
->State
= HAL_TIM_STATE_READY
;
3186 * @brief Initializes the TIM One Pulse Channels according to the specified
3187 * parameters in the TIM_OnePulse_InitTypeDef.
3188 * @param htim : TIM One Pulse handle
3189 * @param sConfig : TIM One Pulse configuration structure
3190 * @param OutputChannel : TIM Channels to be enabled
3191 * This parameter can be one of the following values:
3192 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3193 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3194 * @param InputChannel : TIM Channels to be enabled
3195 * This parameter can be one of the following values:
3196 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3197 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3198 * @retval HAL status
3200 HAL_StatusTypeDef
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef
*htim
, TIM_OnePulse_InitTypeDef
* sConfig
, uint32_t OutputChannel
, uint32_t InputChannel
)
3202 TIM_OC_InitTypeDef temp1
;
3204 /* Check the parameters */
3205 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel
));
3206 assert_param(IS_TIM_OPM_CHANNELS(InputChannel
));
3208 if(OutputChannel
!= InputChannel
)
3212 htim
->State
= HAL_TIM_STATE_BUSY
;
3214 /* Extract the Ouput compare configuration from sConfig structure */
3215 temp1
.OCMode
= sConfig
->OCMode
;
3216 temp1
.Pulse
= sConfig
->Pulse
;
3217 temp1
.OCPolarity
= sConfig
->OCPolarity
;
3218 temp1
.OCNPolarity
= sConfig
->OCNPolarity
;
3219 temp1
.OCIdleState
= sConfig
->OCIdleState
;
3220 temp1
.OCNIdleState
= sConfig
->OCNIdleState
;
3222 switch (OutputChannel
)
3226 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
3228 TIM_OC1_SetConfig(htim
->Instance
, &temp1
);
3233 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
3235 TIM_OC2_SetConfig(htim
->Instance
, &temp1
);
3241 switch (InputChannel
)
3245 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
3247 TIM_TI1_SetConfig(htim
->Instance
, sConfig
->ICPolarity
,
3248 sConfig
->ICSelection
, sConfig
->ICFilter
);
3250 /* Reset the IC1PSC Bits */
3251 htim
->Instance
->CCMR1
&= ~TIM_CCMR1_IC1PSC
;
3253 /* Select the Trigger source */
3254 htim
->Instance
->SMCR
&= ~TIM_SMCR_TS
;
3255 htim
->Instance
->SMCR
|= TIM_TS_TI1FP1
;
3257 /* Select the Slave Mode */
3258 htim
->Instance
->SMCR
&= ~TIM_SMCR_SMS
;
3259 htim
->Instance
->SMCR
|= TIM_SLAVEMODE_TRIGGER
;
3264 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
3266 TIM_TI2_SetConfig(htim
->Instance
, sConfig
->ICPolarity
,
3267 sConfig
->ICSelection
, sConfig
->ICFilter
);
3269 /* Reset the IC2PSC Bits */
3270 htim
->Instance
->CCMR1
&= ~TIM_CCMR1_IC2PSC
;
3272 /* Select the Trigger source */
3273 htim
->Instance
->SMCR
&= ~TIM_SMCR_TS
;
3274 htim
->Instance
->SMCR
|= TIM_TS_TI2FP2
;
3276 /* Select the Slave Mode */
3277 htim
->Instance
->SMCR
&= ~TIM_SMCR_SMS
;
3278 htim
->Instance
->SMCR
|= TIM_SLAVEMODE_TRIGGER
;
3286 htim
->State
= HAL_TIM_STATE_READY
;
3299 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
3300 * @param htim : TIM handle
3301 * @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write
3302 * This parameter can be one of the following values:
3303 * @arg TIM_DMABASE_CR1
3304 * @arg TIM_DMABASE_CR2
3305 * @arg TIM_DMABASE_SMCR
3306 * @arg TIM_DMABASE_DIER
3307 * @arg TIM_DMABASE_SR
3308 * @arg TIM_DMABASE_EGR
3309 * @arg TIM_DMABASE_CCMR1
3310 * @arg TIM_DMABASE_CCMR2
3311 * @arg TIM_DMABASE_CCER
3312 * @arg TIM_DMABASE_CNT
3313 * @arg TIM_DMABASE_PSC
3314 * @arg TIM_DMABASE_ARR
3315 * @arg TIM_DMABASE_RCR
3316 * @arg TIM_DMABASE_CCR1
3317 * @arg TIM_DMABASE_CCR2
3318 * @arg TIM_DMABASE_CCR3
3319 * @arg TIM_DMABASE_CCR4
3320 * @arg TIM_DMABASE_BDTR
3321 * @arg TIM_DMABASE_DCR
3322 * @param BurstRequestSrc : TIM DMA Request sources
3323 * This parameter can be one of the following values:
3324 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3325 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3326 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3327 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3328 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3329 * @arg TIM_DMA_COM: TIM Commutation DMA source
3330 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3331 * @param BurstBuffer : The Buffer address.
3332 * @param BurstLength : DMA Burst length. This parameter can be one value
3333 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
3334 * @retval HAL status
3336 HAL_StatusTypeDef
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef
*htim
, uint32_t BurstBaseAddress
, uint32_t BurstRequestSrc
,
3337 uint32_t* BurstBuffer
, uint32_t BurstLength
)
3339 /* Check the parameters */
3340 assert_param(IS_TIM_DMABURST_INSTANCE(htim
->Instance
));
3341 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress
));
3342 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc
));
3343 assert_param(IS_TIM_DMA_LENGTH(BurstLength
));
3345 if((htim
->State
== HAL_TIM_STATE_BUSY
))
3349 else if((htim
->State
== HAL_TIM_STATE_READY
))
3351 if((BurstBuffer
== 0U) && (BurstLength
> 0U))
3357 htim
->State
= HAL_TIM_STATE_BUSY
;
3360 switch(BurstRequestSrc
)
3362 case TIM_DMA_UPDATE
:
3364 /* Set the DMA Period elapsed callback */
3365 htim
->hdma
[TIM_DMA_ID_UPDATE
]->XferCpltCallback
= TIM_DMAPeriodElapsedCplt
;
3367 /* Set the DMA error callback */
3368 htim
->hdma
[TIM_DMA_ID_UPDATE
]->XferErrorCallback
= TIM_DMAError
;
3370 /* Enable the DMA channel */
3371 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_UPDATE
], (uint32_t)BurstBuffer
, (uint32_t)&htim
->Instance
->DMAR
, ((BurstLength
) >> 8U) + 1U);
3376 /* Set the DMA Period elapsed callback */
3377 htim
->hdma
[TIM_DMA_ID_CC1
]->XferCpltCallback
= TIM_DMADelayPulseCplt
;
3379 /* Set the DMA error callback */
3380 htim
->hdma
[TIM_DMA_ID_CC1
]->XferErrorCallback
= TIM_DMAError
;
3382 /* Enable the DMA channel */
3383 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC1
], (uint32_t)BurstBuffer
, (uint32_t)&htim
->Instance
->DMAR
, ((BurstLength
) >> 8U) + 1U);
3388 /* Set the DMA Period elapsed callback */
3389 htim
->hdma
[TIM_DMA_ID_CC2
]->XferCpltCallback
= TIM_DMADelayPulseCplt
;
3391 /* Set the DMA error callback */
3392 htim
->hdma
[TIM_DMA_ID_CC2
]->XferErrorCallback
= TIM_DMAError
;
3394 /* Enable the DMA channel */
3395 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC2
], (uint32_t)BurstBuffer
, (uint32_t)&htim
->Instance
->DMAR
, ((BurstLength
) >> 8U) + 1U);
3400 /* Set the DMA Period elapsed callback */
3401 htim
->hdma
[TIM_DMA_ID_CC3
]->XferCpltCallback
= TIM_DMADelayPulseCplt
;
3403 /* Set the DMA error callback */
3404 htim
->hdma
[TIM_DMA_ID_CC3
]->XferErrorCallback
= TIM_DMAError
;
3406 /* Enable the DMA channel */
3407 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC3
], (uint32_t)BurstBuffer
, (uint32_t)&htim
->Instance
->DMAR
, ((BurstLength
) >> 8U) + 1U);
3412 /* Set the DMA Period elapsed callback */
3413 htim
->hdma
[TIM_DMA_ID_CC4
]->XferCpltCallback
= TIM_DMADelayPulseCplt
;
3415 /* Set the DMA error callback */
3416 htim
->hdma
[TIM_DMA_ID_CC4
]->XferErrorCallback
= TIM_DMAError
;
3418 /* Enable the DMA channel */
3419 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC4
], (uint32_t)BurstBuffer
, (uint32_t)&htim
->Instance
->DMAR
, ((BurstLength
) >> 8U) + 1U);
3424 /* Set the DMA Period elapsed callback */
3425 htim
->hdma
[TIM_DMA_ID_COMMUTATION
]->XferCpltCallback
= TIMEx_DMACommutationCplt
;
3427 /* Set the DMA error callback */
3428 htim
->hdma
[TIM_DMA_ID_COMMUTATION
]->XferErrorCallback
= TIM_DMAError
;
3430 /* Enable the DMA channel */
3431 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_COMMUTATION
], (uint32_t)BurstBuffer
, (uint32_t)&htim
->Instance
->DMAR
, ((BurstLength
) >> 8U) + 1U);
3434 case TIM_DMA_TRIGGER
:
3436 /* Set the DMA Period elapsed callback */
3437 htim
->hdma
[TIM_DMA_ID_TRIGGER
]->XferCpltCallback
= TIM_DMATriggerCplt
;
3439 /* Set the DMA error callback */
3440 htim
->hdma
[TIM_DMA_ID_TRIGGER
]->XferErrorCallback
= TIM_DMAError
;
3442 /* Enable the DMA channel */
3443 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_TRIGGER
], (uint32_t)BurstBuffer
, (uint32_t)&htim
->Instance
->DMAR
, ((BurstLength
) >> 8U) + 1U);
3449 /* configure the DMA Burst Mode */
3450 htim
->Instance
->DCR
= BurstBaseAddress
| BurstLength
;
3452 /* Enable the TIM DMA Request */
3453 __HAL_TIM_ENABLE_DMA(htim
, BurstRequestSrc
);
3455 htim
->State
= HAL_TIM_STATE_READY
;
3457 /* Return function status */
3462 * @brief Stops the TIM DMA Burst mode
3463 * @param htim : TIM handle
3464 * @param BurstRequestSrc : TIM DMA Request sources to disable
3465 * @retval HAL status
3467 HAL_StatusTypeDef
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef
*htim
, uint32_t BurstRequestSrc
)
3469 /* Check the parameters */
3470 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc
));
3472 /* Abort the DMA transfer (at least disable the DMA channel) */
3473 switch(BurstRequestSrc
)
3475 case TIM_DMA_UPDATE
:
3477 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_UPDATE
]);
3482 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_CC1
]);
3487 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_CC2
]);
3492 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_CC3
]);
3497 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_CC4
]);
3502 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_COMMUTATION
]);
3505 case TIM_DMA_TRIGGER
:
3507 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_TRIGGER
]);
3514 /* Disable the TIM Update DMA request */
3515 __HAL_TIM_DISABLE_DMA(htim
, BurstRequestSrc
);
3517 /* Return function status */
3522 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
3523 * @param htim : TIM handle
3524 * @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
3525 * This parameter can be one of the following values:
3526 * @arg TIM_DMABASE_CR1
3527 * @arg TIM_DMABASE_CR2
3528 * @arg TIM_DMABASE_SMCR
3529 * @arg TIM_DMABASE_DIER
3530 * @arg TIM_DMABASE_SR
3531 * @arg TIM_DMABASE_EGR
3532 * @arg TIM_DMABASE_CCMR1
3533 * @arg TIM_DMABASE_CCMR2
3534 * @arg TIM_DMABASE_CCER
3535 * @arg TIM_DMABASE_CNT
3536 * @arg TIM_DMABASE_PSC
3537 * @arg TIM_DMABASE_ARR
3538 * @arg TIM_DMABASE_RCR
3539 * @arg TIM_DMABASE_CCR1
3540 * @arg TIM_DMABASE_CCR2
3541 * @arg TIM_DMABASE_CCR3
3542 * @arg TIM_DMABASE_CCR4
3543 * @arg TIM_DMABASE_BDTR
3544 * @arg TIM_DMABASE_DCR
3545 * @param BurstRequestSrc : TIM DMA Request sources
3546 * This parameter can be one of the following values:
3547 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3548 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3549 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3550 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3551 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3552 * @arg TIM_DMA_COM: TIM Commutation DMA source
3553 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3554 * @param BurstBuffer : The Buffer address.
3555 * @param BurstLength : DMA Burst length. This parameter can be one value
3556 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
3557 * @retval HAL status
3559 HAL_StatusTypeDef
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef
*htim
, uint32_t BurstBaseAddress
, uint32_t BurstRequestSrc
,
3560 uint32_t *BurstBuffer
, uint32_t BurstLength
)
3562 /* Check the parameters */
3563 assert_param(IS_TIM_DMABURST_INSTANCE(htim
->Instance
));
3564 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress
));
3565 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc
));
3566 assert_param(IS_TIM_DMA_LENGTH(BurstLength
));
3568 if((htim
->State
== HAL_TIM_STATE_BUSY
))
3572 else if((htim
->State
== HAL_TIM_STATE_READY
))
3574 if((BurstBuffer
== 0U) && (BurstLength
> 0U))
3580 htim
->State
= HAL_TIM_STATE_BUSY
;
3583 switch(BurstRequestSrc
)
3585 case TIM_DMA_UPDATE
:
3587 /* Set the DMA Period elapsed callback */
3588 htim
->hdma
[TIM_DMA_ID_UPDATE
]->XferCpltCallback
= TIM_DMAPeriodElapsedCplt
;
3590 /* Set the DMA error callback */
3591 htim
->hdma
[TIM_DMA_ID_UPDATE
]->XferErrorCallback
= TIM_DMAError
;
3593 /* Enable the DMA channel */
3594 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_UPDATE
], (uint32_t)&htim
->Instance
->DMAR
, (uint32_t)BurstBuffer
, ((BurstLength
) >> 8U) + 1U);
3599 /* Set the DMA Period elapsed callback */
3600 htim
->hdma
[TIM_DMA_ID_CC1
]->XferCpltCallback
= TIM_DMACaptureCplt
;
3602 /* Set the DMA error callback */
3603 htim
->hdma
[TIM_DMA_ID_CC1
]->XferErrorCallback
= TIM_DMAError
;
3605 /* Enable the DMA channel */
3606 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC1
], (uint32_t)&htim
->Instance
->DMAR
, (uint32_t)BurstBuffer
, ((BurstLength
) >> 8U) + 1U);
3611 /* Set the DMA Period elapsed callback */
3612 htim
->hdma
[TIM_DMA_ID_CC2
]->XferCpltCallback
= TIM_DMACaptureCplt
;
3614 /* Set the DMA error callback */
3615 htim
->hdma
[TIM_DMA_ID_CC2
]->XferErrorCallback
= TIM_DMAError
;
3617 /* Enable the DMA channel */
3618 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC2
], (uint32_t)&htim
->Instance
->DMAR
, (uint32_t)BurstBuffer
, ((BurstLength
) >> 8U) + 1U);
3623 /* Set the DMA Period elapsed callback */
3624 htim
->hdma
[TIM_DMA_ID_CC3
]->XferCpltCallback
= TIM_DMACaptureCplt
;
3626 /* Set the DMA error callback */
3627 htim
->hdma
[TIM_DMA_ID_CC3
]->XferErrorCallback
= TIM_DMAError
;
3629 /* Enable the DMA channel */
3630 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC3
], (uint32_t)&htim
->Instance
->DMAR
, (uint32_t)BurstBuffer
, ((BurstLength
) >> 8U) + 1U);
3635 /* Set the DMA Period elapsed callback */
3636 htim
->hdma
[TIM_DMA_ID_CC4
]->XferCpltCallback
= TIM_DMACaptureCplt
;
3638 /* Set the DMA error callback */
3639 htim
->hdma
[TIM_DMA_ID_CC4
]->XferErrorCallback
= TIM_DMAError
;
3641 /* Enable the DMA channel */
3642 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC4
], (uint32_t)&htim
->Instance
->DMAR
, (uint32_t)BurstBuffer
, ((BurstLength
) >> 8U) + 1U);
3647 /* Set the DMA Period elapsed callback */
3648 htim
->hdma
[TIM_DMA_ID_COMMUTATION
]->XferCpltCallback
= TIMEx_DMACommutationCplt
;
3650 /* Set the DMA error callback */
3651 htim
->hdma
[TIM_DMA_ID_COMMUTATION
]->XferErrorCallback
= TIM_DMAError
;
3653 /* Enable the DMA channel */
3654 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_COMMUTATION
], (uint32_t)&htim
->Instance
->DMAR
, (uint32_t)BurstBuffer
, ((BurstLength
) >> 8U) + 1U);
3657 case TIM_DMA_TRIGGER
:
3659 /* Set the DMA Period elapsed callback */
3660 htim
->hdma
[TIM_DMA_ID_TRIGGER
]->XferCpltCallback
= TIM_DMATriggerCplt
;
3662 /* Set the DMA error callback */
3663 htim
->hdma
[TIM_DMA_ID_TRIGGER
]->XferErrorCallback
= TIM_DMAError
;
3665 /* Enable the DMA channel */
3666 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_TRIGGER
], (uint32_t)&htim
->Instance
->DMAR
, (uint32_t)BurstBuffer
, ((BurstLength
) >> 8U) + 1U);
3673 /* configure the DMA Burst Mode */
3674 htim
->Instance
->DCR
= BurstBaseAddress
| BurstLength
;
3676 /* Enable the TIM DMA Request */
3677 __HAL_TIM_ENABLE_DMA(htim
, BurstRequestSrc
);
3679 htim
->State
= HAL_TIM_STATE_READY
;
3681 /* Return function status */
3686 * @brief Stop the DMA burst reading
3687 * @param htim : TIM handle
3688 * @param BurstRequestSrc : TIM DMA Request sources to disable.
3689 * @retval HAL status
3691 HAL_StatusTypeDef
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef
*htim
, uint32_t BurstRequestSrc
)
3693 /* Check the parameters */
3694 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc
));
3696 /* Abort the DMA transfer (at least disable the DMA channel) */
3697 switch(BurstRequestSrc
)
3699 case TIM_DMA_UPDATE
:
3701 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_UPDATE
]);
3706 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_CC1
]);
3711 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_CC2
]);
3716 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_CC3
]);
3721 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_CC4
]);
3726 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_COMMUTATION
]);
3729 case TIM_DMA_TRIGGER
:
3731 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_TRIGGER
]);
3738 /* Disable the TIM Update DMA request */
3739 __HAL_TIM_DISABLE_DMA(htim
, BurstRequestSrc
);
3741 /* Return function status */
3746 * @brief Generate a software event
3747 * @param htim : TIM handle
3748 * @param EventSource : specifies the event source.
3749 * This parameter can be one of the following values:
3750 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
3751 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
3752 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
3753 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
3754 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
3755 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
3756 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
3757 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
3758 * @note TIM6 and TIM7 can only generate an update event.
3759 * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
3760 * @retval HAL status
3763 HAL_StatusTypeDef
HAL_TIM_GenerateEvent(TIM_HandleTypeDef
*htim
, uint32_t EventSource
)
3765 /* Check the parameters */
3766 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
3767 assert_param(IS_TIM_EVENT_SOURCE(EventSource
));
3769 /* Process Locked */
3772 /* Change the TIM state */
3773 htim
->State
= HAL_TIM_STATE_BUSY
;
3775 /* Set the event sources */
3776 htim
->Instance
->EGR
= EventSource
;
3778 /* Change the TIM state */
3779 htim
->State
= HAL_TIM_STATE_READY
;
3783 /* Return function status */
3788 * @brief Configures the OCRef clear feature
3789 * @param htim : TIM handle
3790 * @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
3791 * contains the OCREF clear feature and parameters for the TIM peripheral.
3792 * @param Channel : specifies the TIM Channel
3793 * This parameter can be one of the following values:
3794 * @arg TIM_CHANNEL_1: TIM Channel 1
3795 * @arg TIM_CHANNEL_2: TIM Channel 2
3796 * @arg TIM_CHANNEL_3: TIM Channel 3
3797 * @arg TIM_CHANNEL_4: TIM Channel 4
3798 * @retval HAL status
3800 HAL_StatusTypeDef
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef
*htim
, TIM_ClearInputConfigTypeDef
* sClearInputConfig
, uint32_t Channel
)
3802 uint32_t tmpsmcr
= 0U;
3804 /* Check the parameters */
3805 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim
->Instance
));
3806 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig
->ClearInputSource
));
3807 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig
->ClearInputPolarity
));
3808 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig
->ClearInputPrescaler
));
3809 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig
->ClearInputFilter
));
3811 /* Process Locked */
3814 htim
->State
= HAL_TIM_STATE_BUSY
;
3816 switch (sClearInputConfig
->ClearInputSource
)
3818 case TIM_CLEARINPUTSOURCE_NONE
:
3821 /* Clear the ETR Bits */
3822 tmpsmcr
&= ~(TIM_SMCR_ETF
| TIM_SMCR_ETPS
| TIM_SMCR_ECE
| TIM_SMCR_ETP
);
3825 htim
->Instance
->SMCR
= tmpsmcr
;
3829 case TIM_CLEARINPUTSOURCE_ETR
:
3831 TIM_ETR_SetConfig(htim
->Instance
,
3832 sClearInputConfig
->ClearInputPrescaler
,
3833 sClearInputConfig
->ClearInputPolarity
,
3834 sClearInputConfig
->ClearInputFilter
);
3846 if(sClearInputConfig
->ClearInputState
!= RESET
)
3848 /* Enable the Ocref clear feature for Channel 1 */
3849 htim
->Instance
->CCMR1
|= TIM_CCMR1_OC1CE
;
3853 /* Disable the Ocref clear feature for Channel 1 */
3854 htim
->Instance
->CCMR1
&= ~TIM_CCMR1_OC1CE
;
3860 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
3861 if(sClearInputConfig
->ClearInputState
!= RESET
)
3863 /* Enable the Ocref clear feature for Channel 2 */
3864 htim
->Instance
->CCMR1
|= TIM_CCMR1_OC2CE
;
3868 /* Disable the Ocref clear feature for Channel 2 */
3869 htim
->Instance
->CCMR1
&= ~TIM_CCMR1_OC2CE
;
3875 assert_param(IS_TIM_CC3_INSTANCE(htim
->Instance
));
3876 if(sClearInputConfig
->ClearInputState
!= RESET
)
3878 /* Enable the Ocref clear feature for Channel 3 */
3879 htim
->Instance
->CCMR2
|= TIM_CCMR2_OC3CE
;
3883 /* Disable the Ocref clear feature for Channel 3 */
3884 htim
->Instance
->CCMR2
&= ~TIM_CCMR2_OC3CE
;
3890 assert_param(IS_TIM_CC4_INSTANCE(htim
->Instance
));
3891 if(sClearInputConfig
->ClearInputState
!= RESET
)
3893 /* Enable the Ocref clear feature for Channel 4 */
3894 htim
->Instance
->CCMR2
|= TIM_CCMR2_OC4CE
;
3898 /* Disable the Ocref clear feature for Channel 4 */
3899 htim
->Instance
->CCMR2
&= ~TIM_CCMR2_OC4CE
;
3907 htim
->State
= HAL_TIM_STATE_READY
;
3915 * @brief Configures the clock source to be used
3916 * @param htim : TIM handle
3917 * @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
3918 * contains the clock source information for the TIM peripheral.
3919 * @retval HAL status
3921 HAL_StatusTypeDef
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef
*htim
, TIM_ClockConfigTypeDef
* sClockSourceConfig
)
3923 uint32_t tmpsmcr
= 0U;
3925 /* Process Locked */
3928 htim
->State
= HAL_TIM_STATE_BUSY
;
3930 /* Check the parameters */
3931 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig
->ClockSource
));
3933 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
3934 tmpsmcr
= htim
->Instance
->SMCR
;
3935 tmpsmcr
&= ~(TIM_SMCR_SMS
| TIM_SMCR_TS
);
3936 tmpsmcr
&= ~(TIM_SMCR_ETF
| TIM_SMCR_ETPS
| TIM_SMCR_ECE
| TIM_SMCR_ETP
);
3937 htim
->Instance
->SMCR
= tmpsmcr
;
3939 switch (sClockSourceConfig
->ClockSource
)
3941 case TIM_CLOCKSOURCE_INTERNAL
:
3943 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
3944 /* Disable slave mode to clock the prescaler directly with the internal clock */
3945 htim
->Instance
->SMCR
&= ~TIM_SMCR_SMS
;
3949 case TIM_CLOCKSOURCE_ETRMODE1
:
3951 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
3952 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim
->Instance
));
3954 /* Check ETR input conditioning related parameters */
3955 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig
->ClockPrescaler
));
3956 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig
->ClockPolarity
));
3957 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig
->ClockFilter
));
3959 /* Configure the ETR Clock source */
3960 TIM_ETR_SetConfig(htim
->Instance
,
3961 sClockSourceConfig
->ClockPrescaler
,
3962 sClockSourceConfig
->ClockPolarity
,
3963 sClockSourceConfig
->ClockFilter
);
3964 /* Get the TIMx SMCR register value */
3965 tmpsmcr
= htim
->Instance
->SMCR
;
3966 /* Reset the SMS and TS Bits */
3967 tmpsmcr
&= ~(TIM_SMCR_SMS
| TIM_SMCR_TS
);
3968 /* Select the External clock mode1 and the ETRF trigger */
3969 tmpsmcr
|= (TIM_SLAVEMODE_EXTERNAL1
| TIM_CLOCKSOURCE_ETRMODE1
);
3970 /* Write to TIMx SMCR */
3971 htim
->Instance
->SMCR
= tmpsmcr
;
3975 case TIM_CLOCKSOURCE_ETRMODE2
:
3977 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
3978 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim
->Instance
));
3980 /* Check ETR input conditioning related parameters */
3981 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig
->ClockPrescaler
));
3982 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig
->ClockPolarity
));
3983 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig
->ClockFilter
));
3985 /* Configure the ETR Clock source */
3986 TIM_ETR_SetConfig(htim
->Instance
,
3987 sClockSourceConfig
->ClockPrescaler
,
3988 sClockSourceConfig
->ClockPolarity
,
3989 sClockSourceConfig
->ClockFilter
);
3990 /* Enable the External clock mode2 */
3991 htim
->Instance
->SMCR
|= TIM_SMCR_ECE
;
3995 case TIM_CLOCKSOURCE_TI1
:
3997 /* Check whether or not the timer instance supports external clock mode 1 */
3998 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim
->Instance
));
4000 /* Check TI1 input conditioning related parameters */
4001 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig
->ClockPolarity
));
4002 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig
->ClockFilter
));
4004 TIM_TI1_ConfigInputStage(htim
->Instance
,
4005 sClockSourceConfig
->ClockPolarity
,
4006 sClockSourceConfig
->ClockFilter
);
4007 TIM_ITRx_SetConfig(htim
->Instance
, TIM_CLOCKSOURCE_TI1
);
4010 case TIM_CLOCKSOURCE_TI2
:
4012 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
4013 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim
->Instance
));
4015 /* Check TI2 input conditioning related parameters */
4016 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig
->ClockPolarity
));
4017 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig
->ClockFilter
));
4019 TIM_TI2_ConfigInputStage(htim
->Instance
,
4020 sClockSourceConfig
->ClockPolarity
,
4021 sClockSourceConfig
->ClockFilter
);
4022 TIM_ITRx_SetConfig(htim
->Instance
, TIM_CLOCKSOURCE_TI2
);
4025 case TIM_CLOCKSOURCE_TI1ED
:
4027 /* Check whether or not the timer instance supports external clock mode 1 */
4028 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim
->Instance
));
4030 /* Check TI1 input conditioning related parameters */
4031 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig
->ClockPolarity
));
4032 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig
->ClockFilter
));
4034 TIM_TI1_ConfigInputStage(htim
->Instance
,
4035 sClockSourceConfig
->ClockPolarity
,
4036 sClockSourceConfig
->ClockFilter
);
4037 TIM_ITRx_SetConfig(htim
->Instance
, TIM_CLOCKSOURCE_TI1ED
);
4040 case TIM_CLOCKSOURCE_ITR0
:
4042 /* Check whether or not the timer instance supports external clock mode 1 */
4043 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim
->Instance
));
4045 TIM_ITRx_SetConfig(htim
->Instance
, TIM_CLOCKSOURCE_ITR0
);
4048 case TIM_CLOCKSOURCE_ITR1
:
4050 /* Check whether or not the timer instance supports external clock mode 1 */
4051 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim
->Instance
));
4053 TIM_ITRx_SetConfig(htim
->Instance
, TIM_CLOCKSOURCE_ITR1
);
4056 case TIM_CLOCKSOURCE_ITR2
:
4058 /* Check whether or not the timer instance supports external clock mode 1 */
4059 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim
->Instance
));
4061 TIM_ITRx_SetConfig(htim
->Instance
, TIM_CLOCKSOURCE_ITR2
);
4064 case TIM_CLOCKSOURCE_ITR3
:
4066 /* Check whether or not the timer instance supports external clock mode 1 */
4067 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim
->Instance
));
4069 TIM_ITRx_SetConfig(htim
->Instance
, TIM_CLOCKSOURCE_ITR3
);
4076 htim
->State
= HAL_TIM_STATE_READY
;
4084 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
4085 * or a XOR combination between CH1_input, CH2_input & CH3_input
4086 * @param htim : TIM handle.
4087 * @param TI1_Selection : Indicate whether or not channel 1 is connected to the
4088 * output of a XOR gate.
4089 * This parameter can be one of the following values:
4090 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
4091 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
4092 * pins are connected to the TI1 input (XOR combination)
4093 * @retval HAL status
4095 HAL_StatusTypeDef
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef
*htim
, uint32_t TI1_Selection
)
4097 uint32_t tmpcr2
= 0U;
4099 /* Check the parameters */
4100 assert_param(IS_TIM_XOR_INSTANCE(htim
->Instance
));
4101 assert_param(IS_TIM_TI1SELECTION(TI1_Selection
));
4103 /* Get the TIMx CR2 register value */
4104 tmpcr2
= htim
->Instance
->CR2
;
4106 /* Reset the TI1 selection */
4107 tmpcr2
&= ~TIM_CR2_TI1S
;
4109 /* Set the the TI1 selection */
4110 tmpcr2
|= TI1_Selection
;
4112 /* Write to TIMxCR2 */
4113 htim
->Instance
->CR2
= tmpcr2
;
4119 * @brief Configures the TIM in Slave mode
4120 * @param htim : TIM handle.
4121 * @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
4122 * contains the selected trigger (internal trigger input, filtered
4123 * timer input or external trigger input) and the ) and the Slave
4124 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
4125 * @retval HAL status
4127 HAL_StatusTypeDef
HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef
*htim
, TIM_SlaveConfigTypeDef
* sSlaveConfig
)
4129 /* Check the parameters */
4130 assert_param(IS_TIM_SLAVE_INSTANCE(htim
->Instance
));
4131 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig
->SlaveMode
));
4132 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig
->InputTrigger
));
4136 htim
->State
= HAL_TIM_STATE_BUSY
;
4138 TIM_SlaveTimer_SetConfig(htim
, sSlaveConfig
);
4140 /* Disable Trigger Interrupt */
4141 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_TRIGGER
);
4143 /* Disable Trigger DMA request */
4144 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_TRIGGER
);
4146 htim
->State
= HAL_TIM_STATE_READY
;
4154 * @brief Configures the TIM in Slave mode in interrupt mode
4155 * @param htim: TIM handle.
4156 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
4157 * contains the selected trigger (internal trigger input, filtered
4158 * timer input or external trigger input) and the ) and the Slave
4159 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
4160 * @retval HAL status
4162 HAL_StatusTypeDef
HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef
*htim
,
4163 TIM_SlaveConfigTypeDef
* sSlaveConfig
)
4165 /* Check the parameters */
4166 assert_param(IS_TIM_SLAVE_INSTANCE(htim
->Instance
));
4167 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig
->SlaveMode
));
4168 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig
->InputTrigger
));
4172 htim
->State
= HAL_TIM_STATE_BUSY
;
4174 TIM_SlaveTimer_SetConfig(htim
, sSlaveConfig
);
4176 /* Enable Trigger Interrupt */
4177 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_TRIGGER
);
4179 /* Disable Trigger DMA request */
4180 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_TRIGGER
);
4182 htim
->State
= HAL_TIM_STATE_READY
;
4190 * @brief Read the captured value from Capture Compare unit
4191 * @param htim : TIM handle.
4192 * @param Channel : TIM Channels to be enabled
4193 * This parameter can be one of the following values:
4194 * @arg TIM_CHANNEL_1 : TIM Channel 1 selected
4195 * @arg TIM_CHANNEL_2 : TIM Channel 2 selected
4196 * @arg TIM_CHANNEL_3 : TIM Channel 3 selected
4197 * @arg TIM_CHANNEL_4 : TIM Channel 4 selected
4198 * @retval Captured value
4200 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
4202 uint32_t tmpreg
= 0U;
4210 /* Check the parameters */
4211 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
4213 /* Return the capture 1 value */
4214 tmpreg
= htim
->Instance
->CCR1
;
4220 /* Check the parameters */
4221 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
4223 /* Return the capture 2 value */
4224 tmpreg
= htim
->Instance
->CCR2
;
4231 /* Check the parameters */
4232 assert_param(IS_TIM_CC3_INSTANCE(htim
->Instance
));
4234 /* Return the capture 3 value */
4235 tmpreg
= htim
->Instance
->CCR3
;
4242 /* Check the parameters */
4243 assert_param(IS_TIM_CC4_INSTANCE(htim
->Instance
));
4245 /* Return the capture 4 value */
4246 tmpreg
= htim
->Instance
->CCR4
;
4263 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
4264 * @brief TIM Callbacks functions
4267 ==============================================================================
4268 ##### TIM Callbacks functions #####
4269 ==============================================================================
4271 This section provides TIM callback functions:
4272 (+) Timer Period elapsed callback
4273 (+) Timer Output Compare callback
4274 (+) Timer Input capture callback
4275 (+) Timer Trigger callback
4276 (+) Timer Error callback
4283 * @brief Period elapsed callback in non blocking mode
4284 * @param htim : TIM handle
4287 __weak
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef
*htim
)
4289 /* Prevent unused argument(s) compilation warning */
4291 /* NOTE : This function Should not be modified, when the callback is needed,
4292 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
4297 * @brief Output Compare callback in non blocking mode
4298 * @param htim : TIM OC handle
4301 __weak
void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef
*htim
)
4303 /* Prevent unused argument(s) compilation warning */
4305 /* NOTE : This function Should not be modified, when the callback is needed,
4306 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
4310 * @brief Input Capture callback in non blocking mode
4311 * @param htim : TIM IC handle
4314 __weak
void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef
*htim
)
4316 /* Prevent unused argument(s) compilation warning */
4318 /* NOTE : This function Should not be modified, when the callback is needed,
4319 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
4324 * @brief PWM Pulse finished callback in non blocking mode
4325 * @param htim : TIM handle
4328 __weak
void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef
*htim
)
4330 /* Prevent unused argument(s) compilation warning */
4332 /* NOTE : This function Should not be modified, when the callback is needed,
4333 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
4338 * @brief Hall Trigger detection callback in non blocking mode
4339 * @param htim : TIM handle
4342 __weak
void HAL_TIM_TriggerCallback(TIM_HandleTypeDef
*htim
)
4344 /* Prevent unused argument(s) compilation warning */
4346 /* NOTE : This function Should not be modified, when the callback is needed,
4347 the HAL_TIM_TriggerCallback could be implemented in the user file
4352 * @brief Timer error callback in non blocking mode
4353 * @param htim : TIM handle
4356 __weak
void HAL_TIM_ErrorCallback(TIM_HandleTypeDef
*htim
)
4358 /* Prevent unused argument(s) compilation warning */
4360 /* NOTE : This function Should not be modified, when the callback is needed,
4361 the HAL_TIM_ErrorCallback could be implemented in the user file
4369 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
4370 * @brief Peripheral State functions
4373 ==============================================================================
4374 ##### Peripheral State functions #####
4375 ==============================================================================
4377 This subsection permit to get in run-time the status of the peripheral
4385 * @brief Return the TIM Base state
4386 * @param htim : TIM Base handle
4389 HAL_TIM_StateTypeDef
HAL_TIM_Base_GetState(TIM_HandleTypeDef
*htim
)
4395 * @brief Return the TIM OC state
4396 * @param htim : TIM Ouput Compare handle
4399 HAL_TIM_StateTypeDef
HAL_TIM_OC_GetState(TIM_HandleTypeDef
*htim
)
4405 * @brief Return the TIM PWM state
4406 * @param htim : TIM handle
4409 HAL_TIM_StateTypeDef
HAL_TIM_PWM_GetState(TIM_HandleTypeDef
*htim
)
4415 * @brief Return the TIM Input Capture state
4416 * @param htim : TIM IC handle
4419 HAL_TIM_StateTypeDef
HAL_TIM_IC_GetState(TIM_HandleTypeDef
*htim
)
4425 * @brief Return the TIM One Pulse Mode state
4426 * @param htim : TIM OPM handle
4429 HAL_TIM_StateTypeDef
HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef
*htim
)
4435 * @brief Return the TIM Encoder Mode state
4436 * @param htim : TIM Encoder handle
4439 HAL_TIM_StateTypeDef
HAL_TIM_Encoder_GetState(TIM_HandleTypeDef
*htim
)
4452 /** @addtogroup TIM_Private_Functions
4457 * @brief TIM DMA error callback
4458 * @param hdma : pointer to DMA handle.
4461 void TIM_DMAError(DMA_HandleTypeDef
*hdma
)
4463 TIM_HandleTypeDef
* htim
= ( TIM_HandleTypeDef
* )((DMA_HandleTypeDef
* )hdma
)->Parent
;
4465 htim
->State
= HAL_TIM_STATE_READY
;
4467 HAL_TIM_ErrorCallback(htim
);
4471 * @brief TIM DMA Delay Pulse complete callback.
4472 * @param hdma : pointer to DMA handle.
4475 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef
*hdma
)
4477 TIM_HandleTypeDef
* htim
= ( TIM_HandleTypeDef
* )((DMA_HandleTypeDef
* )hdma
)->Parent
;
4479 htim
->State
= HAL_TIM_STATE_READY
;
4481 if (hdma
== htim
->hdma
[TIM_DMA_ID_CC1
])
4483 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_1
;
4485 else if (hdma
== htim
->hdma
[TIM_DMA_ID_CC2
])
4487 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_2
;
4489 else if (hdma
== htim
->hdma
[TIM_DMA_ID_CC3
])
4491 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_3
;
4493 else if (hdma
== htim
->hdma
[TIM_DMA_ID_CC4
])
4495 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_4
;
4498 HAL_TIM_PWM_PulseFinishedCallback(htim
);
4500 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_CLEARED
;
4503 * @brief TIM DMA Capture complete callback.
4504 * @param hdma : pointer to DMA handle.
4507 void TIM_DMACaptureCplt(DMA_HandleTypeDef
*hdma
)
4509 TIM_HandleTypeDef
* htim
= ( TIM_HandleTypeDef
* )((DMA_HandleTypeDef
* )hdma
)->Parent
;
4511 htim
->State
= HAL_TIM_STATE_READY
;
4513 if (hdma
== htim
->hdma
[TIM_DMA_ID_CC1
])
4515 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_1
;
4517 else if (hdma
== htim
->hdma
[TIM_DMA_ID_CC2
])
4519 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_2
;
4521 else if (hdma
== htim
->hdma
[TIM_DMA_ID_CC3
])
4523 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_3
;
4525 else if (hdma
== htim
->hdma
[TIM_DMA_ID_CC4
])
4527 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_4
;
4530 HAL_TIM_IC_CaptureCallback(htim
);
4532 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_CLEARED
;
4536 * @brief TIM DMA Period Elapse complete callback.
4537 * @param hdma : pointer to DMA handle.
4540 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef
*hdma
)
4542 TIM_HandleTypeDef
* htim
= ( TIM_HandleTypeDef
* )((DMA_HandleTypeDef
* )hdma
)->Parent
;
4544 htim
->State
= HAL_TIM_STATE_READY
;
4546 HAL_TIM_PeriodElapsedCallback(htim
);
4550 * @brief TIM DMA Trigger callback.
4551 * @param hdma : pointer to DMA handle.
4554 static void TIM_DMATriggerCplt(DMA_HandleTypeDef
*hdma
)
4556 TIM_HandleTypeDef
* htim
= ( TIM_HandleTypeDef
* )((DMA_HandleTypeDef
* )hdma
)->Parent
;
4558 htim
->State
= HAL_TIM_STATE_READY
;
4560 HAL_TIM_TriggerCallback(htim
);
4564 * @brief Time Base configuration
4565 * @param TIMx : TIM periheral
4566 * @param Structure : TIM Base configuration structure
4569 void TIM_Base_SetConfig(TIM_TypeDef
*TIMx
, TIM_Base_InitTypeDef
*Structure
)
4571 uint32_t tmpcr1
= 0U;
4574 /* Set TIM Time Base Unit parameters ---------------------------------------*/
4575 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx
))
4577 /* Select the Counter Mode */
4578 tmpcr1
&= ~(TIM_CR1_DIR
| TIM_CR1_CMS
);
4579 tmpcr1
|= Structure
->CounterMode
;
4582 if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx
))
4584 /* Set the clock division */
4585 tmpcr1
&= ~TIM_CR1_CKD
;
4586 tmpcr1
|= (uint32_t)Structure
->ClockDivision
;
4589 /* Set the auto-reload preload */
4590 tmpcr1
&= ~TIM_CR1_ARPE
;
4591 tmpcr1
|= (uint32_t)Structure
->AutoReloadPreload
;
4595 /* Set the Autoreload value */
4596 TIMx
->ARR
= (uint32_t)Structure
->Period
;
4598 /* Set the Prescaler value */
4599 TIMx
->PSC
= (uint32_t)Structure
->Prescaler
;
4601 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx
))
4603 /* Set the Repetition Counter value */
4604 TIMx
->RCR
= Structure
->RepetitionCounter
;
4607 /* Generate an update event to reload the Prescaler
4608 and the repetition counter(only for TIM1 and TIM8) value immediatly */
4609 TIMx
->EGR
= TIM_EGR_UG
;
4613 * @brief Time Ouput Compare 1 configuration
4614 * @param TIMx to select the TIM peripheral
4615 * @param OC_Config : The ouput configuration structure
4618 static void TIM_OC1_SetConfig(TIM_TypeDef
*TIMx
, TIM_OC_InitTypeDef
*OC_Config
)
4620 uint32_t tmpccmrx
= 0U;
4621 uint32_t tmpccer
= 0U;
4622 uint32_t tmpcr2
= 0U;
4624 /* Disable the Channel 1: Reset the CC1E Bit */
4625 TIMx
->CCER
&= ~TIM_CCER_CC1E
;
4627 /* Get the TIMx CCER register value */
4628 tmpccer
= TIMx
->CCER
;
4629 /* Get the TIMx CR2 register value */
4632 /* Get the TIMx CCMR1 register value */
4633 tmpccmrx
= TIMx
->CCMR1
;
4635 /* Reset the Output Compare Mode Bits */
4636 tmpccmrx
&= ~TIM_CCMR1_OC1M
;
4637 tmpccmrx
&= ~TIM_CCMR1_CC1S
;
4638 /* Select the Output Compare Mode */
4639 tmpccmrx
|= OC_Config
->OCMode
;
4641 /* Reset the Output Polarity level */
4642 tmpccer
&= ~TIM_CCER_CC1P
;
4643 /* Set the Output Compare Polarity */
4644 tmpccer
|= OC_Config
->OCPolarity
;
4646 if(IS_TIM_CCXN_INSTANCE(TIMx
, TIM_CHANNEL_1
))
4648 /* Check parameters */
4649 assert_param(IS_TIM_OCN_POLARITY(OC_Config
->OCNPolarity
));
4651 /* Reset the Output N Polarity level */
4652 tmpccer
&= ~TIM_CCER_CC1NP
;
4653 /* Set the Output N Polarity */
4654 tmpccer
|= OC_Config
->OCNPolarity
;
4655 /* Reset the Output N State */
4656 tmpccer
&= ~TIM_CCER_CC1NE
;
4659 if(IS_TIM_BREAK_INSTANCE(TIMx
))
4661 /* Check parameters */
4662 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config
->OCNIdleState
));
4663 assert_param(IS_TIM_OCIDLE_STATE(OC_Config
->OCIdleState
));
4665 /* Reset the Output Compare and Output Compare N IDLE State */
4666 tmpcr2
&= ~TIM_CR2_OIS1
;
4667 tmpcr2
&= ~TIM_CR2_OIS1N
;
4668 /* Set the Output Idle state */
4669 tmpcr2
|= OC_Config
->OCIdleState
;
4670 /* Set the Output N Idle state */
4671 tmpcr2
|= OC_Config
->OCNIdleState
;
4673 /* Write to TIMx CR2 */
4676 /* Write to TIMx CCMR1 */
4677 TIMx
->CCMR1
= tmpccmrx
;
4679 /* Set the Capture Compare Register value */
4680 TIMx
->CCR1
= OC_Config
->Pulse
;
4682 /* Write to TIMx CCER */
4683 TIMx
->CCER
= tmpccer
;
4687 * @brief Time Ouput Compare 2 configuration
4688 * @param TIMx to select the TIM peripheral
4689 * @param OC_Config : The ouput configuration structure
4692 void TIM_OC2_SetConfig(TIM_TypeDef
*TIMx
, TIM_OC_InitTypeDef
*OC_Config
)
4694 uint32_t tmpccmrx
= 0U;
4695 uint32_t tmpccer
= 0U;
4696 uint32_t tmpcr2
= 0U;
4698 /* Disable the Channel 2: Reset the CC2E Bit */
4699 TIMx
->CCER
&= ~TIM_CCER_CC2E
;
4701 /* Get the TIMx CCER register value */
4702 tmpccer
= TIMx
->CCER
;
4703 /* Get the TIMx CR2 register value */
4706 /* Get the TIMx CCMR1 register value */
4707 tmpccmrx
= TIMx
->CCMR1
;
4709 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4710 tmpccmrx
&= ~TIM_CCMR1_OC2M
;
4711 tmpccmrx
&= ~TIM_CCMR1_CC2S
;
4713 /* Select the Output Compare Mode */
4714 tmpccmrx
|= (OC_Config
->OCMode
<< 8U);
4716 /* Reset the Output Polarity level */
4717 tmpccer
&= ~TIM_CCER_CC2P
;
4718 /* Set the Output Compare Polarity */
4719 tmpccer
|= (OC_Config
->OCPolarity
<< 4U);
4721 if(IS_TIM_CCXN_INSTANCE(TIMx
, TIM_CHANNEL_2
))
4723 assert_param(IS_TIM_OCN_POLARITY(OC_Config
->OCNPolarity
));
4725 /* Reset the Output N Polarity level */
4726 tmpccer
&= ~TIM_CCER_CC2NP
;
4727 /* Set the Output N Polarity */
4728 tmpccer
|= (OC_Config
->OCNPolarity
<< 4U);
4729 /* Reset the Output N State */
4730 tmpccer
&= ~TIM_CCER_CC2NE
;
4734 if(IS_TIM_BREAK_INSTANCE(TIMx
))
4736 /* Check parameters */
4737 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config
->OCNIdleState
));
4738 assert_param(IS_TIM_OCIDLE_STATE(OC_Config
->OCIdleState
));
4740 /* Reset the Output Compare and Output Compare N IDLE State */
4741 tmpcr2
&= ~TIM_CR2_OIS2
;
4742 tmpcr2
&= ~TIM_CR2_OIS2N
;
4743 /* Set the Output Idle state */
4744 tmpcr2
|= (OC_Config
->OCIdleState
<< 2);
4745 /* Set the Output N Idle state */
4746 tmpcr2
|= (OC_Config
->OCNIdleState
<< 2);
4749 /* Write to TIMx CR2 */
4752 /* Write to TIMx CCMR1 */
4753 TIMx
->CCMR1
= tmpccmrx
;
4755 /* Set the Capture Compare Register value */
4756 TIMx
->CCR2
= OC_Config
->Pulse
;
4758 /* Write to TIMx CCER */
4759 TIMx
->CCER
= tmpccer
;
4763 * @brief Time Ouput Compare 3 configuration
4764 * @param TIMx to select the TIM peripheral
4765 * @param OC_Config : The ouput configuration structure
4768 static void TIM_OC3_SetConfig(TIM_TypeDef
*TIMx
, TIM_OC_InitTypeDef
*OC_Config
)
4770 uint32_t tmpccmrx
= 0U;
4771 uint32_t tmpccer
= 0U;
4772 uint32_t tmpcr2
= 0U;
4774 /* Disable the Channel 3: Reset the CC2E Bit */
4775 TIMx
->CCER
&= ~TIM_CCER_CC3E
;
4777 /* Get the TIMx CCER register value */
4778 tmpccer
= TIMx
->CCER
;
4779 /* Get the TIMx CR2 register value */
4782 /* Get the TIMx CCMR2 register value */
4783 tmpccmrx
= TIMx
->CCMR2
;
4785 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4786 tmpccmrx
&= ~TIM_CCMR2_OC3M
;
4787 tmpccmrx
&= ~TIM_CCMR2_CC3S
;
4788 /* Select the Output Compare Mode */
4789 tmpccmrx
|= OC_Config
->OCMode
;
4791 /* Reset the Output Polarity level */
4792 tmpccer
&= ~TIM_CCER_CC3P
;
4793 /* Set the Output Compare Polarity */
4794 tmpccer
|= (OC_Config
->OCPolarity
<< 8U);
4796 if(IS_TIM_CCXN_INSTANCE(TIMx
, TIM_CHANNEL_3
))
4798 assert_param(IS_TIM_OCN_POLARITY(OC_Config
->OCNPolarity
));
4800 /* Reset the Output N Polarity level */
4801 tmpccer
&= ~TIM_CCER_CC3NP
;
4802 /* Set the Output N Polarity */
4803 tmpccer
|= (OC_Config
->OCNPolarity
<< 8U);
4804 /* Reset the Output N State */
4805 tmpccer
&= ~TIM_CCER_CC3NE
;
4808 if(IS_TIM_BREAK_INSTANCE(TIMx
))
4810 /* Check parameters */
4811 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config
->OCNIdleState
));
4812 assert_param(IS_TIM_OCIDLE_STATE(OC_Config
->OCIdleState
));
4814 /* Reset the Output Compare and Output Compare N IDLE State */
4815 tmpcr2
&= ~TIM_CR2_OIS3
;
4816 tmpcr2
&= ~TIM_CR2_OIS3N
;
4817 /* Set the Output Idle state */
4818 tmpcr2
|= (OC_Config
->OCIdleState
<< 4U);
4819 /* Set the Output N Idle state */
4820 tmpcr2
|= (OC_Config
->OCNIdleState
<< 4U);
4823 /* Write to TIMx CR2 */
4826 /* Write to TIMx CCMR2 */
4827 TIMx
->CCMR2
= tmpccmrx
;
4829 /* Set the Capture Compare Register value */
4830 TIMx
->CCR3
= OC_Config
->Pulse
;
4832 /* Write to TIMx CCER */
4833 TIMx
->CCER
= tmpccer
;
4837 * @brief Time Ouput Compare 4 configuration
4838 * @param TIMx to select the TIM peripheral
4839 * @param OC_Config : The ouput configuration structure
4842 static void TIM_OC4_SetConfig(TIM_TypeDef
*TIMx
, TIM_OC_InitTypeDef
*OC_Config
)
4844 uint32_t tmpccmrx
= 0U;
4845 uint32_t tmpccer
= 0U;
4846 uint32_t tmpcr2
= 0U;
4848 /* Disable the Channel 4: Reset the CC4E Bit */
4849 TIMx
->CCER
&= ~TIM_CCER_CC4E
;
4851 /* Get the TIMx CCER register value */
4852 tmpccer
= TIMx
->CCER
;
4853 /* Get the TIMx CR2 register value */
4856 /* Get the TIMx CCMR2 register value */
4857 tmpccmrx
= TIMx
->CCMR2
;
4859 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4860 tmpccmrx
&= ~TIM_CCMR2_OC4M
;
4861 tmpccmrx
&= ~TIM_CCMR2_CC4S
;
4863 /* Select the Output Compare Mode */
4864 tmpccmrx
|= (OC_Config
->OCMode
<< 8U);
4866 /* Reset the Output Polarity level */
4867 tmpccer
&= ~TIM_CCER_CC4P
;
4868 /* Set the Output Compare Polarity */
4869 tmpccer
|= (OC_Config
->OCPolarity
<< 12U);
4871 if(IS_TIM_BREAK_INSTANCE(TIMx
))
4873 assert_param(IS_TIM_OCIDLE_STATE(OC_Config
->OCIdleState
));
4875 /* Reset the Output Compare IDLE State */
4876 tmpcr2
&= ~TIM_CR2_OIS4
;
4877 /* Set the Output Idle state */
4878 tmpcr2
|= (OC_Config
->OCIdleState
<< 6);
4881 /* Write to TIMx CR2 */
4884 /* Write to TIMx CCMR2 */
4885 TIMx
->CCMR2
= tmpccmrx
;
4887 /* Set the Capture Compare Register value */
4888 TIMx
->CCR4
= OC_Config
->Pulse
;
4890 /* Write to TIMx CCER */
4891 TIMx
->CCER
= tmpccer
;
4896 * @brief Time Slave configuration
4897 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4898 * the configuration information for TIM module.
4899 * @param sSlaveConfig: The slave configuration structure
4902 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef
*htim
,
4903 TIM_SlaveConfigTypeDef
* sSlaveConfig
)
4905 uint32_t tmpsmcr
= 0U;
4906 uint32_t tmpccmr1
= 0U;
4907 uint32_t tmpccer
= 0U;
4909 /* Get the TIMx SMCR register value */
4910 tmpsmcr
= htim
->Instance
->SMCR
;
4912 /* Reset the Trigger Selection Bits */
4913 tmpsmcr
&= ~TIM_SMCR_TS
;
4914 /* Set the Input Trigger source */
4915 tmpsmcr
|= sSlaveConfig
->InputTrigger
;
4917 /* Reset the slave mode Bits */
4918 tmpsmcr
&= ~TIM_SMCR_SMS
;
4919 /* Set the slave mode */
4920 tmpsmcr
|= sSlaveConfig
->SlaveMode
;
4922 /* Write to TIMx SMCR */
4923 htim
->Instance
->SMCR
= tmpsmcr
;
4925 /* Configure the trigger prescaler, filter, and polarity */
4926 switch (sSlaveConfig
->InputTrigger
)
4930 /* Check the parameters */
4931 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim
->Instance
));
4932 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig
->TriggerPrescaler
));
4933 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig
->TriggerPolarity
));
4934 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig
->TriggerFilter
));
4935 /* Configure the ETR Trigger source */
4936 TIM_ETR_SetConfig(htim
->Instance
,
4937 sSlaveConfig
->TriggerPrescaler
,
4938 sSlaveConfig
->TriggerPolarity
,
4939 sSlaveConfig
->TriggerFilter
);
4943 case TIM_TS_TI1F_ED
:
4945 /* Check the parameters */
4946 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
4947 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig
->TriggerFilter
));
4949 /* Disable the Channel 1: Reset the CC1E Bit */
4950 tmpccer
= htim
->Instance
->CCER
;
4951 htim
->Instance
->CCER
&= ~TIM_CCER_CC1E
;
4952 tmpccmr1
= htim
->Instance
->CCMR1
;
4954 /* Set the filter */
4955 tmpccmr1
&= ~TIM_CCMR1_IC1F
;
4956 tmpccmr1
|= ((sSlaveConfig
->TriggerFilter
) << 4U);
4958 /* Write to TIMx CCMR1 and CCER registers */
4959 htim
->Instance
->CCMR1
= tmpccmr1
;
4960 htim
->Instance
->CCER
= tmpccer
;
4967 /* Check the parameters */
4968 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
4969 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig
->TriggerPolarity
));
4970 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig
->TriggerFilter
));
4972 /* Configure TI1 Filter and Polarity */
4973 TIM_TI1_ConfigInputStage(htim
->Instance
,
4974 sSlaveConfig
->TriggerPolarity
,
4975 sSlaveConfig
->TriggerFilter
);
4981 /* Check the parameters */
4982 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
4983 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig
->TriggerPolarity
));
4984 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig
->TriggerFilter
));
4986 /* Configure TI2 Filter and Polarity */
4987 TIM_TI2_ConfigInputStage(htim
->Instance
,
4988 sSlaveConfig
->TriggerPolarity
,
4989 sSlaveConfig
->TriggerFilter
);
4995 /* Check the parameter */
4996 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
5002 /* Check the parameter */
5003 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
5009 /* Check the parameter */
5010 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
5016 /* Check the parameter */
5017 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
5027 * @brief Configure the TI1 as Input.
5028 * @param TIMx to select the TIM peripheral.
5029 * @param TIM_ICPolarity : The Input Polarity.
5030 * This parameter can be one of the following values:
5031 * @arg TIM_ICPOLARITY_RISING
5032 * @arg TIM_ICPOLARITY_FALLING
5033 * @param TIM_ICSelection : specifies the input to be used.
5034 * This parameter can be one of the following values:
5035 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
5036 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
5037 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
5038 * @param TIM_ICFilter : Specifies the Input Capture Filter.
5039 * This parameter must be a value between 0x00 and 0x0F.
5041 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
5042 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
5043 * protected against un-initialized filter and polarity values.
5045 void TIM_TI1_SetConfig(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICSelection
,
5046 uint32_t TIM_ICFilter
)
5048 uint32_t tmpccmr1
= 0U;
5049 uint32_t tmpccer
= 0U;
5051 /* Disable the Channel 1: Reset the CC1E Bit */
5052 TIMx
->CCER
&= ~TIM_CCER_CC1E
;
5053 tmpccmr1
= TIMx
->CCMR1
;
5054 tmpccer
= TIMx
->CCER
;
5056 /* Select the Input */
5057 if(IS_TIM_CC2_INSTANCE(TIMx
) != RESET
)
5059 tmpccmr1
&= ~TIM_CCMR1_CC1S
;
5060 tmpccmr1
|= TIM_ICSelection
;
5064 tmpccmr1
|= TIM_CCMR1_CC1S_0
;
5067 /* Set the filter */
5068 tmpccmr1
&= ~TIM_CCMR1_IC1F
;
5069 tmpccmr1
|= ((TIM_ICFilter
<< 4U) & TIM_CCMR1_IC1F
);
5071 /* Select the Polarity and set the CC1E Bit */
5072 tmpccer
&= ~(TIM_CCER_CC1P
| TIM_CCER_CC1NP
);
5073 tmpccer
|= (TIM_ICPolarity
& (TIM_CCER_CC1P
| TIM_CCER_CC1NP
));
5075 /* Write to TIMx CCMR1 and CCER registers */
5076 TIMx
->CCMR1
= tmpccmr1
;
5077 TIMx
->CCER
= tmpccer
;
5081 * @brief Configure the Polarity and Filter for TI1.
5082 * @param TIMx to select the TIM peripheral.
5083 * @param TIM_ICPolarity : The Input Polarity.
5084 * This parameter can be one of the following values:
5085 * @arg TIM_ICPOLARITY_RISING
5086 * @arg TIM_ICPOLARITY_FALLING
5087 * @param TIM_ICFilter : Specifies the Input Capture Filter.
5088 * This parameter must be a value between 0x00 and 0x0F.
5091 static void TIM_TI1_ConfigInputStage(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICFilter
)
5093 uint32_t tmpccmr1
= 0U;
5094 uint32_t tmpccer
= 0U;
5096 /* Disable the Channel 1: Reset the CC1E Bit */
5097 tmpccer
= TIMx
->CCER
;
5098 TIMx
->CCER
&= ~TIM_CCER_CC1E
;
5099 tmpccmr1
= TIMx
->CCMR1
;
5101 /* Set the filter */
5102 tmpccmr1
&= ~TIM_CCMR1_IC1F
;
5103 tmpccmr1
|= (TIM_ICFilter
<< 4U);
5105 /* Select the Polarity and set the CC1E Bit */
5106 tmpccer
&= ~(TIM_CCER_CC1P
| TIM_CCER_CC1NP
);
5107 tmpccer
|= TIM_ICPolarity
;
5109 /* Write to TIMx CCMR1 and CCER registers */
5110 TIMx
->CCMR1
= tmpccmr1
;
5111 TIMx
->CCER
= tmpccer
;
5115 * @brief Configure the TI2 as Input.
5116 * @param TIMx to select the TIM peripheral
5117 * @param TIM_ICPolarity : The Input Polarity.
5118 * This parameter can be one of the following values:
5119 * @arg TIM_ICPOLARITY_RISING
5120 * @arg TIM_ICPOLARITY_FALLING
5121 * @param TIM_ICSelection : specifies the input to be used.
5122 * This parameter can be one of the following values:
5123 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
5124 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
5125 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
5126 * @param TIM_ICFilter : Specifies the Input Capture Filter.
5127 * This parameter must be a value between 0x00 and 0x0F.
5129 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
5130 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
5131 * protected against un-initialized filter and polarity values.
5133 static void TIM_TI2_SetConfig(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICSelection
,
5134 uint32_t TIM_ICFilter
)
5136 uint32_t tmpccmr1
= 0U;
5137 uint32_t tmpccer
= 0U;
5139 /* Disable the Channel 2: Reset the CC2E Bit */
5140 TIMx
->CCER
&= ~TIM_CCER_CC2E
;
5141 tmpccmr1
= TIMx
->CCMR1
;
5142 tmpccer
= TIMx
->CCER
;
5144 /* Select the Input */
5145 tmpccmr1
&= ~TIM_CCMR1_CC2S
;
5146 tmpccmr1
|= (TIM_ICSelection
<< 8U);
5148 /* Set the filter */
5149 tmpccmr1
&= ~TIM_CCMR1_IC2F
;
5150 tmpccmr1
|= ((TIM_ICFilter
<< 12U) & TIM_CCMR1_IC2F
);
5152 /* Select the Polarity and set the CC2E Bit */
5153 tmpccer
&= ~(TIM_CCER_CC2P
| TIM_CCER_CC2NP
);
5154 tmpccer
|= ((TIM_ICPolarity
<< 4U) & (TIM_CCER_CC2P
| TIM_CCER_CC2NP
));
5156 /* Write to TIMx CCMR1 and CCER registers */
5157 TIMx
->CCMR1
= tmpccmr1
;
5158 TIMx
->CCER
= tmpccer
;
5162 * @brief Configure the Polarity and Filter for TI2.
5163 * @param TIMx to select the TIM peripheral.
5164 * @param TIM_ICPolarity : The Input Polarity.
5165 * This parameter can be one of the following values:
5166 * @arg TIM_ICPOLARITY_RISING
5167 * @arg TIM_ICPOLARITY_FALLING
5168 * @param TIM_ICFilter : Specifies the Input Capture Filter.
5169 * This parameter must be a value between 0x00 and 0x0F.
5172 static void TIM_TI2_ConfigInputStage(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICFilter
)
5174 uint32_t tmpccmr1
= 0U;
5175 uint32_t tmpccer
= 0U;
5177 /* Disable the Channel 2: Reset the CC2E Bit */
5178 TIMx
->CCER
&= ~TIM_CCER_CC2E
;
5179 tmpccmr1
= TIMx
->CCMR1
;
5180 tmpccer
= TIMx
->CCER
;
5182 /* Set the filter */
5183 tmpccmr1
&= ~TIM_CCMR1_IC2F
;
5184 tmpccmr1
|= (TIM_ICFilter
<< 12U);
5186 /* Select the Polarity and set the CC2E Bit */
5187 tmpccer
&= ~(TIM_CCER_CC2P
| TIM_CCER_CC2NP
);
5188 tmpccer
|= (TIM_ICPolarity
<< 4U);
5190 /* Write to TIMx CCMR1 and CCER registers */
5191 TIMx
->CCMR1
= tmpccmr1
;
5192 TIMx
->CCER
= tmpccer
;
5196 * @brief Configure the TI3 as Input.
5197 * @param TIMx to select the TIM peripheral
5198 * @param TIM_ICPolarity : The Input Polarity.
5199 * This parameter can be one of the following values:
5200 * @arg TIM_ICPOLARITY_RISING
5201 * @arg TIM_ICPOLARITY_FALLING
5202 * @param TIM_ICSelection : specifies the input to be used.
5203 * This parameter can be one of the following values:
5204 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
5205 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
5206 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
5207 * @param TIM_ICFilter : Specifies the Input Capture Filter.
5208 * This parameter must be a value between 0x00 and 0x0F.
5210 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
5211 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
5212 * protected against un-initialized filter and polarity values.
5214 static void TIM_TI3_SetConfig(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICSelection
,
5215 uint32_t TIM_ICFilter
)
5217 uint32_t tmpccmr2
= 0U;
5218 uint32_t tmpccer
= 0U;
5220 /* Disable the Channel 3: Reset the CC3E Bit */
5221 TIMx
->CCER
&= ~TIM_CCER_CC3E
;
5222 tmpccmr2
= TIMx
->CCMR2
;
5223 tmpccer
= TIMx
->CCER
;
5225 /* Select the Input */
5226 tmpccmr2
&= ~TIM_CCMR2_CC3S
;
5227 tmpccmr2
|= TIM_ICSelection
;
5229 /* Set the filter */
5230 tmpccmr2
&= ~TIM_CCMR2_IC3F
;
5231 tmpccmr2
|= ((TIM_ICFilter
<< 4U) & TIM_CCMR2_IC3F
);
5233 /* Select the Polarity and set the CC3E Bit */
5234 tmpccer
&= ~(TIM_CCER_CC3P
| TIM_CCER_CC3NP
);
5235 tmpccer
|= ((TIM_ICPolarity
<< 8U) & (TIM_CCER_CC3P
| TIM_CCER_CC3NP
));
5237 /* Write to TIMx CCMR2 and CCER registers */
5238 TIMx
->CCMR2
= tmpccmr2
;
5239 TIMx
->CCER
= tmpccer
;
5243 * @brief Configure the TI4 as Input.
5244 * @param TIMx to select the TIM peripheral
5245 * @param TIM_ICPolarity : The Input Polarity.
5246 * This parameter can be one of the following values:
5247 * @arg TIM_ICPOLARITY_RISING
5248 * @arg TIM_ICPOLARITY_FALLING
5249 * @param TIM_ICSelection : specifies the input to be used.
5250 * This parameter can be one of the following values:
5251 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
5252 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
5253 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
5254 * @param TIM_ICFilter : Specifies the Input Capture Filter.
5255 * This parameter must be a value between 0x00 and 0x0F.
5256 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
5257 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
5258 * protected against un-initialized filter and polarity values.
5261 static void TIM_TI4_SetConfig(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICSelection
,
5262 uint32_t TIM_ICFilter
)
5264 uint32_t tmpccmr2
= 0U;
5265 uint32_t tmpccer
= 0U;
5267 /* Disable the Channel 4: Reset the CC4E Bit */
5268 TIMx
->CCER
&= ~TIM_CCER_CC4E
;
5269 tmpccmr2
= TIMx
->CCMR2
;
5270 tmpccer
= TIMx
->CCER
;
5272 /* Select the Input */
5273 tmpccmr2
&= ~TIM_CCMR2_CC4S
;
5274 tmpccmr2
|= (TIM_ICSelection
<< 8U);
5276 /* Set the filter */
5277 tmpccmr2
&= ~TIM_CCMR2_IC4F
;
5278 tmpccmr2
|= ((TIM_ICFilter
<< 12U) & TIM_CCMR2_IC4F
);
5280 /* Select the Polarity and set the CC4E Bit */
5281 tmpccer
&= ~TIM_CCER_CC4P
;
5282 tmpccer
|= ((TIM_ICPolarity
<< 12U) & TIM_CCER_CC4P
);
5284 /* Write to TIMx CCMR2 and CCER registers */
5285 TIMx
->CCMR2
= tmpccmr2
;
5286 TIMx
->CCER
= tmpccer
;
5290 * @brief Selects the Input Trigger source
5291 * @param TIMx to select the TIM peripheral
5292 * @param InputTriggerSource : The Input Trigger source.
5293 * This parameter can be one of the following values:
5294 * @arg TIM_TS_ITR0 : Internal Trigger 0
5295 * @arg TIM_TS_ITR1 : Internal Trigger 1
5296 * @arg TIM_TS_ITR2 : Internal Trigger 2
5297 * @arg TIM_TS_ITR3 : Internal Trigger 3
5298 * @arg TIM_TS_TI1F_ED : TI1 Edge Detector
5299 * @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
5300 * @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
5301 * @arg TIM_TS_ETRF : External Trigger input
5304 static void TIM_ITRx_SetConfig(TIM_TypeDef
*TIMx
, uint16_t InputTriggerSource
)
5306 uint32_t tmpsmcr
= 0U;
5308 /* Get the TIMx SMCR register value */
5309 tmpsmcr
= TIMx
->SMCR
;
5310 /* Reset the TS Bits */
5311 tmpsmcr
&= ~TIM_SMCR_TS
;
5312 /* Set the Input Trigger source and the slave mode*/
5313 tmpsmcr
|= InputTriggerSource
| TIM_SLAVEMODE_EXTERNAL1
;
5314 /* Write to TIMx SMCR */
5315 TIMx
->SMCR
= tmpsmcr
;
5318 * @brief Configures the TIMx External Trigger (ETR).
5319 * @param TIMx to select the TIM peripheral
5320 * @param TIM_ExtTRGPrescaler : The external Trigger Prescaler.
5321 * This parameter can be one of the following values:
5322 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
5323 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
5324 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
5325 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
5326 * @param TIM_ExtTRGPolarity : The external Trigger Polarity.
5327 * This parameter can be one of the following values:
5328 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
5329 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
5330 * @param ExtTRGFilter : External Trigger Filter.
5331 * This parameter must be a value between 0x00 and 0x0F
5334 static void TIM_ETR_SetConfig(TIM_TypeDef
* TIMx
, uint32_t TIM_ExtTRGPrescaler
,
5335 uint32_t TIM_ExtTRGPolarity
, uint32_t ExtTRGFilter
)
5337 uint32_t tmpsmcr
= 0U;
5339 tmpsmcr
= TIMx
->SMCR
;
5341 /* Reset the ETR Bits */
5342 tmpsmcr
&= ~(TIM_SMCR_ETF
| TIM_SMCR_ETPS
| TIM_SMCR_ECE
| TIM_SMCR_ETP
);
5344 /* Set the Prescaler, the Filter value and the Polarity */
5345 tmpsmcr
|= (uint32_t)(TIM_ExtTRGPrescaler
| (TIM_ExtTRGPolarity
| (ExtTRGFilter
<< 8U)));
5347 /* Write to TIMx SMCR */
5348 TIMx
->SMCR
= tmpsmcr
;
5352 * @brief Enables or disables the TIM Capture Compare Channel x.
5353 * @param TIMx to select the TIM peripheral
5354 * @param Channel : specifies the TIM Channel
5355 * This parameter can be one of the following values:
5356 * @arg TIM_CHANNEL_1: TIM Channel 1
5357 * @arg TIM_CHANNEL_2: TIM Channel 2
5358 * @arg TIM_CHANNEL_3: TIM Channel 3
5359 * @arg TIM_CHANNEL_4: TIM Channel 4
5360 * @param ChannelState : specifies the TIM Channel CCxE bit new state.
5361 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
5364 void TIM_CCxChannelCmd(TIM_TypeDef
* TIMx
, uint32_t Channel
, uint32_t ChannelState
)
5368 /* Check the parameters */
5369 assert_param(IS_TIM_CC1_INSTANCE(TIMx
));
5370 assert_param(IS_TIM_CHANNELS(Channel
));
5372 tmp
= TIM_CCER_CC1E
<< Channel
;
5374 /* Reset the CCxE Bit */
5377 /* Set or reset the CCxE Bit */
5378 TIMx
->CCER
|= (uint32_t)(ChannelState
<< Channel
);
5385 #endif /* HAL_TIM_MODULE_ENABLED */
5393 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/