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Increment eeprom version
[betaflight.git] / lib / main / STM32F1 / Drivers / STM32F1xx_HAL_Driver / Src / stm32f1xx_ll_adc.c
blob2912d5d1a534f205c5c29062806ea881f02bcb00
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_adc.c
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 12-May-2017
7 * @brief ADC LL module driver
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37 #if defined(USE_FULL_LL_DRIVER)
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32f1xx_ll_adc.h"
41 #include "stm32f1xx_ll_bus.h"
42
43 #ifdef USE_FULL_ASSERT
44 #include "stm32_assert.h"
45 #else
46 #define assert_param(expr) ((void)0U)
47 #endif
48
49 /** @addtogroup STM32F1xx_LL_Driver
50 * @{
51 */
52
53 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
54
55 /** @addtogroup ADC_LL ADC
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /* Private constants ---------------------------------------------------------*/
62 /* Private macros ------------------------------------------------------------*/
63
64 /** @addtogroup ADC_LL_Private_Macros
65 * @{
66 */
67
68 /* Check of parameters for configuration of ADC hierarchical scope: */
69 /* common to several ADC instances. */
70 /* Check of parameters for configuration of ADC hierarchical scope: */
71 /* ADC instance. */
72 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
73 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
74 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
75 )
76
77 #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
78 ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
79 || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
80 )
81
82 #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
83 ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
84 || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
85 )
86
87 /* Check of parameters for configuration of ADC hierarchical scope: */
88 /* ADC group regular */
89 #if defined(ADC3)
90 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
91 ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
92 ? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
93 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
94 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
95 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
96 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
97 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
98 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
99 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
100 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
101 ) \
102 : \
103 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
104 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
105 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
106 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
107 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
108 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3) \
109 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \
110 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \
111 ) \
112 )
113 #else
114 #if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC)
115 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
116 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
117 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
118 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
119 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
120 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
121 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
122 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
123 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
124 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
125 )
126 #else
127 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
128 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
129 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
130 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
131 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
132 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
133 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
134 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
135 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
136 )
137 #endif
138 #endif
139 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
140 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
141 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
142 )
143
144 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
145 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
146 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
147 )
148
149 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
150 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
151 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
152 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
153 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
154 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
155 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
156 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
157 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
158 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
159 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
160 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
161 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
162 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
163 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
164 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
165 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
166 )
167
168 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
169 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
170 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
171 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
172 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
173 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
174 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
175 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
176 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
177 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
178 )
179
180 /* Check of parameters for configuration of ADC hierarchical scope: */
181 /* ADC group injected */
182 #if defined(ADC3)
183 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
184 ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
185 ? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
186 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
187 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
188 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
189 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
190 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
191 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
192 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
193 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
194 ) \
195 : \
196 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
197 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
198 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
199 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
200 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
201 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3) \
202 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
203 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \
204 ) \
205 )
206 #else
207 #if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC)
208 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
209 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
210 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
211 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
212 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
213 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
214 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
215 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
216 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
217 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
218 )
219 #else
220 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
221 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
222 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
223 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
224 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
225 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
226 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
227 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
228 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
229 )
230 #endif
231 #endif
232 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
233 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
234 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
235 )
236
237 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
238 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
239 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
240 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
241 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
242 )
243
244 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
245 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
246 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
247 )
248
249 #if defined(ADC_MULTIMODE_SUPPORT)
250 /* Check of parameters for configuration of ADC hierarchical scope: */
251 /* multimode. */
252 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
253 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
254 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
255 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_FAST) \
256 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_SLOW) \
257 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
258 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
259 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
260 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
261 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM) \
262 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM) \
263 )
264
265 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
266 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
267 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
268 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
269 )
270
271 #endif /* ADC_MULTIMODE_SUPPORT */
272 /**
273 * @}
274 */
275
276
277 /* Private function prototypes -----------------------------------------------*/
278
279 /* Exported functions --------------------------------------------------------*/
280 /** @addtogroup ADC_LL_Exported_Functions
281 * @{
282 */
283
284 /** @addtogroup ADC_LL_EF_Init
285 * @{
286 */
287
288 /**
289 * @brief De-initialize registers of all ADC instances belonging to
290 * the same ADC common instance to their default reset values.
291 * @param ADCxy_COMMON ADC common instance
292 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
293 * @retval An ErrorStatus enumeration value:
294 * - SUCCESS: ADC common registers are de-initialized
295 * - ERROR: not applicable
296 */
297 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
298 {
299 /* Check the parameters */
300 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
301
302 /* Force reset of ADC clock (core clock) */
303 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1);
304
305 /* Release reset of ADC clock (core clock) */
306 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1);
307
308 return SUCCESS;
309 }
310
311 /**
312 * @brief Initialize some features of ADC common parameters
313 * (all ADC instances belonging to the same ADC common instance)
314 * and multimode (for devices with several ADC instances available).
315 * @note The setting of ADC common parameters is conditioned to
316 * ADC instances state:
317 * All ADC instances belonging to the same ADC common instance
318 * must be disabled.
319 * @param ADCxy_COMMON ADC common instance
320 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
321 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
322 * @retval An ErrorStatus enumeration value:
323 * - SUCCESS: ADC common registers are initialized
324 * - ERROR: ADC common registers are not initialized
325 */
326 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
327 {
328 ErrorStatus status = SUCCESS;
329
330 /* Check the parameters */
331 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
332 #if defined(ADC_MULTIMODE_SUPPORT)
333 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
334 #endif /* ADC_MULTIMODE_SUPPORT */
335
336 /* Note: Hardware constraint (refer to description of functions */
337 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
338 /* On this STM32 serie, setting of these features is conditioned to */
339 /* ADC state: */
340 /* All ADC instances of the ADC common group must be disabled. */
341 if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
342 {
343 /* Configuration of ADC hierarchical scope: */
344 /* - common to several ADC */
345 /* (all ADC instances belonging to the same ADC common instance) */
346 /* - multimode (if several ADC instances available on the */
347 /* selected device) */
348 /* - Set ADC multimode configuration */
349 /* - Set ADC multimode DMA transfer */
350 /* - Set ADC multimode: delay between 2 sampling phases */
351 #if defined(ADC_MULTIMODE_SUPPORT)
352 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
353 {
354 MODIFY_REG(ADCxy_COMMON->CR1,
355 ADC_CR1_DUALMOD,
356 ADC_CommonInitStruct->Multimode
357 );
358 }
359 else
360 {
361 MODIFY_REG(ADCxy_COMMON->CR1,
362 ADC_CR1_DUALMOD,
363 LL_ADC_MULTI_INDEPENDENT
364 );
365 }
366 #endif
367 }
368 else
369 {
370 /* Initialization error: One or several ADC instances belonging to */
371 /* the same ADC common instance are not disabled. */
372 status = ERROR;
373 }
374
375 return status;
376 }
377
378 /**
379 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
380 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
381 * whose fields will be set to default values.
382 * @retval None
383 */
384 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
385 {
386 /* Set ADC_CommonInitStruct fields to default values */
387 /* Set fields of ADC common */
388 /* (all ADC instances belonging to the same ADC common instance) */
389
390 #if defined(ADC_MULTIMODE_SUPPORT)
391 /* Set fields of ADC multimode */
392 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
393 #endif /* ADC_MULTIMODE_SUPPORT */
394 }
395
396 /**
397 * @brief De-initialize registers of the selected ADC instance
398 * to their default reset values.
399 * @note To reset all ADC instances quickly (perform a hard reset),
400 * use function @ref LL_ADC_CommonDeInit().
401 * @param ADCx ADC instance
402 * @retval An ErrorStatus enumeration value:
403 * - SUCCESS: ADC registers are de-initialized
404 * - ERROR: ADC registers are not de-initialized
405 */
406 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
407 {
408 ErrorStatus status = SUCCESS;
409
410 /* Check the parameters */
411 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
412
413 /* Disable ADC instance if not already disabled. */
414 if(LL_ADC_IsEnabled(ADCx) == 1U)
415 {
416 /* Set ADC group regular trigger source to SW start to ensure to not */
417 /* have an external trigger event occurring during the conversion stop */
418 /* ADC disable process. */
419 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
420
421 /* Set ADC group injected trigger source to SW start to ensure to not */
422 /* have an external trigger event occurring during the conversion stop */
423 /* ADC disable process. */
424 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
425
426 /* Disable the ADC instance */
427 LL_ADC_Disable(ADCx);
428 }
429
430 /* Check whether ADC state is compliant with expected state */
431 /* (hardware requirements of bits state to reset registers below) */
432 if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
433 {
434 /* ========== Reset ADC registers ========== */
435 /* Reset register SR */
436 CLEAR_BIT(ADCx->SR,
437 ( LL_ADC_FLAG_STRT
438 | LL_ADC_FLAG_JSTRT
439 | LL_ADC_FLAG_EOS
440 | LL_ADC_FLAG_JEOS
441 | LL_ADC_FLAG_AWD1 )
442 );
443
444 /* Reset register CR1 */
445 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
446
447 CLEAR_BIT(ADCx->CR1,
448 ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DUALMOD
449 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
450 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
451 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
452 | ADC_CR1_AWDCH )
453 );
454 #else
455
456 CLEAR_BIT(ADCx->CR1,
457 ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM
458 | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO
459 | ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE
460 | ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH )
461 );
462 #endif
463
464 /* Reset register CR2 */
465 CLEAR_BIT(ADCx->CR2,
466 ( ADC_CR2_TSVREFE
467 | ADC_CR2_SWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL
468 | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL
469 | ADC_CR2_ALIGN | ADC_CR2_DMA
470 | ADC_CR2_RSTCAL | ADC_CR2_CAL
471 | ADC_CR2_CONT | ADC_CR2_ADON )
472 );
473
474 /* Reset register SMPR1 */
475 CLEAR_BIT(ADCx->SMPR1,
476 ( ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
477 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
478 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
479 );
480
481 /* Reset register SMPR2 */
482 CLEAR_BIT(ADCx->SMPR2,
483 ( ADC_SMPR2_SMP9
484 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
485 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
486 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
487 );
488
489 /* Reset register JOFR1 */
490 CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
491 /* Reset register JOFR2 */
492 CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
493 /* Reset register JOFR3 */
494 CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
495 /* Reset register JOFR4 */
496 CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
497
498 /* Reset register HTR */
499 SET_BIT(ADCx->HTR, ADC_HTR_HT);
500 /* Reset register LTR */
501 CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
502
503 /* Reset register SQR1 */
504 CLEAR_BIT(ADCx->SQR1,
505 ( ADC_SQR1_L
506 | ADC_SQR1_SQ16
507 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
508 );
509
510 /* Reset register SQR2 */
511 CLEAR_BIT(ADCx->SQR2,
512 ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
513 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
514 );
515
516
517 /* Reset register JSQR */
518 CLEAR_BIT(ADCx->JSQR,
519 ( ADC_JSQR_JL
520 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
521 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
522 );
523
524 /* Reset register DR */
525 /* bits in access mode read only, no direct reset applicable */
526
527 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
528 /* bits in access mode read only, no direct reset applicable */
529
530 }
531
532 return status;
533 }
534
535 /**
536 * @brief Initialize some features of ADC instance.
537 * @note These parameters have an impact on ADC scope: ADC instance.
538 * Affects both group regular and group injected (availability
539 * of ADC group injected depends on STM32 families).
540 * Refer to corresponding unitary functions into
541 * @ref ADC_LL_EF_Configuration_ADC_Instance .
542 * @note The setting of these parameters by function @ref LL_ADC_Init()
543 * is conditioned to ADC state:
544 * ADC instance must be disabled.
545 * This condition is applied to all ADC features, for efficiency
546 * and compatibility over all STM32 families. However, the different
547 * features can be set under different ADC state conditions
548 * (setting possible with ADC enabled without conversion on going,
549 * ADC enabled with conversion on going, ...)
550 * Each feature can be updated afterwards with a unitary function
551 * and potentially with ADC in a different state than disabled,
552 * refer to description of each function for setting
553 * conditioned to ADC state.
554 * @note After using this function, some other features must be configured
555 * using LL unitary functions.
556 * The minimum configuration remaining to be done is:
557 * - Set ADC group regular or group injected sequencer:
558 * map channel on the selected sequencer rank.
559 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
560 * - Set ADC channel sampling time
561 * Refer to function LL_ADC_SetChannelSamplingTime();
562 * @param ADCx ADC instance
563 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
564 * @retval An ErrorStatus enumeration value:
565 * - SUCCESS: ADC registers are initialized
566 * - ERROR: ADC registers are not initialized
567 */
568 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
569 {
570 ErrorStatus status = SUCCESS;
571
572 /* Check the parameters */
573 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
574
575 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
576 assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
577
578 /* Note: Hardware constraint (refer to description of this function): */
579 /* ADC instance must be disabled. */
580 if(LL_ADC_IsEnabled(ADCx) == 0U)
581 {
582 /* Configuration of ADC hierarchical scope: */
583 /* - ADC instance */
584 /* - Set ADC conversion data alignment */
585 MODIFY_REG(ADCx->CR1,
586 ADC_CR1_SCAN
587 ,
588 ADC_InitStruct->SequencersScanMode
589 );
590
591 MODIFY_REG(ADCx->CR2,
592 ADC_CR2_ALIGN
593 ,
594 ADC_InitStruct->DataAlignment
595 );
596
597 }
598 else
599 {
600 /* Initialization error: ADC instance is not disabled. */
601 status = ERROR;
602 }
603 return status;
604 }
605
606 /**
607 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
608 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
609 * whose fields will be set to default values.
610 * @retval None
611 */
612 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
613 {
614 /* Set ADC_InitStruct fields to default values */
615 /* Set fields of ADC instance */
616 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
617
618 /* Enable scan mode to have a generic behavior with ADC of other */
619 /* STM32 families, without this setting available: */
620 /* ADC group regular sequencer and ADC group injected sequencer depend */
621 /* only of their own configuration. */
622 ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
623
624 }
625
626 /**
627 * @brief Initialize some features of ADC group regular.
628 * @note These parameters have an impact on ADC scope: ADC group regular.
629 * Refer to corresponding unitary functions into
630 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
631 * (functions with prefix "REG").
632 * @note The setting of these parameters by function @ref LL_ADC_Init()
633 * is conditioned to ADC state:
634 * ADC instance must be disabled.
635 * This condition is applied to all ADC features, for efficiency
636 * and compatibility over all STM32 families. However, the different
637 * features can be set under different ADC state conditions
638 * (setting possible with ADC enabled without conversion on going,
639 * ADC enabled with conversion on going, ...)
640 * Each feature can be updated afterwards with a unitary function
641 * and potentially with ADC in a different state than disabled,
642 * refer to description of each function for setting
643 * conditioned to ADC state.
644 * @note After using this function, other features must be configured
645 * using LL unitary functions.
646 * The minimum configuration remaining to be done is:
647 * - Set ADC group regular or group injected sequencer:
648 * map channel on the selected sequencer rank.
649 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
650 * - Set ADC channel sampling time
651 * Refer to function LL_ADC_SetChannelSamplingTime();
652 * @param ADCx ADC instance
653 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
654 * @retval An ErrorStatus enumeration value:
655 * - SUCCESS: ADC registers are initialized
656 * - ERROR: ADC registers are not initialized
657 */
658 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
659 {
660 ErrorStatus status = SUCCESS;
661
662 /* Check the parameters */
663 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
664 #if defined(ADC3)
665 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource));
666 #else
667 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
668 #endif
669 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
670 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
671 {
672 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
673 }
674 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
675 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
676
677 /* Note: Hardware constraint (refer to description of this function): */
678 /* ADC instance must be disabled. */
679 if(LL_ADC_IsEnabled(ADCx) == 0U)
680 {
681 /* Configuration of ADC hierarchical scope: */
682 /* - ADC group regular */
683 /* - Set ADC group regular trigger source */
684 /* - Set ADC group regular sequencer length */
685 /* - Set ADC group regular sequencer discontinuous mode */
686 /* - Set ADC group regular continuous mode */
687 /* - Set ADC group regular conversion data transfer: no transfer or */
688 /* transfer by DMA, and DMA requests mode */
689 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
690 /* ADC conversion. */
691 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
692 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
693 {
694 MODIFY_REG(ADCx->CR1,
695 ADC_CR1_DISCEN
696 | ADC_CR1_DISCNUM
697 ,
698 ADC_REG_InitStruct->SequencerLength
699 | ADC_REG_InitStruct->SequencerDiscont
700 );
701 }
702 else
703 {
704 MODIFY_REG(ADCx->CR1,
705 ADC_CR1_DISCEN
706 | ADC_CR1_DISCNUM
707 ,
708 ADC_REG_InitStruct->SequencerLength
709 | LL_ADC_REG_SEQ_DISCONT_DISABLE
710 );
711 }
712
713 MODIFY_REG(ADCx->CR2,
714 ADC_CR2_EXTSEL
715 | ADC_CR2_CONT
716 | ADC_CR2_DMA
717 ,
718 ADC_REG_InitStruct->TriggerSource
719 | ADC_REG_InitStruct->ContinuousMode
720 | ADC_REG_InitStruct->DMATransfer
721 );
722
723 /* Set ADC group regular sequencer length and scan direction */
724 /* Note: Hardware constraint (refer to description of this function): */
725 /* Note: If ADC instance feature scan mode is disabled */
726 /* (refer to ADC instance initialization structure */
727 /* parameter @ref SequencersScanMode */
728 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
729 /* this parameter is discarded. */
730 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
731 }
732 else
733 {
734 /* Initialization error: ADC instance is not disabled. */
735 status = ERROR;
736 }
737 return status;
738 }
739
740 /**
741 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
742 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
743 * whose fields will be set to default values.
744 * @retval None
745 */
746 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
747 {
748 /* Set ADC_REG_InitStruct fields to default values */
749 /* Set fields of ADC group regular */
750 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
751 /* ADC conversion. */
752 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
753 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
754 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
755 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
756 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
757 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
758 }
759
760 /**
761 * @brief Initialize some features of ADC group injected.
762 * @note These parameters have an impact on ADC scope: ADC group injected.
763 * Refer to corresponding unitary functions into
764 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
765 * (functions with prefix "INJ").
766 * @note The setting of these parameters by function @ref LL_ADC_Init()
767 * is conditioned to ADC state:
768 * ADC instance must be disabled.
769 * This condition is applied to all ADC features, for efficiency
770 * and compatibility over all STM32 families. However, the different
771 * features can be set under different ADC state conditions
772 * (setting possible with ADC enabled without conversion on going,
773 * ADC enabled with conversion on going, ...)
774 * Each feature can be updated afterwards with a unitary function
775 * and potentially with ADC in a different state than disabled,
776 * refer to description of each function for setting
777 * conditioned to ADC state.
778 * @note After using this function, other features must be configured
779 * using LL unitary functions.
780 * The minimum configuration remaining to be done is:
781 * - Set ADC group injected sequencer:
782 * map channel on the selected sequencer rank.
783 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
784 * - Set ADC channel sampling time
785 * Refer to function LL_ADC_SetChannelSamplingTime();
786 * @param ADCx ADC instance
787 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
788 * @retval An ErrorStatus enumeration value:
789 * - SUCCESS: ADC registers are initialized
790 * - ERROR: ADC registers are not initialized
791 */
792 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
793 {
794 ErrorStatus status = SUCCESS;
795
796 /* Check the parameters */
797 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
798 #if defined(ADC3)
799 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource));
800 #else
801 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
802 #endif
803 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
804 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
805 {
806 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
807 }
808 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
809
810 /* Note: Hardware constraint (refer to description of this function): */
811 /* ADC instance must be disabled. */
812 if(LL_ADC_IsEnabled(ADCx) == 0U)
813 {
814 /* Configuration of ADC hierarchical scope: */
815 /* - ADC group injected */
816 /* - Set ADC group injected trigger source */
817 /* - Set ADC group injected sequencer length */
818 /* - Set ADC group injected sequencer discontinuous mode */
819 /* - Set ADC group injected conversion trigger: independent or */
820 /* from ADC group regular */
821 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
822 /* ADC conversion. */
823 /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
824 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
825 {
826 MODIFY_REG(ADCx->CR1,
827 ADC_CR1_JDISCEN
828 | ADC_CR1_JAUTO
829 ,
830 ADC_INJ_InitStruct->SequencerDiscont
831 | ADC_INJ_InitStruct->TrigAuto
832 );
833 }
834 else
835 {
836 MODIFY_REG(ADCx->CR1,
837 ADC_CR1_JDISCEN
838 | ADC_CR1_JAUTO
839 ,
840 LL_ADC_REG_SEQ_DISCONT_DISABLE
841 | ADC_INJ_InitStruct->TrigAuto
842 );
843 }
844
845 MODIFY_REG(ADCx->CR2,
846 ADC_CR2_JEXTSEL
847 ,
848 ADC_INJ_InitStruct->TriggerSource
849 );
850
851 /* Note: Hardware constraint (refer to description of this function): */
852 /* Note: If ADC instance feature scan mode is disabled */
853 /* (refer to ADC instance initialization structure */
854 /* parameter @ref SequencersScanMode */
855 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
856 /* this parameter is discarded. */
857 LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
858 }
859 else
860 {
861 /* Initialization error: ADC instance is not disabled. */
862 status = ERROR;
863 }
864 return status;
865 }
866
867 /**
868 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
869 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
870 * whose fields will be set to default values.
871 * @retval None
872 */
873 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
874 {
875 /* Set ADC_INJ_InitStruct fields to default values */
876 /* Set fields of ADC group injected */
877 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
878 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
879 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
880 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
881 }
882
883 /**
884 * @}
885 */
886
887 /**
888 * @}
889 */
890
891 /**
892 * @}
893 */
894
895 #endif /* ADC1 || ADC2 || ADC3 */
896
897 /**
898 * @}
899 */
900
901 #endif /* USE_FULL_LL_DRIVER */
902
903 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/